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features l unity-gain stable bandwidth: 900mhz l low power: 50mw l low differential gain/phase errors: 0.025%/0.02 l high slew rate: 1700v/ m s l gain flatness: 0.1db to 135mhz l high output current (80ma) wideband, low-power, current-feedback operational amplifier applications l medical imaging l high-resolution video l high-speed signal processing l communications l pulse amplifiers l adc/dac gain amplifier l monitor preamplifier l ccd imaging amplifier description the opa658 is an ultra-wideband, low power current feed- back video operational amplifier featuring high slew rate and low differential gain/phase error. the current feedback de- sign allows for superior large signal bandwidth, even at high gains. the low differential gain/phase errors, wide bandwidth and low quiescent current make the opa658 a perfect choice for numerous video, imaging and communications applications. the opa658 is optimized for low gain operation and is also available in dual (opa2658) configurations. c comp current mirror in in + v out i bias i bias +v s ? s current mirror buffer opa658 opa658 opa658 sbos045a C march 1994 C revised june 2003 www.ti.com production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. copyright ? 1994-2003, texas instruments incorporated all trademarks are the property of their respective owners. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
opa658 2 sbos045a www.ti.com 1 2 3 4 8 7 6 5 nc +v s output nc nc ?nput +input ? s nc = no connection 1 2 3 5 4 +v s ?nput output ? s +input top view dip, so pin configuration absolute maximum ratings (1) supply ............................................................................................... 5.5v internal power dissipation ........................... see thermal characteristics differential input voltage .................................................................. 1.2v input voltage range ............................................................................ v s storage temperature range: p, u, ub, n .................... C40 c to +125 c lead temperature (soldering, 10s) ............................................... +300 c (soldering, so 3s) .......................................... +260 c junction temperature (t j ) ............................................................ +150 c note: (1) stresses above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum conditions for extended periods may affect device reliability. electrostatic discharge sensitivity this integrated circuit can be damaged by esd. texas instru- ments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degrada- tion to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. specified package temperature package ordering transport product package-lead designator (1) range marking number media, quantity opa658 so-8 surface-mount d C40 c to +85 c opa658u opa658u rails, 100 " """" opa658u/2k5 tape and reel, 2500 opa658 so-8 surface-mount d C40 c to +85 c opa658ub opa658ub rails, 100 " """" opa658ub/2k5 tape and reel, 2500 opa658 sot23-5 dbv C40 c to +85 c a58 opa658n/250 tape and reel, 250 " """" opa658n/3k tape and reel, 3000 opa658 dip-8 p C40 c to +85 c opa658p opa658p rails, 50 note: (1) for the most current specifications and package information, refer to our web site at www.ti.com. package/ordering information top view sot23
opa658 3 sbos045a www.ti.com frequency response closed-loop bandwidth (1) g = +1 (2) 900 [ (3) mhz g = +2 680 400 [ mhz g = +5 370 [ mhz g = +10 200 [ mhz slew rate (4) g = +2, 2v step 1700 1000 [ v/ m s at minimum specified temperature 1500 900 [ v/ m s settling time: 0.01% g = +2, 2v step 15 [ ns 0.1% g = +2, 2v step 11.5 [ ns 1% g = +2, 2v step 6 [ ns spurious-free dynamic range f = 5mhz, g = +2, v o = 2v pp 68 [ dbc f = 20mhz, g= +2, v o = 2v pp 56 [ dbc 3rd-order intercept point f = 10mhz, 4dbm each tone 40 [ dbm differential gain g = +2, ntsc, v o = 1.4v pp , r l = 150 w 0.025 [ % differential phase g = +2, ntsc, v o = 1.4v pp , r l = 150 w 0.02 [ degrees bandwidth for 0.1db flatness g = +2 135 (5) [ mhz offset voltage input offset voltage v cm = 0v 3 5.5 2 4.5 mv over temperature range 5 8 4 7mv power-supply rejection ratio v s = 4.7 to 5.5v 55 64 58 67 db input bias current noninverting v cm = 0v 5.7 30 [ 18 m a over temperature range 10 80 [ 35 m a inverting v cm = 0v 1.1 35 [[ m a over temperature range 30 75 [[ m a noise input voltage noise density f = 100hz 16 [ nv/ ? hz f = 2khz 4.9 [ nv/ ? hz f = 10khz 3.2 [ nv/ ? hz f = 1mhz 3.2 [ nv/ ? hz f b = 100hz to 200mhz 45.3 [ m vrms input bias current noise density inverting: f = 1mhz 32 [ pa/ ? hz noninverting: f = 1mhz 11.9 [ pa/ ? hz input voltage range common-mode input range over temperature range 2.5 2.9 [[ v common-mode rejection v cm = 1v 45 50 [[ db input impedance noninverting 500 || 1 [ k w || pf inverting 50 [ w open-loop transresistance open-loop transresistance v o = 2v, r l = 100 w 150 190 200 250 k w over temperature range v o = 2v, r l = 100 w 100 150 k w output voltage output no load 2.7 2.9 [[ v over temperature range 2.5 2.75 [[ v voltage output r l = 250 w 2.7 2.9 [[ v over temperature range 2.5 2.7 [[ v voltage output r l = 100 w 2.2 2.8 [[ v over temperature range 2.0 2.5 [[ v output current, sourcing 80 120 [[ ma over temperature 70 [ ma output current, sinking 60 80 [[ ma over temperature 35 [ ma short circuit current 150 [ ma output resistance 0.1mhz, g = +2 0.02 [ w power supply specified operating voltage 5 [ v operating voltage range 4.5 5.5 [[ v quiescent current v s = 5v 5 7.75 4.5 5.75 ma over temperature range 5.5 8.5 4.7 6.5 ma temperature range specification: p, u, n, ub C40 +85 [[ c thermal resistance, q ja p dip-8 100 [ c/w u so-8 125 [ c/w n sot23-5 150 [ c/w (1) frequency response can be strongly influenced by pc board parasitics. the demonstration boards show low parasitic layouts f or this part. refer to the demonstration board layout for details. (2) at g = +1, r fb = 560 w for dip and 402 w for so-8. (3) an asterisk ( [ ) specifies the same value as the grade to the left. (4) slew rate is rate of change from 10% to 90% of output voltage step. (5) this specification is pc board layout dependent. electrical characteristics at t a = +25 c, v s = 5v, r l = 100 w , and r fb = 402 w, unless otherwise noted. opa658p, u, n opa658ub parameter condition min typ max min typ max units
opa658 4 sbos045a www.ti.com typical characteristics at t a = +25 c, v s = 5v, r l = 100 w , and r fb = 402 w , unless otherwise noted. power-supply rejection ratio and common-mode rejection vs temperature 75 70 65 60 55 50 45 ?5 ?0 ?5 0 25 50 75 100 125 psrr , cmr (db) cmr psr temperature ( c) psr+ psrr 55 50 45 40 35 30 25 ? ? ? ? 0 1 2 3 4 common-mode rejection vs input common-mode voltage common-mode rejection (db) common-mode voltage (v) supply current vs temperature 5.5 5.0 4.5 4.0 3.5 ?5 ?0 ?5 0 25 50 75 100 125 ambient temperature ( c) supply current ( ma) 120 110 100 90 80 70 ?5 ?0 ?5 0 25 50 75 100 125 output current vs temperature ambient temperature ( c) output current ( ma) i o i o + 3.20 3.10 3.00 2.90 2.80 2.70 2.60 2.50 2.40 2.30 output swing vs temperature temperature ( c) ?0 ?0 ?0 0 20 40 60 80 100 output swing (v) +v o r l = 250 w r l = 100 w ? o ? o +v o noninverting input bias current vs temperature ?5 ?0 ?5 0 25 50 75 100 125 ambient temperature ( c) noninverting input bias current i b + ( a) 10 9 8 7 6 5 4 3 2
opa658 5 sbos045a www.ti.com typical characteristics (cont.) at t a = +25 c, v s = 5v, r l = 100 w , and r fb = 402 w , unless otherwise noted. inverting input bias current vs temperature ?5 ?0 ?5 0 25 50 75 100 125 temperature ( c) inverting input bias current i b ?( a) 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 10 6 10 5 10 4 10 3 10 2 10 1 1 45 0 ?5 ?0 ?35 ?80 ?25 1k 10k 100k 1m 10m 100m 1g open-loop transimpedance and phase vs frequency frequency (hz) transimpedance ( w ) open-loop phase ( ) phase transimpedance open-loop gain and phase vs frequency frequency (hz) 60 40 20 0 ?0 ?0 ?0 45 0 ?5 ?0 ?35 ?80 ?25 1k 10k 100k 1m 10m 100m 1g open-loop gain (db) open-loop phase ( ) gain phase 6 3 0 ? ? ? 1m 10m 100m 1g closed-loop bandwidth frequency (hz) gain (db) so-8 bandwidth = 881mhz, r fb = 402 w g = +1 dip bandwidth = 949mhz, r fb = 560 w 9 6 3 0 e3 e6 1m 10m 100m 1g closed-loop bandwidth frequency (hz) gain (db) dip bandwidth = 682mhz so-8 bandwidth = 680mhz g = +2 20 17 14 11 8 5 2 1m 10m 100m 1g closed-loop bandwidth frequency (hz) gain (db) so-8/dip bandwidth= 372mhz g = +5
opa658 6 sbos045a www.ti.com typical characteristics (cont.) at t a = +25 c, v s = 5v, r l = 100 w , and r fb = 402 w , unless otherwise noted. 26 23 20 17 14 11 8 1m 10m 100m 1g closed-loop bandwidth frequency (hz) gain (db) so-8/dip bandwidth = 200mhz g = +10 160 120 80 40 0 ?0 ?0 ?20 ?60 time (5ns/div) small-signal transient response output voltage (mv) g = +2 40 35 30 25 20 15 10 10 100 90 80 70 60 50 40 30 20 recommended isolation resistance vs capacitive load capacitive load (pf) isolation resistance g = +2 opa658 c l 1k w r iso 402 w 402 w 1.6 1.2 0.8 0.4 0 ?.4 ?.8 ?.2 ?.6 large-signal transient response time (5ns/div) output voltage (v) g = +2 ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?00 100k 1m 10m 100m harmonic distortion vs frequency frequency (hz) harmonic distortion (dbc) 2f o 3f o 5mhz harmonic distortion vs output swing output swing (v pp ) ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?00 01 234 harmonic distortion (dbc) 2f o 3f o g = +2
opa658 7 sbos045a www.ti.com typical characteristics (cont.) at t a = +25 c, v s = 5v, r l = 100 w , and r fb = 402 w , unless otherwise noted. 10mhz harmonic distortion vs output swing output swing (v pp ) ?0 ?0 ?0 ?0 ?00 0.01 0.1 2f o 14v10 harmonic distortion (dbc) 3f o ?0 ?5 ?0 ?5 ?0 ?5 ?5 ?0 ?5 0 25 50 75 100 125 temperature ( c) harmonic distortion vs temperature? harmonic distortion (dbc) 3f o 2f o v o = 2v pp g = +2 harmonic distortion vs gain noninverting gain (v/v) ?0 ?5 ?0 ?5 ?0 ?5 harmonic distortion (dbc) 012345678910 3f o 2f o f o = 5mhz v o = 2v pp input voltage and current noise vs frequency frequency (hz) 100 10 1 voltage noise (nv/ ? hz) current noise (pa/ ? hz) 10 2 10 3 10 4 10 5 10 6 10 7 noninverting noise inverting current noise voltage noise
opa658 8 sbos045a www.ti.com for noninverting operation, the input signal is applied to the noninverting (high impedance buffer) input. the output (buffer) error current (i e ) is generated at the low impedance inverting input. the signal generated at the output is fed back to the inverting input such that the overall gain is (1 + r fb /r ff ). where a voltage-feedback amplifier has two symmetrical high impedance inputs, a current-feedback amplifier has a low inverting (buffer output) impedance and a high noninverting (buffer input) impedance. the closed-loop gain for the opa658 can be calculated using equations 1 and 2. inverting gain r r loop gain fb ff = - ? ? ? ? + 1 1 (1) noninverting gain r r loop gain where loop gain t r r r fb ff o fb rs fb ff = + ? ? + = + + ? ? ? ? ? ? 1 1 1 1 (2) at higher gains, the small value inverting input impedance causes an apparent loss in bandwidth. this can be seen from equation 3. f f actual a s fb fb ff bw bw r r r r v ? [ ] ( ) + ? ? ? ? + ? ? ? ? ? ? = + ( ) 2 1 25 1 1 . (3) this loss in bandwidth at high gains can be corrected without affecting stability by lowering the value of the feedback resistor from the specified value of 402 w . offset voltage and noise the output offset is the algebraic sum of the input offset voltage and bias current errors. the output offset for the model of figure 2 is calculated by equation 4. output offset voltage ib r r r v r r ib r n n fb ff io fb ff n fb = + ? ? ? ? + ? ? ? ? 1 1 (4) applications information theory of operation conventional op amps depend on feedback to drive their inputs to the same potential, however the current-feedback op amps inverting and noninverting inputs are connected by a unity-gain buffer, thus enabling the inverting input to automatically assume the same potential as the noninverting input. this results in very low impedance at the inverting input to sense the feedback as an error current signal. discussion of performance the opa658 is a low-power, unity-gain stable, current- feedback operational amplifier which operates on 5v power supply. the current-feedback architecture offers the follow- ing important advantages over voltage-feedback architec- tures: (1) the high slew rate allows the large-signal perfor- mance to approach the small-signal performance, and (2) there is very little bandwidth degradation at higher gain settings. the current-feedback architecture of the opa658 provides the traditional strength of excellent large-signal response plus wide bandwidth, making it a good choice for use in high- resolution video, medical imaging and digital-to-analog con- verter (dac) i/v conversion. the low-power requirements make it an excellent choice for numerous portable applica- tions. dc gain transfer characteristics the circuit in figure 1 shows the equivalent circuit for calculating the dc gain. when operating the device in the inverting mode, the input signal error current (i e ) is amplified by the open loop transimpedance gain (t o ). the output signal generated is equal to t o x i e . negative feedback is applied through r fb such that the device operates at a gain equal to Cr fb /r ff . figure 1. equivalent circuit. figure 2. output offset voltage equivalent circuit. v o t o c c l s r s (50 w ) c 1 v i v n r ff r fb i e + r fb r ff ib i r n ib n v io
opa658 9 sbos045a www.ti.com the feedback resistor value acts as the frequency response compensation element for a current-feedback type amplifier. the 402 w used in setting the specification achieves a nomi- nal maximally-flat butterworth response while assuming a 2pf output pin parasitic. increasing the feedback resistor will overcompensate the amplifier, rolling off the frequency re- sponse, while decreasing it will decrease phase margin, peaking up the frequency response. note that a noninverting, unity-gain buffer application still requires a feedback resistor for stability (560 w for so-8, 402 w for dip, and 324 w for sot23). d) connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. for short connections, consider the trace and the input to the next device as a lumped capacitive load. relatively wide traces (50 mils to 100 mils) should be used, preferably with ground and power planes opened up around them. estimate the total capacitive load and set r iso from the plot of recommended r iso vs capacitive load. low parasitic loads may not need an r iso since the opa658 is nominally compensated to operate with a 2pf parasitic load. if a long trace is required and the 6db signal loss intrinsic to doubly-terminated transmission lines is acceptable, imple- ment a matched impedance transmission line using microstrip or stripline techniques (consult an ecl design handbook for microstrip and stripline layout techniques). a 50 w environ- ment is not necessary onboard, and in fact a higher imped- ance environment will improve distortion as shown in the distortion vs load plot. with a characteristic impedance de- fined based on board material and desired trace dimensions, a matching series resistor into the trace from the output of the amplifier is used as well as a terminating shunt resistor at the input of the destination device. remember also that the terminating impedance will be the parallel combination of the shunt resistor and the input impedance of the destination device; the total effective impedance should match the trace impedance. multiple destination devices are best handled as separate transmission lines, each with their own series and shunt terminations. if the 6db attenuation loss of a doubly-terminated line is unacceptable, a long trace can be series-terminated at the source end only. this will help isolate the line capacitance from the op amp output, but will not preserve signal integrity as well as a doubly-terminated line. if the shunt impedance at the destination end is finite, there will be some signal attenuation due to the voltage divider formed by the series and shunt impedances. e) socketing a high-speed part like the opa658 is not recommended. the additional lead length and pin-to-pin capacitance introduced by the socket creates an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable response. best re- sults are obtained by soldering the part onto the board. if socketing for the dip package is desired, high-frequency, flush-mount pins (for instance, mckenzie technology #710c) can give good results. if all terms are divided by the gain (1 + r fb /r ff ) it can be observed that input referred offsets improve as gain in- creases. the effective noise at the output can be determined by taking the root sum of the squares of equation 4 and applying the spectral noise values found in the typical characteristics section. this applies to noise from the op amp only. note that both the noise figure (nf) and the equivalent input offset voltages improve as the closed-loop gain increases (by keeping r fb fixed and reducing r ff with r n = 0 w ). increasing bandwidth at high gains the closed-loop bandwidth can be extended at high gains by reducing the value of the feedback resistor r fb . this band- width reduction is caused by the feedback current being split between r s and r ff (refer to figure 1). as the gain increases (for a fixed r fb ), more feedback current is shunted through r ff , which reduces closed-loop bandwidth. circuit layout and basic operation achieving optimum performance with a high-frequency am- plifier such as the opa658 requires careful attention to layout parasitics and selection of external components. rec- ommendations for pc board layout and component selection include: a) minimize parasitic capacitance to any ac ground for all of the signal i/o pins. parasitic capacitance on the output and inverting input pins can cause instability; on the noninverting input it can react with the source impedance to cause unintentional bandlimiting. to reduce unwanted capacitance, a window around the signal i/o pins should be opened in all of the ground and power planes. otherwise, ground and power planes should be unbroken elsewhere on the board. b) minimize the distance (< 0.25") from the two power pins to high-frequency 0.1 m f decoupling capacitors. at the pins, the ground and power-plane layout should not be in close proximity to the signal i/o pins. avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. larger (2.2 m f to 6.8 m f) decou- pling capacitors, effective at lower frequencies, should also be used. these may be placed somewhat farther from the device and may be shared among several devices in the same area of the pc board. c) careful selection and placement of external compo- nents will preserve the high-frequency performance of the opa658 . resistors should be a very low reactance type. surface-mount resistors work best and allow a tighter overall layout. metal film or carbon composition axially-leaded resis- tors can also provide good high-frequency performance. again, keep their leads as short as possible. never use wire- wound type resistors in a high-frequency application. since the output pin and the inverting input pin are most sensitive to parasitic capacitance, always position the feed- back and series output resistor, if any, as close as possible to the package pins. other network components, such as noninverting input termination resistors, should also be placed close to the package.
opa658 10 sbos045a www.ti.com the opa658 is nominally specified for operation using 5v power supplies. a 10% tolerance on the supplies, or an ecl C5.2v for the negative supply, is within the maximum specified total supply voltage of 11v. higher supply voltages can break down internal junctions possibly leading to cata- strophic failure. single-supply operation is possible as long as common-mode voltage constraints are observed. the common-mode input and output voltage specifications can be interpreted as a required headroom to the supply voltage. observing this input and output headroom requirement will allow non-standard or single-supply operation. figure 3 shows one approach to single-supply operation. thermal considerations the opa658 will not require heatsinking under most operat- ing conditions. maximum desired junction temperature will set a maximum allowed internal power dissipation as de- scribed below. in no case should the maximum junction temperature be allowed to exceed 175 c. operating junction temperature (t j ) is given by t a + p d q ja . the total internal power dissipation (p d ) is the sum of quiescent power (p dq ) and additional power dissipated in the output stage (p dl ) to deliver load power. quiescent power is simply the specified no-load supply current times the total supply voltage across the part. p dl will depend on the required output signal and load but would, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to 1/2 either supply voltage (for equal bipolar supplies). under this condition p dl = v s 2 /(4 r l ) where r l includes feedback network loading. note that it is the power in the output stage and not into the load that determines internal power dissipation. as an example, compute the maximum t j for an opa658n at a v = +2, r l = 100 w , r fb = 402 w , v s = 5v, and the specified maximum t a = +85 c. p d = 10v 8.5ma + 5 2 /[4 (100 w || 804 w )] = 155mw maximum t j = 85 c + 0.155w 150 c/w = 108 c driving capacitive loads the opa658s output stage has been optimized to drive low resistive loads. capacitive loads, however, will decrease the amplifiers phase margin which may cause high-frequency peaking or oscillations. capacitive loads greater than 5pf should be buffered by connecting a small resistance, usually 10 w to 35 w , in series with the output as illustrated in figure 5. this is particularly important when driving high capacitance loads such as flash adcs. in general, capacitive loads should be minimized for opti- mum high-frequency performance. coaxial lines can be driven if the cable is properly terminated. the capacitance of coaxial cable (29pf/foot for rg-58) will not load the amplifier when the coaxial cable or transmission line is terminated with its characteristic impedance. figure 4. closed-loop output impedance vs frequency. esd protection esd static damage has been well recognized for mosfet devices, but any semiconductor device deserves protection from this potentially damaging source. this is particularly true for very high-speed, fine geometry processes. esd static damage can cause subtle changes in amplifier input characteristics without necessarily destroying the de- vice. in precision operational amplifiers, this may cause a noticeable degradation of offset voltage and drift. therefore, static protection is strongly recommended when handling the opa658. output drive capability the opa658 has been optimized to drive 75 w and 100 w resistive loads. the device can drive 2v pp into a 75 w load. this high-output drive capability makes the opa658 an ideal choice for a wide range of rf, if, and video applications. in many cases, additional buffer amplifiers are unneeded. many demanding high-speed applications such as analog-to- digital converter (adc)/dac buffers require op amps with low wideband output impedance. for example, low output imped- ance is essential when driving the signal-dependent capaci- tances at the inputs of flash adcs. as shown in figure 4, the opa658 maintains very low closed-loop output impedance over frequency. closed-loop output impedance increases with frequency since loop gain is decreasing with frequency. figure 3. single-supply operation. 402 w opa658 v ac 402 w r l +v s +v s v s 2 r out v s 2 v out = + a v v ac a v = +2 100 10 1 0.1 0.01 0.001 10k 100k 1m 10m 100m output impedance ( w ) frequency (hz) g = +2
opa658 11 sbos045a www.ti.com appear at f o 3 df. the 2-tone, 3rd-order spurious plot shown in figure 7 indicates how far below these two equal power, closely-spaced tones the intermodulation spurious will be. the single-tone power is at a matched 50 w load. the unique design of the opa658 provides much greater spuri- ous free range than what a 2-tone, 3rd-order intermodulation intercept specification would predict. this can be seen in figure 7 as the spurious-free range actually increases at the higher output power levels. compensation the opa658 is internally compensated and is stable in unity gain with a phase margin of approximately 62 , and approxi- mately 64 in a gain of +2v/v when used with the recom- mended feedback resistor value. frequency response for other gains are shown in the typical characteristics. the high-frequency response of the opa658 in a good layout is very flat with frequency. distortion the opa658s harmonic distortion characteristics into a 100 w load are shown versus frequency and power output in the typical characteristics. distortion can be further im- proved by increasing the load resistance as illustrated in figure 6. remember to include the contribution of the feed- back resistance when calculating the effective load resis- tance seen by the amplifier. narrowband communication channel requirements will ben- efit from the opa658s wide bandwidth and low intermodulation distortion on low quiescent power. if output signal power at two closely spaced frequencies is required, 3rd-order nonlinearities in any amplifier will cause spurious power at frequencies very near the two fundamental frequen- cies. if the two test frequencies, f 1 and f 2 , are specified in terms of average and delta frequency, f o = (f 1 + f 2 )/2 and df = w f 2 C f 1 w , the two, 3rd-order, close-in spurious tones will differential gain and phase differential gain (dg) and differential phase (dp) are among the more important specifications for video applications. dg is defined as the percent change in closed-loop gain over a specified change in output voltage level. dp is defined as the change in degrees of the closed-loop phase over the same output voltage change. both dg and dp are specified at the ntsc sub-carrier frequency of 3.58mhz and the pal sub- carrier of 4.43mhz. all ntsc measurements were performed using a tektronix model vm700a video measurement set. dg/dp of the opa658 were measured with the amplifier in a gain of +2v/v with 75 w input impedance and the output back-terminated in 75 w . the input signal selected from the generator was a 0v to 1.4v modulated ramp with sync pulse. with these conditions the test circuit shown in figure 8 delivered a 100ire modulated ramp to the 75 w input of the videoanalyzer. the signal averaging feature of the analyzer was used to establish a reference against which the perfor- figure 5. driving capacitive loads. figure 6. 5mhz harmonic distortion vs load resistance. figure 7. 3rd-order spurious level vs frequency. figure 8. configuration for testing differential gain/phase. opa658 50 w r iso r l c l 10 w to 35 w 402 w 402 w ?5 ?0 ?5 ?0 ?5 ?0 ?5 5mhz harmonic distortion vs load resistance (g = +2) load resistance ( w ) harmonic distortion (dbc) 10 100 1k g = +2 v o = 2v pp f o = 5mhz 3f o 2f o ?5 ?0 ?5 ?0 ?5 ?0 ?8 ?6 ?4 ?2 ?0 ? ? ? ? 0 2 4 3rd-order spurious level (dbc) 2-tone, 3rd-order spurious levels single-tone power (dbm) 20mhz 10mhz 5mhz opa658 75 w 75 w 402 w 402 w 75 w 75 w tek tsg 130a tek vm700a
opa658 12 sbos045a www.ti.com mance of the amplifier was measured. signal averaging was also used to measure the dg and dp of the test signal in order to eliminate the generators contribution to measured ampli- fier performance. typical performance of the opa658 is 0.025% differential gain and 0.02 differential phase to both ntsc and pal standards. design-in tools demonstration boards several pc boards are available to assist in the initial evaluation of circuit performance using the opa658 in its three package styles. all of these are available free as an unpopulated pc board delivered with descriptive documen- tation. the summary information for these boards is shown in table i. to request any of these boards, check the texas instru- ments web site at www.ti.com. board literature part request product package number number opa658u so-8 dem-opa68xu sbou009 opa658n sot23-5 dem-opa6xxn sbou010 opa658p dip-8 dem-opa68xp sbou008 table i. demo board part/ordering numbers.
package option addendum www.ti.com 11-apr-2013 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) op temp (c) top-side markings (4) samples opa658n/250 obsolete sot-23 dbv 5 tbd call ti call ti 0 to 70 opa658n/3k obsolete sot-23 dbv 5 tbd call ti call ti opa658nb/250 obsolete sot-23 dbv 5 tbd call ti call ti opa658nb/3k obsolete sot-23 dbv 5 tbd call ti call ti opa658p obsolete pdip p 8 tbd call ti call ti opa658u obsolete soic d 8 tbd call ti call ti opa658u-1 obsolete soic d 8 tbd call ti call ti opa658u/2k5 obsolete soic d 8 tbd call ti call ti opa658ub obsolete soic d 8 tbd call ti call ti opa658ub/2k5 obsolete soic d 8 tbd call ti call ti (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) multiple top-side markings will be inside parentheses. only one top-side marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire top-side marking for that device. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and
package option addendum www.ti.com 11-apr-2013 addendum-page 2 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.

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