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| september 2013 doc id 18309 rev 6 1/75 1 L99PM60J power management ic with lin transceiver features one 5 v low-drop voltage regulators (100 ma, continuous mode) no electrolytic capacitor required on regulator output (only 220 nf ceramic typ.) ultra-low quiescent current in v bat-standby (7 a) and v 1-standby (45 a) window watchdog and advanced fail-safe functionality configurable fail-safe output programmable reset threshold (4.6 v; 3.5 v) v s monitoring / temperature measurement lin 2.1 compliant (sae j2602 compatible) transceiver high-speed lin flash mode up to 100 kbit/s st spi interface for mode control and diagnostics 2 high-side drivers, e.g. led or hall (r dson,typ = 7 ) 2 low-side drivers (r dson,typ = 2 ) outputs are short-circuit protected direct drive feature for high sides temperature warning and thermal shutdown applications automotive ecus requiring lin and power management features such as door zone, and body control modules description the L99PM60J is a power management system ic that features one low-drop regulator, a direct drive for high-side drivers, and a lin 2.1 compliant sae j2602 transceiver. the integrated standard serial peripheral interface (spi) controls all L99PM60J operation modes and provides driver diagnostic functions. table 1. device summary package order codes tube tape and reel powersso-16 L99PM60J L99PM60Jtr powersso-16 * $ 3 * & ) 7 www.st.com
contents L99PM60J 2/75 doc id 18309 rev 6 contents 1 block diagram and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1.1 voltage regulator failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1.2 voltage regulator behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 power control in operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.2.1 active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.2 flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.3 v 1-standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.4 v bat-standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 wake up from standby modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4 cyclic contact supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5 functional overview (truth table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.6 window ? watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.7 fail safe mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.7.1 temporary failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.7.2 nonrecoverable failures ? entering forced v bat-standby mode . . . . . . . . 19 2.7.3 fail safe output (out1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.8 reset output (nreset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.9 lin bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.9.1 error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.9.2 wake up (from lin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.10 serial peripheral interface (st spi standard) . . . . . . . . . . . . . . . . . . . . . 23 3 protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.1 high side driver outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.1.1 out1 reprogramming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.2 low side driver outputs rel1, rel2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.3 spi diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4 power supply fail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.1 vs overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 L99PM60J contents doc id 18309 rev 6 3/75 4.2 vs undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.3 temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 28 5 typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.2 esd protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.3 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.4.1 supply and supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.4.2 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.4.3 power-on reset (v s ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.4.4 voltage regulator v 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.4.5 reset output (v 1 supervision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.4.6 watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.4.7 high-side outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.4.8 low-side drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.4.9 direct drive / voltage supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.4.10 lin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.4.11 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7 st spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.1 spi communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.1.1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.1.2 command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.1.3 operating code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.1.4 global status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.1.5 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.1.6 address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.1.7 write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.1.8 format of data shifted out at sdo during write cycle . . . . . . . . . . . . . . 52 7.1.9 read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.1.10 format of data shifted out at sdo during read cycle . . . . . . . . . . . . . . . 53 7.1.11 read and clear status operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7.1.12 format of data shifted out at sdo during ?read and clear status? operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 contents L99PM60J 4/75 doc id 18309 rev 6 7.1.13 read device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 7.2 spi registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 7.2.1 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 8 package and pcb thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 8.1 powersso-16 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 9 package and packaging information . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 9.1 ecopack ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 9.2 powersso-16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 9.3 powersso-16 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 L99PM60J list of tables doc id 18309 rev 6 5/75 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin descriptions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3. wake up sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 4. functional overview (truth table). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 5. fail safe conditions and exit modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 6. failures management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 7. absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 8. esd protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 9. operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 10. temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 11. supply and supply monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 12. oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 13. power-on reset (v s ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 14. voltage regulator v 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 15. reset output (v 1 supervision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 16. watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 17. output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 18. relay drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 19. input: drv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 20. output: vsout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 21. lin transmit data input: pin txd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 22. lin receive data output: pin rxd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 23. lin transmitter and receiver: pin lin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 24. lin transceiver timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 25. lin flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 26. input: csn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 27. input csn for flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 28. inputs: clk, di . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 29. di timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 30. output do. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 31. do timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 32. csn timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 33. rxdl/nint timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 34. command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 35. operating code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 36. global status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 37. detailed global status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 38. configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 39. addressing mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 40. write command format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 41. format of data shifted out at sdo during write cycle: global status register . . . . . . . . . . . 52 table 42. format of data shifted out at sdo during write cycle: data byte . . . . . . . . . . . . . . . . . . . . 52 table 43. read command format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 44. format of data shifted out at sdo during read cycle: global status register. . . . . . . . . . . . 53 table 45. format of data shifted out at sdo during read cycle: data byte . . . . . . . . . . . . . . . . . . . . . 53 table 46. read and clear status? command format? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 47. format of data shifted out at sdo during ?read and clear status? operation: global status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 list of tables L99PM60J 6/75 doc id 18309 rev 6 table 48. format of data shifted out at sdo during read cycle: data byte . . . . . . . . . . . . . . . . . . . . . 55 table 49. read device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 50. id-header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 51. family identifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 52. silicon version. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 53. silicon version code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 54. spi-frame-id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 55. spi register: command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 56. spi register: mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 57. spi register: ctrl register selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 58. spi register: stat register selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 59. overview of control register data byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 60. control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 61. control register 1, 1 st data byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 62. control register 1, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 63. control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 64. control register 2, 1 st data byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 65. control register 2, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 66. overview of status register data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 67. global status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 68. status register 1, command and data byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 69. status register 1, data byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 70. status register 1, bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 71. status register 2, command and data byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 72. status register 2, data byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 73. status register 2, bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 74. status register 3, command and data byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 75. status register 3, data byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 76. status register 3, bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 77. status register 4, command and data byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 78. status register 4, data byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 79. status register 4, bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 80. powersso-16 thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 81. powersso-16 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 82. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 L99PM60J list of figures doc id 18309 rev 6 7/75 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2. pin connection powersso-16 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3. supply voltage operation summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 figure 4. operating modes ? main states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 5. watchdog in normal operating mode (no errors) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 6. watchdog with error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 7. watchdog in flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 8. recovery after forced vbat due to multiple watchdog failure . . . . . . . . . . . . . . . . . . . . . . 20 figure 9. recovery after forced vbat due to multiple tsd2 failure . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 10. recovery after forced vbat due to short at v 1 failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 11. thermal shutdown protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 12. typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 13. watchdog timing (missing watchdog trigger) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 14. watchdog early, late and safe windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 15. lin transmit, receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 16. spi ? input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 17. spi ? output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 18. spi transition parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 19. spi global status register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 20. read configuration register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 21. write configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 22. format of data shifted out at sdo during write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 23. format of data shifted out at sdo during read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 24. format of data shifted out at sdo during ?read and clear status? operation . . . . . . . . . . 55 figure 25. thermal data of powersso-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 26. r thj-amb vs pcb copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 27. v 1 thermal impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 28. thermal fitting model of v 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 29. powersso-16 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 30. powersso-16 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 31. powersso-16 tape and reel shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 block diagram and pin descriptions L99PM60J 8/75 doc id 18309 rev 6 1 block diagram and pin descriptions figure 1. block diagram table 2. pin descriptions and functions pin symbol function 1 gnd ground 2 nreset nreset output to micro controller; internal pull-up of typ. 100 k (reset state = low) 3 do spi: serial data output 4 di spi: serial data input 5 v1 voltage regulator 1 output: 5 v supply e.g. micro controller 6 clk spi: serial clock input 7 rxd/nint receiver output of the lin 2.1 transceiver or interrupt: 8 drv/vsm/tmp direct drive for high-side drivers out1/2; v s and temperature monitoring 9 csn spi: chip select not input ' , 9 u h j 9 p $ + l j k 6 l g h 6 3 , / 2 * , & : l q g r z : d w f k g r j 9 v & 6 1 & / . ' 2 2 8 7 2 8 7 ) 6 2 / r z 6 l g h 2 x w s x w & o d p s 9 / , 1 6 $ ( - / , 1 5 [ ' 1 , 1 7 7 [ ' 1 5 h v h w * 1 ' 5 ( / 5 ( / ' l u h f w ' u l y h ' 5 9 9 6 0 7 0 3 9 v 0 r q l w r u l q j 9 v 8 q g h u y r o w d j h 2 y h u y r o w d j h 6 k x w g r z q 7 h p s 0 r q l w r u l q j / , 1 f r p s o l d q w / r z 6 l g h 2 x w s x w & o d p s + l j k 6 l g h 9 u h j 0 r q l w r u $ * 9 7 h p s 3 u h z d u q l q j 6 k x w g r z q L99PM60J block diagram and pin descriptions doc id 18309 rev 6 9/75 figure 2. pin connection powersso-16 (top view) note: it is recommended to connect pin gnd directly to the heat slug. 10 out2 high side drivers (7 , typ.): to supply e.g. led's, hall sensors, external contacts 11 out1/fso high side driver (7 , typ.): to supply e.g. led's, hall sensors, external contacts 12 txd transmitter input of the lin 2.1 transceiver 13 v s power supply voltage 14 rel1 low side driver (2 typ.): e.g. relay 15 rel2 low side driver (2 typ.): e.g. relay 16 lin lin bus line table 2. pin descriptions and functions (continued) pin symbol function ' , 2 8 7 * 1 ' 3 r z h u 6 6 2 1 5 ( 6 ( 7 ' 2 ' 5 9 9 6 0 7 0 3 & / . 5 [ ' 1 , 1 7 / , 1 2 8 7 ) 6 2 5 ( / 5 ( / & 6 1 7 [ ' 9 v 9 7 $ % * 1 ' $ * 9 detailed description L99PM60J 10/75 doc id 18309 rev 6 2 detailed description 2.1 voltage regulator the L99PM60J contains a fully protected low drop voltage regulator, which is designed for very fast transient response. the output voltage is stable with loads capacitors > 220 nf the v 1 voltage regulator provides 5 v supply voltage and up to 100 ma continuous load current and is mainly intended for supply of the system microcontroller. the v 1 regulator is embedded in the power management and failsafe functionality of the device and operates according to the selected operating mode. in addition the regulator v 1 drives the L99PM60J internal 5 v loads. the voltage regulator is protected against overload and overtemperature. an external reverse current protection has to be provided by the application circuitry to prevent the input capacitor from being discharged by negative transients or low input voltage. current limitation of the regulator ensures fast charge of external bypass capacitors. the output voltage is stable for ceramic load capacitors > 220 nf. if device temperature exceeds tsd1 threshold, all outputs (outx, relx, lin) are deactivated except v 1 . hence the micro controller has the possibility for interaction or error logging. in case of exceeding tsd2 threshold (tsd2 > tsd1), also v 1 is deactivated (see state chart figure 11 ). a timer is started and the voltage regulator is deactivated for t tsd . during this time, all other walk-up sources (lin) are disabled. after 1 sec., the voltage regulator tries to restart automatically. if the restart fails 7 times without clearing and thermal shutdown condition still exists, the L99PM60J enters the v bat-standby mode. in case of short to gnd at ?v 1 ? after initial turn on (v 1 < v 1fail for t > tv1short) the L99PM60J enters the v bat-standby mode. reactivation (wake-up) of the device can be achieved with signals from lin. 2.1.1 voltage regulator failure the v 1, regulator output voltage is monitored. in case of a drop below the v 1 ? fail thresholds (v 1 < v 1fail for t > t v1fail ), the v 1 -fail bit is latched. the fail bits can be cleared by a dedicated spi command. short to ground detection at power-on, in case of short detection on v 1 , the regulator output switches off after t v1short and the L99PM60J turns to forced v bat-standby mode. the forced v bat tsd2/shtv1 and v 1fail lists are set. during normal mode, once the regulator exceeded the v 1fail threshold, in case of short detection on v 1 , the device turns to force v bat-standby mode only after thermal shutdown tsd2 detection. in this case the forced v bat tsd2/shtv1 bit is set. v 1 undervoltage warning for the L99PM60J 2 different v 1 reset thresholds can be selected. the higher threshold v rt2 is set by default. if the lower threshold is selected the v 1 undervoltage warning flag is set, if the voltage on v 1 output drops below the higher threshold. this bit is latched and can be read and optionally cleared. L99PM60J detailed description doc id 18309 rev 6 11/75 v 1 failure failsafe activation if the voltage on v 1 output drops below the selected v 1 reset threshold the reset output is pulled to ground. if the v 1 output voltage remains below the v 1 reset threshold for longer than t fso , fail safe mode is activated additionally. for more details about failsafe please refer to chapter fail safe mode 2.1.2 voltage regulator behaviour figure 3. supply voltage operation summary 2.2 power control in operating modes the L99PM60J can be operated in 4 different operating modes: active flash v 1-standby v bat-standby 2.2.1 active mode all functions are available and the device is controlled by the st spi interface. 9 v > 9 @ 9 > 9 @ 1 u h v h w > 9 @ 9 1 9 ' 3 9 3 2 5 & r o g 6 w d u w e l w l v v h w x v 9 5 7 + + l j k / r z 3 r z h u r q 5 h v h w w k u h v k r o g 9 i d l o , i w ! w y v k r u w 9 v k r u w g h w h f w h g ? 9 e d w w v w d q g e \ 9 i d l o e l w l v v h w 9 v x y e l w l v w v h w w w ) 7 w 5 5 w 5 5 w ! w ) 7 1 r 5 h v h w j h q h u d w h g w ! w ) 7 w : ' 5 w : ' 5 9 6 8 9 , q d f w l y h $ f w l y h , q d f w l y h 5 h d g & o h d u ) 6 2 % l w 9 , 1 & r q w u r o 5 h j l v w h u v d u h v h w w r g h i d x o w y d o x h v ' l v d e o h g ' l v d e o h g 9 $ % 6 p l q + l j k = * u r x q g h g & r q w u r o 5 h j l v w h u v d u h v h w w r g h i d x o w y d o x h v ) d l o 6 d i h 2 x w s x w x v 9 $ % p l q 9 6 p l q i r u 9 d f w l y h f r q w u r o 9 6 6 9 9 6 v x s s o \ x q g h u y r o w d j h 9 3 2 5 3 r z h u 2 q u h v h w y r o w d j h 9 1 9 q r p l q d o y r o w d j h 9 5 6 7 5 h v h w w k u h v k r o g y r o w d j h 9 i d l o 9 i d l o w k u h v k r o g $ * 9 w ) 6 2 w ) 7 9 x q g h u y r o w d j h i l o w h u w l p h w 5 5 5 h v h w u h d f w l r q w l p h u w : ' 5 : d w f k g r j u h v h w s x o v h w l p h w ) 6 2 ) 6 2 v l j q d o i l o w h u w l p h detailed description L99PM60J 12/75 doc id 18309 rev 6 2.2.2 flash mode to program the system microcontroller, the L99PM60J can be operated in flash mode where the internal watchdog is disabled. in addition the spi-interface and low power modes are not available in flash mode. the mode can be entered if the following condition is applied v csn > v flash at exit from flash mode (v csn < v flash ) no nreset pulse is generated and the watchdog starts with a long open window. note: ?high? level for flash mode selection is v csn > v flash . for all other operation modes, standard 5v logic signals are required. 2.2.3 v 1-standby mode the transition from active mode to v 1-standby mode is controlled by spi. to supply the micro controller in a low power mode, the voltage regulator 1 (v 1 ) remains active. in order to reduce the current consumption, the regulator goes in low current mode as soon as the supply current of the microcontroller goes below the i cmp current threshold. at this transition, the L99PM60J also deactivates the internal watchdog. relay outputs and lin transmitter are switched off in v 1-standby mode. high side outputs remain in the configuration programmed prior to the standby command. a cyclic contact supply (for cyclic monitoring of external contacts) can be activated by spi and using the direct drive input (drv). each wake up event sets the device into the active mode and forces the rxd/nint pin to the low level. note: input txd must be at recessive (high) level and csn must be at high level in order to achieve minimum standby current in v 1-standby mode. interrupt the interrupt signal (linked to rxdl/nint internally) indicates a wake-up event from v 1-standby mode. in case of activity on lin or spi access the nint pin is pulled low for t interupt in case of v 1-standby mode and (i v1 > i cmp ), the device remains in standby mode, the v 1 regulator switches to high current mode and the watchdog starts. no interrupt signal is generated. 2.2.4 v bat-standby mode the transition from active mode to v bat-standby mode is initiated by an spi command. in v bat-standby mode, the voltage regulator, relay outputs and lin transmitter are switched off. high side outputs remain in the configuration programmed prior to the standby command. in v bat-standby mode the current consumption of the L99PM60J is reduced to a minimum level. L99PM60J detailed description doc id 18309 rev 6 13/75 note: inputs txdl and csn must be terminated to gnd in v bat-standby to achieve minimum standby current. this can be achieved with the internal esd protection diodes of the microcontroller (microcontroller is not supplied in this mode; v 1 is pulled to gnd). 2.3 wake up from standby modes a wake-up from standby mode switches the device to active mode. this can be initiated by one or more of the following sources: all wake-up events from v 1-standby mode (except i v1 > i cmp ) are indicated to the microcontroller by a low-pulse at rxdl/nint (duration: t interupt ) wake-up from v 1-standby by spi access might be used to check the interrupt service handler. 2.4 cyclic contact supply in v 1-standby mode, any high side driver output (out1..2) can be used to supply external contacts. direct drive feature for high side drivers must be enabled by spi to control the high side driver outputs by drv/vsm/tmp pin. table 3. wake up sources wake up source description lin bus activity always active i v1 > i cmp device remains in v 1-standby mode with watchdog enabled (if i cmp = 0) and v 1 goes into high current mode (increased current consumption). no interrupt is generated. spi access always active (except in v bat-standby mode) wake up event: csn is low and first rising edge on clk detailed description L99PM60J 14/75 doc id 18309 rev 6 2.5 functional overview (truth table) table 4. functional overview (truth table) function comments operating modes active mode v 1-standby static mode (cyclic sense) v bat-standby static mode (cyclic sense) voltage-regulator, v 1 v out =5v on on (1) off reset-generator on on off window watchdog v 1 monitor on off (on: i_v1 > i cmp-threshold and i cmp =0) off direct drive on / off (2) on / off (2) off relay driver on off off lin lin 2.1 on off (3) off (3) fso (if configured by spi), active by default fail safe output out1/fso off (4) out1/fso off (4) out1/fso off (4) oscillator on (5) off v s -monitor on (6) off 1. supply the processor in low current mode. 2. selectable from spi 3. the bus state is internally stored w hen going to standby mode. a change of bus state leads to a wake-up after exceeding of internal filter time 4. on in failsafe condition: if standby mode is entered with active fail safe mode, the output remains on in standby mode. 5. activated when direct drive feature is enabled from spi and drv/vsm/tmp pin is high. 6. on when out1/2 are activated during direct drive L99PM60J detailed description doc id 18309 rev 6 15/75 figure 4. operating modes ? main states 2.6 window ? watchdog during normal operation, the watchdog monitors the micro controller within a t sw trigger cycle in v bat-standby and flash program modes, the watchdog circuit is automatically disabled. after wake-up, the watchdog starts with a long open window. after serving the watchdog, the microcontroller may send the device back to v 1-standby mode after power-on or standby mode, the watchdog is started with a long open window t lw . the long open window allows the micro controller to run its own setup and then to trigger the $ f w l y h 0 r g h 9 2 1 5 h v h w * h q h u d w r u d f w l y h : d w f k g r j d f w l y h 9 6 w d q g e \ 0 r g h 9 2 1 5 h v h w * h q h u d w r u d f w l y h : d w f k g r j 2 ) ) l i , y , f p s r u , & 0 3 9 e d w 6 w d q g e \ 0 r g h 9 2 ) ) 5 h v h w * h q h u d w r u 2 ) ) 1 u h v h w o r z : d w f k g r j 2 ) ) + 6 ' / 6 ' 2 ) ) : d n h x s ( y h q w : d n h x s ( y h q w 6 3 , f r p p d q g 9 e d w v w d u w x s $ o o u h j l v w h u v 6 h w w r g h i d x o w & r o g v w d u w e l w v h w w r ? 9 v ! 9 s r u [ 7 k h u p d o 6 k x w g r z q 7 6 ' 2 5 [ : ' i d l o ) o d v k 0 r g h : d w f k g r j 2 ) ) 9 & 6 1 ! 9 i o d v k 9 & 6 1 ! 9 i o d v k 9 & 6 1 9 i o d v k 9 & 6 1 ! 9 i o d v k 6 3 , f r p p d q g 2 5 [ 7 k h u p d o 6 k x w g r z q 7 6 ' 2 5 9 i d l o 9 9 i r u p v d i w h u v z l w f k 2 1 2 5 [ : ' ) d l o x u h $ * 9 detailed description L99PM60J 16/75 doc id 18309 rev 6 watchdog via the spi. the trigger is finally accepted when the csn input becomes high after the transmission of the spi word. writing ?1? to the watchdog trigger bit terminates the long open window and start the window watchdog subsequently, the micro controller has to serve the watchdog by alternating the watchdog trigger bit within the safe trigger area (refer to watchdog chapter). a correct watchdog trigger signal immediately starts the next cycle. after 8 watchdog failures in sequence, the v 1 regulator is switched off for t v1off if subsequently, 7 additional watchdog failures occur, the v 1 regulator is completely turned off and the device goes into v bat-standby mode until a walk-up occurs. in case of a watchdog failure, the outputs (relx, outx) are switched off and the device enters fail safe mode (i. e. all control registers are set to default values, except out1 when not used as fso.) the following diagrams illustrate the watchdog behavior of the L99PM60J. the diagrams are split into 3 parts. first diagram shows the functional behavior of the watchdog without any error. the second diagram covers the behavior covering all the error conditions, which can affect the watchdog behavior. third diagram shows the transition in and out of flash mode. all three diagrams can be overlapped to get all the possible state transitions under all circumstances. for a better readability, those transitions have been split in normal operating, operating with errors and flash mode. figure 5. watchdog in normal operating mode (no errors) : ' 2 ) ) o r q j r s h q z l q g r z : l q g r z 0 r g h s u r s s h u w u l j j h u l q : l q g r z p r g h 7 5 , * ? j r 6 w d q g e \ 9 6 w e \ $ 1 ' , 9 , & 0 3 9 6 w e \ $ 1 ' , 9 ! , & 0 3 9 % $ 7 6 w d q g e \ 9 6 w d q g e \ $ f w l y h p r g h $ f w l y h p r g h $ * 9 : d n h x s $ 1 ' 9 ! 9 u v w w k u 9 ! 9 u v w w k u j r 6 w d q g e \ L99PM60J detailed description doc id 18309 rev 6 17/75 figure 6. watchdog with error conditions figure 7. watchdog in flash mode : ' 2 ) ) o r q j r s h q z l q g r z : l q g r z 0 r g h s u r s s h u w u l j j h u l q : l q g r z p r g h 7 5 , * ? : ' i d l o 7 6 ' : ' i d l o 7 6 ' i r u f h g 9 % $ 7 9 9 u w k 9 9 u w k 9 ! 9 u w k 9 % $ 7 6 w d q g e \ 9 6 w d q g e \ , 9 , & 0 3 : d w f k g r j i d l o f r x q w h u l q f u h p h q w h g e \ h d f k : ' i d l o h y h q w 5 h v h w w r ] h u r e \ h d f k s u r s h u w u l j j h u i r u f h g 9 % $ 7 [ : ' i d l o [ 7 6 ' 6 k r u w 9 $ f w l y h p r g h $ f w l y h p r g h $ * 9 : ' 2 ) ) o r q j r s h q z l q g r z : l q g r z 0 r g h ) / $ 6 + p r g h ) / $ 6 + p r g h ( [ l w ) / $ 6 + p r g h ) / $ 6 + p r g h $ f w l y h p r g h $ f w l y h p r g h $ * 9 detailed description L99PM60J 18/75 doc id 18309 rev 6 2.7 fail safe mode 2.7.1 temporary failures L99PM60J enters fail safe mode in case of: watchdog failure v 1 turn on failure ?v 1 short (v 1 < v 1fail for t > t v1short ) v 1 undervoltage (v 1 < v rth for t > t uv1 ) ? fail safe mode only entered if v s > v suv thermal shutdown tsd2 spi failure ? di stuck to gnd or v cc (spi frame = ?00 00? or ?ff ff?) the fail safe functionality is also available in v 1-standby mode. during v 1-standby mode the fails safe mode is entered in the following cases: v 1 undervoltage (v 1 < v rth for t > t v1fs ) ? fail safe mode only entered if v s > v suv watchdog failure (if watchdog still running due to i v1 > i cmp ) thermal shutdown tsd2 in fail safe mode the L99PM60J returns to a default state with all outputs turned off. the fail safe condition is indicated to the remaining system. the conditions during fails safe mode are: all outputs are turned off all control registers are set to default values (except out1/fso configuration). write operations to control registers are blocked until the fail safe condition is cleared lin transmitter and spi remains on corresponding failure bits in status registers are set. fso bit (bit 0 global status register) is set out1/fso is activated if configured as fail safe output out1 is configured as fail safe output unless it is disabled by spi. if the fail safe mode was entered it keeps active until the fail safe condition is removed and the fail safe was read by spi. depending on the root cause of the fail safe, the actions to quit fail safe mode can be different. L99PM60J detailed description doc id 18309 rev 6 19/75 2.7.2 nonrecoverable failures ? entering forced v bat-standby mode if the failsafe condition persists and all attempts to return to normal system operation fail, the L99PM60J enters the forced vbatstby mode in order to prevent damage to the system. the forced vbatstby mode can be terminated by any regular wake-up event. the root cause of the forced vbatstby is indicated in the spi status registers the forced vbatstby mode is entered in case of: multiple watchdog failures: forced sleep wd = 1 (15x watchdog failure) multiple thermal shutdown 2: forced sleep tsd2/shtv1 = 1 (7x tsd2) v 1 short at turn-on: forced sleep tsd2/shtv1 = 1 (v 1 < v 1fail for t > t v1short ) table 5. fail safe conditions and exit modes failure source failure condition diagnosis exit from fail safe mode c (oscillator) watchdog, early write failure or expired window failsafe = 1; wdfail=n+1 propper trigger in window mode and read fail safe bit v 1 short at turn-on failsafe = 1; forced sleep tsd2/shtv1 = 1 read&clear sr3 after wake v 1 detailed description L99PM60J 20/75 doc id 18309 rev 6 figure 8. recovery after forced vbat due to multiple watchdog failure figure 9. recovery after forced vbat due to multiple tsd2 failure * $ 3 * & ) 7 9 1 5 h v h w ) d l o v d i h 0 r g h 3 r z h u 0 r g h p v l q d f w l y h / 2 : l : d w f k g r j 0 r g h : l q g r z ) 6 2 2 x w s x w 2 i i 6 3 , & 6 : d n h x s h y h q w p v w ) 6 2 ) 6 2 ) 6 2 7 5 , * 7 5 , * w w : l q g r z 5 x q : l q g r z [ > p v @ ) 6 2 ) r u f h g 6 o h h s : ' e l w l v o d w f k h g d q g p x v w e h f o h d u h g w r w h u p l q d w h ) d l o v d i h 0 r g h d q g s h u p l w : u l w h w r f r q w u r o u h j l v w h u v ) r u f h g 9 e d w v w e \ $ f w l y h 5 h d g & o h d u 6 5 7 5 , * 7 5 , * b b b b 9 1 5 h v h w ) d l o v d i h 0 r g h 3 r z h u 0 r g h p v l q d f w l y h 6 3 , & 6 : d n h x s h y h q w w ) 6 2 ) 6 2 w w 5 x q ) 6 2 ) r u f h g 9 e d w v w e \ $ f w l y h 5 h d g & o h d u 6 5 ) 6 2 2 x w s x w 5 h d g & o h d u 6 5 ) r u f h g 6 o h h s 7 6 ' 6 + 7 9 e l w l v o d w f k h g d q g p x v w e h f o h d u h g w r w h u p l q d w h ) d l o v d i h 0 r g h d q g s h u p l w : u l w h w r f r q w u r o u h j l v w h u v * $ 3 * & ) 7 L99PM60J detailed description doc id 18309 rev 6 21/75 figure 10. recovery after forced vbat due to short at v 1 failure 2.7.3 fail safe output (out1) the device provides a high side output (out1) which can be used as failsafe output. the default configuration after power on for out1 is failsafe output. the failsafe output is protected against overvoltage and undervoltage (undervoltage can be masked by spi for out1). see control register 2 . overcurrent in case of overcurrent condition, fso switches off. the according status bit is latched and can be read and optionally cleared by spi. the drivers remain off until the status is cleared. in case overvoltage or undervoltage condition, fso is switched off. the according status bit is latched and can be read and optionally cleared by spi. the drivers remain off until the status is cleared. with the out uv shutdown enable bit (control register 2) the fso can be excluded from a switch off in case of vs undervoltage. if the bit is set to ?1? the driver switches off, otherwise the drivers remain on. in case of open-load condition, the according status register is latched. the status can be read and optionally cleared by spi. the fso is not switch off. note: the maximum voltage and current applied to the high side outputs is specified in chapter 4 ?absolute maximum ratings?. appropriate external protection may be required in order to respect these limits under application conditions. 9 1 5 h v h w ) d l o v d i h 0 r g h 3 r z h u 0 r g h p v l q d f w l y h 6 3 , & 6 : d n h x s h y h q w w ) 6 2 w w 5 x q ) 6 2 ) r u f h g 9 e d w v w e \ $ f w l y h 5 h d g & o h d u 6 5 ) 6 2 2 x w s x w ) r u f h g 6 o h h s 7 6 ' 6 + 7 9 e l w l v o d w f k h g d q g p x v w e h f o h d u h g w r w h u p l q d w h ) d l o v d i h 0 r g h d q g s h u p l w : u l w h w r f r q w u r o u h j l v w h u v * $ 3 * & ) 7 detailed description L99PM60J 22/75 doc id 18309 rev 6 2.8 reset output (nreset) if v 1 is turned on and the voltage exceeds the v 1 reset threshold, the reset output ?nreset? is pulled up by internal pull up resistor to v 1 voltage after a reset delay time t reset . this is necessary for a defined start of the micro controller when the application is switched on. since the nreset output is realized as an open drain output it is also possible to connect an external nreset open drain nreset source to the output. it must be considered that as soon the nreset is released from the L99PM60J the watchdog timing starts. a reset pulse t reset is generated in case of: v 1 drops below v rth (configurable by spi) for more than v 1uft watchdog failure 2.9 lin bus interface general features: speed communication up to 20kbit/s. lin 2.1 compliant (sae j2602 compatible) transceiver. function range from +40v to -18v dc at lin pin. gnd disconnection fail safe at module level. off mode: does not disturb network. gnd shift operation at system level. micro controller interface with cmos compatible i/o pins. esd and transient immunity according to iso7637 and en / iec61000-4-2 matched output slopes and propagation delay in order to further reduce the current consumption in standby mode, the integrated lin bus interface offers an ultra low current consumption. 2.9.1 error handling the L99PM60J provides the following 3 error handling features which are not described in the lin spec. revision 2.1, but are realized in different stand alone lin transceivers / micro controllers to switch the application back to normal operation mode. at vs > vpor (i.e. vs power-on reset threshold), the lin transceiver is enabled. the lin transmitter is disabled in case of the following errors: dominant txdl time out lin permanent recessive thermal shutdown 1 v s overvoltage / v s undervoltage the lin receiver is not disabled in case of any failure condition. dominant txd time out if txd is in dominant state (low) for more than t dom(txdl) (typ) the transmitter is disabled. the status bit is latched and can be read and optionally cleared by spi. the transmitter remains disabled until the status register is cleared. this feature can be disabled via spi. L99PM60J detailed description doc id 18309 rev 6 23/75 permanent recessive if txd changes to dominant (low) state but rxd signal does not follow within t lin , the transmitter is disabled. the status bit is latched and can be read and optionally cleared by spi. the transmitter remains disabled until the status register is cleared. permanent dominant if the bus state is dominant (low) for more than t dom(txdl) (typ.) a permanent dominant status is detected. the status bit is latched and can be read and optionally cleared by spi. the transmitter is not switched off 2.9.2 wake up (from lin) in standby mode the L99PM60J can receive a wake up from lin bus. for the wake up feature the L99PM60J logic differentiates two different conditions. normal wake up normal wake up can occur when the lin transceiver was set in standby mode while lin was in recessive (high) state. a dominant level at lin for t > t linbus , switches the L99PM60J to active mode. a interrupt is generated at the rxd/nint pin. wake up from short to gnd condition if the lin transceiver was set in standby mode while lin was in dominant (low) state, recessive level at lin for t linbus , switches the L99PM60J to active mode. an interrupt is generated at the rxd/nint pin. note: a wake up caused by a message on the bus starts the voltage regulator and the microcontroller to switch the application back to normal operation mode. 2.10 serial peripheral interface (st spi standard) a 16 bit spi is used for bi-directional communication with the micro controller. during active mode, the spi triggers the watchdog controls the modes and status of all L99PM60J modules (incl. input and output drivers) provides driver output diagnostic provide L99PM60J diagnostic (incl. overtemperature warning, L99PM60J operation status) the spi can be driven by a micro controller with its spi peripheral running in following mode: cpol = 0 and cpha = 0. for this mode input data is sampled by the low to high transition of the clock clk, and output data is changed from the high to low transition of clk. this device is not limited to micro controller with a built-in spi. only three cmos-compatible output pins and one input pin are needed to communicate with the device. a fault condition can be detected by setting csn to low. if csn = 0, the do-pin reflects the global error flag (fault condition) of the device. detailed description L99PM60J 24/75 doc id 18309 rev 6 chip select not (csn) the input pin is used to select the serial interface of this device. when csn is high, the output pin (do) is in high impedance state. a low signal activates the output driver and a serial communication can be started. the state during csn = 0 is called a communication frame. serial data in (di) the input pin is used to transfer data serial into the device. the data applied to the di is sampled at the rising edge of the clk signal and shifted into an internal 16 bit shift register. at the rising edge of the csn signal the contents of the shift register is transferred to data input register. the writing to the selected data input register is only enabled if exactly 16 bits are transmitted within one communication frame (i.e. csn low). if more or less clock pulses are counted within one frame the complete frame is ignored. this safety function is implemented to avoid an activation of the output stages by a wrong communication frame. note: due to this safety functionality a daisy chaining of spi is not possible. instead, a parallel operation of the spi bus by controlling the csn signal of the connected ic's is recommended. serial data out (do) the data output driver is activated by a logical low level at the csn input and goes from high impedance to a low or high level depending on the global error flag (fault condition). the first rising edge of the clk input after a high to low transition of the csn pin transfers the content of the selected status register into the data out shift register. each subsequent falling edge of the clk shifts the next bit out. serial clock (clk) the clk input is used to synchronize the input and output serial bit streams. the data input (di) is sampled at the rising edge of the clk and the data output (do) changes with the falling edge of the clk signal. the spi can be driven with a clk frequency up to f clk . L99PM60J protection and diagnosis doc id 18309 rev 6 25/75 3 protection and diagnosis 3.1 high side driver outputs the device provides a total of 2 high side outputs out1,2, (7 typ. at @ 25c) to drive e.g. led's or hall sensors the high side outputs are protected against overvoltage and undervoltage (undervoltage can be masked by spi for out1). see section : control register 2 overcurrent overtemperature (a) in case of overcurrent or overtemperature (tsd1) condition, the drivers switches off. the according status bit is latched and can be read and optionally cleared by spi. the drivers remain off until the status is cleared. in case overvoltage/undervoltage condition, the drivers is switched off. the according status bit is latched and can be read and optionally cleared by spi. the drivers remain off until the status is cleared. the driver can be excluded from undervoltage shutdown. with the out uv shutdown enable bit (control register 2) the drivers can be excluded from a switch off in case of vs undervoltage. if the bit is set to ?1? the driver switches off, otherwise the drivers remain on. in case of open-load condition, the according status register is latched. the status can be read and optionally cleared by spi. the high sides is not switch off. in case of a fail safe condition, the high side drivers are switched off. the control bits are set to default values. (except out1/fso if it is used as a high-side output) note: the maximum voltage and current applied to the high side outputs is specified in chapter 4 ?absolute maximum ratings?. appropriate external protection may be required in order to respect these limits under application conditions. 3.1.1 out1 reprogramming to change the setting for out1 from fso (default) to normal output configuration (on/off or direct drive) a spi safety sequence is required. first write command with a specific pattern to conf register needs to be provided in order to enable the write access for configuration bits of out1. with an spi write command to control register 1 the bits for out1 can be modified. the write command to control register 1 must follow the write command to the conf register (no other spi command in between these 2 commands) safety sequence: 1. write to conf register (0x0011 1111; 1010 101x) x: don?t care for unlocking sequence but according to description of watchdog timing 2. write to ctrl register 1 (0x0000 0001; xxxx xxxx) x: values according to description of ctrl reg1 a. except out1 when configured as fso protection and diagnosis L99PM60J 26/75 doc id 18309 rev 6 3.2 low side driver outputs rel1, rel2 the outputs rel1, rel2 (r dson = 2 typ. at 25 c) are specially designed to drive relay loads. typical relays used have the following characteristics: relay type 1: on-state: r = 160 typical + 10%, l = 300 mh: off-state: 240 mh relay type 2: on-state: r = 220 typical + 10 %, l = 420 mh: off-state: 330 mh the outputs provide an active output zener clamping (44 v typ) feature for the demagnetisation of the relay coil, even though a load dump condition exists. the low side drivers switch off in case of: v s overvoltage and undervoltage (can be masked by spi) control register 2, bit0 overcurrent overtemperature in case of overload or overtemperature (tsd1) condition, the drivers switches off. the according status bit is latched and can be read and optionally cleared by spi. the drivers remain off until the status is cleared. in case v s overvoltage and undervoltage condition, the drivers is switched off. the according status bit is latched and can be read and optionally cleared by spi. the drivers remain off until the status is cleared. with the ls ovuv shutdown enable bit (control register 2) the drivers can be excluded from a switch off in case of overvoltage and undervoltage. if the bit is set to ?1? the driver switches off, otherwise the drivers remain on. 3.3 spi diagnosis digital diagnosis features are provided by spi (for details please refer to section 7.2: spi registers ) v 1 reset threshold programmable overtemperature including pre warning open-load separately for each out1,2 overload status separately for each output stage v s-supply overvoltage/undervoltage v 1-fail bit v 1 undervoltage chip reset bit (start from power-on reset) number of unsuccessful v 1 restarts after thermal shutdown number of sequential watchdog failures lin diagnosis (permanent recessive/dominant, dominant txd) device state (wake-up from v1stby or vbatstby) forced vbatstby after wd-fail, forced vbatstby after overtemperature watchdog timer state (diagnosis of watchdog) failsafe status spi communication error L99PM60J power supply fail doc id 18309 rev 6 27/75 4 power supply fail overvoltage and undervoltage detection on v s 4.1 v s overvoltage if the supply voltage vs reaches the overvoltage threshold (v sov ) the outputs out1,2, rel1,2 and lin are switched to high impedance state (load protection). the overvoltage bit is set and can be cleared with a ?read and clear? command. outputs rel1,2 can be excluded from a shutdown in case of overvoltage by spi 4.2 v s undervoltage if the supply voltage vs drops below the undervoltage threshold voltage (v suv ) the outputs out1,2, rel1,2, lin are switched to high impedance state. the undervoltage bit is set and can be cleared with the ?read and clear? command. outputs rel1,2 can be excluded from a shutdown in case of undervoltage by spi output out1,2 can be excluded from a shutdown in case of undervoltage by spi power supply fail L99PM60J 28/75 doc id 18309 rev 6 4.3 temperature warning and thermal shutdown figure 11. thermal shutdown protection and diagnosis note: with the first transition into the tsd2 state failsafe mode is entered. the thermal state machine recovers the same state were it was before entering standby mode. in case of a tsd2 it enters tsd1 state. $ f w l y h 0 r g h 6 w d q g e \ 0 r g h v g x u l q j f \ f o l f v h q v h 7 h p s h u d w x u h : d u q l q j ' l d j q r v l v 7 : 7 6 ' $ o o r x w s x w v h [ f h s w 9 r i i ' l d j q r v l v 7 6 ' 7 m ! 7 6 ' ? 5 h d g d q g & o h d u ? 2 5 3 r z h u r q u h v h w 7 6 ' $ o o r x w s x w v r i i 9 r i i i r u v h f ' l d j q r v l v 7 6 ' 7 m ! 7 6 ' 9 e d w v w e \ $ o o r x w s x w v l q f o 9 r i i [ 7 6 ' 3 r z h u r q u h v h w 6 3 , f r p p d q g ? 5 h d g d q g & o h d u ? 2 5 3 r z h u r q u h v h w 7 ! v h f 3 r z h u 2 q 5 h v h w $ o o r x w s x w v l q f o 9 r i i 9 v ! 9 : d n h x s h y h q w $ * 9 L99PM60J typical application doc id 18309 rev 6 29/75 5 typical application figure 12. typical application diagram ' , 9 5 ( * 9 p $ + l j k 6 l g h 6 3 , / 2 * , & : l q g r z : d w f k g r j 9 v & 6 1 & / . ' 2 2 x w 2 x w ) 6 2 + l j k 6 l g h 2 k p 9 5 ( * 0 r q l w r u 9 6 0 r q l w r u l q j 7 h p s 0 r q l w r u l q j 9 / , 1 / , 1 5 [ ' 1 , 1 7 7 [ ' 1 5 ( 6 * 1 ' 6 7 0 $ ) n ) / $ 6 + . 5 $ 0 & \ f o l f & r q w d f w 0 r q l w r u l q j + d o o & r q w d f w 6 x s s o \ 5 ( / 5 ( / 0 9 6 9 % $ 7 $ - $ 5 f \ f o l f u h d g r x w ( [ s u h v v 8 s 8 s ' r z q w r ? & , 2 $ ' & n r k p n r k p n r k p n r k p w r ? & , 2 q ) w r ? & , 2 5 3 x o o 8 s ' l u h f w ' u l y h ' 5 9 9 6 0 7 0 3 , 2 & x u u h q w w r e h o l p l w h g e h o r z d s s u p $ & x u u h q w w r e h o l p l w h g e h o r z d s s u p $ 2 k p / r z 6 l g h 2 x w s x w & o d p s 2 k p / r z 6 l g h 2 x w s x w & o d p s 2 k p 8 q g h u y r o w d j h 2 y h u y r o w d j h 6 k x w g r z q 7 h p s 3 u h z d u q l q j 6 k x w g r z q 5 3 x o o 8 s $ * 9 electrical specifications L99PM60J 30/75 doc id 18309 rev 6 6 electrical specifications 6.1 absolute maximum ratings note: all maximum ratings are absolute ratings. leaving the limitation of any of these values may cause an irreversible damage of the integrated circuit! loss of ground or ground shift with externally grounded loads: esd structures are configured for nominal currents only. if external loads are connected to different grounds, the current load must be limited to this nominal current. 6.2 esd protection table 7. absolute maximum rating symbol parameter / test condition value [dc voltage] unit v s dc supply voltage / ?jump start? -0.3 to +28 v load dump -0.3 to +40 v v 1 stabilized supply voltage, logic supply -0.3 to +5.25 v v di v clk v txd v do v rxd v nreset v drv logic input / output voltage range -0.3 to v 1 +0.3 v v csn multi level input -0.3 to vs + 0.3 v v rel1 v rel2, low-side output voltage range -0.3 to +40 v v out1..2, high-side output voltage range -0.3 to v s +0.3 v i in_put current injection into v s related input pins 10 ma iout_inj current injection into v s related outputs 10 ma v lin lin bus i/o voltage range -20 to +40 v table 8. esd protection parameter value unit all pins (1) +/-2 kv all output pins (2) +/-4 kv lin +/-8 (2) +/-10 (3) +/-7 (4) kv all pins (5) +/-500 v L99PM60J electrical specifications doc id 18309 rev 6 31/75 6.3 thermal data corner pins (5) +/-750 v all pins (6) +/-200 v 1. hbm (human body model, 100pf, 1.5 k ) according to mil 883c, method 3015.7 or eia/jesd22a114-a 2. hbm with all none zapped pins grounded. 3. indirect esd test according to iec 61000-4-2 (150 pf, 330 ) and ?hardware requirements for lin and flexray interfaces in automotive applications? (version 1.1, 2009-12-02) 4. direct esd test according to iec 61000-4-2 (150 pf, 330 ) and ?hardware requirements for lin and flexray interfaces in automotive a pplications? (version 1.1, 2009-12-02); c bus,lin = 220 pf 5. charged device model 6. machine model: c = 200 pf; r = 0 table 8. esd protection (continued) parameter value unit table 9. operating junction temperature symbol parameter value unit t j operating junction temperature -40 to 150 c r thja thermal resistance junction / ambient see figure 26 k/w table 10. temperature warning and thermal shutdown symbol parameter min. typ. max. unit t w on thermal overtemperature warning threshold t j (1) 1. non-overlapping 120 130 140 c t sd1 off thermal shutdown junction temperature 1 t j (1) 130 140 150 c t sd2off thermal shutdown junction temperature 2 t j (1) 150 160 170 c t sd2 on hysteresis 5 c t sd12hys electrical specifications L99PM60J 32/75 doc id 18309 rev 6 6.4 electrical characteristics 6.4.1 supply and supply monitoring the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6v< v s < 18v; 4.8 v < v 1 < 5.2 v; all outputs open; t j = -40 c to 130 c, unless otherwise specified. 6.4.2 oscillator the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 4.5 v < v s < 28 v; all outputs open; t j = -40 c to 130 c, unless otherwise specified. table 11. supply and supply monitoring symbol parameter test condition min. typ. max. unit v sabsmin (1) 1. for v s > v sabsmin the v 1 and nreset output are actively driven. v s < v sabsmin the v 1 output is connected to ground by passive pull down resistor of 1m . v s absolute minimum value for controlling v 1 and nreset outputs v s increasing / decreasing ? 2.5 ? v v s supply voltage range 6 13.5 18 v v suv vs uv-threshold voltage v s increasing / decreasing 5.11 5.81 v v hyst_uv undervoltage hysteresis 0.04 0.1 0.15 v v sov vs ov-threshold voltage v s increasing / decreasing 18 22 v v hyst_ov overvoltage hysteresis hysteresis 0.5 1 1.5 v i v(act) current consumption in active mode v s = 12 v; txd lin high; v 1 =5v; hs/ls drivers off; v lin >(v s -1.5v) 612ma i v(bat) current consumption in v bat- standby mode v s =12v; v 1 = off; v lin >(v s -1.5v) 1716a i v(v1) current consumption in v 1-standby mode v s =12v; v 1 =5v; hs/ls drivers off; v lin >(v s -1.5v); i v1 (v s -1.5v); i v1 L99PM60J electrical specifications doc id 18309 rev 6 33/75 6.4.3 power-on reset (v s ) all outputs open; t j = -40 c to 130 c, unless otherwise specified. 6.4.4 voltage regulator v 1 the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 v v s 28 v; t j = -40 c to 130 c, unless otherwise specified. table 12. oscillator symbol parameter test condition min. typ. max. unit f clk oscillation frequency 0.808 1.0 1.35 mhz table 13. power-on reset (v s ) symbol parameter test condition min. typ. max. unit v por v por threshold (v s increasing) 3.45 4.5 v v por v por threshold (v s decreasing) (1) 1. this threshold is valid if vs had already reac hed 7v previously 2.2 2.6 3.5 v table 14. voltage regulator v 1 symbol parameter test condition min. typ. max. unit v 1 output voltage 5.0 v v 1 output voltage tolerance active mode i load = 6 ma... 50 ma, v s = 13.5 v +/-2 % vhc1 output voltage tolerance active mode, high current i load = 50 ma... 100 ma, v s = 13.5 v +/-2.5 % vstb1 output voltage tolerance v 1-standby mode i load = 0ua...5ma v s = 13.5v -2 +4.5 % vdp1 drop-out voltage i load = 50 ma; v s = 4.5 v 0.2 0.4 v i load = 100 ma; v = 4.5 v 0.3 0.5 v icc1 output current in active mode max. continuous load current 100 ma iccmax1 short circuit output current current limitation 400 600 950 ma cload1 load capacitor1 ceramic 0.22 f ttsd v 1 deactivation time after thermal shutdown 1s i cmp_rise current comp. rising threshold rising current 2.1 4.6 6.8 ma i cmp_fail current comp. falling threshold falling current 1.5 3.6 6.0 ma electrical specifications L99PM60J 34/75 doc id 18309 rev 6 note: nominal capacitor value required for stability of the regulator. tested with 220nf ceramic (+/- 20%). capacitor must be located close to the regulator output pin. 6.4.5 reset output (v 1 supervision) the voltages are referred to gnd and currents are assumed positive, when the current flows into the pin. 4.0 v < v s =28v; t j = -40 to 130 c, unless otherwise specified. 6.4.6 watchdog 4.5 v < v s <28v; 4.8v L99PM60J electrical specifications doc id 18309 rev 6 35/75 figure 13. watchdog timing (missing watchdog trigger) figure 14. watchdog early, late and safe windows 6.4.7 high-side outputs outputs (out1?2); the voltages are referred to gnd and currents are assumed positive, when the current flows into the pin. 6v< v s < 18 v; 4.8 v < v 1 < 5.2 v; t j = -40 c to 130 c, unless otherwise specified. t wdr watchdog reset pulse time 1.5 2 2.5 ms t v1off v 1 deactivation duration after 8 consecutive wd failures 150 200 250 ms table 16. watchdog (continued) symbol parameter test condition min. typ. max. unit w / : w / : w / : w / : w / : w / : w / : w / : w / : w / : w / : w / : w / : w / : w / : w 9 r i i 9 1 5 ( 6 ( 7 w w $ * 9 h d u o \ z d w f k g r j i d l o x u h x q g h i l q h g v d i h w u l j j h u d u h d x q g h i l q h g o d w h z d w f k g r j i d l o x u h 7 ( ) : q b p d [ 7 6 : q b p l q 7 6 : q b p d [ 7 / ) : q b p l q w l p h 7 6 : q 6 d i h z l q g r z 7 ( ) : q ( d u o \ ) d l o x u h z l q g r z 7 / ) : q / d w h i d l o x u h z l q g r z $ * 9 electrical specifications L99PM60J 36/75 doc id 18309 rev 6 6.4.8 low-side drivers outputs (rel1?2); the voltages are referred to gnd and currents are assumed positive, when the current flows into the pin. 6v v s 18 v; 4.8 v v 1 5.2 v; t j = -40 to 130 c, unless otherwise specified. 6.4.9 direct drive / voltage supply monitoring input: drv the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. table 17. output symbol parameter test condition min. typ. max. unit rdson dc output resistance i load = 60 ma at t j =25c 0712 iout short circuit shutdown current 8 v < v s < 16 v 140 235 330 ma t scf short circuit filter time tested by scan chain 64 * t osc iold open-load detection current 1 0.5 2 4.2 ma t oldt open-load filter time tested by scan chain 64 * t osc sr slew rate 0.2 0.5 0.8 v/s t donhs switch on delay time 0.2 v s 53560s t doffhs switch off delay time 0.8 v s 20 95 150 s t scf short circuit filter time tested by scan chain 64 * t osc i fw (1) 1. parameter guaranteed by design loss of gnd current (esd structure) 100 ma table 18. relay drivers symbol parameter test condition min. typ. max. unit r dson dc output resistance i load =100ma @ t j =25c 0 2 3 i out short circuit shut down current 8 v < v s < 16 v 250 375 500 ma v z output clamp voltage (1) i load = 100 ma 40 44 48 v t onhl turn on delay time to 10% v out 2.5 50 100 s t offlh turn off delay time to 90% v out 550100s t scf short circuit filter time tested by scan chain 64 * t osc sr slew rate 0.2 2 4 v/s 1. the output is capable to switch off relay coils with the impedance of r l = 160 ; l = 300 mh (r l = 220 ; l = 420 mh); at v s = 40 v (load dump condition). L99PM60J electrical specifications doc id 18309 rev 6 37/75 6v v s 18 v; 4.8 v v 1 5.2 v; all outputs open; t j = -40 c to 130 c, unless otherwise specified. output: vsout the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6v v s 18 v; 4.8 v v 1 5.2 v; all outputs open; t j = -40 c to 130 c, unless otherwise specified. 6.4.10 lin lin 2.1 compliant for baud rates up to 20 kbit/s (sae j2602 compatible) baud rate of the lin bus can be upgraded up to 100 kbits by spi bit configuration (lin flash bit 3 cr2). the voltages are referred to gnd and currents are assumed positive, when the current flows into the pin. 6v < v s < 18 v; 4.8 v < v 1 < 5.2 v; t junction = -40 c to 130 c unless otherwise specified. table 19. input: drv symbol parameter test condition min. typ. max. unit vdrvlow input voltage low level normal mode, v 1 = 5 v 1.0 2.3 2.9 v vdrvhigh input voltage high level normal mode, v 1 = 5 v 1.5 2.8 3.8 v vdrvhys vcsnhigh ? vcsnlow normal mode, v 1 = 5 v 0.4 0.75 1.5 v idrvpd pull down current at input normal mode, v in =1.5v 5 30 60 a c in (1) 1. value of input capacity is not measured in production test. parameter guaranteed by design. input capacitance 0 v < v 1 <5.2v 25 35 pf table 20. output: vsout symbol parameter test condition min. typ. max. unit vsout output voltage v s =6v; v s = 10 v; v s =18v 0.195 v s 0.2 v s 0.205 v s v vsoutuv v s output voltage in case of undervoltage v s = 4.5 v; vsm selected 0.0 v vsoutov v s output voltage in case of overvoltage v s = 24 v; vsm selected 5.0 v vtroom t sense output voltage at 25 c v s = 12 v; t = 25 c 1.38 v vtsense t sense output voltage t = 25 c; t= 130 c; t=-40c 3.5 mv/k i vsout pull-up pull-down current ability 2 ma electrical specifications L99PM60J 38/75 doc id 18309 rev 6 table 21. lin transmit data input: pin txd symbol parameter test condition min. typ. max. unit v txdow input voltage dominant level normal mode; v 1 =5v 0.8 1.9 v v txdhigh input voltage recessive level normal mode; v 1 =5v 2.9 3.5 v v txdhys v txdhigh ? v txdow normal mode; v 1 = 5 v 0.5 1.0 1.5 v i txdpu txd pull up resistor normal mode; v 1 =5v 20 k i txdpd txd pull-down current test mode; v in =10v 480 a table 22. lin receive data output: pin rxd symbol parameter test condition min. typ. max. unit v rxdow output voltage dominant level normal mode; v 1 = 5 v; 2 ma 0.2 0.5 v v rxdhigh output voltage recessive level normal mode; v 1 =5v; 2ma 4.5 v table 23. lin transmitter and receiver: pin lin symbol parameter test condition min. typ. max. unit v thdom receiver threshold voltage recessive to dominant state 0.4 v s 0.45 v s 0.5 v s v v busdom receiver dominant state 0.4 v s v v threc receiver threshold voltage dominant to recessive state 0.5 v s 0.55 v s 0.6 v s v v busrec receiver recessive state 0.6 v s v v thhys receiver threshold hysteresis v threc ? v thdom 0.07 v s 0.1 v s 0.175 v s v v thcnt receiver tolerance center value (v threc + v thdom )/2 0.475 v s 0.5 v s 0.525 v s v v thwkup receiver walk-up threshold voltage 1.0 1.5 2 v v thwkdwn receiver walk-up threshold voltage v s - 3.5 v s -2.5 v s -1.5 v t linbus dominant time for walk-up via bus sleep mode edge: recessive- dominant 64 * t osc s i lindomsc transmitter input current limit in dominant state v txd = v txdlow ; v lin =v batmax =18v 40 100 180 ma i bus_pas_dom input leakage current at the receiver incl. pull-up resistor v txd = v txdhigh ; v lin =0v; v bat =12v (1) -1 ma i bus_pas_rec transmitter input current in recessive state v txd = v txdhigh ; 8 v < v lin <18v; 8v L99PM60J electrical specifications doc id 18309 rev 6 39/75 i bus_no_gnd input current if loss of gnd at device gnd = v s ; 0 v < v lin <18v; v bat =12v -1 1 ma i bus input current if loss of v bat at device gnd = v s ; 0 v < v lin <18v 100 a v lindom lin voltage level in dominant state v txd = v txdlow ; i lin = 40 ma 1.2 v v linrec lin voltage level in recessive state v txd = v txdhigh ; i lin = 10 a 0.8 vs v r linup lin output pull up resistor v lin =0v 20 40 60 k 1. slave mode table 23. lin transmitter and receiver: pin lin (continued) symbol parameter test condition min. typ. max. unit table 24. lin transceiver timing symbol parameter test condition min. typ. max. unit t rxpd receiver propagation delay time t rxpd =max(t rxpdr , t rxpdf ); t rxpdf = t(0.5 rxd) - t(0.45 v lin ); t rxpdr = t(0.5 rxd) - t(0.55 v lin ); c rxd =20pf; v s =12v; r bus =1k , c bus =1nf; r bus =660k , c bus =6.8nf; r bus =500k , c bus =10nf 6s t rxpd_sym symmetry of receiver propagation delay time (rising vs. falling edge) t rxpd_sym = t rxpdr ? t rxpdf -2 2 s d1 duty cycle 1 th rec (max) = 0.744 * v s ; th dom (max) = 0.581 * v s ; v s =7?18v; t bit =50s; d1 = t bus_rec (min)/(2 x t bit ) r bus =1k , c bus =1nf; r bus =660k , c bus =6.8nf; r bus =500k , c bus =10nf 0.396 d2 duty cycle 2 th rec (min) = 0.422 * v s ; th dom (min) = 0.284 * v s ; v s = 7.6 ?18 v; t bit =50s; d1 = t bus_rec (max)/(2 x t bit ) r bus =1k , c bus =1nf; r bus =660k , c bus =6.8nf; r bus =500k , c bus =10nf 0.581 d3 duty cycle 3 th rec (max) = 0.778 * v s ; th dom (max) = 0.616 * v s ; v s =7?18v; t bit =96s; d3 = t bus_rec (min)/(2 x t bit ) r bus =1k , c bus =1nf; r bus =660k , c bus =6.8nf; r bus =500k , c bus =10nf 0.417 electrical specifications L99PM60J 40/75 doc id 18309 rev 6 figure 15. lin transmit, receive timing 6.4.11 spi input: csn the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6v v s 18 v; 4.8 v v 1 5.2 v; all outputs open; t j = -40 c to 130 c, unless otherwise specified. d4 duty cycle 4 th rec (min) = 0.389 * v s ; th dom (min) = 0.251 * v s ; v s =7.6?18v; t bit =96s; d1 = t bus_rec (max)/(2 x t bit ) r bus =1k , c bus =1nf; r bus =660k , c bus =6.8nf; r bus =500k , c bus =10nf 0.590 t dom(txdl) txdl dominant time-out 12 ms t lin lin permanent recessive time-out 40 s rdson on resistance 10.5 16 table 24. lin transceiver timing (continued) symbol parameter test condition min. typ. max. unit table 25. lin flash mode symbol parameter test condition min. typ. max. unit srf lin slew rate falling edge from 20% to 80% of v lin ; v s =12v; r bus = 150 ; c bus =1nf ?13?v/s w l p h w l p h 9 7 [ ' 9 / , 1 9 7 + u h f 9 7 + g r p w l p h 9 5 [ ' 9 / , 1 g r p 9 / , 1 u h f w 7 ; s g i w 7 ; s g u w 5 ; s g i w 5 ; s g u $ * 9 L99PM60J electrical specifications doc id 18309 rev 6 41/75 input csn for flash mode 6v v s 18 v, 4.5 v v 1 5.3 v; t j = -40 c to 130 c; voltages are referred to gnd, all outputs open inputs: clk, di the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6v < v s < 18 v; 4.8 v < v 1 < 5.2 v; all outputs open; t j = -40c to 130c, unless otherwise specified. table 26. input: csn symbol parameter test condition min. typ. max. unit vcsnlow input voltage low level normal mode; v 1 = 5 v 0.8 1.9 2.5 v vcsnhigh input voltage high level normal mode; v 1 = 5 v 1.5 2.9 3.5 v vcsnhys vcsnhigh ? vcsnlow normal mode; v 1 = 5 v 0.5 1.0 1.5 v icsnpu csn pull up resistor normal mode; v 1 =5v 10 20 35 k icsnpd csn pull-down current test mode, v in = 10 v 480 a table 27. input csn for flash mode symbol parameter test condition min. typ. max. unit v flashl input level v csn exit flash mode) v 1 = 5 v 6.1 7.25 8.4 v v flashh input level v csn entering flash mode v 1 = 5 v 7.4 8.4 9.4 v v flashhys input voltage hysteresis v 1 = 5 v 0.6 0.8 1.0 v table 28. inputs: clk, di symbol parameter test condition min. typ. max. unit t set delay time from standby to active mode switching from standby to active mode. time until output drivers are enabled after csn going to high. 160 300 us v in l input low level v 1 = 5 v 1.0 2.3 2.9 v v in h input high level v 1 = 5 v 1.5 2.8 3.8 v v in hyst input hysteresis v 1 = 5 v 0.4 0.75 1.5 v i in pull down current at input v in = 1.5 v 5 30 60 a c in (1) 1. value of input capacity is not measured in production test. parameter guaranteed by design. input capacitance at input csn, clk, di and pwm 1,2 0v < v 1 < 5.2 v 10 15 pf f clk spi input frequency at clk 1 mhz electrical specifications L99PM60J 42/75 doc id 18309 rev 6 di timing (b) the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6v < v s < 18 v; 4.8 v < v 1 < 5.2 v; all outputs open; t j = -40c to 130c, unless otherwise specified. output do the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6v < v s < 18 v; 4.8 v < v 1 < 5.2 v; all outputs open; t j = -40c to 130c, unless otherwise specified. b. see figure 16: spi ? input timing . table 29. di timing symbol parameter test condition min. typ. max. unit t clk clock period v 1 = 5 v 1000 ? ns t clkh clock high time v 1 = 5 v 400 ? ns t clkl clock low time v 1 = 5 v 400 ? ns t set csn csn setup time, csn low before rising edge of clk v 1 = 5 v 400 ? ns t set clk clk setup time, clk high before rising edge of csn v 1 = 5 v 400 ? ns t set di di setup time v 1 = 5 v 200 ? ns t hold di di hold time v 1 = 5 v 200 ? ns t r in rise time of input signal di, clk, csn v 1 =5v ? 100 ns t f in fall time of input signal di, clk, csn v 1 =5v ? 100 ns table 30. output do symbol parameter test condition min. typ. max. unit v dol output low level v 1 =5v; i d =-4ma 0.5 v v doh output high level v = 5 v; i d =4ma 4.5 v i dolk 3-state leakage current v csn =v 1 ; 0 v < v do electrical specifications L99PM60J 44/75 doc id 18309 rev 6 figure 16. spi ? input timing table 33. rxdl/nint timing symbol parameter test condition min. typ. max. unit t interupt interrupt pulse duration walk-up from v 1stby by lin ? 56 ? s 9 & & 9 & & 9 & & 9 & & 9 & & 9 & & 9 d o l g 9 d o l g & 6 1 & / . ' , w v h w & 6 1 w & / . + w v h w & / . w & / . / w k r o g ' , w v h w ' , $ * 9 L99PM60J electrical specifications doc id 18309 rev 6 45/75 figure 17. spi ? output timing 7 i & / . 7 u & / . & / . 9 f f 9 f f 9 f f ' 2 o r z w r k l j k 9 f f 9 f f 7 u ' 2 7 g ' 2 9 f f 9 f f 7 i ' 2 ' 2 k l j k w r o r z 7 i & 6 1 7 u & 6 1 & 6 1 9 f f 9 f f 9 f f 7 h q ' 2 b w u l b / 7 h q ' 2 b w u l b + 7 g l v ' 2 b / b w u l 7 g l v ' 2 b + b w u l $ * 9 electrical specifications L99PM60J 46/75 doc id 18309 rev 6 figure 18. spi transition parameters figure 19. spi global status register access $ * 9 & 6 1 g 2 1 w w u l q i l q w 2 ) ) w g 2 ) ) w 2 ) ) v w d w h 2 1 v w d w h 2 ) ) v w d w h 2 1 v w d w h 2 1 w r x w s x w f x u u h q w r i d g u l y h u r x w s x w f x u u h q w r i d g u l y h u & 6 1 o r z w r k l j k g d w d i u r p v k l i w u h j l v w h u l v w u d q v i h u u h g w r r x w s x w s r z h u v z l w f k h v w & 6 1 b + , p l q & 6 1 & / . ' , ' 2 & 6 1 k l j k w r o r z d q g & / . v w d \ v o r z v w d w x v l q i r u p d w l r q r i g d w d e l w i d x o w f r q g l w l r q l v w u d q v i h u h g w r ' 2 ' , g d w d l v q r w d f f h s w h g ' 2 v w d w x v l q i r u p d w l r q r i g d w d e l w i d x o w f r q g l w l r q z l o o v w d \ d v o r q j d v & 6 1 l v o r z w l p h w l p h w l p h w l p h $ * 9 L99PM60J st spi doc id 18309 rev 6 47/75 7 st spi 7.1 spi communication flow 7.1.1 general description the proposed spi communication is based on a standard spi interface structure using csn (chip select not), sdi (serial data in), sdo (serial data out/error) and sck (serial clock) signal lines. at device start-up the master reads the st spi L99PM60J 48/75 doc id 18309 rev 6 the L99PM60J st spi doc id 18309 rev 6 49/75 7.1.5 configuration register the st spi L99PM60J 50/75 doc id 18309 rev 6 figure 20. read configuration register figure 21. write configuration register $ $ $ $ $ $ & 6 1 6 ' , & r p p d q g ' ' ' ' ' ' ' ' ) d l o 6 d i h 9 v i d l o 9 i d l o 7 : 7 6 ' r u 7 6 ' 1 2 7 & k l s 5 h v 2 5 & r p p ( u u & r p ( u u r u * ( ) 6 ' 2 * o r e d o 6 w d w x v ' d w d e l w $ * 9 ' ' ' ' ' ' ' ' $ $ $ $ $ $ ' ' ' ' ' ' ' ' ) d l o 6 d i h 9 v i d l o 9 i d l o 7 : 7 6 ' r u 7 6 ' 1 2 7 & k l s 5 h v 2 5 & r p p ( u u & r p ( u u r u * ( ) & 6 1 6 ' 2 6 ' , & r p p d q g * o r e d o 6 w d w x v ' d w d e l w ' d w d s u h y l r x v f r q w h q w r i w k h u h j l v w h u $ * 9 L99PM60J st spi doc id 18309 rev 6 51/75 7.1.6 address mapping the ram memory area consists of 8 bit registers. for the device information (rom memory area) the eight bits of the memory cell are used. all unused ram and rom addresses are read as ?0?. note: 1 the register definition for ram address 00h is unused. a register value of all 0 must cause the device to enter a failsafe state (interpreted as ?sdi stuck to gnd? failure). 2 rom address 3fh is unused. an attempt to access this address must be recognized as a communication error (?sdi stuck to v cc ? failure) and must cause the device to enter a failsafe state. 7.1.7 write operation the write operation starts with a command byte followed by 1 data byte. table 39. addressing mapping ram address description access rom address description access 3fh st spi L99PM60J 52/75 doc id 18309 rev 6 oc0, oc1: operating code (00 for ?write? mode) a0 to a5: address bits an attempt to write 00h at ram address 00h is recognized as a failure (sdi stuck to gnd). the device enters a failsafe state. 7.1.8 format of data shifted out at sdo during write cycle failures are indicated by activating the corresponding bit of the L99PM60J st spi doc id 18309 rev 6 53/75 7.1.9 read operation the read operation starts with a command byte followed by 1 data byte. the content of the data byte is ?don?t care?. the content of the addressed register is shifted out at sdo within the same frame (?in-frame response?). oc0, oc1: operating code (01 for ?read? mode) a0 to a5: address bits 7.1.10 format of data shifted out at sdo during read cycle failures are indicated by activating the corresponding bit of the st spi L99PM60J 54/75 doc id 18309 rev 6 figure 23. format of data shifted out at sdo during read cycle 7.1.11 read and clear status operation the ?read and clear status? operation starts with a command byte followed by 1 data byte. the content of the data byte is ?don?t care?. the content of the addressed status register is transferred to sdo within the same frame (?in-frame response?) and is subsequently cleared. a ?read and clear status? operation with address 3fh clears all status registers (incl. the L99PM60J st spi doc id 18309 rev 6 55/75 7.1.12 format of data shifted out at sdo during ?read and clear status? operation failures are indicated by activating the corresponding bit of the st spi L99PM60J 56/75 doc id 18309 rev 6 7.1.13 read device information the device information is stored at the rom addresses defined below and is read using the respective operating code. the L99PM60J st spi doc id 18309 rev 6 57/75 definition of the silicon version code: the st spi L99PM60J 58/75 doc id 18309 rev 6 overview of control register data bytes table 56. spi register: mode selection read/write mode selection 00 write 01 read 1 0 read and clear 1 1 read device info table 57. spi register: ctrl register selection ctrl register 1, 2 ctrl register selection 000001 ctrl register1 000010 ctrl register2 table 58. spi register: stat register selection stat register. 1?4 stat register selection 010001 stat register1 010010 stat register2 010011 stat register3 010100 stat register4 table 59. overview of control register data byte 1 st data byte control register 1 defaults11110000 funct. out2_2 out2_1 out1_2 out1_1 icmp sandby select go standby trig group hs control mode control control register 2 defaults00010111 funct. rel2 rel1 vsm en reset level lin flash lin txd timeout enable out uv shutdown enable ls ovuv shutdown enable group ls control other control L99PM60J st spi doc id 18309 rev 6 59/75 control register 1 table 60. control register 1 command byte 1 st data byte read/ write address xx000001 data, 8bit table 61. control register 1, 1 st data byte group hs control mode control defaults 1 1 1 1 0 0 0 0 funct. out2_2 out2_1 out1_2 out1_1 icmp standby select go standby trig table 62. control register 1, bits bit name comment 7 out2 select mode of out2 note: note: in direct drive, pin drv/vsout, can be used as an input to directly switch on/off out2 6 out2_2 out2_1 active mode v 1-standby v bat-standby 00 off 01 on 10 direct drive off vsm enable 0direct drive 1off 11 direct drive off vsm enable 0direct drive 1off st spi L99PM60J 60/75 doc id 18309 rev 6 5 out1 select mode of out1 note: in direct drive, pin drv/vsout, can be used as an input to directly switch on/off out1 to change the setting for out1 from fso (default) to normal output configuration (on/off or direct drive) a spi safety sequence needs to be followed. first write command with a specific pattern to conf register needs to be provided in order to enable the write access for configuration bits of out1. with an spi write command to control register 1 the bits for out1 can be modified. the write command to control register 1 must follow the write command to the conf register (no other spi command in between these 2 commands) safety sequence: ? write to conf register (0x0011 1111; 1010 101x) x: don?t care for unlocking sequence but according to description of watchdog timing ? write to ctrl register 1 (0x0000 0001; xxxx xxxx) x: values according to description of ctrl reg1 4 3icmp v 1 load current supervision ? 0: enabled; watchdog is disabled in v 1-standby when the v 1loadcurrent < i cmpthreshold ? 1: disabled; watchdog is automatically disabled when v 1-standby is entered 2stby select select standby mode ?0: v bat-standby mode ?1: v 1-standby mode 1go stby execute standby mode ? 0: no action ? 1: execute standby mode 0 trig trigger bit for watchdog table 62. control register 1, bits (continued) bit name comment out2_2 out2_1 active mode v 1-standby v bat-standby 00 off 01 on 10 direct drive off vsm enable 0 direct drive 1off 1 1 fso fso fso L99PM60J st spi doc id 18309 rev 6 61/75 control register 2 table 63. control register 2 command byte 1 st data byte read/ write address xx000010 data, 8bit table 64. control register 2, 1 st data byte group ls control other control defaults 0 0 0 1 0 1 1 1 function rel2 rel1 vsm enable reset level lin flash lin txd timeout enable out uv shutdown enable ls ovuv shutdown enable table 65. control register 2, bits bit name comment 7 rel2 select mode of rel2 6 rel1 select mode of rel1 5 vsm enable select pin drv/vsout as input/output rel2 active mode v 1 standby v bat standby 0 rel2 off 1 rel2 on rel2 off rel2 active mode v 1 standby v bat standby 0 rel1 off 1 rel1 on rel1 off vsm enable active mode v 1 standby v bat standby 0 drv/vsout pin used as input (direct drive) (1) 1 drv/vsout pin used as input (direct drive) (1) out2_2 out2_1 drv/vsout used as 00output (v s /5 voltage) 01output (v s /5 voltage) 10 output (t sense voltage) 11output (v s /5 voltage) 1. usage of direct drive feature is not only related to the configuration of drv/vsout as an input. refer to truth table of out1/2 for the direct drive feature. st spi L99PM60J 62/75 doc id 18309 rev 6 4 reset level select v 1 reset level ?0: 3.5 v ?1: 4.6 v 3lin flash select maximum lin communication speed ? 0: 20 kbit/s ? 1: 100 kbit/s 2 lin txd timeout enable enable / disable monitoring of txd ? 0: no txd monitoring ? 1: txd monitoring; lin transmitter is switched off if txdl is dominant for t > 12 ms 1 out uv shutdown enable select undervoltage shutdown for hs driver ? 0: no undervoltage shutdown ? 1: undervoltage shutdown 0 ls ovuv shutdown enable shutdown of ls drivers in case of overvoltage / undervoltage 0: no shutdown of low sides in case of overvoltage / undervoltage 1: shutdown low sides in case of overvoltage / undervoltage table 65. control register 2, bits bit name comment L99PM60J st spi doc id 18309 rev 6 63/75 7.2.1 status register status register 1 table 66. overview of status register data bytes 1 st data byte status register 1 funct. ov uv ol out2 ol out1 oc out2 oc out1 oc rel2 oc rel1 group diagnosis 1 status register 2 funct. res lin perm dom lin txd dom lin perm rec res lin wake device state device state group diagnosis 2 status register 3 funct. wd fail wd fail wd fail wd fail forced sleep wd forced sleep tsd/shtv1 wd timer state1 wd timer state0 group diagnosis 3 status register 4 funct. v 1 uv warn v 1 restart v 1 restart v 1 restart v 1 fail tsd2 tsd1 tw group diagnosis 4 table 67. global status register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 global error flag communicatio n error (1) not (chip reset or comm. error i.e. cold start (2) tsd2 or tsd1 (3) tw v 1 fail vs fail (ov/uv) fail safe (4) 1. invalid clock count 2. cleared with clr command on sr3 3. cleared with ?read and clear? on sr4 4. cleared with a valid wd trigger (wd fail) or by clear ing the corresponding status register related to failure table 68. status register 1, command and data byte command byte 1 st data byte read/write address xx010001 data, 8bit st spi L99PM60J 64/75 doc id 18309 rev 6 status register 2 table 69. status register 1, data byte 1 st data byte function ov uv ol out2 ol out1 oc out2 oc out1 oc rel2 oc rel1 group diagnosis 1 table 70. status register 1, bits bit name comment 7ov overvoltage event occurred since last read out bit is latched until a ?read and clear? access 6uv undervoltage event occurred since last read out bit is latched until a ?read and clear? access 5ol out2 open-load event occurred since last read out bit is latched until a ?read and clear? access 4ol out1 3oc out2 overcurrent event occurred since last read out bit is latched until a ?read and clear? access 2oc out1 1 oc rel2 0 oc rel1 table 71. status register 2, command and data byte command byte 1 st data byte read/write address xx010010 data, 8bit table 72. status register 2, data byte 1 st data byte function res lin perm dom lin txd dom lin perm rec res lin wake device state device state group diagnosis 2 table 73. status register 2, bits bit name comment 7 res reserved 6 lin perm dom lin bus is dominant for t > 12 ms bit is latched until a ?read and clear? access 5 lin txd dom txdl pin is dominant for t > 12 ms; transmitter is disabled; bit is latched until a ?read and clear? access L99PM60J st spi doc id 18309 rev 6 65/75 status register 3 4 lin perm rec lin bus does not follow txdl within 40 s; transmitter is disabled; bit is latched until a ?read and clear? access 3 res reserved 2 lin wake wake up from lin; bit is latched until a ?read and clear? access 1 device state state from which the device woke up bit is latched until a ?read and clear access?. after a ?read and clear access?, the device state is updated. after a wake up, device state is ?01: v 1-standby ?10: v bat-standby 0 device state table 74. status register 3, command and data byte command byte 1 st data byte read/write address xx010011 data, 8bit table 75. status register 3, data byte 1 st data byte function wd fail_3 wd fail_2 wd fail_1 wd fail_0 forced sleep wd forced sleep tsd/shtv1 wd timer state_1 wd timer state_0 group diagnosis 3 table 76. status register 3, bits bit name comment 7wd fail_3 number of missing watchdog triggers (15 missing watchdog trigger forces the device into v bat-standby ). bits are not clearable; are cleared with a proper watchdog trigger 6wd fail_2 5wd fail_1 4wd fail_0 table 73. status register 2, bits (continued) bit name comment device state device state state from which the device woke up 00active 01v 1-standby 10v bat-standby st spi L99PM60J 66/75 doc id 18309 rev 6 status register 4 3 forced sleep wd device was forced to vbat mode because of multiple watchdog errors bits are latched until a read and clear access 2 forced sleep tsd/shtv1 device was forced to vbat or multiple thermal shutdown events or a short on v 1 during start-up. bits are latched until a read and clear access 1 wd timer state_1 status of watchdog counter of selected watchdog timing bits are not clearable 0 wd timer state_0 table 77. status register 4, command and data byte command byte 1 st data byte read/write address xx010100 data, 8bit table 78. status register 4, data byte 1 st data byte function v 1 uv warn v 1 restart_2 v 1 restart_1 v 1 restart_0 v 1 fail tsd2 tsd1 tw group diagnosis 4 table 79. status register 4, bits bit name comment 7v 1 uv warn v 1 undervoltage pre-warning (v 1 < 4.5 v) bit is latched until a read and clear access 6v 1 restart_2 number of tsd2 events which caused a restart of v 1 regulator (7 tsd2 events forces the device into v bat-standby ) bits are latched until a read and clear access 5v 1 restart_1 4v 1 restart_0 3v 1 fail v 1 fail (v 1 < 2 v for t > 2 s) event occurred since last read out bit is latched until a ?read and clear access? table 76. status register 3, bits (continued) bit name comment wd_timer_state_1 wd_timer_state_0 counter 000%-33% 0 1 33% - 66% 1 1 66% - 100% L99PM60J st spi doc id 18309 rev 6 67/75 2 tsd2 thermal warning / shutdown1 / shutdown2 occurred since last readout bits are latched until a ?read and clear access? 1 tsd1 0tw table 79. status register 4, bits (continued) bit name comment package and pcb thermal data L99PM60J 68/75 doc id 18309 rev 6 8 package and pcb thermal data 8.1 powersso-16 thermal data figure 25. thermal data of powersso-16 note: board finish thickness 1.6 mm +/- 10%; board double layer; board dimension 77 x 86; board material fr4; cu thickness 0.070 mm (front and back side); thermal vias separation 1.2 mm; thermal via diameter 0.3 mm +/- 0.08 mm; cu thickness on vias 0.025 mm; footprint dimension 2.5 mm x 4.2 mm figure 26. r thj-amb vs pcb copper area in open box free air condition $ * 9 5 7 + m b d p e ? & : 3 & % & x k h d w v l q n d u h d f p a 5 7 + m b d p e y v & x k h d w v l q n d u h d 5 7 + m d p e $ * 9 L99PM60J package and pcb thermal data doc id 18309 rev 6 69/75 figure 27. v 1 thermal impedance figure 28. thermal fitting model of v 1 equation 1: pulse calculation formula where 100 zth (c/w) 100 zth (c/w) cu=8 cm2 cu=2 cm2 cu=foot print 10 100 zth (c/w) cu=8 cm2 cu=2 cm2 cu=foot print 10 100 zth (c/w) cu=8 cm2 cu=2 cm2 cu=foot print 10 100 zth (c/w) cu=8 cm2 cu=2 cm2 cu=foot print 1 10 100 0.0001 0.001 0.01 0.1 1 10 100 1000 zth (c/w) time (s) cu=8 cm2 cu=2 cm2 cu=foot print ag00064v1 1 10 100 0.0001 0.001 0.01 0.1 1 10 100 1000 zth (c/w) time (s) cu=8 cm2 cu=2 cm2 cu=foot print $ * 9 z th r th ? z thp 1 ? () + = t p t ? = package and pcb thermal data L99PM60J 70/75 doc id 18309 rev 6 table 80. powersso-16 thermal parameter area/island (cm 2 )fp28 r1 (c/w) 1.5 r2 (c/w) 3 r3 (c/w) 5 r4 (c/w) 20 6 6 r5 (c/w) 28 21 10 r6 (c/w) 32 25 21 c1 (ws/c) 0.0008 c2 (ws/c) 0.01 c3 (ws/c) 0.05 c4 (ws/c) 0.2 0.3 0.3 c5 (ws/c) 0.5 1 1.5 c6 (ws/c) 4 6 8 L99PM60J package and packaging information doc id 18309 rev 6 71/75 9 package and packaging information 9.1 ecopack ? in order to meet environmental requirements, st offers these devices in different grades of ecopack? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com .ecopack ? is an st trademark. 9.2 powersso-16 package information figure 29. powersso-16 package dimensions a g00110v1 package and packaging information L99PM60J 72/75 doc id 18309 rev 6 table 81. powersso-16 mechanical data symbol millimeters min. typ. max. a 1.25 1.72 a1 0.00 0.10 a2 1.10 1.62 b 0.18 0.36 c 0.19 0.25 d 4.80 5.00 e 3.80 4.00 e0.50 h 5.80 6.20 h 0.25 0.50 l 0.40 1.27 k0 8 x 1.90 2.50 y 3.60 4.20 ddd 0.10 L99PM60J package and packaging information doc id 18309 rev 6 73/75 9.3 powersso-16 packing information figure 30. powersso-16 tube shipment (no suffix) figure 31. powersso-16 tape and reel shipment (no suffix) a b c a g00111v1 all dimensions are in mm. base q.ty 100 bulk q.ty 2000 tube length ( 0.5) 532 a1.85 b6.75 c ( 0.1) 0.6 reel dimension base q.ty 2500 bulk q.ty 2500 a (max) 330 b (min) 1.5 c ( 0.2) 13 f 20.2 g (+ 2 / -0) 12.4 n (min) 60 t (max) 18.4 tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb. 1986 all dimensions are in mm. tape width w 12 tape hole spacing p0 ( 0.1) 4 component spacing p 8 hole diameter d ( 0.05) 1.5 hole diameter d1 (min) 1.5 hole position f ( 0.1) 5.5 compartment depth k (max) 4.5 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed a g00112v1 revision history L99PM60J 74/75 doc id 18309 rev 6 10 revision history table 82. document revision history date revision changes 26-jan-2011 1 initial release. 09-mar-2011 2 updated section 3.2: low side driver outputs rel1, rel2 updated figure 8: recovery after forced vbat due to multiple watchdog failure table 11: supply and supply monitoring : ?i v(bat) (v 1-standby ): updated test condition and minimum, typical and maximum values ?i v(v1) : updated typical value table 13: power-on reset (v s ) ?v por (v s decreasing): updated minimun and typical values table 14: voltage regulator v 1 ? vstb1: updated minimum and maximum values ?i cmp_rise , i cmp_fail : updated minimum, typical and maximum values table 15: reset output (v 1 supervision) ?v rt2 (increasing/ decreasing): updated minimux, typical and maximum values table 17: output ? iold: updated minimux, typical and maximum values table 18: relay drivers ?v z : added typical value table 20: output: vsout : ? vsout: added minimum and maximum values table 26: input: csn : ? icsnpu: added minimum aln maximum values table 39: addressing mapping ? updated ram address: inserted control register 1 25-mar-2011 3 updated following tables: ? table 13: power-on reset (v s ) : v por decreasing: updated minimum value ? table 14: voltage regulator v 1 : i cmp_rise : updated minimum value i cmp_fail : updated minimum and maximum values ? table 15: reset output (v 1 supervision) : v rt1 : added row v rt2 : updated test condition and maximum value 28-apr-2011 4 changed document state from preliminary data to final datasheet 03-nov-2011 5 updated figure 8: recovery after forced vbat due to multiple watchdog failure table 11: supply and supply monitoring : ?i v(act) , i v(bat) , i v(v1) : updated test conditions ?i v(v1)cs : added row 19-sep-2013 6 updated disclaimer. L99PM60J doc id 18309 rev 6 75/75 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statem ents and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - swed en - switzerland - united kingdom - united states of america www.st.com |
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