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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. advance information for pre-production products; subject to change without notice. drv8343-q1 slvse12 ? march 2018 drv8343-q1 automotive 5.5 to 60-v three-phase smart gate driver with three integrated current shunt amplifiers 1 1 features 1 ? aec-q100 qualified for automotive applications ? temperature grade 1: ? 40 c t a 125 c ? hbm esd classification level 2 ? triple half-bridge gate driver ? dedicated source (shx) and drain (dlx) pins to support independent mosfet control ? drives 3 high-side and 3 low-side n-channel mosfets (nmos) ? smart gate drive architecture ? adjustable slew rate control ? 1.5-ma to 1-a peak source current ? 3-ma to 2-a peak sink current ? integrated gate driver power supplies ? supports 100% pwm duty cycle ? high-side charge pump ? low-side linear regulator ? 3 integrated current sense amplifiers (csas) ? adjustable gain (5, 10, 20, 40 v/v) ? bidirectional or unidirectional support ? spi and hardware interface available ? 6x, 3x, 1x, and independent pwm modes ? supports 3.3-v, and 5-v logic inputs ? charge pump output can be used to drive the reverse supply protection mosfet ? linear voltage regulator, 3.3 v, 30 ma ? integrated protection features ? vm undervoltage lockout (uvlo) ? charge pump undervoltage (cpuv) ? short to battery (sht_bat) ? short to ground (sht_gnd) ? mosfet overcurrent protection (ocp) ? gate driver fault (gdf) ? thermal warning and shutdown (otw/otsd) ? fault condition indicator (nfault) 2 applications ? 12-v and 24-v automotive motor-control applications ? bldc and bdc motor modules ? fans and blowers ? fuel and water pumps ? solenoid drive 3 description the drv8343-q1 device is an integrated gate driver for three-phase applications. the device provides three half-bridge gate drivers, each capable of driving high-side and low-side n-channel power mosfets. the dedicated source and drain pins enable the independent mosfet control for solenoid application. the drv8343-q1 generates the correct gate drive voltages using an integrated charge pump for the high-side mosfets and a linear regulator for the low-side mosfets. the smart gate drive architecture supports peak gate drive currents up to 1-a source and 2-a. the drv8343-q1 can operate from a single power supply and supports a wide input supply range of 5.5 to 60 v for the gate driver. the 6x, 3x, 1x, and independent input pwm modes allow for simple interfacing to controller circuits. the configuration settings for the gate driver and device are highly configurable through the spi or hardware (h/w) interface. the drv8343-q1 device integrates three low-side current sense amplifiers that allow bidirectional current sensing on all three phases of the drive stage. a low-power sleep mode is provided to achieve low quiescent current. internal protection functions are provided for undervoltage lockout, charge pump fault, mosfet overcurrent, mosfet short circuit, phase- node short to supply and ground, gate driver fault, and overtemperature. fault conditions are indicated on the nfault pin with details through the device registers for the spi device variant. device information (1) part number package body size (nom) drv8343-q1 htqfp (48) 7.00 mm 7.00 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. simplified schematic 5.5 to 60 v drv8343-q1 three-phase smart gate driver pwm gate drive current sense sense output 3x sense amplifiers n-channel mosfets nfault spi or h/w 3.3 v 30 ma protection controller 3.3-v ldo copyright ? 2017, texas instruments incorporated advance information tools & software technical documents ordernow productfolder support &community
2 drv8343-q1 slvse12 ? march 2018 www.ti.com product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 device comparison table ..................................... 3 6 pin configuration and functions ......................... 3 7 specifications ......................................................... 7 7.1 absolute maximum ratings ...................................... 7 7.2 esd ratings .............................................................. 7 7.3 recommended operating conditions ....................... 8 7.4 thermal information .................................................. 8 7.5 electrical characteristics ........................................... 9 7.6 spi timing requirements ...................................... 15 8 detailed description ............................................ 16 8.1 overview ................................................................. 16 8.2 functional block diagram ....................................... 17 8.3 feature description ................................................. 19 8.4 device functional modes ........................................ 50 8.5 programming ........................................................... 51 8.6 register maps ......................................................... 53 9 application and implementation ........................ 68 9.1 application information ............................................ 68 9.2 typical application ................................................. 68 10 power supply recommendations ..................... 75 10.1 bulk capacitance sizing ....................................... 75 11 layout ................................................................... 76 11.1 layout guidelines ................................................. 76 11.2 layout example .................................................... 77 12 device and documentation support ................. 78 12.1 device support ...................................................... 78 12.2 documentation support ........................................ 78 12.3 receiving notification of documentation updates 78 12.4 community resources .......................................... 78 12.5 trademarks ........................................................... 78 12.6 electrostatic discharge caution ............................ 79 12.7 glossary ................................................................ 79 13 mechanical, packaging, and orderable information ........................................................... 79 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. date revision notes march 2018 0.1 initial release december 2018 0.2 ? advance information ? recommended operating conditions updated ? electrical characteristics updated ? table 10 updated ? register maps updated advance information
3 drv8343-q1 www.ti.com slvse12 ? march 2018 product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 5 device comparison table (1) for more information on the device name and device options, see the device nomenclature section. device variant (1) interface (1) drv8343-q1 drv8343h hardware drv8343s spi (1) pwr = power, i = input, o = output, nc = no connection, od = open-drain output 6 pin configuration and functions drv8343h php powerpad ? package 48-pin htqfp with exposed thermal pad top view pin functions ? drv8343h pin type (1) description no. name 1 cpl pwr charge pump switching node. connect a x5r or x7r, 47-nf, vm-rated ceramic capacitor between the cph and cpl pins 2 cph pwr charge pump switching node. connect a x5r or x7r, 47-nf, vm-rated ceramic capacitor between the cph and cpl pins 3 vcp pwr charge pump output. connect a x5r or x7r, 1- f, 50-v ceramic capacitor between the vcp and vm pins 4 vm pwr gate driver power supply input. connect to the bridge power supply. connect a x5r or x7r, 0.1- f, vm-rated ceramic and greater than or equal to 10-uf local capacitance between the vm and pgnd pins 5 vdrain i high-side mosfet drain sense input. connect to the common point of the mosfet drains 6 gha o high-side gate driver output. connect to the gate of the high-side power mosfet 7 sha i high-side source sense input. connect to the high-side power mosfet source. if high-side power mosfet is not used, connect to gnd advance information 48 nc 13 snb 1 cpl 36 enable 47 pgnd 14 spb 2 cph 35 gain 46 inlc 15 slb 3 vcp 34 vds 45 inhc 16 glb 4 vm 33 idrive 44 inlb 17 dlb 5 vdrain 32 mode 43 inhb 18 shb 6 gha 31 nfault 42 inla 19 ghb 7 sha 30 vref 41 inha 20 ghc 8 dla 29 soa 40 ndiag 21 shc 9 gla 28 sob 39 dvdd 22 dlc 10 sla 27 soc 38 agnd 23 glc 11 spa 26 snc 37 cal 24 slc 12 sna 25 spc not to scale thermal pad
4 drv8343-q1 slvse12 ? march 2018 www.ti.com product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated pin functions ? drv8343h (continued) pin type (1) description no. name 8 dla i low-side mosfet drain sense input. connect to the low-side mosfet drain 9 gla o low-side gate driver output. connect to the gate of the low-side power mosfet 10 sla i low-side source sense input. connect to the low-side power mosfet source 11 spa i low-side current shunt amplifier input. connect to the low-side power mosfet source and high-side of the current shunt resistor 12 sna i current sense amplifier input. connect to the low-side of the current shunt resistor 13 snb i low-side source sense input. connect to the low-side power mosfet source 14 spb i low-side current shunt amplifier input. connect to the low-side power mosfet source and high-side of the current shunt resistor 15 slb i low-side source sense input. connect to the low-side power mosfet source 16 glb o low-side gate driver output. connect to the gate of the low-side power mosfet 17 dlb i low-side mosfet drain sense input. connect to the low-side mosfet drain 18 shb i high-side source sense input. connect to the high-side power mosfet source. if high-side power mosfet is not used, connect to gnd 19 ghb o high-side gate driver output. connect to the gate of the high-side power mosfet 20 ghc o high-side gate driver output. connect to the gate of the high-side power mosfet 21 shc i high-side source sense input. connect to the high-side power mosfet source. if high-side power mosfet is not used, connect to gnd 22 dlc i low-side mosfet drain sense input. connect to the low-side mosfet drain 23 glc o low-side gate driver output. connect to the gate of the low-side power mosfet 24 slc i low-side source sense input. connect to the low-side power mosfet source 25 spc i low-side current shunt amplifier input. connect to the low-side power mosfet source and high-side of the current shunt resistor 26 snc i current sense amplifier input. connect to the low-side of the current shunt resistor 27 soc o current sense amplifier output 28 sob o current sense amplifier output 29 soa o current sense amplifier output 30 vref pwr current sense amplifier power supply input and reference. connect a x5r or x7r, 0.1- f, 6.3-v ceramic cap between vref and agnd 31 nfault od fault indicator output. this pin is pulled logic low during a fault condition and requires an external pullup resistor 32 mode i pwm input mode setting. this pin is a 4-level input pin set by an external resistor 33 idrive i gate drive output current setting. this pin is a 7-level input pin set by an external resistor 34 vds i vds monitor trip point setting. this pin is a 7-level input pin set by an external resistor 35 gain i amplifier gain setting. the pin is a 4-level input pin set by an external resistor 36 enable i gate driver enable. when this pin is logic low the device goes to a low-power sleep mode. an 8 to 40- s low pulse can be used to reset fault conditions 37 cal i amplifier calibration input. set logic high to internally short amplifier inputs 38 agnd pwr device analog ground. connect to system ground 39 dvdd pwr 3.3-v internal regulator output. connect a x5r or x7r, 1- f, 6.3-v ceramic capacitor between the dvdd and agnd pins. this regulator can externally source up to 30 ma. 40 ndiag i control pin for open load diagnostic and offline short-to-battery and short-to-ground diagnostic. to enable the diagnostics at device power-up, do not connect this pin (or tie it to ground). to disable the diagnostics, connect this pin to the dvdd pin. 41 inha i high-side gate driver control input. this pin controls the output of the high-side gate driver 42 inla i low-side gate driver control input. this pin controls the output of the low-side gate driver 43 inhb i high-side gate driver control input. this pin controls the output of the high-side gate driver 44 inlb i low-side gate driver control input. this pin controls the output of the low-side gate driver 45 inhc i high-side gate driver control input. this pin controls the output of the high-side gate driver 46 inlc i low-side gate driver control input. this pin controls the output of the low-side gate driver 47 pgnd pwr device power ground. connect to system ground 48 nc nc no connect. do not connect anything to this pin ? thermal pad pwr must be connected to ground advance information
5 drv8343-q1 www.ti.com slvse12 ? march 2018 product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) pwr = power, i = input, o = output, nc = no connection, od = open-drain output, pp = push-pull drv8343s php powerpad ? package 48-pin htqfp with exposed thermal pad top view pin functions ? drv8343s pin type (1) description no. name 1 cpl pwr charge pump switching node. connect a x5r or x7r, 47-nf, vm-rated ceramic capacitor between the cph and cpl pins 2 cph pwr charge pump switching node. connect a x5r or x7r, 47-nf, vm-rated ceramic capacitor between the cph and cpl pins 3 vcp pwr charge pump output. connect a x5r or x7r, 1- f, 50-v ceramic capacitor between the vcp and vm pins 4 vm pwr gate driver power supply input. connect to the bridge power supply. connect a x5r or x7r, 0.1- f, vm-rated ceramic and greater than or equal to 10-uf local capacitance between the vm and pgnd pins 5 vdrain i high-side mosfet drain sense input. connect to the common point of the mosfet drains 6 gha o high-side gate driver output. connect to the gate of the high-side power mosfet 7 sha i high-side source sense input. connect to the high-side power mosfet source. if high-side power mosfet is not used, connect to gnd 8 dla i low-side mosfet drain sense input. connect to the low-side mosfet drain 9 gla o low-side gate driver output. connect to the gate of the low-side power mosfet 10 sla i low-side source sense input. connect to the low-side power mosfet source 11 spa i low-side current shunt amplifier input. connect to the low-side power mosfet source and high-side of the current shunt resistor 12 sna i current sense amplifier input. connect to the low-side of the current shunt resistor 13 snb i low-side source sense input. connect to the low-side power mosfet source 14 spb i low-side current shunt amplifier input. connect to the low-side power mosfet source and high-side of the current shunt resistor 15 slb i low-side source sense input. connect to the low-side power mosfet source 16 glb o low-side gate driver output. connect to the gate of the low-side power mosfet 17 dlb i low-side mosfet drain sense input. connect to the low-side mosfet drain advance information 48 nc 13 snb 1 cpl 36 enable 47 pgnd 14 spb 2 cph 35 nscs 46 inlc 15 slb 3 vcp 34 sclk 45 inhc 16 glb 4 vm 33 sdi 44 inlb 17 dlb 5 vdrain 32 sdo 43 inhb 18 shb 6 gha 31 nfault 42 inla 19 ghb 7 sha 30 vref 41 inha 20 ghc 8 dla 29 soa 40 vsdo 21 shc 9 gla 28 sob 39 dvdd 22 dlc 10 sla 27 soc 38 agnd 23 glc 11 spa 26 snc 37 cal 24 slc 12 sna 25 spc not to scale thermal pad
6 drv8343-q1 slvse12 ? march 2018 www.ti.com product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated pin functions ? drv8343s (continued) pin type (1) description no. name 18 shb i high-side source sense input. connect to the high-side power mosfet source. if high-side power mosfet is not used, connect to gnd 19 ghb o high-side gate driver output. connect to the gate of the high-side power mosfet 20 ghc o high-side gate driver output. connect to the gate of the high-side power mosfet 21 shc i high-side source sense input. connect to the high-side power mosfet source. if high-side power mosfet is not used, connect to gnd 22 dlc i low-side mosfet drain sense input. connect to the low-side mosfet drain 23 glc o low-side gate driver output. connect to the gate of the low-side power mosfet 24 slc i low-side source sense input. connect to the low-side power mosfet source 25 spc i low-side current shunt amplifier input. connect to the low-side power mosfet source and high-side of the current shunt resistor 26 snc i current sense amplifier input. connect to the low-side of the current shunt resistor 27 soc o current sense amplifier output 28 sob o current sense amplifier output 29 soa o current sense amplifier output 30 vref pwr current sense amplifier power supply input and reference. connect a x5r or x7r, 0.1- f, 6.3-v ceramic cap between vref and agnd 31 nfault od fault indicator output. this pin is pulled logic low during a fault condition and requires an external pullup resistor 32 sdo pp serial data output. data is shifted out on the rising edge of the sclk pin. vsdo determines logic level on the output 33 sdi i serial data input. data is captured on the falling edge of the sclk pin 34 sclk i serial clock input. serial data is shifted out and captured on the corresponding rising and falling edge on this pin 35 nscs i serial chip select. a logic low on this pin enables serial interface communication 36 enable i gate driver enable. when this pin is logic low the device goes to a low-power sleep mode. an 8- to 40- s low pulse can be used to reset fault conditions 37 cal i amplifier calibration input. set logic high to internally short amplifier inputs 38 agnd pwr device analog ground. connect to system ground 39 dvdd pwr 3.3-v internal regulator output. connect a x5r or x7r, 1- f, 6.3-v ceramic capacitor between the dvdd and agnd pins. this regulator can externally source up to 30 ma. 40 vsdo pwr supply pin for sdo output. connect to 5-v or 3.3-v depending on the desired logic level 41 inha i high-side gate driver control input. this pin controls the output of the high-side gate driver 42 inla i low-side gate driver control input. this pin controls the output of the low-side gate driver 43 inhb i high-side gate driver control input. this pin controls the output of the high-side gate driver 44 inlb i low-side gate driver control input. this pin controls the output of the low-side gate driver 45 inhc i high-side gate driver control input. this pin controls the output of the high-side gate driver 46 inlc i low-side gate driver control input. this pin controls the output of the low-side gate driver 47 pgnd pwr device power ground. connect to system ground 48 nc nc no connect. do not connect anything to this pin ? thermal pad pwr must be connected to ground advance information
7 drv8343-q1 www.ti.com slvse12 ? march 2018 product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) continuous high-side gate pin (ghx) and phase node pin voltage (shx) should be limited to ? 2 v minimum for an absolute maximum of 65 v on vm. at 60 v and below, the full specification of ? 5 v continuous on ghx and shx is allowable. 7 specifications 7.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) min max unit gate driver power supply pin voltage (vm) ? 0.3 65 v voltage differential between ground pins (agnd, bgnd, dgnd, pgnd) ? 0.3 0.3 v mosfet drain sense pin voltage (vdrain) ? 0.3 65 v charge pump pin voltage (cph, vcp) ? 0.3 v vm + 13.5 v charge-pump negative-switching pin voltage (cpl) ? 0.3 v vm v internal logic regulator pin voltage (dvdd) ? 0.3 3.8 v voltage difference between vm and vdrain ? 10 10 v digital pin voltage (cal, enable, gain, idrive, inhx, inlx, mode, nfault, nscs, sclk, sdi, sdo, vds, ndiag) ? 0.3 5.75 v continuous high-side gate drive pin voltage (ghx) ? 5 (2) v vcp + 0.5 v transient 200-ns high-side gate drive pin voltage (ghx) ? 7 v vcp + 0.5 v high-side gate drive pin voltage with respect to shx (ghx) ? 0.3 13.5 v continuous high-side source sense pin voltage (shx, dlx) ? 5 (2) v vm + 5 v transient 200-ns high-side source sense pin voltage (shx, dlx) ? 7 v vm + 7 v continuous high-side source sense pin voltage (shx, dlx) ? 5 (2) v drain + 5 v transient 200-ns high-side source sense pin voltage (shx, dlx) ? 7 v drain + 7 v continuous low-side gate drive pin voltage (glx) ? 0.5 18 v gate drive pin source current (ghx, glx) internally limited a gate drive pin sink current (ghx, glx) internally limited a continuous low-side source sense pin voltage (slx) ? 1 1 v transient 200-ns low-side source sense pin voltage (slx) ? 3 3 v continuous shunt amplifier input pin voltage (snx, spx) ? 1 1 v transient 200-ns shunt amplifier input pin voltage (snx, spx) ? 3 3 v reference input pin voltage (vref) ? 0.3 5.75 v shunt amplifier output pin voltage (sox) ? 0.3 v vref + 0.3 v shunt amplifier output current (sox) 0 8 ma push-pull output buffer reference voltage (vsdo) ? 0.3 5.75 v push-pull output current (sdo) 0 10 ma open drain pullup voltage (nfault) ? 0.3 5.75 v open drain output current (nfault) 0 10 ma operating junction temperature, t j ? 40 150 c storage temperature, t stg ? 65 150 c (1) aec q100-002 indicates that hbm stressing shall be in accordance with the ansi/esda/jedec js-001 specification. 7.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per aec q100-002 (1) 2000 v charged-device model (cdm), per aec q100-011 all pins 500 corner pins (1, 10, 11, 20, 21, 30, 31, and 40) 750 v advance information
8 drv8343-q1 slvse12 ? march 2018 www.ti.com product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) vm recommended operating condition for electrical characteristic table. product life time depends on vm voltage. the device is intended for 12 ? v and 24 ? v battery automotive system. (2) power dissipation and thermal limits must be observed 7.3 recommended operating conditions min max unit gate driver v vm power supply voltage (vm) continuous 5.5 50 v power supply voltage (vm) transient over voltage (1) 5.5 60 v v i input voltage (cal, enable, gain, idrive, inhx, inlx, mode, nscs, sclk, sdi, vds, vsdo, ndiag) 0 5.5 v f pwm applied pwm signal (inhx, inlx) 0 200 (2) khz i gate_hs high-side average gate-drive current (ghx) 0 25 (2) ma i gate_ls low-side average gate-drive current (glx) 0 25 (2) ma i dvdd external load current (dvdd) 0 30 (2) ma v vref reference voltage input (vref) 3 5.5 v v sdo push-pull voltage (sdo) 3 5.5 v v od open drain pullup voltage (nfault) 0 5.5 v t a operating ambient temperature ? 40 125 c (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report . 7.4 thermal information thermal metric (1) drv8343-q1 unit php (htqfp) 48 pins r ja junction-to-ambient thermal resistance 26.5 c/w r jc(top) junction-to-case (top) thermal resistance 16.3 c/w r jb junction-to-board thermal resistance 6.7 c/w jt junction-to-top characterization parameter 0.2 c/w jb junction-to-board characterization parameter 6.8 c/w r jc(bot) junction-to-case (bottom) thermal resistance 1.0 c/w advance information
9 drv8343-q1 www.ti.com slvse12 ? march 2018 product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) specified by design and characterization data (2) does not include olp/shorts diagnostic delay time in the h/w device 7.5 electrical characteristics over recommended operating conditions unless otherwise noted. typical limits apply for t a = 25 c and v vm = 24 v parameter test conditions min typ max unit power supplies (dvdd, vcp, vm) i vm vm operating supply current v vm = 24 v, enable = 3.3 v, inhx/inlx = 0 v, shx = 0 v 8 14 ma i vmq vm sleep mode supply current enable = 0 v, v vm = 24 v, t a = 25 c 12 20 a enable = 0 v, v vm = 24 v, t a = 125 c (1) 50 t rst (1) reset pulse time enable = 0 v period to reset faults 5 40 s t wake (2) turnon time enable = 3.3 v to outputs ready, v vm > v uvlo 1 ms t sleep turnoff time enable = 0 v to device sleep mode 1 ms v dvdd dvdd regulator voltage v vm > 6 v, i dvdd = 0 to 30 ma 3 3.3 3.6 v v vm = 5.5 to 6 v, i dvdd = 0 to 20 ma 3 3.3 3.6 v v vcp vcp operating voltage with respect to vm v vm = 13 v, i vcp = 0 to 25 ma 8.4 11 12.5 v v vm = 10 v, i vcp = 0 to 20 ma 6.3 9 10 v vm = 8 v, i vcp = 0 to 15 ma 5.4 7 8 v vm = 5.5 v, i vcp = 0 to 5 ma 4 5 6 logic-level inputs (cal, enable, inhx, inlx, sclk, sdi) v il input logic low voltage 0 0.7 v v ih input logic high voltage 1.6 5.5 v v hys input logic hysteresis 100 mv i il input logic low current v vin = 0 v ? 5 5 a i ih input logic high current v vin = 5 v 50 70 a r pd pulldown resistance to agnd 100 k t pd propagation delay inhx/inlx input buffer and digital core propagation delay. dead time is excluded. 200 ns logic level input (nscs) v il,nscs input logic low voltage 0 0.7 v v ih,nscs input logic high voltage 1.6 5.5 v r pu,nscs pullup resistance to dvdd 50 k four-level h/w input (gain) v i1 input mode 1 voltage tied to agnd 0 v v i2 input mode 2 voltage 47 k 5% to tied agnd 1.2 v v i3 input mode 3 voltage hi-z 2 v v i4 input mode 4 voltage tied to dvdd 3.3 v r pu pullup resistance internal pullup to dvdd 50 k r pd pulldown resistance internal pulldown to agnd 84 k seven-level h/w inputs (mode, idrive, vds) v i1 input mode 1 voltage tied to agnd 0 v v i2 input mode 2 voltage 18 k 5% tied to agnd 0.5 v v i3 input mode 3 voltage 75 k 5% tied to agnd 1.1 v v i4 input mode 4 voltage hi-z 1.65 v v i5 input mode 5 voltage 75 k 5% tied to dvdd 2.2 v v i6 input mode 6 voltage 18 k 5% tied to dvdd 2.8 v v i7 input mode 7 voltage tied to dvdd 3.3 v r pu pullup resistance internal pullup to dvdd 73 k r pd pulldown resistance internal pulldown to agnd 73 k push-pull output (sdo) advance information
10 drv8343-q1 slvse12 ? march 2018 www.ti.com product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics (continued) over recommended operating conditions unless otherwise noted. typical limits apply for t a = 25 c and v vm = 24 v parameter test conditions min typ max unit r pu,sdo internal pullup to vsdo = 5 v 40 65 ? to vsdo = 3.3 v 60 95 r pd,sdo internal pulldown to gnd 30 50 ? open drain output (nfault) v ol output logic low voltage i o = 5 ma 0.1 v i oz output high impedance leakage v o = 5 v ? 2 2 a gate drivers (ghx, glx) v gsh (1) high-side gate drive voltage with respect to shx v vm = 13 v, i vcp = 0 to 25 ma, ghx no output load 8.4 11 12.5 v v vm = 10 , i vcp = 0 to 20 ma, ghx no output load 6.3 9 10 v vm = 8 v, i vcp = 0 to 15 ma, ghx no output load 5.4 7 8 v vm = 5.5 v, i vcp = 0 to 5 ma, ghx no output load 4 5 6 v gsl (1) low-side gate drive voltage with respect to pgnd v vm = 12 v, i vcp = 0 to 25 ma, glx no output load 9 11 12 v v vm = 10 v, i vcp = 0 to 20 ma, glx no output load 9.9 10.0 10.1 v vm = 8 v, i vcp = 0 to 15 ma, glx no output load 7.9 8.0 8.1 v vm = 5.5 v, i vcp = 0 to 5 ma, glx no output load 5.4 5.5 5.6 t dead gate drive dead time spi device dead_time = 00b 500 ns dead_time = 01b 1000 dead_time = 10b 2000 dead_time = 11b 4000 h/w device 1000 t drive peak current gate drive time spi device tdrive = 00b 500 ns tdrive = 01b 1000 tdrive = 10b 2000 tdrive = 11b 3000 h/w device 3000 t drive_max peak current gate drive max time idrivep_hx = 0000b, 0001b, 0010b, 0011b 20 s advance information
11 drv8343-q1 www.ti.com slvse12 ? march 2018 product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics (continued) over recommended operating conditions unless otherwise noted. typical limits apply for t a = 25 c and v vm = 24 v parameter test conditions min typ max unit i drivep peak source gate current spi device idrivep_hx or idrivep_lx = 0000b (ghx) 1.5 ma idrivep_hx or idrivep_lx = 0000b (glx) 2.7 idrivep_hx or idrivep_lx = 0001b (ghx) 3.5 idrivep_hx or idrivep_lx = 0001b (glx) 3.9 idrivep_hx or idrivep_lx = 0010b (ghx) 5 idrivep_hx or idrivep_lx = 0010b (glx) 6.5 idrivep_hx or idrivep_lx = 0011b (ghx/glx) 10 idrivep_hx or idrivep_lx = 0100b (ghx/glx) 15 idrivep_hx or idrivep_lx = 0101b (ghx/glx) 50 idrivep_hx or idrivep_lx = 0110b (ghx/glx) 60 idrivep_hx or idrivep_lx = 0111b (ghx/glx) 65 idrivep_hx or idrivep_lx = 1000b (ghx/glx) 200 idrivep_hx or idrivep_lx = 1001b (ghx/glx) 210 idrivep_hx or idrivep_lx = 1010b (ghx/glx) 260 idrivep_hx or idrivep_lx = 1011b (ghx/glx) 265 idrivep_hx or idrivep_lx = 1100b (ghx/glx) 735 idrivep_hx or idrivep_lx = 1101b (ghx/glx) 800 idrivep_hx or idrivep_lx = 1110b (ghx/glx) 935 idrivep_hx or idrivep_lx = 1111b (ghx/glx) 1000 h/w device idrive = tied to agnd (ghx) 1.5 idrive = tied to agnd (glx) 2.7 idrive = 18 k 5% tied to agnd (ghx) 5 idrive = 18 k 5% tied to agnd (glx) 6.5 idrive = 75 k 5% tied to agnd (ghx/glx) 10 idrive = hi-z (ghx/glx) 60 idrive = 75 k 5% tied to dvdd (ghx/glx) 200 idrive = 18 k 5% tied to dvdd (ghx/glx) 260 idrive = tied to dvdd (ghx/glx) 1000 advance information
12 drv8343-q1 slvse12 ? march 2018 www.ti.com product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics (continued) over recommended operating conditions unless otherwise noted. typical limits apply for t a = 25 c and v vm = 24 v parameter test conditions min typ max unit i driven peak sink gate current spi device idrivep_hx or idrivep_lx = 0000b 3 ma idrivep_hx or idrivep_lx = 0001b 7 idrivep_hx or idrivep_lx = 0010b 10 idrivep_hx or idrivep_lx = 0011b 20 idrivep_hx or idrivep_lx = 0100b 30 idrivep_hx or idrivep_lx = 0101b 100 idrivep_hx or idrivep_lx = 0110b 120 idrivep_hx or idrivep_lx = 0111b 130 idrivep_hx or idrivep_lx = 1000b 400 idrivep_hx or idrivep_lx = 1001b 420 idrivep_hx or idrivep_lx = 1010b 520 idrivep_hx or idrivep_lx = 1011b 530 idrivep_hx or idrivep_lx = 1100b 1470 idrivep_hx or idrivep_lx = 1101b 1600 idrivep_hx or idrivep_lx = 1110b 1870 idrivep_hx or idrivep_lx = 1111b 2000 h/w device idrive = tied to agnd 3 idrive = 18 k 5% tied to agnd 10 idrive = 75 k 5% tied to agnd 20 idrive = hi-z 120 idrive = 75 k 5% tied to dvdd 400 idrive = 18 k 5% tied to dvdd 520 idrive = tied to dvdd 2000 i holdp gate holding source current after t drive spi device idrivep_hx = 0000b 1.5 ma idrivep_hx = 0001b 3.5 idrivep_hx = 0010b 5 idrivep_hx = 0011b 10 all other idrive settings 15 h/w device idrive tied to agnd 1.5 idrive = 18 k 5% tied to agnd 5 idrive = 75 k 5% tied to agnd 10 all other idrive settings 15 i holdn gate holding sink current after t drive spi device idrivep_hx = 0000b 3 ma idrivep_hx = 0001b 7 idrivep_hx = 0010b 10 idrivep_hx = 0011b 20 all other idrive settings 30 h/w device idrive tied to agnd 3 idrive = 18 k 5% tied to agnd 10 idrive = 75 k 5% tied to agnd 20 all other idrive settings 30 i strong gate strong pulldown current (ghx to shx and glx to pgnd) idrivep_hx = 0000b, 0001b, 0010b, 0011b 30 ma all other idrive settings 2 a r off gate hold off resistor ghx to shx and glx to pgnd 150 k current shunt amplifier (snx, sox, spx, vref) advance information
13 drv8343-q1 www.ti.com slvse12 ? march 2018 product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics (continued) over recommended operating conditions unless otherwise noted. typical limits apply for t a = 25 c and v vm = 24 v parameter test conditions min typ max unit g csa amplifier gain spi device csa_gain = 00b, csa_fet = 0b 4.9 5 5.1 v/v csa_gain = 01b, csa_fet = 0b 9.8 10 10.2 csa_gain = 10b, csa_fet = 0b 19.6 20 20.4 csa_gain = 11b, csa_fet = 0b 39.2 40 40.8 spi device csa_gain = 00b, csa_fet = 1b 4.85 5 5.15 csa_gain = 01b, csa_fet = 1b 9.7 10 10.3 csa_gain = 10b, csa_fet = 1b 19.4 20 20.6 csa_gain = 11b, csa_fet = 1b 38.8 40 41.2 h/w device gain = tied to agnd 4.9 5 5.1 gain = 47 k 5% tied to agnd 9.8 10 10.2 gain = hi-z 19.6 20 20.4 gain = tied to dvdd 39.2 40 40.8 t set (1) settling time to 1% v o_step = 0.5 v, g csa = 5 v/v 150 ns v o_step = 0.5 v, g csa = 10 v/v 300 v o_step = 0.5 v, g vsa = 20 v/v 600 v o_step = 0.5 v, g csa = 40 v/v 1200 v com common mode input range ? 0.15 0.15 v v diff differential mode input range ? 0.3 0.3 v v off input offset error v sp = v sn = 0 v, vref = 3.3 v, g csa = 10, 20, 40 v/v ? 4 4 mv v off input offset error v sp = v sn = 0 v, vref = 3.3 v, g csa = 5 v/v ? 5 5 mv v drift (1) drift offset v sp = v sn = 0 v 10 v/ c v linear sox output voltage linear range 0.25 v vref ? 0.25 v v bias sox output voltage bias spi device v sp = v sn = 0 v, cal = 3.3 v, vref_div = 0b v vref ? 0.3 v v sp = v sn = 0 v, cal = 3.3 v, vref_div = 1b v vref / 2 h/w device v sp = v sn = 0 v, cal = 3.3 v v vref / 2 i bias spx/snx input bias current 100 a v slew (1) sox output slew rate 60-pf load 10 v/ s i vref vref input current v vref = 5 v 2 3 ma ugb (1) unity gain bandwidth 60-pf load 1 mhz protection circuits v uvlo vm undervoltage lockout vm falling, uvlo report 5.2 5.4 v vm rising, uvlo recovery 5.4 5.6 v uvlo,dvdd dvdd undervoltage lockout 2.9 v v uvlo_hys vm undervoltage hysteresis rising to falling threshold 200 mv t uvlo_deg vm undervoltage deglitch time vm falling, uvlo report 11.5 s v cpuv charge pump undervoltage lockout vcp falling, cpuv report v vm + 2.1 v v gs_clamp high-side gate clamp positive clamping voltage 15 16.5 19 v negative clamping voltage ? 0.7 v ola open load active mode detection threshold dlx ? vdrain 150 300 400 mv slx ? shx, ? 1 < slx < 0 150 300 400 i ol open load current 2.5 ma advance information
14 drv8343-q1 slvse12 ? march 2018 www.ti.com product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics (continued) over recommended operating conditions unless otherwise noted. typical limits apply for t a = 25 c and v vm = 24 v parameter test conditions min typ max unit t olp open load passive diagnostic delay spi device olp_shrt_dly = 00b 0.25 ms olp_shrt_dly = 01b 1.25 olp_shrt_dly = 10b 5 olp_shrt_dly = 11b 11.5 h/w device after t wake and t shorts elapse 5 t shorts offline short-to- battery and short- to-gnd diagnostic delay spi device olp_shrt_dly = 00b 0.1 ms olp_shrt_dly = 01b 0.5 olp_shrt_dly = 10b 2 olp_shrt_dly = 11b 4.4 h/w device after t wake elapses 2 v vds_ocp v ds overcurrent trip voltage spi device vds_lvl = 0000b 0.06 v vds_lvl = 0001b 0.13 vds_lvl = 0010b 0.2 vds_lvl = 0011b 0.26 vds_lvl = 0100b 0.31 vds_lvl = 0101b 0.45 vds_lvl = 0110b 0.53 vds_lvl = 0111b 0.6 vds_lvl = 1000b 0.68 vds_lvl = 1001b 0.75 vds_lvl = 1010b 0.94 vds_lvl = 1011b 1.13 vds_lvl = 1100b 1.3 vds_lvl = 1101b 1.5 vds_lvl = 1110b 1.7 vds_lvl = 1111b 1.88 h/w device vds = tied to agnd 0.06 vds = 18 k 5% tied to agnd 0.13 vds = 75 k 5% tied to agnd 0.26 vds = hi-z 0.6 vds = 75 k 5% tied to dvdd 1.13 vds = 18 k 5% tied to dvdd 1.88 vds = tied to dvdd disabled t ocp_deg v ds and v sense overcurrent deglitch time spi device ocp_deg=000b 2.5 s ocp_deg = 001b 4.75 ocp_deg = 010b 6.75 ocp_deg = 011b 8.75 ocp_deg = 100b 10.25 ocp_deg = 101b 11.5 ocp_deg = 110b 16.5 ocp_deg = 111b 20.5 h/w device 4.75 advance information
15 drv8343-q1 www.ti.com slvse12 ? march 2018 product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics (continued) over recommended operating conditions unless otherwise noted. typical limits apply for t a = 25 c and v vm = 24 v parameter test conditions min typ max unit v sen_ocp v sense overcurrent trip voltage spi device sen_lvl = 00b 0.25 v sen_lvl = 01b 0.5 sen_lvl = 10b 0.75 sen_lvl = 11b 1 h/w device 1 t retry overcurrent fault retry time spi device tretry = 00b 2 ms trerty = 01b 4 tretry = 10b 6 tretry = 11b 8 t hys (1) thermal hysteresis die temperature, t j 20 c t otsd (1) thermal shutdown temperature die temperature, t j 150 170 185 c t otw (1) thermal warning temperature die temperature, t j 130 150 165 c (1) specified by design and characterization data 7.6 spi timing requirements (1) over recommended operating conditions unless otherwise noted. typical limits apply for t a = 25 c and v vm = 24 v min nom max unit t ready spi ready after enable vm > uvlo, enable = 3.3 v 1 ms t clk sclk minimum period 100 ns t clkh sclk minimum high time 50 ns t clkl sclk minimum low time 50 ns t su_sdi sdi input data setup time 20 ns t h_sdi sdi input data hold time 30 ns t d_sdo sdo output data delay time sclk high to sdo valid, c l = 20 pf 30 ns t su_nscs nscs input setup time 50 ns t h_nscs nscs input hold time 50 ns t hi_nscs nscs minimum high time before active low 500 ns t dis_nscs nscs disable time nscs high to sdo high impedance 10 ns figure 1. spi slave mode timing diagram t hi_nscs t su_nscs t clk t clkh t clkl msb lsb t h_sdi t su_sdi z z msb lsb t h_nscs t dis_nscs x x t d_sdo nscs sclk sdi sdo advance information
16 drv8343-q1 slvse12 ? march 2018 www.ti.com product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 8 detailed description 8.1 overview the drv8343-q1 device is an integrated 5.5 to 60-v gate driver for three-phase motor drive applications. these devices decrease system complexity by integrating three independent half-bridge gate drivers, charge pump, and linear regulator for the supply voltages of the high-side and low-side gate drivers. the device also integrates three current shunt (or current sense) amplifiers. a standard serial peripheral interface (spi) provides a simple method for configuring the various device settings and reading fault diagnostic information through an external controller. alternatively, a hardware interface (h/w) option allows for configuring the most common settings through fixed external resistors. the gate drivers support external n-channel high-side and low-side power mosfets and can drive up to 1-a source, 2-a sink peak currents with a 25-ma average output current. a doubler charge pump generates the supply voltage of the high-side gate drive. this charge pump architecture regulates the vcp output to v vm + 11 v. the supply voltage of the low-side gate driver is generated using a linear regulator from the vm power supply that regulates to 11 v. a smart gate drive architecture provides the ability to dynamically adjust the strength of the gate drive output current which lets the gate driver control the v ds switching speed of the power mosfet. this feature lets the user remove the external gate drive resistors and diodes, reducing the component count in the bill of materials (bom), cost, and area of the printed circuit board (pcb). the architecture also uses an internal state machine to protect against short-circuit events in the gate driver, control the half-bridge dead time, and protect against dv/dt parasitic turnon of the external power mosfet. the drv8343 device integrates three bidirectional current sense amplifiers for monitoring the current level through each of the external half-bridges using a low-side shunt resistor. the gain setting of the current sense amplifiers can be adjusted through the spi or hardware interface. the spi method providing additional flexibility to adjust the output bias point. in addition to the high level of device integration, the drv8343-q1 device provides a wide range of integrated protection features. these features include power supply undervoltage lockout (uvlo), charge pump undervoltage lockout (cpuv) , short to supply (sht_bat), short-to-ground (sht_gnd), open-load detection (old), v ds overcurrent monitoring (ocp), gate driver short-circuit detection (gdf), and overtemperature shutdown (otw and otsd). fault events are indicated by the nfault pin with detailed information available in the spi registers on the spi device version. the drv8343-q1 device is available in a 0.5-mm pin pitch, 7 7 mm, htqfp surface-mount package. advance information
17 drv8343-q1 www.ti.com slvse12 ? march 2018 product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.2 functional block diagram figure 2. block diagram for drv8343h advance information gate driver gate driver gate driver digital core control inputs power vcp charge pump dvdd linear regulator vgls linear regulator protection smart gate drive output offset bias gha hs vcp gla ls vgls vm ghb hs vcp shb glb ls vgls vm ghc hs vcp shc glc ls vgls vm vdrain vm 4.7 ? f vm vcp >10 ? f cph cpl 47 nf vgls inha inla inhb inlb inhc inlc enable mode idrive vds a v a v a v r sen r sen r sen spc snc spb snb spa sna soc sob soa vref 0.1 ? f cal gain dvdd agnd 1 ? f 30 ma pgnd vcc sha dla fault output nfault r pu vcc dlc dlb sla slb slc 1 ? f
18 drv8343-q1 slvse12 ? march 2018 www.ti.com product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated functional block diagram (continued) figure 3. block diagram for drv8343s gate driver gate driver gate driver digital core power gha hs vcp sha gla ls vgls vm ghb hs vcp shb glb ls vgls vm ghc hs vcp shc glc ls vgls vm vdrain vm 4.7 ? f vm vcp >10 ? f cph cpl 47 nf vcp charge pump dvdd linear regulator vgls linear regulator vgls protection smart gate drive dvdd agnd 1 ? f 30 ma dla nfault r pu vcc fault output dlc dlb sla slb slc vcc 1 ? f control inputs output offset bias a v a v a v spi inha inla inhb inlb inhc inlc enable vsdo soc sob soa vref 0.1 ? f cal r sen r sen spc snc spb snb spa sna r sen sdi sdo sclk nscs vcc 0.1 ? f pgnd vsdo dvdd advance information
19 drv8343-q1 www.ti.com slvse12 ? march 2018 product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) the vcc pin is not a pin on the drv8343-q1 device, but a vcc supply voltage pullup is required for the open-drain output, nfault. these pins can also be pulled up to dvdd. 8.3 feature description table 1 lists the recommended values of the external components for the gate driver. table 1. drv8343-q1 external components components pin 1 pin 2 recommended c vm1 vm gnd x5r or x7r, 4.7- f, vm-rated capacitor c vm2 vm gnd 10 f, vm-rated capacitor c vcp vcp vm x5r or x7r, 50-v, 1- f capacitor c sw cph cpl x5r or x7r, 47-nf, vm-rated capacitor c dvdd dvdd agnd x5r or x7r, 1- f, 6.3-v capacitor r nfault vcc (1) nfault pullup resistor r idrive idrive agnd or dvdd drv8343-q1 hardware interface r vds vds agnd or dvdd drv8343-q1 hardware interface r mode mode agnd or dvdd drv8343-q1 hardware interface r gain gain agnd or dvdd drv8343-q1 hardware interface c vref vref agnd or dgnd optional capacitor rated for vref r asense spa sna and pgnd sense shunt resistor r bsense spb snb and pgnd sense shunt resistor r csense spc snc and pgnd sense shunt resistor 8.3.1 three phase smart gate drivers the drv8343-q1 device integrates three, half-bridge gate drivers, each capable of driving high-side and low- side n-channel power mosfets. a doubler charge pump provides the correct gate bias voltage to the high-side mosfet across a wide operating voltage range in addition to providing 100% support of the duty cycle. an internal linear regulator provides the gate bias voltage for the low-side mosfets. the half-bridge gate drivers can be used in combination to drive a three-phase motor or separately to drive other types of loads. the drv8343-q1 device implements a smart gate drive architecture which allows the user to dynamically adjust the gate drive current without requiring external resistors to limit the gate current. additionally, this architecture provides a variety of protection features for the external mosfets including automatic dead time insertion, prevent of parasitic dv/dt gate turnon, and gate fault detection. 8.3.1.1 pwm control modes the drv8343-q1 device provides eight different pwm control modes in the spi device and seven different modes in the h/w device to support various commutation and control methods. texas instruments does not recommend changing the mode pin or pwm_mode register during operation of the power mosfets. set all inhx and inlx pins to logic low before making a mode pin or pwm_mode register change. table 2 shows the different mode settings for the spi device. the mode bit setting of 100b is not available in the h/w device. table 2. 6x pwm mode truth table h/w device spi device mode settings tied to agnd 000b 6x pwm 18 k to agnd 001b 3x pwm 75 k to agnd 010b 1x pwm hi-z 011b independent half-bridge (for all three half-bridges) not available 100b phases a and b are independent half-bridges, phase c is independent fet 75 k to dvdd 101b phases b and c are independent half-bridges, phase a is independent fet 18 k to dvdd 110b phases a is independent half-bridge, phase b and c are independent fet tied to dvdd 111b independent mosfet (for all three half-bridges) advance information
20 drv8343-q1 slvse12 ? march 2018 www.ti.com product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.3.1.1.1 6x pwm mode (pwm_mode = 000b or mode pin tied to agnd) in 6x pwm mode, each half-bridge supports three output states: low, high, or high-impedance (hi-z). the corresponding inhx and inlx signals control the output state as listed in table 3 . table 3. 6x pwm mode truth table inlx inhx glx ghx shx + dlx 0 0 l l hi-z 0 1 l h h 1 0 h l l 1 1 l l hi-z figure 4. 6-pwm mode 8.3.1.1.2 3x pwm mode (pwm_mode = 001b or mode pin = 18 k to agnd) in 3x pwm mode, the inhx pin controls each half-bridge and supports two output states: low or high. the inlx pin is used to put the half bridge in the hi-z state. if the hi-z state is not required, tie all inlx pins to logic high. the corresponding inhx and inlx signals control the output state as listed in table 4 . table 4. 3x pwm mode truth table inlx inhx glx ghx shx + dlx 0 x l l hi-z 1 0 h l l 1 1 l h h 6-pwm inha inla inhb inlb inhc inlc mcu pwm mcu pwm mcu pwm mcu pwm mcu pwm mcu pwm advance information
21 drv8343-q1 www.ti.com slvse12 ? march 2018 product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) !pwm is the inverse of the pwm signal. figure 5. 3-pwm mode 8.3.1.1.3 1x pwm mode (pwm_mode = 010b or mode pin = 75 k to agnd) in 1x pwm mode, the drv8343-q1 device uses 6-step block commutation tables that are stored internally. this feature allows for a three-phase bldc motor to be controlled using one pwm sourced from a simple controller. the pwm is applied on the inha pin and determines the output frequency and duty cycle of the half-bridges. the half-bridge output states are managed by the inla, inhb, and inlb pins which are used as state logic inputs. the state inputs can be controlled by an external controller or connected directly to the digital outputs of the hall effect sensor from the motor (inla = hall_a, inhb = hall_b, inlb = hall_c). the 1x pwm mode usually operates with synchronous rectification (low-side mosfet recirculation); however, the mode can be configured to use asynchronous rectification (mosfet body diode freewheeling) on spi devices. this configuration is set using the 1pwm_com bit in the spi registers. the inhc input controls the direction through the 6-step commutation table which is used to change the direction of the motor when hall effect sensors are directly controlling the state of the inla, inhb, and inlb inputs. tie the inhc pin low if this feature is not required. the inlc input brakes the motor by turning off all high-side mosfets and turning on all low-side mosfets when the inlc pin is pulled low. this brake is independent of the state of the other input pins. tie the inlc pin high if this feature is not required. in the spi device, the brake and coast mode can also be selected by the 1pwm_brake register (see table 21 ). table 5. synchronous 1x pwm mode logic and hall inputs gate drive outputs (1) state inhc = 0 inhc = 1 phase a phase b phase c description inla inhb inlb inla inhb inlb gha gla ghb glb ghc glc stop 0 0 0 0 0 0 l l l l l l stop align 1 1 1 1 1 1 pwm !pwm l h l h align 1 1 1 0 0 0 1 l l pwm !pwm l h b c 2 1 0 0 0 1 1 pwm !pwm l l l h a c 3 1 0 1 0 1 0 pwm !pwm l h l l a b 4 0 0 1 1 1 0 l l l h pwm !pwm c b 5 0 1 1 1 0 0 l h l l pwm !pwm c a 6 0 1 0 1 0 1 l h pwm !pwm l l b a 3-pwm inha inla inhb inlb inhc inlc mcu pwm mcu pwm mcu pwm advance information
22 drv8343-q1 slvse12 ? march 2018 www.ti.com product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated table 6. asynchronous 1x pwm mode 1pwm_com = 1 (spi only) logic and hall inputs gate drive outputs state inhc = 0 inhc = 1 phase a phase b phase c description inla inhb inlb inla inhb inlb gha gla ghb glb ghc glc stop 0 0 0 0 0 0 l l l l l l stop align 1 1 1 1 1 1 pwm l l h l h align 1 1 1 0 0 0 1 l l pwm l l h b c 2 1 0 0 0 1 1 pwm l l l l h a c 3 1 0 1 0 1 0 pwm l l h l l a b 4 0 0 1 1 1 0 l l l h pwm l c b 5 0 1 1 1 0 0 l h l l pwm l c a 6 0 1 0 1 0 1 l h pwm l l l b a figure 6 and figure 7 show the different possible configurations in 1x pwm mode. figure 6. 1x pwm ? simple controller figure 7. 1x pwm ? hall effect sensor 8.3.1.1.4 independent half-bridge pwm mode (pwm_mode = 011b or mode pin is > 500 k to agnd or hi-z) in independent half-bridge pwm mode, the inhx pin controls each half-bridge independently and supports two output states: low or high. the corresponding inhx and inlx signals control the output state as listed in table 7 . the inlx pin is used to change the half-bridge to high impedance. if the high-impedance (hi-z) state is not required, tie all inlx pins logic high. table 7. independent half-bridge mode truth table inlx inhx glx ghx 0 x l l 1 0 h l 1 1 l h 8.3.1.1.5 phases a and b are independent half-bridges, phase c is independent fet (mode = 100b) in this mode, phases a and b are independent half-bridge control, with independent fault handling and dead time enforcement by the device. phase c is independent fet mode where the dead time inserted by the device is bypassed and both mosfets can be turned-on at the same time. this mode is not available in the h/w version. 8.3.1.1.6 phases b and c are independent half-bridges, phase a is independent fet (mode = 101b or mode pin is 75 k to dvdd) in this mode, phases b and c are independent half-bridge control, with independent fault handling and dead time enforcement by the device. phase a is independent fet mode where the dead time inserted by the device is bypassed and both mosfets can be turned-on at the same time. 8.3.1.1.7 phases a is independent half-bridge, phases b and c are independent fet (mode = 110b or mode pin is 18 k to dvdd) in this mode, phase a is independent half-bridge control, with dead time enforcement by the device. phases b and c are independent fet mode where the dead time is bypassed and both mosfets in a given phase can be turned-on at the same time. fault handling is also done independently for each fet in phases b and c. inha inla inhb inlb inhc inlc pwm state0 state1 state2 dir nbrake mcu_pwm mcu_gpio mcu_gpio bldc motor h h h advance information inha inla inhb inlb inhc inlc pwm state0 state1 state2 dir nbrake mcu_pwm mcu_gpio mcu_gpio mcu_gpio mcu_gpio mcu_gpio bldc motor
23 drv8343-q1 www.ti.com slvse12 ? march 2018 product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.3.1.1.8 independent mosfet drive mode (pwm_mode = 111b or mode pin tied to dvdd) in independent mosfet drive mode, the inhx and inlx pins control the outputs, ghx and glx, respectively. this control mode lets the drv8343-q1 device drive separate high-side and low-side loads with each half- bridge. these types of loads include unidirectional brushed dc motors, solenoids, and low-side and high-side switches. in this mode, turning on both the high-side and low-side mosfets at the same time in a given half- bridge gate driver is possible to use the device as a high-side or low-side driver. the dead time (t dead ) is bypassed in the mode and must be inserted by the external mcu. table 8. independent pwm mode truth table inlx inhx glx ghx 0 0 l l 0 1 l h 1 0 h l 1 1 h h figure 8 shows how the drv8343-q1 device can be used to connect a high-side load and a low-side load at the same time with one half-bridge and drive the loads independently. in this mode, the vds monitors are active for both the mosfets to protect from an overcurrent condition. figure 8. independent pwm high-side and low-side drivers if the half-bridge is used to implement only a high-side or low-side driver, using the vds monitors to help protect from an overcurrent condition is possible as shown in figure 9 or figure 10 . the unused gate driver can stay disconnected. advance information inhx inlx ghx gate driver hs vcp shx glx ls vgls vm vdrain slx/spx v ds v ds + + load load dlx
24 drv8343-q1 slvse12 ? march 2018 www.ti.com product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated figure 9. one high-side driver figure 10. one low-side driver figure 11 shows how the drv8343-q1 device can be used to connect a solenoid load where both the high-side and low-side mosfets can be turned on at the same time to drive the load without causing shoot-through. ti recommends having the external diodes for current recirculation. if a half-bridge is not used, the gate pins (ghx and glx) can stay unconnected and the sense pins (shx and dlx) can be tied directly or with a resistor to gnd. figure 11. solenoid drive configuration 8.3.1.2 device interface modes the drv8343-q1 device supports two different interface modes (spi and hardware) to let the end application design for either flexibility or simplicity. the two interface modes share the same four pins, allowing the different versions to be pin-to-pin compatible. this compatibility lets application designers evaluate with one interface version and potentially switch to another with minimal modifications to their circuit design and layout. 8.3.1.2.1 serial peripheral interface (spi) the spi devices support a serial communication bus that lets an external controller send and receive data with the drv8343-q1 device. this support lets the external controller configure device settings and read detailed fault information. the interface is a four wire interface using the sclk, sdi, sdo, and nscs pins which are described as follows: inhx inlx ghx gate driver hs vcp shx glx ls vgls vm vdrain slx/spx v ds v ds + + load dlx inhx inlx ghx gate driver hs vcp shx glx ls vgls vm vdrain slx/spx v ds v ds + + load dlx advance information + hs_vsd ghx shx vdrain + glx dlx slx ph_c + hs_vsd ghx shx vdrain + glx dlx slx ph_b + hs_vsd ghx shx vdrain + glx dlx slx ph_a ls_vsd ls_vsd ls_vsd
25 drv8343-q1 www.ti.com slvse12 ? march 2018 product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated ? the sclk pin is an input that accepts a clock signal to determine when data is captured and propagated on the sdi and sdo pins. ? the sdi pin is the data input. ? the sdo pin is the data output. the sdo pin has a push-pull output structure. ? the nscs pin is the chip select input. a logic low signal on this pin enables spi communication with the drv8343-q1 device. for more information on the spi, see the spi communication section. 8.3.1.2.2 hardware interface hardware interface devices convert the four spi pins into four resistor-configurable inputs which are gain, idrive, mode, and vds. this conversion lets the application designer configure the most common device settings by tying the pin logic high or logic low, or with a simple pullup or pulldown resistor. this removes the requirement for an spi bus from the external controller. general fault information can still be obtained through the nfault pin. ? the gain pin configures the gain of the current sense amplifier. ? the idrive pin configures the gate drive current strength. ? the mode pin configures the pwm control mode. ? the vds pin configures the voltage threshold of the v ds overcurrent monitors. for more information on the hardware interface, see the pin diagrams section. figure 12. spi figure 13. hardware interface 8.3.1.3 gate driver voltage supplies the voltage supply for the high-side gate driver is created using a doubler charge pump that operates from the vm voltage supply input. the charge pump lets the gate driver correctly bias the high-side mosfet gate with respect to the source across a wide input supply voltage range. the charge pump is regulated to keep a fixed output voltage of v vm + 11 v and supports an average output current of 25 ma. when v vm is less than 12 v, the charge pump operates in full doubler mode and generates v vcp = 2 v vm ? 1.5 v when unloaded. the charge pump is continuously monitored for undervoltage events to prevent under-driven mosfet conditions. the charge pump requires a x5r or x7r, 1- f, 50-v ceramic capacitor between the vm and vcp pins to act as the storage capacitor. additionally, a x5r or x7r, 47-nf, vm-rated ceramic capacitor is required between the cph and cpl pins to act as the flying capacitor. advance information idrive mode gain vds r gain dvdd dvdd dvdd dvdd dvdd dvdd r vds hardware interface sdi sdo sclk spi nscs dvdd vsdo
26 drv8343-q1 slvse12 ? march 2018 www.ti.com product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated figure 14. charge pump architecture the voltage supply of the low-side gate driver is created using a linear regulator that operates from the vm voltage supply input. the linear regulator lets the gate driver correctly bias the low-side mosfet gate with respect to ground. the linear regulator output is fixed at 11 v and supports an output current of 25 ma. 8.3.1.4 smart gate drive architecture the drv8343-q1 gate drivers use an adjustable, complimentary, push-pull topology for both the high-side and low-side drivers. this topology allows for both a strong pullup and pulldown of the external mosfet gates. figure 15. charge pump architecture additionally, the gate drivers use a smart gate drive architecture to provide additional control of the external power mosfets, additional steps to protect the mosfets, and optimal tradeoffs between efficiency and robustness. this architecture is implemented through two components called idrive and tdrive which are described in the idrive: mosfet slew-rate control section and tdrive: mosfet gate drive control section. figure 16 shows the high-level functional block diagram of the gate driver. advance information vm vcp 1 ? f vm cph charge pump control vm cpl 47 nf v gate v drain gate drive (internal) mosfet (external) v gate v gate v gate 10 ma 60 ma 210 ma 1 a 20 ma 120 ma 420 ma 2 a i source off on off off off off off off
27 drv8343-q1 www.ti.com slvse12 ? march 2018 product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated the idrive gate drive current and tdrive gate drive time should be initially selected based on the parameters of the external power mosfet used in the system and the desired rise and fall times (see the application and implementation section). the high-side gate driver also implements a zener clamp diode to help protect the external mosfet gate from overvoltage conditions in the case of external short-circuit events on the mosfet. figure 16. gate driver block diagram 8.3.1.4.1 idrive: mosfet slew-rate control the idrive component implements adjustable gate drive current to control the mosfet v ds slew rates. the mosfet v ds slew rates are a critical factor for optimizing radiated emissions, energy, and duration of diode recovery spikes, dv/dt gate turnon resulting in shoot-through, and switching voltage transients related to parasitics in the external half-bridge. the idrive component operates on the principal that the mosfet v ds slew rates are predominately determined by the rate of gate charge (or gate current) delivered during the mosfet q gd or miller charging region. by letting the gate driver adjust the gate current, the gate driver can effectively control the slew rate of the external power mosfets. the idrive component lets the drv8343-q1 device dynamically switch between gate drive currents either through a register setting on spi devices or the idrive pin on hardware interface devices. the spi devices provide 16 i drive settings ranging from 1.5-ma to 1-a source and 3-ma to 2-a sink. hardware interface devices provide 7 i drive settings within the same ranges. the setting of the gate drive current is delivered to the gate during the turnon and turnoff of the external power mosfet for the t drive duration. after the mosfet turnon or turnoff, the gate driver switches to a smaller hold current (i hold ) to improve the gate driver efficiency. in the event of an overcurrent condition, the idrive component is automatically decreased to help prevent device damage. for additional details on the idrive settings, see the register maps section for the spi devices and the pin diagrams section for the hardware interface devices. 8.3.1.4.2 tdrive: mosfet gate drive control the tdrive component is an integrated gate drive state machine that provides automatic dead time insertion through handshaking between the high-side and low-side gate drivers, parasitic dv/dt gate turnon prevention, and mosfet gate fault detection. advance information inlx control inputs inhx digital core level shifters vcp 150 k v gs + ghx shx vm level shifters vgls 150 k v gs + glx pgnd slx/spx dlx
28 drv8343-q1 slvse12 ? march 2018 www.ti.com product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated the first component of the tdrive state machine is automatic dead time insertion. dead time is period of time between the switching of the external high-side and low-side mosfets to make sure that they do not cross conduct and cause shoot-through. the drv8343-q1 device uses v gs voltage monitors to measure the mosfet gate-to-source voltage and determine the correct time to switch instead of relying on a fixed time value. this feature lets the dead time of the gate driver adjust for variation in the system such as temperature drift and variation in the mosfet parameters. an additional digital dead time (t dead ) can be inserted and is adjustable through the registers on spi devices. the second component of the tdrive state machine is parasitic dv/dt gate turnon prevention. to implement this component, the tdrive state machine enables a strong pulldown current (i strong ) on the opposite mosfet gate whenever a mosfet is switching. the strong pulldown occurs for the tdrive duration. this feature helps remove parasitic charge that couples into the mosfet gate when the voltage half-bridge switch node slews rapidly. the third component implements a gate-fault detection scheme to detect pin-to-pin solder defects, a mosfet gate failure, or a mosfet gate stuck-high or stuck-low voltage condition. this implementation is done with a pair of v gs gate-to-source voltage monitors for each half-bridge gate driver. when the gate driver receives a command to change the state of the half-bridge it starts to monitor the gate voltage of the external mosfet. if, at the end of the t drive period, the v gs voltage has not increased the correct threshold, the gate driver reports a fault. to make sure that a false gate drive fault (gdf) is not detected, a t drive time should be selected that is longer than the time required to charge or discharge the mosfet gate. the t drive time does not increase the pwm time and will terminate if another pwm command is received while active. in the spi device, for idrive bit settings of 0000b, 0001b, 0010b, and 0011b, a longer t drive time of 20- s is automatically selected by the tdrive_max bit. if the 20- s t drvie time is not required, write a 0 to the tdrive_max bit to disable it and set the t drive time by the tdrive bits. for all other idrive settings, writing to the tdrive_max bit is disabled. this option is not available in the h/w device. for additional details on the tdrive settings, see the register maps section for spi devices and the pin diagrams section for hardware interface devices. figure 17 shows an example of the tdrive state machine in operation. figure 17. tdrive state machine v ghx v inhx v inlx i ghx i drive i hold v glx t drive t dead i glx i drive i hold t dead t drive i drive i strong t drive t dead t dead t drive i hold i hold i hold i hold i strong i drive i hold i hold advance information
29 drv8343-q1 www.ti.com slvse12 ? march 2018 product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.3.1.4.3 propagation delay the propagation delay time (t pd ) is measured as the time between an input logic edge to a detected output change. this time has three parts consisting of the digital input deglitcher delay, the digital propagation delay, and the delay through the analog gate drivers. the input deglitcher prevents high-frequency noise on the input pins from affecting the output state of the gate drivers. to support multiple control modes and dead time insertion, a small digital delay is added as the input command propagates through the device. lastly, the analog gate drivers have a small delay that contributes to the overall propagation delay of the device. 8.3.1.4.4 mosfet v ds monitors the gate drivers implement adjustable v ds voltage monitors to detect overcurrent or short-circuit conditions on the external power mosfets. when the monitored voltage is greater than the v ds trip point (v vds_ocp ) for longer than the deglitch time (t ocp ), an overcurrent condition is detected and action is taken according to the device v ds fault mode. the high-side v ds monitors measure the voltage between the vdrain and shx pins. the low-side v ds monitors measure the voltage between the dlx and slx pins. if the current sense amplifier is unused, tie the sp pins to the common ground point of the external half-bridges. for the spi devices, the reference point of the low-side v ds monitor can be changed between the spx and snx pins if desired with the ls_ref register setting. the v vds_ocp threshold is programmable from 0.06 v to 1.88 v. for additional information on the v ds monitor levels, see the register maps section for spi devices and in the pin diagrams section hardware interface device. figure 18. drv8343-q1 v ds monitors 8.3.1.4.5 vdrain sense pin the drv8343-q1 device provides a separate sense pin for the common point of the high-side mosfet drain. this pin is called vdrain. this pin lets the sense line for the overcurrent monitors (vdrain) and the power supply (vm) stay separate and prevent noise on the vdrain sense line. this separation also lets implementation of a small filter on the gate driver supply (vm) or insertion of a boost converter to support lower voltage operation if desired. care must still be used when designing the filter or separate supply because vm is still the reference point for the vcp charge pump that supplies the high-side gate drive voltage (v gsh ). the vm supply must not drift too far from the vdrain supply to avoid violating the v gs voltage specification of the external power mosfets. ghx shx glx vm vdrain slx + v ds + v ds + v ds + v ds r sense snx pgnd ls_ref (spi only) 0 1 v vds_ocp v vds_ocp dlx advance information
30 drv8343-q1 slvse12 ? march 2018 www.ti.com product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.3.1.4.6 nfault pin the nfault pin has an open-drain output and should be pulled up to a 5 v or 3.3 v supply. when a fault is detected, the nfault line is logic low. for a 3.3-v pullup the nfault pin can be tied to the dvdd pin with a resistor (refer to the application and implementation section). for a 5-v pullup an external 5-v supply must be used. figure 19. nfault pin during the power-up sequence, or when going from sleep mode, the digital core of the device is enabled to a vm voltage of approximately 3.3 v and the device is fully operational after vm exceeds 5.5 v. after the digital core is alive if the vm does not exceed 5.5 v within 100- s the device will flag a uvlo fault. in the h/w device, the nfault pin is driven low. in the spi device, the fault and ulvo bits will be latched high 8.3.2 dvdd linear voltage regulator a 3.3-v, 30-ma linear regulator is integrated into the drv8343-q1 device and is available for use by external circuitry. this regulator can provide the supply voltage for a low-power mcu or other circuitry supporting low current. the output of the dvdd regulator should be bypassed near the dvdd pin with a x5r or x7r, 1- f, 6.3- v ceramic capacitor routed directly back to the adjacent agnd ground pin. the dvdd nominal, no-load output voltage is 3.3 v. when the dvdd load current exceeds 30 ma, the regulator functions like a constant-current source. the output voltage drops significantly with a current load greater than 30 ma. figure 20. dvdd linear regulator block diagram use equation 1 to calculate the power dissipated in the device by the dvdd linear regulator. (1) for example, at a v vm of 24 v, drawing 20 ma out of dvdd results in a power dissipation as shown in equation 2 . (2) p 24 v 3.3 v 20 ma 414 mw u vm dvdd dvdd p v v i u dvdd agnd + 0.1 ? f 3.3 v, 30 ma vm ref output nfault advance information
31 drv8343-q1 www.ti.com slvse12 ? march 2018 product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.3.3 pin diagrams figure 21 shows the input structure for the logic level pins, inhx, inlx, cal, enable, nscs, sclk, and sdi. the input can be driven with a voltage or external resistor. figure 21. logic-level input pin structure figure 22 shows the structure of the four level input pin, gain, on hardware interface devices. the input can be set with an external resistor. figure 22. four level input pin structure figure 23 shows the structure of the seven level input pins, mode, idrive and vds, on hardware interface devices. the input can be set with an external resistor. advance information dvdd logic high input v ih state tied to dvdd resistance v il tied to agnd logic low 100 k 40 v/v gain 20v/v 10 v/v 5 v/v + + + dvdd v i4 state tied to dvdd resistance v i3 hi-z (>500 k ?wr agnd) v i2 47 n?? 5% to agnd v i1 tied to agnd dvdd 50 k 84 k
32 drv8343-q1 slvse12 ? march 2018 www.ti.com product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated figure 23. seven level input pin structure figure 24 shows the structure of the open-drain output pin, nfault. the open-drain output requires an external pullup resistor to function correctly. figure 24. open-drain output pin structure 8.3.4 low-side current sense amplifiers the drv8343-q1 integrates three, high-performance low-side current sense amplifiers for current measurements using low-side shunt resistors in the external half-bridges. low-side current measurements are commonly used to implement overcurrent protection, external torque control, or brushless dc commutation with the external controller. all three amplifiers can be used to sense the current in each of the half-bridge legs or one amplifier can be used to sense the sum of the half-bridge legs. the current sense amplifiers include features such as programmable gain, offset calibration, unidirectional and bidirectional support, and a voltage reference pin (vref). 1/2 a idrive 260 / 520 ma 200 / 400 ma 60 / 120 ma + + + dvdd v i7 state tied to dvdd resistance v i6 18 k 5% to dvdd v i5 75 k 5% to dvdd v i4 hi-z (>500 k ? to agnd) dvdd v i3 75 k 5% to agnd v i2 18 n?? 5% to agnd v i1 tied to agnd + + + 10 / 20 ma 5 / 10 ma 1.5 / 3 ma 73 k 73 k disabled vds 1.88 v 1.13 v 0.60 v 0.26 v 0.13 v 0.06 v independent mosfet mode ph a as ind. half bridge ph b & ph c as ind. fet ph b & ph c as ind. half bridge, ph a as ind. fet independent half-bridge 1x pwm 3x pwm 6x pwm dvdd active output no fault state inactive status fault active inactive r pu advance information
33 drv8343-q1 www.ti.com slvse12 ? march 2018 product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.3.4.1 bidirectional current sense operation the sox pin on the drv8343 outputs an analog voltage equal to the voltage across the spx and snx pins multiplied by the gain setting (g csa ). the gain setting is adjustable between four different levels: 5 v/v, 10 v/v, 20 v/v, and 40 v/v. use equation 3 to calculate the current through the shunt resistor. (3) figure 25. bidirectional current sense configuration figure 26. bidirectional current sense output spx snx sox v ref ? + + i 0.1 ? f r6 r4 r3 r2 r5 r1 r1 r4 r3 r2 r5 r sense v cc vref sox csa sense v v 2 i g r u so (v) sp sn (v) v ref v vref / 2 v linear advance information
34 drv8343-q1 slvse12 ? march 2018 www.ti.com product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated figure 27. bidirectional current sense regions 0 v v vref / 2 v so(off)max v so(off)min vref v vref 0.25 v 0.25 v 0 v i r i r so sp sn so v off , v drift 0.3 v 0.3 v v so(range ) v so(range+) spsn r i a v advance information
35 drv8343-q1 www.ti.com slvse12 ? march 2018 product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.3.4.2 unidirectional current sense operation (spi only) on the drv8343-q1 spi device, use the vref_div bit to remove the vref divider. in this case the curren sense amplifier operates unidirectionally and the sox pin outputs an analog voltage equal to the voltage across the spx and snx pins multiplied by the gain setting (g csa ). use equation 4 to calculate the current through the shunt resistor. (4) figure 28. unidirectional current-sense configuration figure 29. unidirectional current-sense output spx snx sox v ref + + i 0.1 ? f r6 r4 r3 r2 r5 r1 r1 r4 r3 r2 r5 r sense v cc vref sox csa sense v v i g r u advance information so (v) sp sn (v) v ref v vref 0.3 v v linear
36 drv8343-q1 slvse12 ? march 2018 www.ti.com product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated figure 30. unidirectional current-sense regions 8.3.4.3 amplifier calibration modes to minimize dc offset and drift over temperature, a dc calibration mode is provided and enabled through the spi register (csa_cal_x). this option is not available on the h/w interface device. when the calibration setting is enabled, the inputs to the amplifier are shorted and the shunt resistor is disconnected. dc calibration can be done at any time, even when the half-bridges are operating. for the best results, perform manual calibration during the switching off period to decrease the potential noise impact to the amplifier. figure 31 shows a diagram of the calibration mode. when a csa_cal_x bit is enabled, the corresponding amplifier goes to the calibration mode. in both the spi and h/w device options, the cal pin can be used to perform dc calibration to all the three amplifiers at the same time. when the cal pin is pulled high, the inputs of all the three amplifiers are shorted and the shunt resistors are disconnected which lets the host microcontroller perform manual calibration. figure 31. amplifier manual calibration advance information v vref 0.3 v v so(off)max v so(off)min v ref v vref 0.25 v 0.25 v 0 v 0 v i r so sp sn so v off , v drift 0.3 v v so(range) spsn r i a v r sense !cal !cal r sp sp r sn sn cal cal r f - + - + r g r out vref sox
37 drv8343-q1 www.ti.com slvse12 ? march 2018 product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated in addition to the manual calibration, the drv8343-q1 device provides an auto calibration feature on both the spi and h/w device versions to minimize the amplifier input offset after power up and during run time to account for temperature and device variation. auto calibration is automatically performed on device power up for both the h/w and spi device options. the power up auto calibration starts immediately after the vref pin crosses the minimum operational vref voltage. wait 50 s for the power up auto calibration routine to complete after the vref pin voltage crosses the minimum vref operational voltage. the auto calibration functions by performing a trim routine of the amplifier to minimize the amplifier input offset, after which the trim codes are stored in the device and the amplifiers are ready for normal operation. for the spi device option, auto calibration can also be performed again during run time by enabling the cal_mode register setting. note auto calibration happens only in the bidirectional mode. if unidirectional mode is selected and auto calibration is commanded, the amplifier will switch to bidirectional mode to perform the auto calibration routine. after auto calibration routine is complete, the amplifier will revert to unidirectional mode. for the spi device option, auto calibration can also be performed again during run time by enabling the auto_cal register setting. auto calibration can then be commanded with the corresponding csa_cal_x register setting to rerun the auto calibration routine. during auto calibration all of the amplifiers will be configured for the maximum gain setting in order to improve the accuracy of the calibration routine. for manual calibration, after writing a 1 to the cal_csa_x bits or taking the cal pin high, the micro-controller needs to wait for 50 s before performing manual calibration. this 50 s wait time is for the auto calibration routine to complete. ti recommends that after the 50 s expires, the micro-controller reads the outputs of the amplifiers to determine the offset and then perform the manual calibration routine. 8.3.4.4 mosfet v ds sense mode (spi only) the current sense amplifiers on the drv8343-q1 spi device can be configured to amplify the voltage across the external low-side mosfet v ds . this configuration lets the external controller measure the voltage drop across the mosfet r ds(on) without the shunt resistor and then calculate the half-bridge current level. this setting is not available in the h/w device. to enable this mode set the csa_fet bit to 1. the positive input of the amplifier is then internally connected to the dlx pin with an internal clamp to prevent high voltage on the dlx pin from damaging the sense amplifier inputs. during this mode of operation, the spx pins should stay disconnected. when the csa_fet bit is set to 1, the negative reference for the low-side v ds monitor is automatically set to the snx pin, regardless of the state of the state of the ls_ref bit. this setting is implemented to prevent disabling of the low-side v ds monitor. if the system operates in mosfet v ds current sense mode, route the dlx and snx pins with kelvin connections across the drain and source of the external low-side mosfets. advance information
38 drv8343-q1 slvse12 ? march 2018 www.ti.com product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated figure 32. resistor sense configuration figure 33. v ds current sense mode when operating in mosfet v ds current sense mode, the amplifier is enabled at the end of the t drive time. at this time, the amplifier input is connected to the dlx pin, and the sox output is valid. when the low-side mosfet receives a signal to turn off, the amplifier inputs, spx and snx, are shorted together internally. 8.3.5 gate driver protective circuits the drv8343-q1 device is protected against vm undervoltage, charge pump undervoltage, mosfet vds overcurrent, gate driver shorts, and overtemperature events. the drv8343-q1 device also provides a detection mechanism for open-load, offline short-to-supply, and offline short-to-ground conditions. when a fault occurs, the individual fault bit is set high along with the global fault bit in the fault status register for the spi device. the fault bit is or ? ed with all the other individual status bits. in the h/w device, only the nfault pin is driven low during a fault condition. some of the protection and detection features can be disabled through spi in the spi device, or the ndiag pin in the h/w device ghx shx glx agnd vdrain snx spx a v sox 0 1 csa_fet = 0 ls_ref = 0 (spi only) vm + v ds low-side v ds monitor + v ds high-side v ds monitor 10 k 10 k 10 k dlx r sense slx advance information glx agnd snx spx a v 0 1 csa_fet = 1 ls_ref = x (spi only) + v ds low-side v ds monitor 10 k 10 k 10 k dlx ghx shx vdrain vm + v ds high-side v ds monitor sox slx
drv8343-q1 www.ti.com slvse12 ? march 2018 39 product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated table 9. fault action and response fault condition configuration report gate driver logic recovery vm undervoltage (uvlo) v vm < v uvlo ? nfault hi-z disabled automatic: v vm > v uvlo charge pump undervoltage (cpuv) v vcp < v cpuv dis_cpuv = 0b nfault hi-z active automatic: v vcp > v cpuv dis_cpuv = 1b none active active v ds overcurrent (vds_ocp) v ds > v vds_ocp ocp_mode = 00b nfault hi-z active latched: clr_flt, enable pulse ocp_mode = 01b nfault hi-z active retry: t retry ocp_mode = 10b nfault active active report only ocp_mode = 11b none active active no action v sense overcurrent (sen_ocp) v sp > v sen_ocp ocp_mode = 00b nfault hi-z active latched: clr_flt, enable pulse ocp_mode = 01b nfault hi-z active retry: t retry ocp_mode = 10b nfault active active report only ocp_mode = 11b none active active no action gate driver fault (gdf) gate voltage stuck > t drive dis_gdf = 0b nfault hi-z active latched: clr_flt, enable pulse dis_gdf = 1b none active active no action thermal warning (otw) t j > t otw otw_rep = 0b none active active no action otw_rep = 1b nfault active active automatic: t j < t otw ? t hys thermal shutdown (otsd) t j > t otsd otsd_mode = 0b nfault hi-z active latched: clr_flt, enable pulse otsd_mode = 1b nfault hi-z active automatic: t j < t otsd ? t hys open load passive (olp) no load detected en_olp = 0b none hi-z active no action en_olp = 1b nfault hi-z active report only open load active (ola) no load detected en_ola_x = 0b none active active no action en_ola_x = 1b nfault active active report only offline short-to-supply (sht_bat) phase node short-to-supply en_sht_tst = 0b none hi-z active no action en_sht_tst = 1b nfault hi-z active report only offline short-to-ground (sht_gnd) phase node short-to-ground en_sht_tst = 0b none hi-z active no action en_sht_tst = 1b nfault hi-z active report only advance information
40 drv8343-q1 slvse12 ? march 2018 www.ti.com product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.3.5.1 vm supply undervoltage lockout (uvlo) if at any time the input supply voltage on the vm pin falls lower than the v uvlo threshold, all of the external mosfets are disabled, the charge pump is disabled, and the nfault pin is driven low. the fault and vm_uvlo bits are also latched high in the registers on spi devices. normal operation starts again (gate driver operation and the nfault pin is released) when the vm undervoltage condition clears. the vm_uvlo bit stays set until cleared through the clr_flt bit or an enable pin reset pulse (t rst ). 8.3.5.2 vcp charge pump undervoltage lockout (cpuv) if at any time the voltage on the vcp pin (charge pump) falls lower than the cpuv threshold voltage of the charge pump, all of the external mosfets are disabled and the nfault pin is driven low. the fault and cpuv bits are also latched high in the registers in the spi device. normal operation starts again (gate driver operation and the nfault pin is released) when the vcp undervoltage condition is removed. the fault and cpuv bits stay set until cleared through the clr_flt bit or an enable pin reset pulse (t rst ). setting the dis_cpuv bit high on the spi devices disables this protection feature. if the dis_cpuv bit is set high and a charge pump undervoltage condition occurs, the device keeps operating but the cpuv fault bit is set high in the spi register until cleared through the clr_flt bit or an enable pin reset pulse (t rst ). cpuv protection cannot be disabled in the h/w device. 8.3.5.3 mosfet v ds overcurrent protection (vds_ocp) a mosfet overcurrent event is sensed by monitoring the vds voltage drop across the external mosfet r ds(on) . if the voltage across an enabled mosfet exceeds the v vds_ocp threshold for longer than the t ocp_deg deglitch time, a vds_ocp event is recognized and action is done according to the ocp_mode. on hardware interface devices, the v vds_ocp threshold is set with the vds pin, the t ocp_deg is fixed at 4 s, and the ocp_mode is configured for latched shutdown but can be disabled by tying the vds pin to dvdd. in the spi device, the v vds_ocp threshold is set through the vds_lvl spi register, the t ocp_deg is set through the ocp_deg bits in the spi register, and the ocp_mode bit can operate in four different modes: v ds latched shutdown, v ds automatic retry, v ds report only, and v ds disabled. 8.3.5.3.1 v ds latched shutdown (ocp_mode = 00b) after a vds_ocp event in this mode, all external mosfets are disabled and the nfault pin is driven low. the fault, vds_ocp, and corresponding mosfet ocp bits are latched high in the spi registers. normal operation starts again (gate driver operation and the nfault pin is released) when the vds_ocp condition clears and a clear faults command is issued either through the clr_flt bit or an enable reset pulse (t rst ). this is the default mode in both the h/w and spi device options. 8.3.5.3.2 v ds automatic retry (ocp_mode = 01b) after a vds_ocp event in this mode, all the external mosfets are disabled and the nfault pin is driven low. the fault, vds_ocp, and corresponding mosfet ocp bits are latched high in the spi registers. normal operation starts again automatically (gate driver operation and the nfault pin is released) after the t retry time elapses. the fault, vds_ocp, and mosfet ocp bits stay latched until the t retry period expires. 8.3.5.3.3 v ds report only (ocp_mode = 10b) no protective action occurs after a vds_ocp event in this mode. the overcurrent event is reported by driving the nfault pin low and latching the fault, vds_ocp, and corresponding mosfet ocp bits high in the spi registers. the gate drivers continue to operate as usual. the external controller manages the overcurrent condition by acting appropriately. the reporting clears (nfault pin is released) when the vds_ocp condition clears and a clear faults command is issued either through the clr_flt bit or an enable reset pulse (t rst ). 8.3.5.3.4 v ds disabled (ocp_mode = 11b) no action occurs after a vds_ocp event in this mode. the vds overcurrent monitor is disabled for all three half-bridges at the same time and the dis_vds_x bits are locked. in the h/w device, vds_ocp is disabled for all three half-bridges at the same time through the vds pin. advance information
41 drv8343-q1 www.ti.com slvse12 ? march 2018 product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.3.5.4 v sense overcurrent protection (sen_ocp) half-bridge overcurrent is also monitored by sensing the voltage drop across the external current-sense resistor with the sp pin. if at any time, the voltage on the sp input of the current-sense amplifier exceeds the v sen_ocp threshold for longer than the t ocp_deg deglitch time, a sen_ocp event is recognized and action is done according to the ocp_mode. on hardware interface devices, the v sense threshold is fixed at 1 v, t ocp_deg is fixed at 4 s, and the ocp_mode for v sense is fixed for latched shutdown. in the spi device, the v sense threshold is set through the sen_lvl spi register, the t ocp_deg is set through the ocp_deg spi register, and the ocp_mode bit can operate in four different modes: v sense latched shutdown, v sense automatic retry, v sense report only, and v sense disabled. 8.3.5.4.1 v sense latched shutdown (ocp_mode = 00b) after a sen_ocp event in this mode, all the external mosfets are disabled and the nfault pin is driven low. the fault and sen_ocp bits are latched high in the spi registers. normal operation starts again (gate driver operation and the nfault pin is released) when the sen_ocp condition clears and a clear faults command is issued either through the clr_flt bit or an enable reset pulse (t rst ). this is the default mode in both the h/w and spi device options. 8.3.5.4.2 v sense automatic retry (ocp_mode = 01b) after a sen_ocp event in this mode, all the external mosfets are disabled and the nfault pin is driven low. the fault, sen_ocp, and corresponding sense ocp bits are latched high in the spi registers. normal operation starts again automatically (gate driver operation and the nfault pin is released) after the t retry time elapses. the fault, sen_ocp, and sense ocp bits stay latched until the t retry period expires. 8.3.5.4.3 v sense report only (ocp_mode = 10b) no protective action occurs after a sen_ocp event in this mode. the overcurrent event is reported by driving the nfault pin low and latching the fault and sen_ocp bits high in the spi registers. the gate drivers continue to operate. the external controller manages the overcurrent condition by acting appropriately. the reporting clears (nfault released) when the sen_ocp condition clears and a clear faults command is issued either through the clr_flt bit or an enable reset pulse (t rst ). 8.3.5.4.4 v sense disabled (ocp_mode = 11b) no action occurs after a sen_ocp event in this mode. the sen_ocp overcurrent monitor is disabled for all three half-bridges at the same time and the dis_sen_x bits are locked. in the h/w device, sen_ocp is disabled for all three half-bridges at the same time through the vds pin. 8.3.5.5 gate driver fault (gdf) the ghx and glx pins are monitored such that if the voltage on the external mosfet gate does not increase or decrease after the t drive time, a gate driver fault is detected. this fault may be encountered if the ghx or glx pins are shorted to the pgnd, shx, slx, or vm pins. additionally, a gate driver fault may be encountered if the selected idrive setting is not sufficient to turn on the external mosfet within the t drive period. after a gate drive fault is detected, all external mosfets are disabled and the nfault pin driven low. in addition, the fault, gdf, and corresponding vgs bits are latched high in the spi registers. normal operation starts again (gate driver operation and the nfault pin is released) when the gate driver fault condition is removed and a clear faults command is issued either through the clr_flt bit or an enable reset pulse (t rst ). in the spi device, setting the dis_gdf bit high disables this protection feature. if dis_gdf bit is set high and a gate drive fault occurs, the device keeps operating but the appropriate vgs fault bit is set high in the spi register until cleared through the clr_flt bit or an enable pin reset pulse (t rst ). gdf cannot be disabled in the h/w device option. gate driver faults can indicate that the selected idrive or t drive settings are too low to slew the external mosfet in the desired time. increasing either the idrive or t drive setting can resolve gate driver faults in these cases. alternatively, if a gate-to-source short occurs on the external mosfet, a gate driver fault is reported because of the mosfet gate not turning on. the t drive time also refers to the gdf fault blanking time. fault handling is done as follows based on the mode setting: ? in 6x, 3x, and 1x pwm modes a gdf fault in one of the external mosfets turns off all the mosfets. ? in independent half-bridge mode (mode = 011b or mode pin is hi-z) a gdf fault in one half-bridge only advance information
42 drv8343-q1 slvse12 ? march 2018 www.ti.com product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated disables both the mosfets in that half-bridge. the mosfets in the other half-bridges operate as commanded. ? in independent mosfet mode (mode = 111b or mode pin tied to dvdd) a gdf fault in a mosfet only disables that particular mosfet. all the other mosfets operate as commanded. the same fault handling scheme applies for mode = 100b, 101b, and 110b. ? a gdf fault in phases set as independent half-bridge disables both mosfets in that particular phase. ? a gdf fault in phases set as independent fet mode disables the mosfet where the fault occurred. 8.3.5.6 thermal warning (otw) if the die temperature exceeds the trip point of the thermal warning (t otw ), the otw bit is set in the registers of spi devices. the device performs no additional action and continues to function. when the die temperature falls lower than the hysteresis point of the thermal warning, the otw bit clears automatically. the otw bit can also be configured to report on the nfault pin by setting the otw_rep bit to 1 through the spi registers. otw is not available in the h/w device. 8.3.5.7 thermal shutdown (otsd) if the die temperature exceeds the trip point of the thermal shutdown limit (t otsd ), all the external mosfets are disabled, the charge pump is shut down, and the nfault pin is driven low. in addition, the fault and otsd bits are latched high. this protection feature cannot be disabled. the overtemperature protection can operate in two different modes. 8.3.5.7.1 latched shutdown (otsd_mode = 0b) in latched shutdown mode, after a otsd event, normal operation starts again (motor driver operation and the nfault line released) when the otsd condition is removed and a clear faults command has been issued either through the clr_flt bit or an nsleep reset pulse. this is the default mode for a otsd event in the spi device. when the drv8343-q1 device hits thermal shutdown, the otsd, cpuv, and fault bits are latched in the spi register. clearing the fault through the clr_flt bit or an nsleep reset pulse will clear the ostd and fault bits, but the cpuv bit remains latched. the cpuv bit will be cleared by another clr_flt bit or an nsleep reset pulse. 8.3.5.7.2 automatic recovery (otsd_mode = 1b) in automatic recovery mode, after a otsd event, normal operation starts again (motor driver operation and the nfault line released) when the junction temperature falls to less than the overtemperature threshold limit minus the hysteresis (t otsd ? t hys ). the otsd bit stays latched high indicating that a thermal event occurred until a clear faults command is issued either through the clr_flt bit or an nsleep reset pulse. this is the default mode for a otsd event in the h/w device. 8.3.5.8 open load detection (old) if the load is disconnected from the device, an open load is detected and the nfault pin is latched low. in the drv8343-q1 device, the fault, ol_sht, and the corresponding open load (ol_ph_x) bits in the spi register are latched high. when the open-load condition is removed, and the mcu clears the fault through either the clr_flt bit or an enable-pin reset pulse (t rst ), the device is ready to drive the motor based on the input commands. 8.3.5.8.1 open load detection in passive mode (olp) in open load detection in passive mode, open load diagnosis is performed without the motor in motion. if the motor is disconnected from the device an open load is detected and the nfault pin will latch low until a clear faults command is issued by the mcu either through the clr_flt bit or an enable reset pulse. the fault also clears when the device is power cycled or comes out of sleep mode. olp is designed for applications having capacitance less than the values listed in table 10 between motor phase pins to ground. advance information
43 drv8343-q1 www.ti.com slvse12 ? march 2018 product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated table 10. open load passive diagnostic run-time capacitance (nf) olp_shts_dly (ms) 5 0.25 26 1.25 110 5 270 11.5 when the open load test is running, all external mosfets are disabled. for the h/w device option, at power-up or after going from sleep mode, the offline short-to-supply (sht_bat) and short-to-ground (sht_gnd) diagnostics run first followed by the olp diagnostic if the ndiag pin is left as no connect or tied to gnd. if the ndiag pin is tied to dvdd (or an external 3.3 v) the open load test is not performed. if a short condition is detected, the olp diagnostic is not run (see offline shorts diagnostics ). if a short condition and open load occurs on a given phase at device power-up, for example, only the short condition is reported on the nfault pin and through the spi fault register. in the spi device option the olp test is performed when commanded through spi. if both short and olp diagnostics are enabled simultaneously and a short condition is detection, only the short condition is reported on the nfault pin and through the spi fault register. the sequence to perform open load diagnostics in passive mode is as follows: 1. device powered up (enable = 1). 2. mode is selected by spi. 3. hi-z all three half-bridges by turning-off all the external mosfets. 4. write a 1 to the en_olp bit in the spi register and olp is performed. ? if an open load is detected, the nfault pin is driven low, and the fault bit, the old bit, and the respective ol_ph_x bit are latched high. when the open load condition is removed, a clear faults command must be issued by the mcu either through the clr_flt bit or an enable reset pulse which resets the ol_ph_x register bit and causes the nfault pin to go high. ? if open load is not detected, the en_olp bits return to default setting (0b) after t ol expires. the en_olp register keeps the written command until the diagnostic is complete. the half bridges must stay in hi-z state for the entire duration of the test. while open load diagnostic is running, if an input change occurs or the en_olp bit is set low, the open load test is aborted to start normal operation again, and no fault is reported. olp should not be performed if the motor is energized. the open load detection checks for a high impedance connection on the motor phase pins (shx or dlx). the diagnostic has two major steps as listed in the olp steps section. the sequencing of the pullup and pulldown current varies depending on the load connections. figure 34 a simplified h-bridge configuration as an example for open load detection. advance information
44 drv8343-q1 slvse12 ? march 2018 www.ti.com product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated figure 34. circuit for open load detection in passive mode 8.3.5.8.1.1 olp steps the olp algorithm list is as follows: ? the pullup current source is enabled. if a load is connected, current passes through the pullup resistor and the olx_pu comparator output stays low. if an open load condition occurs, the current through the pullup resistor goes 0 and the olx_pu comparator trips high. ? the pulldown current source is enabled. in the same way, the olx_pd comparator output either stays low to indicate load-connected, or trips high to indicate an open load condition. ? if both the olx_pu and olx_pd comparators report an open load, the ol_ph_x bit in the spi register latches high, and the nfault line goes low, to indicate an ol fault. when the ol condition is removed, a clear faults command must be issued by the micro-controller either through the clr_flt bit or an enable reset pulse which resets open load register bits. the charge pump stays active during this fault condition. the load connections shown in figure 35 are not supported olp. vm vm ol1_pu output vm v ref ol1_pu output olx_pu v ref olx_pd shx / dlx shx / dlx slx + + advance information
45 drv8343-q1 www.ti.com slvse12 ? march 2018 product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated figure 35. load configurations not supported 8.3.5.8.2 open load detection in active mode (ola) an open load in active mode is disabled by default in the spi device and can be enabled independently per half- bridge by writing a 1 to the en_ola_x bit. in the h/w device, ola runs if the ndiag pin is left as unconnected or tied to gnd. ola is detected when the motor gets disconnected from the driver when it is commutating. figure 36 shows a simplified h-bridge configuration for ola implementation during high-side current recirculation. when the voltage drop across the body diode of the mosfet does not exhibit overshoot greater than the vola over vm between the time the low-side fet is switched off and the high side fet is switched on during an output pwm cycle. an open load is not detected if the energy stored in the inductor is high enough to cause an overshoot greater than the v ola over vm caused by the fly-back current flowing through the body diode of the high-side fet. figure 36. circuit for open load detection in active mode note depending on the operating conditions and on external circuitry, such as the output capacitors, an open load could be reported even though the load is present. this case might occur during a direction change or for small load currents respectively small pwm duty cycles. therefore, ti recommends evaluating the open load diagnosis only in known suitable operating conditions and to ignore it otherwise. sh2 dl2 sh1 dl1 vm sh2 dl2 sh1 dl1 vm sh2 dl2 sh1 dl1 vm + detects old if the diode v f drop < v ola no old detected if the diode v f drop > v ola + advance information + hs_vsd ghx shx vdrain + glx dlx slx vdrain ls_vsd vdrain vm ipu ipd
46 drv8343-q1 slvse12 ? march 2018 www.ti.com product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated the device has a failure counter to avoid inadvertent triggering of the open load active diagnosis. three consecutive occurrences of the internal open load signal must occur, essentially three consecutive pwm pulses without freewheeling detected, before an open load is reported through the nfault pin and in the respective spi register. in the spi device, depending on the load configuration and the pwm sequence, ola on one phase can latch all three ol_ph_x bits high. in that case, the olp diagnostic can be initiated to determine which phase has the open load condition. the load connections shown in figure 35 are not supported by ola. for ola to function correctly, place capacitors between the motor phase node and gnd. this capacitor is required for bldc, bi-directional bdc and unidirectional bdc motors at the phase node. if a solenoid load is connected, as shown in figure 11 , the capacitor is not required. size the capacitors according equation 5 . make sure that the capacitor (c phase ) is placed on the pcb. where ? v th is the threshold voltage of the mosfet. ? v ola(min) is 200 mv. (5) the values of c rss and c oss of the mosfets should be used for 0-v v ds . derating of c phase must be considered when selecting the capacitance. 8.3.5.9 offline shorts diagnostics the device detects short-to-battery and short-to-ground conditions when the motor is not commutating. these offline diagnostics can be activated in the spi device by setting the en_sht_tst bit high. both the short-to- battery and short-to-ground diagnostics run when the en_sht_tst bit is set high. in the h/w device, these diagnostics run at power-up or when going from the sleep mode if the ndiag pin is left unconnected or tied to gnd. to disable the diagnostics in the h/w device, connect the ndiag pin to the dvdd supply (or an external 3.3 v or 5 v rail). the short-to-supply diagnostic runs first (see offline short-to-supply diagnostic (sht_bat) ) followed by the short-to-ground diagnostic (see offline short-to-ground diagnostic (sht_gnd) ). in the spi device, the duration for this diagnostics is selected through the olp_shts_dly register. in the h/w device, the duration is fixed to 2 ms. 8.3.5.9.1 offline short-to-supply diagnostic (sht_bat) when the en_sht_tst bit is set high, all the pulldown current sources on the dlx pins are enabled. the voltage across each pulldown source is individually measured and compared to an internal threshold (v th ). if the voltage across any of the current sources exceeds v th , the drv8343-q1 device flags that as a fault condition. the nfault pin is driven low, and in the spi device the fault, ol_sht, and the corresponding sht_bat_x bit is set. figure 37 shows the internal circuit for the short to battery detection. th rss phase os s ola(min) v c c c v u t advance information
47 drv8343-q1 www.ti.com slvse12 ? march 2018 product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated figure 37. offline short-to-supply detection circuit in the spi device, depending on the load configuration, sht_bat on one phase can latch all three sht_bat_x bits high. to determine which phase has a short-to-supply fault condition, the external mosfets can be enabled and the appropriate vds_lx fault bit is latched indicating the faulty phase node. sht_bat is not supported for load configurations shown in figure 35 . 8.3.5.9.2 offline short-to-ground diagnostic (sht_gnd) when the en_sht_tst bit is set high, all the pullup current sources on the shx pins are enabled. the voltage across each pullup source is individually measured and compared to an internal threshold (v th ). if the voltage across any of the current sources exceeds v th , the drv8343-q1 device flags that as a fault condition. the nfault pin is driven low, and in the spi device the fault, ol_sht, and the corresponding sht_gnd_x bit is set. figure 38 shows the internal circuit for the short-to-ground detection. short to ground (sht_gnd) diagnostic circuit v th v th v th gha ghb sha ghc shb shc dlc dlb glc dla glb glc vm advance information
48 drv8343-q1 slvse12 ? march 2018 www.ti.com product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated figure 38. offline short-to-ground detection circuit in the spi device, depending on the load configuration, sht_gnd on one phase can latch all three sht_gnd_x bits high. to determine which phase has a short-to-ground fault condition, the external mosfets can be enabled and the appropriate vds_hx fault bit is latched indicating the faulty phase node. sht_gnd is not supported for load configurations shown in figure 35 . 8.3.5.10 reverse supply protection the circuit in figure 39 can be implemented to help protect the system from reverse supply conditions. this circuit requires the following additional components: ? n-channel mosfet ? npn bjt ? diode ? 10-k ? and 43-k ? resistors gha ghb sha ghc shb shc dlc dlb glc dla glb glc vm short to supply (sht_bat) diagnostic circuit v th v th v th vm advance information
49 drv8343-q1 www.ti.com slvse12 ? march 2018 product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated figure 39. reverse supply protection gha sha gla ghb shb glb vm ghc shc glc vm vdrain dla dlc dlb sla slb spc snc r sen v bat cpl cph vcp vm 47 nf 1 f 0.1 f bulk 10 f (min) + 10 k 43 k advance information
50 drv8343-q1 slvse12 ? march 2018 www.ti.com product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.4 device functional modes 8.4.1 gate driver functional modes 8.4.1.1 sleep mode the enable pin manages the state of the drv8343-q1 device. when the enable pin is low, the device goes to a low-power sleep mode. in sleep mode, all gate drivers are disabled, all external mosfets are disabled, the charge pump is disabled, the dvdd regulator is disabled, and the spi bus is disabled. the t sleep time must elapse after a falling edge on the enable pin before the device goes to sleep mode. the device comes out of sleep mode automatically if the enable pin is pulled high. the t wake time must elapse before the device is ready for inputs. in sleep mode and when v vm < v uvlo , all external mosfets are disabled. the high-side gate pins, ghx, are pulled to the shx pin by an internal resistor and the low-side gate pins, glx, are pulled to the pgnd pin by an internal resistor. 8.4.1.2 operating mode when the enable pin is high and the v vm voltage is greater than the v uvlo voltage, the device goes to operating mode. the t wake time must elapse before the device is ready for inputs. in this mode the charge pump, low-side gate regulator, dvdd regulator, and spi bus are active. 8.4.1.3 fault reset (clr_flt or enable reset pulse) in the case of device latched faults, the drv8343-q1 device goes to a partial shutdown state to help protect the external power mosfets and system. when the fault condition clears, the device can go to the operating state again by either setting the clr_flt spi bit on spi devices or issuing a result pulse to the enable pin on either interface variant. the enable reset pulse (t rst ) consists of a high-to-low-to-high transition on the enable pin. the low period of the sequence should fall with the t rst time window or else the device will start the complete shutdown sequence. the reset pulse has no effect on any of the regulators, device settings, or other functional blocks advance information
51 drv8343-q1 www.ti.com slvse12 ? march 2018 product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.5 programming this section applies only to the drv8343-q1 spi devices. 8.5.1 spi communication 8.5.1.1 spi on drv8343-q1 spi devices, an spi bus is used to set device configurations, operating parameters, and read out diagnostic information. the spi operates in slave mode and connects to a master controller. the spi input data (sdi) word consists of a 16-bit word, with an 8-bit command and 8 bits of data. the spi output data (sdo) word consists of 8-bit register data. the first 8 bits are don ? t care bits. a valid frame must meet the following conditions: ? the sclk pin should be low when the nscs pin transitions from high to low and from low to high. ? the nscs pin should be pulled high for at least 400 ns between words. ? when the nscs pin is pulled high, any signals at the sclk and sdi pins are ignored and the sdo pin is placed in the hi-z state. ? data is captured on the falling edge of the sclk pin and data is propagated on the rising edge of the sclk pin. ? the most significant bit (msb) is shifted in and out first. ? a full 16 sclk cycles must occur for transaction to be valid. ? if the data word sent to the sdi pin is less than or more than 16 bits, a frame error occurs and the data word is ignored. ? for a write command, the existing data in the register being written to is shifted out on the sdo pin following the 8-bit command data. 8.5.1.1.1 spi format the sdi input data word is 16 bits long and consists of the following format: ? 1 read or write bit, w (bit b15) ? 7 address bits, a (bits b14 through b8) ? 8 data bits, d (bits b7 through b0) the sdo output data word is 16 bits long and the first 5 bits are don't care bits. the data word is the content of the register being accessed. for a write command (w0 = 0), the response word on the sdo pin is the data currently in the register being written to. for a read command (w0 = 1), the response word is the data currently in the register being read. table 11. sdi input data word format r/w address data b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 w0 0 0 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 table 12. sdo output data word format r/w don't care data b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 w0 x x x x x x x d7 d6 d5 d4 d3 d2 d1 d0 advance information
52 drv8343-q1 slvse12 ? march 2018 www.ti.com product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated figure 40. spi slave timing diagram advance information nscs sclk sdi sdo msb lsb z z msb lsb x x capture point propagate point
53 drv8343-q1 www.ti.com slvse12 ? march 2018 product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.6 register maps this section applies only to the drv8343-q1 spi devices. note do not modify reserved registers or addresses not listed in the register map ( table 13 ). writing to these registers may have unintended effects. for all reserved bits, the default value is 0. to help prevent erroneous spi writes from the master controller, set the lock bits to lock the spi registers. table 13. drv8343-q1 register map register name 7 6 5 4 3 2 1 0 access type address fault status fault gdf cpuv uvlo ocp otw otsd ol_sht r 0x00 diag status a sa_oc sht_gnd_a sht_bat_a ol_ph_a vgs_la vgs_ha vds_la vds_ha r 0x01 diag status b sb_oc sht_gnd_b sht_bat_b ol_ph_b vgs_lb vgs_hb vds_lb vds_hb r 0x02 diag status c sc_oc sht_gnd_c sht_bat_c ol_ph_c vgs_lc vgs_hc vds_lc vds_hc r 0x03 ic1 control clr_flt pwm_mode 1pwm_com 1pwm_dir 1pwm_brake rw 0x04 ic2 control otsd_mode olp_shts_dly en_sht_tst en_olp en_ola_c en_ola_b en_ola_a rw 0x05 ic3 control idrivep_la idrivep_ha rw 0x06 ic4 control idrivep_lb idrivep_hb rw 0x07 ic5 control idrivep_lc idrivep_hc rw 0x08 ic6 control vds_lvl_la vds_lvl_ha rw 0x09 ic7 control vds_lvl_lb vds_lvl_hb rw 0x0a ic8 control vds_lvl_lc vds_lvl_hc rw 0x0b ic9 control coast tretry dead_time tdrive_max tdrive rw 0x0c ic10 control lock dis_cpuv dis_gdf ocp_deg rw 0x0d ic11 control rsvd otw_rep cbc dis_vds_c dis_vds_b dis_vds_a ocp_mode rw 0x0e ic12 control ls_ref csa_fet csa_gain_c csa_gain_b csa_gain_a rw 0x0f ic13 control cal_mode vref_div sen_lvl_c sev_lvl_b sen_lvl_a rw 0x10 ic14 control rsvd dis_sen_c dis_sen_b dis_sen_a csa_cal_c csa_cal_b csa_cal_a rw 0x11 complex bit access types are encoded to fit into small table cells. table 14 shows the codes that are used for access types in this section. table 14. status registers access type codes access type code description read type r r read reset or default value - n value after reset or the default value 8.6.1 status registers table 15 lists the memory-mapped registers for the status registers. all register offset addresses not listed in table 15 should be considered as reserved locations and the register contents should not be modified. the status registers are used to reporting warning and fault conditions. status registers are read-only registers. table 15. status registers summary table address register name section 0x00 fault status go 0x01 diag status a go 0x02 diag status b go 0x03 diag status c go advance information
54 drv8343-q1 slvse12 ? march 2018 www.ti.com product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.6.1.1 fault status register (address = 0x00) [reset = 0x00] fault status is shown in figure 41 and described in table 16 . figure 41. fault status register 7 6 5 4 3 2 1 0 fault gdf cpuv uvlo ocp otw otsd ol_sht r-0b r-0b r-0b r-0b r-0b r-0b r-0b r-0b table 16. fault status register field descriptions bit field type default description 7 fault r 0b logic or of fault status registers 6 gdf r 0b indicates gate drive fault condition 5 cpuv r 0b indicates charge pump undervoltage fault condition 4 uvlo r 0b indicates undervoltage lockout fault condition 3 ocp r 0b indicated overcurrent fault condition either by vds or sen_ocp 2 otw r 0b indicates overtemperature warning 1 otsd r 0b indicates overtemperature shutdown 0 ol_sht r 0b indicates open load detection, or offline short-to-supply or gnd detection 8.6.1.2 diag status a register (address = 0x01) [reset = 0x00] diag status a is shown in figure 42 and described in table 17 . figure 42. diag status a register 7 6 5 4 3 2 1 0 sa_oc sht_gnd_a sht_bat_a ol_ph_a vgs_la vgs_ha vds_la vds_ha r-0b r-0b r-0b r-0b r-0b r-0b r-0b r-0b table 17. diag status a register field descriptions bit field type default description 7 sa_oc r 0b indicates overcurrent on phase a sense amplifier 6 sht_gnd_a r 0b indicates offline short-to-ground fault in phase a 5 sht_bat_a r 0b indicates offline short to battery fault in phase a 4 ol_ph_a r 0b indicates open load fault in phase a 3 vgs_la r 0b indicates gate drive fault on the a low-side mosfet 2 vgs_ha r 0b indicates gate drive fault on the a high-side mosfet 1 vds_la r 0b indicates vds overcurrent fault on the a low-side mosfet 0 vds_ha r 0b indicates vds overcurrent fault on the a high-side mosfet advance information
55 drv8343-q1 www.ti.com slvse12 ? march 2018 product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.6.1.3 diag status b register (address = 0x02) [reset = 0x00] diag status b is shown in figure 43 and described in table 18 . figure 43. diag status b register 7 6 5 4 3 2 1 0 sb_oc sht_gnd_b sht_bat_b ol_ph_b vgs_lb vgs_hb vds_lb vds_hb r-0b r-0b r-0b r-0b r-0b r-0b r-0b r-0b table 18. diag status b register field descriptions bit field type default description 7 sb_oc r 0b indicates overcurrent on phase b sense amplifier 6 sht_gnd_b r 0b indicates offline short-to-ground fault in phase b 5 sht_bat_b r 0b indicates offline short to battery fault in phase b 4 ol_ph_b r 0b indicates open load fault in phase b 3 vgs_lb r 0b indicates gate drive fault on the b low-side mosfet 2 vgs_hb r 0b indicates gate drive fault on the b high-side mosfet 1 vds_lb r 0b indicates vds overcurrent fault on the b low-side mosfet 0 vds_hb r 0b indicates vds overcurrent fault on the b high-side mosfet 8.6.1.4 diag status c register (address = 0x03) [reset = 0x00] diag status c iss shown in figure 44 and described in table 19 . figure 44. diag status c register 7 6 5 4 3 2 1 0 sc_oc sht_gnd_c sht_bat_c ol_ph_c vgs_lc vgs_hc vds_lc vds_hc r-0b r-0b r-0b r-0b r-0b r-0b r-0b r-0b table 19. diag status c register field descriptions bit field type default description 7 sc_oc r 0b indicates overcurrent on phase c sense amplifier 6 sht_gnd_c r 0b indicates offline short-to-ground fault in phase c 5 sht_bat_c r 0b indicates offline short to battery fault in phase c 4 ol_ph_c r 0b indicates open load fault in phase c 3 vgs_lc r 0b indicates gate drive fault on the c low-side mosfet 2 vgs_hc r 0b indicates gate drive fault on the c high-side mosfet 1 vds_lc r 0b indicates vds overcurrent fault on the c low-side mosfet 0 vds_hc r 0b indicates vds overcurrent fault on the c high-side mosfet advance information
56 drv8343-q1 slvse12 ? march 2018 www.ti.com product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.6.2 control registers table 20 lists the memory-mapped registers for the control registers. all register offset addresses not listed in table 20 should be considered as reserved locations and the register contents should not be modified. the ic control registers are used to configure the device. control registers are read and write capable. table 20. control registers summary table address register name section 0x04 ic1 control go 0x05 ic2 control go 0x06 ic3 control go 0x07 ic4 control go 0x08 ic5 control go 0x09 ic6 control go 0x0a ic7 control go 0x0b ic8 control go 0x0c ic9 control go 0x0d ic10 control go 0x0e ic11 control go 0x0f ic12 control go 0x10 ic13 control go 0x11 ic14 control go 8.6.2.1 ic1 control register (address = 0x04) [reset = 0x00] ic1 control is shown in figure 45 and described in table 21 . figure 45. ic1 control register 7 6 5 4 3 2 1 0 clr_flt pwm_mode 1pwm_com 1pwm_dir 1pwm_brake r/w-0b r/w-000b r/w-0b r/w-0b r/w-00b table 21. ic1 control field descriptions bit field type default description 7 clr_flt r/w 0b write a 1 to this bit to clear all latched fault bits. this bit automatically resets after being written 6-4 pwn_mode r/w 000b 000b = 6x pwm mode 001b = 3x pwm mode 010b = 1x pwm mode 011b = independent half-bridge (for all phases) 100b = phases a and b are independent half-bridges, phase c is independent fet 101b = phases b and c are independent half-bridges, phase a is independent fet 110b = phase a is independent half-bridge, phases b and c are independent fet 111b =independent fet (for all phases) 3 1pwm_com r/w 0b 0b = 1x pwm mode uses synchronous rectification 1b = 1x pwm mode uses asynchronous rectification (diode freewheeling) 2 1pwm_dir r/w 0b in 1x pwm mode this bit is or ? ed with the inhc (dir) input advance information
57 drv8343-q1 www.ti.com slvse12 ? march 2018 product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated table 21. ic1 control field descriptions (continued) bit field type default description 1-0 1pwm_brake r/w 00b 00b = outputs follow commanded inputs 01b = turn on all three low-side mosfets 10b = turn on all three high-side mosfets 11b = turn off all six mosfets (coast) 8.6.2.2 ic2 control register (address = 0x05) [reset = 0x40] ic2 control is shown in figure 46 and described in table 22 . figure 46. ic2 control register 7 6 5 4 3 2 1 0 otsd_mode olp_shts_dly en_sht_tst en_olp en_ola_c en_ola_b en_ola_a r/w-0b r/w-10b r/w-0b r/w-0b r/w-0b r/w-0b r/w-0b table 22. ic2 control field descriptions bit field type default description 7 otsd_mode r/w 0b 0b = overtemperature condition will cause a latched fault 1b = overtemperature condition will cause an automatic recovery when the fault condition is removed 6-5 olp_shts_dly r/w 10b 00b = olp delay is 0.25 ms and shorts test delay is 0.1 ms 01b = olp delay is 1.25 ms and shorts test delay is 0.5 ms 10b = olp delay is 5 ms and shorts test delay is 2 ms 11b = olp delay is 11.5 ms and shorts test delay is 4.4 ms 4 en_sht_tst r/w 0b write a 1 to enable offline short to battery and ground diagnoses 3 en_olp r/w 0b write a 1 to enable open load diagnostic in standby mode. when open load test is complete en_olp returns to the default setting 2 en_ola_c r/w 0b write a 1 to enable open load active diagnostic on phase c 1 en_ola_b r/w 0b write a 1 to enable open load active diagnostic on phase b 0 en_ola_a r/w 0b write a 1 to enable open load active diagnostic on phase a advance information
58 drv8343-q1 slvse12 ? march 2018 www.ti.com product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.6.2.3 ic3 control register (address = 0x06) [reset = 0xff] ic3 control is shown in figure 47 and described in table 23 . figure 47. ic3 control register 7 6 5 4 3 2 1 0 idrivep_la idrivep_ha r/w-1111b r/w-1111b table 23. ic3 control field descriptions bit field type default description 7-4 idrivep_la r/w 1111b 0000b = 1.5 ma 0001b = 3.5 ma 0010b = 5 ma 0011b = 10 ma 0100b = 15 ma 0101b = 50 ma 0110b = 60 ma 0111b = 65 ma 1000b = 200 ma 1001b = 210 ma 1010b = 260 ma 1011b = 265 ma 1100b = 735 ma 1101b = 800 ma 1110b = 935 ma 1111b = 1000 ma 3-0 idrivep_ha r/w 1111b 0000b = 1.5 ma 0001b = 3.5 ma 0010b = 5 ma 0011b = 10 ma 0100b = 15 ma 0101b = 50 ma 0110b = 60 ma 0111b = 65 ma 1000b = 200 ma 1001b = 210 ma 1010b = 260 ma 1011b = 265 ma 1100b = 735 ma 1101b = 800 ma 1110b = 935 ma 1111b = 1000 ma advance information
59 drv8343-q1 www.ti.com slvse12 ? march 2018 product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.6.2.4 ic4 control register (address = 0x07) [reset = 0xff] ic4 control is shown in figure 48 and described in table 24 . figure 48. ic4 control register 7 6 5 4 3 2 1 0 idrivep_lb idrivep_hb r/w-1111b r/w-1111b table 24. ic4 control field descriptions bit field type default description 7-4 idrivep_lb r/w 1111b 0000b = 1.5 ma 0001b = 3.5 ma 0010b = 5 ma 0011b = 10 ma 0100b = 15 ma 0101b = 50 ma 0110b = 60 ma 0111b = 65 ma 1000b = 200 ma 1001b = 210 ma 1010b = 260 ma 1011b = 265 ma 1100b = 735 ma 1101b = 800 ma 1110b = 935 ma 1111b = 1000 ma 3-0 idrivep_hb r/w 1111b 0000b = 1.5 ma 0001b = 3.5 ma 0010b = 5 ma 0011b = 10 ma 0100b = 15 ma 0101b = 50 ma 0110b = 60 ma 0111b = 65 ma 1000b = 200 ma 1001b = 210 ma 1010b = 260 ma 1011b = 265 ma 1100b = 735 ma 1101b = 800 ma 1110b = 935 ma 1111b = 1000 ma advance information
60 drv8343-q1 slvse12 ? march 2018 www.ti.com product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.6.2.5 ic5 control register (address = 0x08) [reset = 0xff] ic5 control is shown in figure 49 and described in table 25 . figure 49. ic5 control register 7 6 5 4 3 2 1 0 idrivep_lc idrivep_hc r/w-1111b r/w-1111b table 25. ic5 control field descriptions bit field type default description 7-4 idrivep_lc r/w 1111b 0000b = 1.5 ma 0001b = 3.5 ma 0010b = 5 ma 0011b = 10 ma 0100b = 15 ma 0101b = 50 ma 0110b = 60 ma 0111b = 65 ma 1000b = 200 ma 1001b = 210 ma 1010b = 260 ma 1011b = 265 ma 1100b = 735 ma 1101b = 800 ma 1110b = 935 ma 1111b = 1000 ma 3-0 idrivep_hc r/w 1111b 0000b = 1.5 ma 0001b = 3.5 ma 0010b = 5 ma 0011b = 10 ma 0100b = 15 ma 0101b = 50 ma 0110b = 60 ma 0111b = 65 ma 1000b = 200 ma 1001b = 210 ma 1010b = 260 ma 1011b = 265 ma 1100b = 735 ma 1101b = 800 ma 1110b = 935 ma 1111b = 1000 ma advance information
61 drv8343-q1 www.ti.com slvse12 ? march 2018 product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.6.2.6 ic6 control register (address = 0x09) [reset = 0x99] ic6 control is shown in figure 50 and described in table 26 . figure 50. ic6 control register 7 6 5 4 3 2 1 0 vds_lvl_la vds_lvl_ha r/w-1001b r/w-1001b table 26. ic6 control field descriptions bit field type default description 7-4 vds_lvl_la r/w 1001b 0000b = 0.06 v 0001b = 0.13 v 0010b = 0.2 v 0011b = 0.26 v 0100b = 0.31 v 0101b = 0.45 v 0110b = 0.53 v 0111b = 0.6 v 1000b = 0.68 v 1001b = 0.75 v 1010b = 0.94 v 1011b = 1.13 v 1100b = 1.3 v 1101b = 1.5 v 1110b = 1.7 v 1111b = 1.88 v 3-0 vds_lvl_ha r/w 1001b 0000b = 0.06 v 0001b = 0.13 v 0010b = 0.2 v 0011b = 0.26 v 0100b = 0.31 v 0101b = 0.45 v 0110b = 0.53 v 0111b = 0.6 v 1000b = 0.68 v 1001b = 0.75 v 1010b = 0.94 v 1011b = 1.13 v 1100b = 1.3 v 1101b = 1.5 v 1110b = 1.7 v 1111b = 1.88 v advance information
62 drv8343-q1 slvse12 ? march 2018 www.ti.com product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.6.2.7 ic7 control register (address = 0x0a) [reset = 0x99] ic7 control is shown in figure 51 and described in table 27 . figure 51. ic7 control register 7 6 5 4 3 2 1 0 vds_lvl_lb vds_lvl_hb r/w-1001b r/w-1001b table 27. ic7 control field descriptions bit field type default description 7-4 vds_lvl_lb r/w 1001b 0000b = 0.06 v 0001b = 0.13 v 0010b = 0.2 v 0011b = 0.26 v 0100b = 0.31 v 0101b = 0.45 v 0110b = 0.53 v 0111b = 0.6 v 1000b = 0.68 v 1001b = 0.75 v 1010b = 0.94 v 1011b = 1.13 v 1100b = 1.3 v 1101b = 1.5 v 1110b = 1.7 v 1111b = 1.88 v 3-0 vds_lvl_hb r/w 1001b 0000b = 0.06 v 0001b = 0.13 v 0010b = 0.2 v 0011b = 0.26 v 0100b = 0.31 v 0101b = 0.45 v 0110b = 0.53 v 0111b = 0.6 v 1000b = 0.68 v 1001b = 0.75 v 1010b = 0.94 v 1011b = 1.13 v 1100b = 1.3 v 1101b = 1.5 v 1110b = 1.7 v 1111b = 1.88 v advance information
63 drv8343-q1 www.ti.com slvse12 ? march 2018 product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.6.2.8 ic8 control register (address = 0x0b) [reset = 0x99] ic8 control is shown in figure 52 and described in table 28 . figure 52. ic8 control register 7 6 5 4 3 2 1 0 vds_lvl_lc vds_lvl_hc r/w-1001b r/w-1001b table 28. ic8 control field descriptions bit field type default description 7-4 vds_lvl_lc r/w 1001b 0000b = 0.06 v 0001b = 0.13 v 0010b = 0.2 v 0011b = 0.26 v 0100b = 0.31 v 0101b = 0.45 v 0110b = 0.53 v 0111b = 0.6 v 1000b = 0.68 v 1001b = 0.75 v 1010b = 0.94 v 1011b = 1.13 v 1100b = 1.3 v 1101b = 1.5 v 1110b = 1.7 v 1111b = 1.88 v 3-0 vds_lvl_hc r/w 1001b 0000b = 0.06 v 0001b = 0.13 v 0010b = 0.2 v 0011b = 0.26 v 0100b = 0.31 v 0101b = 0.45 v 0110b = 0.53 v 0111b = 0.6 v 1000b = 0.68 v 1001b = 0.75 v 1010b = 0.94 v 1011b = 1.13 v 1100b = 1.3 v 1101b = 1.5 v 1110b = 1.7 v 1111b = 1.88 v advance information
64 drv8343-q1 slvse12 ? march 2018 www.ti.com product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.6.2.9 ic9 control register (address = 0x0c) [reset = 0x2f] ic9 control is shown in figure 53 and described in table 29 . figure 53. ic9 control register 7 6 5 4 3 2 1 0 coast tretry dead_time tdrive_max tdrive r/w-0b r/w-01b r/w-01b r/w-1b r/w-11b table 29. ic9 control field descriptions bit field type default description 7 coast r/w 0b write a 1 to this bit to put all the mosfets in the hi-z state 6-5 tretry r/w 01b 00b = 2 ms 01b = 4 ms 10b = 6 ms 11b = 8 ms 4-3 dead_time r/w 01b 00b = 500 ns 01b = 1000 ns 10b = 2000 ns 11b = 4000 ns 2 tdrive_max r/w 1b write a 0 to this bit to disable the maximum t drive time of 20 s. this bit is automatically enabled when idrive = 0000b, 0001b, 0010b, or 0011b is selected 1-0 tdrive r/w 11b 00b = 500 ns peak gate-current drive time 01b = 1000 ns peak gate-current drive time 10b = 2000 ns peak gate-current drive time 11b = 3000 ns peak gate-current drive time 8.6.2.10 ic10 control register (address = 0x0d) [reset = 0x61] ic10 control is shown in figure 54 and described in table 30 . figure 54. ic10 control register 7 6 5 4 3 2 1 0 lock dis_cpuv dis_gdf ocp_deg r/w-011b r/w-0b r/w-0b r/w-001b table 30. ic10 control field descriptions bit field type default description 7-5 lock r/w 011b write 110b to lock the settings by ignoring further register writes except to these bits and address 0x04h bit 7 (clr_flt). writing any sequence other than 110b has no effect when unlocked. write 011b to this register to unlock all registers. writing any sequence other than 011b has no effect when locked. 4 dis_cpuv r/w 0b 0b = charge-pump undervoltage lockout fault is enabled 1b = charge-pump undervoltage lockout fault is disabled 3 dis_gdf r/w 0b 0b = gate drive fault is enabled 1b = gate drive fault is disabled advance information
65 drv8343-q1 www.ti.com slvse12 ? march 2018 product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated table 30. ic10 control field descriptions (continued) bit field type default description 2-0 ocp_deg r/w 001b 000b = 2.5 s 001b = 4.75 s 010b = 6.75 s 011b = 8.75 s 100b = 10.25 s 101b = 11.5 s 110b = 16.5 s 111b = 20.5 s 8.6.2.11 ic11 control register (address = 0x0e) [reset = 0x00] ic11 control is shown in figure 55 and described in table 31 . figure 55. ic11 control register 7 6 5 4 3 2 1 0 rsvd otw_rep cbc dis_vds_c dis_vds_b dis_vds_a ocp_mode r/w-0b r/w-0b r/w-0b r/w-0b r/w-0b r/w-0b r/w-00b table 31. ic11 control field descriptions bit field type default description 7 rsvd r/w 0b reserved 6 otw_rep r/w 0b 0b = overtemperature warning is not reported on nfault 1b = overtemperature warning is reported on nfault 5 cbc r/w 0b in retry ocp_mode, for both vds_ocp and sen_ocp, the fault is automatically cleared when a pwm input is given 4 dis_vds_c r/w 0b write a 1 to this bit to disable vds_ocp for mosfets in phase c 3 dis_vds_b r/w 0b write a 1 to this bit to disable vds_ocp for mosfets in phase b 2 dis_vds_a r/w 0b write a 1 to this bit to disable vds_ocp for mosfets in phase a 1-0 ocp_mode r/w 00b 00b = overcurrent causes a latched fault 01b = overcurrent causes an automatic retrying fault 10b = overcurrent is report only but no action is taken 11b = overcurrent is not reported and no action is taken 8.6.2.12 ic12 control register (address = 0x0f) [reset = 0x2a] ic12 control is shown in figure 56 and described in table 32 . figure 56. ic12 control register 7 6 5 4 3 2 1 0 ls_ref csa_fet csa_gain_c csa_gain_b csa_gain_a r/w-0b r/w-0b r/w-10b r/w-10b r/w-10b advance information
66 drv8343-q1 slvse12 ? march 2018 www.ti.com product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated table 32. ic12 control field descriptions bit field type default description 7 ls_ref r/w 0b 0b = vds_ocp for the low-side mosfet is measured across dlx to slx 1b = vds_ocp for the low-side mosfet is measured across dlx to agnd (see figure 33 ) 6 csa_fet r/w 0b 0b = current sense amplifier positive input is spx 1b = current sense amplifier positive input is dlx (also automatically sets the ls_ref bit to 1b 5-4 csa_gain_c r/w 10b 00b = 5 v/v current sense amplifier gain 01b = 10 v/v current sense amplifier gain 10b = 20 v/v current sense amplifier gain 11b = 40 v/v current sense amplifier gain 3-2 csa_gain_b r/w 10b 00b = 5 v/v current sense amplifier gain 01b = 10 v/v current sense amplifier gain 10b = 20 v/v current sense amplifier gain 11b = 40 v/v current sense amplifier gain 1-0 csa_gain_a r/w 10b 00b = 5 v/v current sense amplifier gain 01b = 10 v/v current sense amplifier gain 10b = 20 v/v current sense amplifier gain 11b = 40 v/v current sense amplifier gain 8.6.2.13 ic13 control register (address = 0x10) [reset = 0x7f] ic13 control is shown in figure 57 and described in table 33 . figure 57. ic13 control register 7 6 5 4 3 2 1 0 cal_mode vref_div sen_lvl_c sen_lvl_b sen_lvl_b r/w-0b r/w-1b r/w-11b r/w-11b r/w-11b table 33. ic13 control field descriptions bit field type default description 7 cal_mode r/w 0b 0b = amplifier calibration operates in manual mode 1b = amplifier calibration uses internal auto calibration routine 6 vref_div r/w 1b 0b = sense amplifier reference voltage is vref (unidirectional mode) 1b = sense amplifier reference voltage is vref divided by 2 5-4 sen_lvl_c r/w 11b 00b = sense ocp 0.25 v 01b = sense ocp 0.5 v 10b = sense ocp 0.75 v 11b = sense ocp 1 v 3-2 sen_lvl_b r/w 11b 00b = sense ocp 0.25 v 01b = sense ocp 0.5 v 10b = sense ocp 0.75 v 11b = sense ocp 1 v 1-0 sen_lvl_a r/w 11b 00b = sense ocp 0.25 v 01b = sense ocp 0.5 v 10b = sense ocp 0.75 v 11b = sense ocp 1 v advance information
67 drv8343-q1 www.ti.com slvse12 ? march 2018 product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.6.2.14 ic14 control register (address = 0x10) [reset = 0x00] ic14 control is shown in figure 58 and described in table 34 . figure 58. ic14 control register 7 6 5 4 3 2 1 0 rsvd dis_sen_c dis_sen_b dis_sen_a csa_cal_c csa_cal_b csa_cal_a r/w-00b r/w-0b r/w-0b r/w-0b r/w-0b r/w-0b r/w-0b table 34. ic14 control field descriptions bit field type default description 7-6 rsvd r/w 00b reserved 5 dis_sen_c r/w 0b 0b = sense overcurrent fault is enabled for phase c 1b = sense overcurrent fault is disabled for phase c 4 dis_sen_b r/w 0b 0b = sense overcurrent fault is enabled for phase b 1b = sense overcurrent fault is disabled for phase b 3 dis_sen_a r/w 0b 0b = sense overcurrent fault is enabled for phase a 1b = sense overcurrent fault is disabled for phase a 2 csa_cal_c r/w 0b 0b = normal current sense amplifier c operation 1b = short inputs to current sense amplifier c for offset calibration if cal_mode = 0b 1 csa_cal_b r/w 0b 0b = normal current sense amplifier b operation 1b = short inputs to current sense amplifier b for offset calibration if cal_mode = 0b 0 csa_cal_a r/w 0b 0b = normal current sense amplifier a operation 1b = short inputs to current sense amplifier a for offset calibration if cal_mode = 0b advance information
68 drv8343-q1 slvse12 ? march 2018 www.ti.com product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 9 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 9.1 application information the drv8343-q1 device is primarily used in applications for three-phase brushless dc motor control. the design procedures in the typical application section highlight how to use and configure the drv8343-q1 device. 9.2 typical application 9.2.1 primary application the drv8343-q1 spi device is used in this application example. advance information
69 drv8343-q1 www.ti.com slvse12 ? march 2018 product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated typical application (continued) figure 59. primary application schematic advance information 2 1 cph 4 cpl 3 vm 6 vcp 5 gha 8 vdrain 7 gla 10 sha 9 sna 12 spa 11 spb 14 snb 13 shb 16 glb 15 ghc 18 ghb 17 glc 20 shc 19 snc 22 spc 21 sob 24 soc 23 agnd 47 cal 48 vsdo 45 dvdd 46 inla 43 inha 44 inlb 41 inhb 42 inlc 39 inhc 40 nc 37 pgnd 38 nscs 35 enable 36 sdi 33 sclk 34 31 sdo 32 29 30 27 nfault 28 soa 25 vref 26 gnd (pad) gha sha gla spa sna spb slb glb dlb shb ghb ghc shc gha sha gla spa sna vm vdrain ghb shb glb spb vm ghc shc glc spc vm a b c vm vcc 47 nf 1 f 4.7 f r pu 0.1 f r sense dla sla slb dlb dlc slc dla dlb dlc sla slb slc >10 ? f vdrain dla sla snb snb r sense snc r sense dlc glc slc spc snc vcc 3.3 v, 30 ma 1 f 0.1 f vcc vm + + vm
70 drv8343-q1 slvse12 ? march 2018 www.ti.com product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated typical application (continued) 9.2.1.1 design requirements table 35 lists the example input parameters for the system design. table 35. design parameters example design parameter reference example value nominal supply voltage v vm 24 v supply voltage range 8 v to 45 v mosfet part number csd18536kcs mosfet total gate charge q g 83 nc (typical) at v vgs = 10 v mosfet gate to drain charge q gd 14 nc (typical) target output rise time t r 1000 ns pwm frequency ? pwm 10 khz maximum motor current i max 100 a adc reference voltage v vref 3.3 v winding sense current range i sense ? 40 a to +40 a motor rms current i rms 28.3 a sense resistor power rating p sense 2 w system ambient temperature t a ? 40 c to 125 c 9.2.1.2 detailed design procedure 9.2.1.2.1 external mosfet support the drv8343-q1 mosfet support is based on the capacity of the charge pump and pwm switching frequency of the output. for a quick calculation of mosfet driving capacity, use equation 6 and equation 7 for three phase bldc motor applications. trapezoidal 120 commutation: i vcp > q g ? pwm where ? ? pwm is the maximum desired pwm switching frequency. ? i vcp is the charge pump capacity, which depends on the vm pin voltage. ? the multiplier based on the commutation control method, may vary based on implementation. (6) sinusoidal 180 commutation: i vcp > 3 q g ? pwm (7) 9.2.1.2.1.1 example if a system with a v vm voltage of 8 v (i vcp = 15 ma) uses a maximum pwm switching frequency of 10 khz, then the charge pump can support mosfets using trapezoidal commutation with a q g less than 750 nc, and mosfets using sinusoidal commutation with a q g less than 250 nc. 9.2.1.2.2 idrive configuration the strength of the gate drive current, i drive , is selected based on the gate-to-drain charge of the external mosfets and the target rise and fall times at the outputs. if i drive is selected to be too low for a given mosfet, then the mosfet may not turn on completely within the t drive time and a gate drive fault may be asserted. additionally, slow rise and fall times result in higher switching power losses. ti recommends adjusting these values in the system with the required external mosfets and motor to determine the best possible setting for any application. the i drivep and i driven current for both the low-side and high-side mosfets are independently adjustable on spi devices through the spi registers. on hardware interface devices, both source and sink settings are selected at the same time on the idrive pin. for mosfets with a known gate-to-drain charge q gd , desired rise time (t r ), and a desired fall time (t f ), use equation 8 and equation 9 to calculate the value of i drivep and i driven (respectively). (8) advance information drivep gd r i q t ! u
71 drv8343-q1 www.ti.com slvse12 ? march 2018 product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated (9) 9.2.1.2.2.1 example use equation 10 to calculate the value of i drivep for a gate-to-drain charge of 14 nc and a rise time from 100 to 300 ns. (10) select an i drivep value that is close to 14 ma which will set the i driven value close to 28 ma. for this example, the value of i drivep was selected as 15 ma. 9.2.1.2.3 v ds overcurrent monitor configuration the v ds monitors are configured based on the worst-case motor current and the r ds(on) of the external mosfets as shown in equation 11 . (11) 9.2.1.2.3.1 example the goal of this example is to set the v ds monitor to trip at a current greater than 100 a. according to the csd18536kcs 60 v n-channel nexfet ? power mosfet data sheet , the r ds(on) value is 1.8 times higher at 175 c, and the maximum r ds(on) value at a v gs of 10 v is 1.6 m . from these values, the approximate worst- case value of r ds(on) is 1.8 1.6 m = 2.88 m . using equation 11 with a value of 2.88 m for r ds(on) and a worst-case motor current of 100 a, equation 12 shows the calculated the value of the v ds monitors. (12) for this example, the value of v ds_ocp was selected as 0.31 v. the spi devices allow for adjustment of the deglitch time for the v ds overcurrent monitor. the deglitch time can be set to 2 s, 4 s, 6 s, 8 s, 10 s, 12 s, 16 s, or 20 s. 9.2.1.2.4 sense amplifier bidirectional configuration the sense amplifier gain on the drv8343-q1 device and sense resistor value are selected based on the target current range, vref voltage supply, power rating of the sense resistor, and operating temperature range. in bidirectional operation of the sense amplifier, the dynamic range at the output is approximately calculated as shown in equation 13 . (13) use equation 14 to calculate the approximate value of the selected sense resistor with v o calculated using equation 13 . (14) from equation 13 and equation 14 , select a target gain setting based on the power rating of the target sense resistor. 9.2.1.2.4.1 example in this system example, the value of the vref voltage is 3.3 v with a sense current from ? 40 to +40 a. the linear range of the sox output is 0.25 v to v vref ? 0.25 v (from the v linear specification). the differential range of the sense amplifier input is ? 0.3 to +0.3 v (v diff ). (15) driven drivep i 2 i u ds _ ocp max ds(on)max v i r ! u drivep 12 nc i 14 ma 1000 ns vref o vref v v v 0.25 v 2 ds _ ocp ds _ ocp v 100 a 2.88 m v 0.288 v ! u : ! o 3.3 v v 3.3 v 0.25 v 1.4 v 2 advance information 2 o sense rms v v r p i r a i ! u u
72 drv8343-q1 slvse12 ? march 2018 www.ti.com product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated (16) (17) therefore, the gain setting must be selected as 20 v/v or 40 v/v and the value of the sense resistor must be less than 2.5 m to meet the power rating for the sense resistor. for this example, the gain setting was selected as 20 v/v. the value of the resistor and worst case current can be verified that r < 2.5 m and i max = 40 a does not violate the differential range specification of the sense amplifier input (v spxd ). 9.2.2 application with one sense amplifier in this application, one sense amplifier is used in unidirectional mode for a summing current sense scheme often used in trapezoidal or hall-based bldc commutation control. v v 1.4 v 2.5 m a 14 a 40 a : ! o ! u 2 v 1.4 v r 2 w 28.3 r r 2.5 m a 40 a ! u o : u advance information
73 drv8343-q1 www.ti.com slvse12 ? march 2018 product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated figure 60. alternative application schematic 2 1 cph 4 cpl 3 vm 6 vcp 5 gha 8 vdrain 7 gla 10 sha 9 sna 12 spa 11 spb 14 snb 13 shb 16 glb 15 ghc 18 ghb 17 glc 20 shc 19 snc 22 spc 21 sob 24 soc 23 agnd 47 cal 48 vsdo 45 dvdd 46 inla 43 inha 44 inlb 41 inhb 42 inlc 39 inhc 40 nc 37 pgnd 38 nscs 35 enable 36 sdi 33 sclk 34 31 sdo 32 29 30 27 nfault 28 soa 25 vref 26 gnd (pad) gha sha gla spa sna spb slb glb dlb shb ghb ghc shc gha sha gla spa sna vm vdrain ghb shb glb vm ghc shc glc vm a b c vm vm vcc 47 nf 1 f 4.7 f r pu 0.1 f r sense dla sla slb dlb dlc slc dla dlb dlc sla slb slc >10 ? f vdrain dla sla dlc glc slc spc vcc 3.3 v, 30 ma 1 f 0.1 f vcc + vm + advance information
74 drv8343-q1 slvse12 ? march 2018 www.ti.com product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.2.2.1 design requirements table 36 lists the example design input parameters for system design. table 36. design parameters example design parameter reference example value adc reference voltage v vref 3.3 v sensed current i sense 0 to 40 a motor rms current i rms 28.3 a sense-resistor power rating p sense 3 w system ambient temperature t a ? 40 c to 125 c 9.2.2.2 detailed design procedure 9.2.2.2.1 sense amplifier unidirectional configuration the sense amplifiers are configured to be unidirectional through the registers on spi devices by writing a 0 to the vref_div bit. the sense amplifier gain and sense resistor values are selected based on the target current range, vref, power rating of the sense resistor, and operating temperature range. in unidirectional operation of the sense amplifier, use equation 18 to calculate the approximate value of the dynamic range at the output. (18) use equation 19 to calculate the approximate value of the selected sense resistor. where ? (19) from equation 18 and equation 19 , select a target gain setting based on the power rating of a target sense resistor. 9.2.2.2.1.1 example in this system example, the value of the vref voltage is 3.3 v with a sense current from 0 to 40 a. the linear range of the sox output for the device is 0.25 v to v vref ? 0.25 v (from the v linear specification). the differential range of the sense-amplifier input is ? 0.3 to +0.3 v (v diff ). (20) (21) (22) therefore, the gain setting must be selected as 20 v/v or 40 v/v and the value of the sense resistor must be less than 3.75 m to meet the power rating for the sense resistor. for this example, the gain setting was selected as 20 v/v. the value of the resistor and worst-case current can be verified that r < 3.75 m and i max = 40 a does not violate the differential range specification of the sense amplifier input (v spxd ). v v 2.8 v 3.75 m a 18.7 a 40 a : ! o ! u 2 o sense rms v v r p i r a i ! u u o vref v v 0.5 v advance information o v 3.3 v 0.5 v 2.8 v 2 v 2.8 v r 3 w 28.3 r r 3.75 m a 40 a ! u o : u o vref vref v v 0.25 v 0.25 v v 0.5 v
75 drv8343-q1 www.ti.com slvse12 ? march 2018 product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 10 power supply recommendations the drv8343-q1 device is designed to operate from an input voltage supply (vm) range from 6 v to 60 v. a 0.1- f ceramic capacitor rated for vm must be placed as close to the device as possible. in addition, a bulk capacitor must be included on the vm pin but can be shared with the bulk bypass capacitance for the external power mosfets. additional bulk capacitance is required to bypass the external half-bridge mosfets and should be sized according to the application requirements. 10.1 bulk capacitance sizing having appropriate local bulk capacitance is an important factor in motor drive system design. it is generally beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size. the amount of local capacitance depends on a variety of factors including: ? the highest current required by the motor system ? the power supply's type, capacitance, and ability to source current ? the amount of parasitic inductance between the power supply and motor system ? the acceptable supply voltage ripple ? type of motor (brushed dc, brushless dc, stepper) ? the motor startup and braking methods the inductance between the power supply and motor drive system will limit the rate current can change from the power supply. if the local bulk capacitance is too small, the system will respond to excessive current demands or dumps from the motor with a change in voltage. when adequate bulk capacitance is used, the motor voltage stays stable and high current can be quickly supplied. the data sheet provides a recommended minimum value, but system level testing is required to determine the appropriate sized bulk capacitor. figure 61. motor drive supply parasitics example advance information local bulk capacitor parasitic wire inductance + motor driver power supply motor drive system vm gnd + ic bypass capacitor
76 drv8343-q1 slvse12 ? march 2018 www.ti.com product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 11 layout 11.1 layout guidelines bypass the vm pin to the pgnd pin using a low-esr ceramic bypass capacitor with a recommended value of 0.1 f. place this capacitor as close to the vm pin as possible with a thick trace or ground plane connected to the pgnd pin. additionally, bypass the vm pin using a bulk capacitor rated for vm. this component can be electrolytic. this capacitance must be at least 10 f. additional bulk capacitance is required to bypass the high current path on the external mosfets. this bulk capacitance should be placed such that it minimizes the length of any high current paths through the external mosfets. the connecting metal traces should be as wide as possible, with numerous vias connecting pcb layers. these practices minimize inductance and let the bulk capacitor deliver high current. place a low-esr ceramic capacitor between the cpl and cph pins. this capacitor should be 47 nf, rated for vm, and be of type x5r or x7r. additionally, place a low-esr ceramic capacitor between the vcp and vm pins. this capacitor should be 1 f, rated for 50 v, and be of type x5r or x7r. bypass the dvdd pin to the agnd pin with a 1- f low-esr ceramic capacitor rated for 6.3 v and of type x5r or x7r. place this capacitor as close to the pin as possible and minimize the path from the capacitor to the agnd pin. the vdrain pin can be shorted directly to the vm pin. however, if a significant distance is between the device and the external mosfets, use a dedicated trace to connect to the common point of the drains of the high-side external mosfets. do not connect the slx pins directly to pgnd. instead, use dedicated traces to connect these pins to the sources of the low-side external mosfets. these recommendations offer more accurate v ds sensing of the external mosfets for overcurrent detection. minimize the loop length for the high-side and low-side gate drivers. the high-side loop is from the ghx pin of the device to the high-side power mosfet gate, then follows the high-side mosfet source back to the shx pin. the low-side loop is from the glx pin of the device to the low-side power mosfet gate, then follows the low-side mosfet source back to the pgnd pin. advance information
77 drv8343-q1 www.ti.com slvse12 ? march 2018 product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 11.2 layout example figure 62. layout example advance information 19 ghb thermal pad 18 shb 17 dlb 16 glb 15 slb 14 13 24 23 22 dlc 21 shc 20 ghc 6 gha 7 sha 8 dla 9 gla 10 sla 11 spa 12 sna 1 2 3 vcp 4 vm 5 vdrain 42 43 44 45 46 47 37 38 39 40 41 31 30 vref 29 28 27 26 25 35 34 33 32 36 inhc cal agnd dvdd vsdo inha inla slc spb snb nc pgnd inlb inhb 48 inlc inlc inha inhc inhb inla vcc cal enable nscs sclk sdi so nfault vref soa sob soc s s s d d d d g s s s d d d d g s s s d d d d g s s s d d d d g s s s d d d d g s s s d d d d g glc outc outb outa cpl cph nfault soa sob soc nscs sclk sdi sdo enable snc spc inlb vcc
78 drv8343-q1 slvse12 ? march 2018 www.ti.com product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 12 device and documentation support 12.1 device support 12.1.1 device nomenclature the following figure shows a legend for interpreting the complete device name: 12.2 documentation support 12.2.1 related documentation ? texas instruments, an-1149 layout guidelines for switching power supplies application report ? texas instruments, enhanced fault diagnostics in drv834x-q1 ti technote ? texas instruments, hardware design considerations for an electric bicycle using bldc motor ? texas instruments, layout guidelines for switching power supplies ? texas instruments, sensored 3-phase bldc motor control using msp430 ? application report ? texas instruments, understanding idrive and tdrive in ti motor gate drivers application report 12.3 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 12.4 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 12.5 trademarks powerpad, nexfet, msp430, e2e are trademarks of texas instruments. all other trademarks are the property of their respective owners. advance information (php) (4) drv83 prefix drv83 three phase brushless dc (3) (r) tape and reel r tape and reel t small tape and reel package php 7 7 1 mm qfp series 4 60 v device (s) sense amplifiers 0 no sense amplifiers 3 three current sense amplifiers interface s spi h hardware (q) operating temperature q n40c to 125c (q1) qualified to use in automotive environment
79 drv8343-q1 www.ti.com slvse12 ? march 2018 product folder links: drv8343-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 12.6 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.7 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 13 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. advance information
package option addendum www.ti.com 21-dec-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples drv8343sphprq1 preview htqfp php 48 1000 tbd call ti call ti -40 to 125 pdrv8343hphprq1 active htqfp php 48 1000 tbd call ti call ti -40 to 125 PDRV8343SPHPRQ1 active htqfp php 48 1000 tbd call ti call ti -40 to 125 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
package option addendum www.ti.com 21-dec-2018 addendum-page 2

important notice and disclaimer ti provides technical and reliability data (including datasheets), design resources (including reference designs), application or other design advice, web tools, safety information, and other resources ? as is ? and with all faults, and disclaims all warranties, express and implied, including without limitation any implied warranties of merchantability, fitness for a particular purpose or non-infringement of third party intellectual property rights. these resources are intended for skilled developers designing with ti products. you are solely responsible for (1) selecting the appropriate ti products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. these resources are subject to change without notice. ti grants you permission to use these resources only for development of an application that uses the ti products described in the resource. other reproduction and display of these resources is prohibited. no license is granted to any other ti intellectual property right or to any third party intellectual property right. ti disclaims responsibility for, and you will fully indemnify ti and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. ti ? s products are provided subject to ti ? s terms of sale ( www.ti.com/legal/termsofsale.html ) or other applicable terms available either on ti.com or provided in conjunction with such ti products. ti ? s provision of these resources does not expand or otherwise alter ti ? s applicable warranties or warranty disclaimers for ti products. mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2018, texas instruments incorporated

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