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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. TPS7A91 sbvs282 ? december 2016 TPS7A91 1-a, high-accuracy, low-noise ldo voltage regulator 1 1 features 1 ? 1.0% accuracy over line, load, and temperature ? low output noise: 4.7 v rms (10 hz ? 100 khz) ? low dropout: 200 mv (max) at 1 a ? wide input voltage range: 1.4 v to 6.5 v ? wide output voltage range: 0.8 v to 5.2 v ? high power-supply ripple rejection (psrr): ? 70 db at dc ? 40 db at 100 khz ? 40 db at 1 mhz ? fast transient response ? adjustable start-up in-rush control with selectable soft-start charging current ? open-drain power-good (pg) output ? 2.5-mm 2.5-mm, 10-pin son package 2 applications ? high-speed analog circuits: ? vco, adc, dac, lvds ? imaging: cmos sensors, video asics ? test and measurement ? instrumentation, medical, and audio ? digital loads: serdes, fpga, dsp 3 description the TPS7A91 is a low-noise (4.7 v rms ), low-dropout (ldo) voltage regulator capable of sourcing 1 a with only 200 mv of maximum dropout. the TPS7A91 output is adjustable with external resistors from 0.8 v to 5.2 v. the TPS7A91 wide input-voltage range supports operation as low as 1.4 v and up to 6.5 v. with 1% output voltage accuracy (over line, load, and temperature) and soft-start capabilities to reduce in- rush current, the TPS7A91 is ideal for powering sensitive analog low-voltage devices [such as voltage-controlled oscillators (vcos), analog-to-digital converters (adcs), digital-to-analog converters (dacs), high-end processors, and field- programmable gate arrays (fpgas)]. the TPS7A91 is designed to power noise-sensitive components such as those found in high-speed communication, video, medical, or test and measurement applications. the very low 4.7- v rms output noise and wideband psrr (40 db at 1 mhz) minimizes phase noise and clock jitter. these features maximize performance of clocking devices, adcs, and dacs. device information (1) part number package body size (nom) TPS7A91 son (10) 2.50 mm 2.50 mm (1) for all available packages, see the orderable addendum at the end of the datasheet. typical application circuit typical application diagram TPS7A91 clock sclk adc out vdd pg enable vdd_vco in en vin en lmk03328 lmx2581 adc3xxx adc3xjxx adc3xjbxx ads4xxbxx ads5xjxx ads12jxxxx c in c out gnd copyright ? 2016, texas instruments incorporated 1.2 v 2.0 v out pg in en TPS7A91 ss_ctrl nr/ss fb c in 10 p f c out 10 f c nr/ss 0.1 p f r 1 r 2 11.8 k : 5.9 k : v out r pg 20 k : pg gnd c ff 10 nf copyright ? 2016, texas instruments incorporated productfolder sample &buy technical documents tools & software support &community
2 TPS7A91 sbvs282 ? december 2016 www.ti.com product folder links: TPS7A91 submit documentation feedback copyright ? 2016, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 4 6.1 absolute maximum ratings ...................................... 4 6.2 esd ratings .............................................................. 4 6.3 recommended operating conditions ....................... 4 6.4 thermal information .................................................. 4 6.5 electrical characteristics ........................................... 5 6.6 typical characteristics .............................................. 6 7 detailed description ............................................ 12 7.1 overview ................................................................. 12 7.2 functional block diagram ....................................... 12 7.3 feature description ................................................. 12 7.4 device functional modes ........................................ 16 8 application and implementation ........................ 17 8.1 application information ............................................ 17 8.2 typical application .................................................. 21 9 power supply recommendations ...................... 22 10 layout ................................................................... 22 10.1 layout guidelines ................................................. 22 10.2 layout example .................................................... 23 11 device and documentation support ................. 24 11.1 device support .................................................... 24 11.2 documentation support ....................................... 24 11.3 receiving notification of documentation updates 24 11.4 community resources .......................................... 25 11.5 trademarks ........................................................... 25 11.6 electrostatic discharge caution ............................ 25 11.7 glossary ................................................................ 25 12 mechanical, packaging, and orderable information ........................................................... 25 4 revision history date revision notes december 2016 * initial release.
3 TPS7A91 www.ti.com sbvs282 ? december 2016 product folder links: TPS7A91 submit documentation feedback copyright ? 2016, texas instruments incorporated 5 pin configuration and functions dsk package 2.5-mm 2.5-mm, 10-pin son top view pin functions pin description name no. i/o en 7 i enable pin. this pin turns the ldo on and off. if v en v ih(en) , the regulator is enabled. if v en v il(en) , the regulator is disabled. the en pin must be connected to in if the enable function is not used. fb 3 i feedback pin. this pin is the input to the control loop error amplifier and is used to set the output voltage of the device. gnd 4 ? device gnd. connect to the device thermal pad. in 9, 10 i input pin. a 10 f or greater input capacitor is required. nr/ss 8 ? noise reduction pin. connect this pin to an external capacitor to bypass the noise generated by the internal band- gap reference. the capacitor reduces the output noise to very low levels and sets the output ramp rate to limit inrush current. out 1, 2 o regulated output. a 10 f or greater capacitor must be connected from this pin to gnd for stability. pg 5 o open-drain power-good indicator pin for the ldo output voltage. a 10-k to 100-k external pullup resistor is required. this pin can be left floating or connected to gnd if not used. ss_ctrl 6 i soft-start control pin. connect this pin either to gnd or in to change the nr/ss capacitor charging current. if a c nr/ss capacitor is not used, ss_ctrl must be connected to gnd to avoid output overshoot. thermal pad ? connect the thermal pad to the printed circuit board (pcb) ground plane, for an example layout see figure 42 . 1 out 10 in 2 out 9 in 3 fb 8 nr/ss 4 gnd 7 en 5 pg 6 ss_ctrl not to scale thermal pad
4 TPS7A91 sbvs282 ? december 2016 www.ti.com product folder links: TPS7A91 submit documentation feedback copyright ? 2016, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6 specifications 6.1 absolute maximum ratings over operating junction temperature range and all voltages with respect to gnd (unless otherwise noted) (1) min max unit voltage in, pg, en ? 0.3 7.0 v in, pg, en (5% duty cycle, pulse duration 200 s) ? 0.3 7.5 out ? 0.3 v in + 0.3 ss_ctrl ? 0.3 v in + 0.3 nr/ss, fb ? 0.3 3.6 current out internally limited a pg (sink current into the device) 5 ma temperature operating junction, t j ? 55 150 c storage, t stg ? 55 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.2 esd ratings value unit v (esd) electrostatic discharge human body model (hbm), per ansi/esda/jedec js-001 (1) 2000 v charged device model (cdm), per jedec specification jesd22-c101 (2) 500 6.3 recommended operating conditions over operating junction temperature range (unless otherwise noted) min max unit v in input supply voltage range 1.4 6.5 v v out output voltage range 0.8 5.2 v i out output current 0 1 a c in input capacitor 10 f c out output capacitor 10 f c nr/ss noise-reduction capacitor 0 10 f c ff feedforward capacitor 0 100 nf r pg power-good pullup resistance 10 100 k ? t j junction temperature ? 40 125 c (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. 6.4 thermal information thermal metric (1) TPS7A91 unit dsk (son) 10 pins r ja junction-to-ambient thermal resistance 56.9 c/w r jc(top) junction-to-case (top) thermal resistance 46.3 c/w r jb junction-to-board thermal resistance 29.1 c/w jt junction-to-top characterization parameter 0.8 c/w jb junction-to-board characterization parameter 29.4 c/w r jc(bot) junction-to-case (bottom) thermal resistance 3.2 c/w
5 TPS7A91 www.ti.com sbvs282 ? december 2016 product folder links: TPS7A91 submit documentation feedback copyright ? 2016, texas instruments incorporated (1) when the device is connected to external feedback resistors at the fb pin, external resistor tolerances are not included. (2) the device is not tested under conditions where v in > v out + 2.5 v and i out = 1 a because the power dissipation is higher than the maximum rating of the package. also, this accuracy specification does not apply on any application condition that exceeds the power dissipation limit of the package under test. 6.5 electrical characteristics over operating temperature range (t j = ? 40 c to +125 c), 1.4 v v in 6.5 v, v out(nom) = 0.8 v, i out = 5 ma, v en = 1.4 v, c in = c out = 10 f, c nr/ss = c ff = 0 nf, ss_ctrl = gnd, and pg pin pulled up to v in with 100 k (unless otherwise noted); typical values are at t j = 25 c parameter test conditions min typ max unit v in input supply voltage range 1.4 6.5 v v ref reference voltage 0.8 v v uvlo input supply uvlo v in rising 1.31 1.39 v v hys(uvlo) input supply uvlo hysteresis 290 mv v out output voltage range 0.8 5.2 v output voltage accuracy (1) 1.4 v v in 6.5 v, 5 ma i out 1 a ? 1.0% 1.0% v out( vin) line regulation 0.005 %/v v out( iout) load regulation (2) 5 ma i out 1 a 0.02 %/a v do dropout voltage v in 1.4 v, i out = 1 a, v fb = 0.8 v ? 3% 200 mv i lim output current limit v out forced at 0.9 v out(nom) , v in = v out(nom) + 300 mv 1.5 1.7 1.9 a i gnd gnd pin current v in = 6.5 v, i out = 5 ma 2.1 3.5 ma v in = 1.4 v, i out = 1 a 4 i sdn shutdown gnd pin current pg = (open), v in = 6.5 v, v en = 0.4 v 0.1 15 a i en en pin current v in = 6.5 v, 0 v v en 6.5 v ? 0.2 0.2 a v il(en) en pin low-level input voltage (device disabled) 0 0.4 v v ih(en) en pin high-level input voltage (device enabled) 1.1 6.5 v i ss_ctrl ss_ctrl pin current v in = 6.5 v, 0 v v ss_ctrl 6.5 v ? 0.2 0.2 a v it(pg) pg pin threshold for pg transitioning low with falling v out , expressed as a percentage of v out(nom) 82% 88.9% 93% v hys(pg) pg pin hysteresis for pg transitioning high with rising v out , expressed as a percentage of v out(nom) 1% v ol(pg) pg pin low-level output voltage v out < v it(pg) , i pg = ? 1 ma (current into device) 0.4 v i lkg(pg) pg pin leakage current v out > v it(pg) , v pg = 6.5 v 1 a i nr/ss nr/ss pin charging current v nr/ss = gnd, v ss_ctrl = gnd 4.0 6.2 9.0 a v nr/ss = gnd, v ss_ctrl = v in 65 100 150 i fb fb pin leakage current v in = 6.5 v, v fb = 0.8 v ? 100 100 na psrr power-supply ripple rejection f = 500 khz, v in = 3.8 v, v out(nom) = 3.3 v, i out = 750ma, c nr/ss = 10 nf, c ff = 10 nf 39 db v n output noise voltage bw = 10 hz to 100 khz, v in = 1.8 v, v out(nom) = 0.8 v, i out = 1.0 a, c nr/ss = 10 nf, c ff = 10 nf 4.7 v rms noise spectral density f = 10 khz, v in = 1.8 v, v out(nom) = 0.8 v, i out = 1.0 a, c nr/ss = 10 nf, c ff = 10 nf 13 nv/ hz r diss output active discharge resistance v en = gnd 250 t sd thermal shutdown temperature shutdown, temperature increasing 160 c reset, temperature decreasing 140
6 TPS7A91 sbvs282 ? december 2016 www.ti.com product folder links: TPS7A91 submit documentation feedback copyright ? 2016, texas instruments incorporated 6.6 typical characteristics at t j = 25 c, 1.4 v v in 6.5 v, v in v out(nom) + 0.3 v, v out = 0.8 v, ss_ctrl = gnd, i out = 5 ma, v en = 1.1 v, c out = 10 f, c nr/ss = c ff = 0 nf, pg pin pulled up to v out with 100 k , and ss_ctrl = gnd (unless otherwise noted) v out = 0.8 v, i out = 1.0 a, c out = 10 f, c nr/ss = c ff = 10 nf figure 1. psrr vs frequency and input voltage v out = 1.2 v, i out = 1.0 a, c out = 10 f, c nr/ss = c ff = 10 nf figure 2. psrr vs frequency and input voltage v out = 3.3 v, i out = 1.0 a, c out = 10 f, c nr/ss = c ff = 10 nf figure 3. psrr vs frequency and input voltage v out = 5 v, i out = 1.0 a, c out = 10 f, c nr/ss = c ff = 10 nf figure 4. psrr vs frequency and input voltage v out = 1.2 v, v in = v en = 1.7 v, c out = 10 f, c nr/ss = c ff = 10 nf figure 5. psrr vs frequency and output current v out = 3.3 v, v in = v en = 3.8 v, c out = 10 f, c nr/ss = c ff = 10 nf figure 6. psrr vs frequency and output current frequency (hz) power-supply rejection ratio (db) 0 10 20 30 40 50 60 70 80 90 10 100 1k 10k 100k 1m 10m v in 3.5 v 3.6 v 3.7 v 3.8 v 4.0 v 4.3 v frequency (hz) power-supply rejection ratio (db) 0 10 20 30 40 50 60 70 80 90 10 100 1k 10k 100k 1m 10m 10 100 1k 10k 100k 1m 10m v in 5.2 v 5.3 v 5.4 v 5.5 v 6 v 6.5 v frequency (hz) power-supply rejection ratio (db) 0 10 20 30 40 50 60 70 80 90 10 100 1k 10k 100k 1m 10m v in 1.4 v 1.5 v 1.8 v 2.0 v 2.5 v 3.0 v frequency (hz) power-supply rejection ratio (db) 0 10 20 30 40 50 60 70 80 90 10 100 1k 10k 100k 1m 10m v in 1.4 v 1.5 v 1.7 v 2.0 v 2.2 v 2.5 v 3.0 v frequency (hz) power-supply rejection ratio (db) 0 10 20 30 40 50 60 70 80 90 10 100 1k 10k 100k 1m 10m i out = 100 ma i out = 250 ma i out = 500 ma i out = 750 ma i out = 1a frequency (hz) power-supply rejection ratio (db) 0 10 20 30 40 50 60 70 80 90 10 100 1k 10k 100k 1m 10m i out = 100 ma i out = 250 ma i out = 500 ma i out = 750 ma i out = 1a
7 TPS7A91 www.ti.com sbvs282 ? december 2016 product folder links: TPS7A91 submit documentation feedback copyright ? 2016, texas instruments incorporated typical characteristics (continued) at t j = 25 c, 1.4 v v in 6.5 v, v in v out(nom) + 0.3 v, v out = 0.8 v, ss_ctrl = gnd, i out = 5 ma, v en = 1.1 v, c out = 10 f, c nr/ss = c ff = 0 nf, pg pin pulled up to v out with 100 k , and ss_ctrl = gnd (unless otherwise noted) v out = 1.2 v, v in = v en = 1.7 v, i out = 1.0 a, c out = 10 f, c ff = 10 nf figure 7. psrr vs frequency and c nr/ss v in = v out + 1.0 v, i out = 1.0 a, c in = c out = 10 f, c nr/ss = c ff = 10 nf, v rms bw = 10 hz to 100 khz figure 8. spectral noise density vs frequency and output voltage v in = 2.2 v, v out = 1.2 v, i out = 1.0 a, c in = c out = 10 f, c ff = 10 nf, v rms bw = 10 hz to 100 khz figure 9. spectral noise density vs frequency and c nr/ss v in = 2.2 v, v out = 1.2 v, i out = 1.0 a, c in = c out = 10 f, c nr/ss = 10 nf, v rms bw = 10 hz to 100 khz figure 10. spectral noise density vs frequency and c ff v in = 2.2 v, v out = 1.2 v, i out = 1.0 a, c in = 10 f, c nr/ss = c ff = 10 nf, v rms bw = 10 hz to 100 khz figure 11. spectral noise density vs frequency and c out v in = 1.4 v, v out = 0.8 v figure 12. current limit foldback frequency (hz) noise ( p v ? hz) 0.001 0.01 0.1 1 10 10 100 1k 10k 100k 1m 10m c out 10 p f, 5.4 p v rms 22 p f, 5.4 p v rms 100 p f, 6.1 p v rms output voltage (mv) current limit (a) 0 100 200 300 400 500 600 700 800 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 temperature -40 q c 0 q c 25 q c 85 q c 125 q c frequency (hz) noise ( p v ? hz) 0.001 0.01 0.1 1 10 10 100 1k 10k 100k 1m 10m c nr none, 10.3 p v rms 10 nf, 5.4 p v rms 100 nf, 4.7 p v rms 1 p f, 4.7 p v rms frequency (hz) noise ( p v ? hz) 0.001 0.01 0.1 1 10 10 100 1k 10k 100k 1m 10m c ff none, 9 p v rms 10 nf, 5.4 p v rms 100 nf, 4.9 p v rms frequency (hz) power-supply rejection ratio (db) 0 10 20 30 40 50 60 70 80 90 10 100 1k 10k 100k 1m 10m c nr = open c nr = 10 nf c nr = 100 nf c nr = 1 uf c nr = 10 uf frequency (hz) noise ( p v ? hz) 0.001 0.01 0.1 1 10 10 100 1k 10k 100k 1m 10m v out 0.8 v, 4.7 p v rms 1.2 v, 5.4 p v rms 1.8 v, 5.9 p v rms 3.3 v, 9.2 p v rms 5 v, 12.48 p v rms
8 TPS7A91 sbvs282 ? december 2016 www.ti.com product folder links: TPS7A91 submit documentation feedback copyright ? 2016, texas instruments incorporated typical characteristics (continued) at t j = 25 c, 1.4 v v in 6.5 v, v in v out(nom) + 0.3 v, v out = 0.8 v, ss_ctrl = gnd, i out = 5 ma, v en = 1.1 v, c out = 10 f, c nr/ss = c ff = 0 nf, pg pin pulled up to v out with 100 k , and ss_ctrl = gnd (unless otherwise noted) v in = 1.4 v, v out = 0.8 v figure 13. current limit vs temperature v in = 5.5 v figure 14. dropout voltage vs output current i out = 1 a figure 15. dropout voltage vs input voltage v in = 1.4 v figure 16. load regulation i out = 50 ma figure 17. line regulation v en = 0.4 v figure 18. shutdown current vs input voltage input voltage (v) shutdown current ( p a) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 0 0.5 1 1.5 2 2.5 3 temperature -40 q c 0 q c 25 q c 85 q c 125 q c input voltage (v) dropout voltage (mv) 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 0 50 100 150 200 250 300 350 400 temperature -40 q c 0 q c 25 q c 85 q c 125 q c output current (ma) accuracy (%) 0 200 400 600 800 1000 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 temperature -40 q c 0 q c 25 q c 85 q c 125 q c temperature ( q c) current limit (a) -50 -25 0 25 50 75 100 125 150 1.5 1.6 1.7 1.8 1.9 output current (ma) dropout voltage (mv) 0 200 400 600 800 1000 0 25 50 75 100 125 150 175 200 temperature -40 q c 0 q c 25 q c 85 q c 125 q c input voltage (v) accuracy (%) 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 temperature -40 q c 0 q c 25 q c 85 q c 125 q c
9 TPS7A91 www.ti.com sbvs282 ? december 2016 product folder links: TPS7A91 submit documentation feedback copyright ? 2016, texas instruments incorporated typical characteristics (continued) at t j = 25 c, 1.4 v v in 6.5 v, v in v out(nom) + 0.3 v, v out = 0.8 v, ss_ctrl = gnd, i out = 5 ma, v en = 1.1 v, c out = 10 f, c nr/ss = c ff = 0 nf, pg pin pulled up to v out with 100 k , and ss_ctrl = gnd (unless otherwise noted) v in = 1.4 v figure 19. ground current vs output current figure 20. ground current vs input voltage figure 21. pg low level voltage vs pg current (v in = 1.4 v) figure 22. pg low level voltage vs pg current (v in = 6.5 v) figure 23. pg threshold vs temperature v in = v pg = 6.5 v figure 24. pg leakage current vs temperature temperature ( q c) power good threshold (%) -50 -25 0 25 50 75 100 125 150 86 87 88 89 90 91 92 93 pg falling pg rising temperature ( q c) pg pin leakage current (na) -50 -25 0 25 50 75 100 125 150 0 10 20 30 40 50 60 70 80 90 100 pg current (ma) pg low level output voltage (mv) 0 0.5 1 1.5 2 2.5 3 0 100 200 300 400 500 600 temperature -40 q c 0 q c 25 q c 85 q c 125 q c pg current (ma) pg low level output voltage (mv) 0 0.5 1 1.5 2 2.5 3 0 100 200 300 400 500 600 temperature -40 q c 0 q c 25 q c 85 q c 125 q c output current (ma) ground current (ma) 0 200 400 600 800 1000 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 3.75 4 temperature -40 q c 0 q c 25 q c 85 q c 125 q c input voltage (v) ground current (ma) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 0 0.5 1 1.5 2 2.5 3 temperature -40 q c 0 q c 25 q c 85 q c 125 q c
10 TPS7A91 sbvs282 ? december 2016 www.ti.com product folder links: TPS7A91 submit documentation feedback copyright ? 2016, texas instruments incorporated typical characteristics (continued) at t j = 25 c, 1.4 v v in 6.5 v, v in v out(nom) + 0.3 v, v out = 0.8 v, ss_ctrl = gnd, i out = 5 ma, v en = 1.1 v, c out = 10 f, c nr/ss = c ff = 0 nf, pg pin pulled up to v out with 100 k , and ss_ctrl = gnd (unless otherwise noted) figure 25. soft-start current vs temperature (ss_ctrl = gnd) figure 26. soft-start current vs temperature (ss_ctrl = v in ) figure 27. enable threshold vs temperature figure 28. input uvlo threshold vs temperature v in = 1.5 v, i out = 100 ma to 1 a to 100 ma at 1 a/ s, c out = 10 f, v pg = v out figure 29. load transient response (v out = 1.2 v) v in = 5.5 v, i out = 100 ma to 1 a to 100 ma at 1 a/ s, c out = 10 f, v pg = v out figure 30. load transient response (v out = 5.0 v) time (10 p s/div) i out 500 ma/div v out 50 mv/div v pg 1 v/div i out 500 ma/div time (10 p s/div) v out 20 mv/div v pg 1 v/div temperature ( q c) enable threshold (v) -50 -25 0 25 50 75 100 125 150 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 v il(en) v ih(en) temperature ( q c) undervoltage lockout (v) -50 -25 0 25 50 75 100 125 150 1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4 uvlo falling uvlo rising temperature ( q c) nr/ss charging current ( p a) -50 -25 0 25 50 75 100 125 150 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 v in 1.4 v 6.5 v temperature ( q c) nr/ss charging current ( p a) -50 -25 0 25 50 75 100 125 150 60 70 80 90 100 110 120 130 140 150 v in 1.4 v 6.5 v
11 TPS7A91 www.ti.com sbvs282 ? december 2016 product folder links: TPS7A91 submit documentation feedback copyright ? 2016, texas instruments incorporated typical characteristics (continued) at t j = 25 c, 1.4 v v in 6.5 v, v in v out(nom) + 0.3 v, v out = 0.8 v, ss_ctrl = gnd, i out = 5 ma, v en = 1.1 v, c out = 10 f, c nr/ss = c ff = 0 nf, pg pin pulled up to v out with 100 k , and ss_ctrl = gnd (unless otherwise noted) v in = 1.4 v to 6.5 v to 1.4 v at 2 v/ s, v out = 0.8 v, i out = 1 a, c nr/ss = c ff = 10 nf, v pg = v out figure 31. line transient v in = 1.4 v, v pg = v out figure 32. start-up (ss_ctrl = gnd, c nr/ss = 0 nf) v in = 1.4 v, v pg = v out figure 33. start-up (ss_ctrl = gnd, c nr/ss = 10 nf) v in = 1.4 v, v pg = v out figure 34. start-up (ss_ctrl = v in , c nr/ss = 10 nf) v in = 1.4 v, v pg = v out figure 35. start-up (ss_ctrl = v in , c nr/ss = 1 f) v pg 200 mv/div time (2 ms/div) v out 200 mv/div v en 1 v/div v pg 200 mv/div time (500 p s/div) v out 200 mv/div v en 1 v/div v pg 200 mv/div time (50 p s/div) v out 200 mv/div v en 1 v/div v pg 1 v/div time (200 p s/div) v in 2 v/div v out 20 mv/div time (50 p s/div) v pg 200mv/div v out 200 mv/div v en 1 v/div
12 TPS7A91 sbvs282 ? december 2016 www.ti.com product folder links: TPS7A91 submit documentation feedback copyright ? 2016, texas instruments incorporated 7 detailed description 7.1 overview the TPS7A91 is a low-noise, high psrr, low dropout (ldo) regulator capable of sourcing a 1-a load with only 200 mv of maximum dropout. the TPS7A91 can operate down to a 1.4-v input voltage and a 0.8-v output voltage. this combination of low-noise, high psrr, and low dropout voltage makes the device an ideal ldo to power a multitude of loads from noise-sensitive communication components in high-speed communications applications to high-end microprocessors or field-programmable gate arrays (fpgas). as shown in the functional block diagram section, the TPS7A91 linear regulator features a low-noise, 0.8-v internal reference that can be filtered externally to obtain even lower output noise. the internal protection circuitry (such as the undervoltage lockout) prevents the device from turning on before the input is high enough to ensure accurate regulation. foldback current limiting is also included, allowing the output to source the rated output current when the output voltage is in regulation but reduces the allowable output current during short-circuit conditions. the internal power-good detection circuit allows users to sequence down-stream supplies and be alerted if the output voltage is below a regulation threshold. 7.2 functional block diagram 7.3 feature description 7.3.1 output enable the enable pin for the TPS7A91 is active high. the output voltage is enabled when the enable pin voltage is greater than v ih(en) and disabled with the enable pin voltage is less than v il(en) . if independent control of the output voltage is not needed, then connect the enable pin to the input. the TPS7A91 has an internal pulldown mosfet that connects a discharge resistor from v out to ground when the device is disabled to actively discharge the output voltage. 7.3.2 dropout voltage (v do ) dropout voltage (v do ) is defined as the v in ? v out voltage at the rated current (i rated ) of 1 a, where the pass- fet is fully on and in the ohmic region of operation. v do indirectly specifies a minimum input voltage above the nominal programmed output voltage at which the output voltage is expected to remain in regulation. if the input falls below the nominal output regulation, then the output follows the input. + charge pump current limit 0.8-v v ref thermal shutdown error amp internal controller out pg en nr/ss in i nr/ss gnd active discharge + 0.889 x v ref 200 pf uvlo circuits r nr/ss = 280 k : psrr boost soft-start control ss_ctrl fb
13 TPS7A91 www.ti.com sbvs282 ? december 2016 product folder links: TPS7A91 submit documentation feedback copyright ? 2016, texas instruments incorporated feature description (continued) dropout voltage is determined by the r ds(on) of the pass-fet. therefore, if the ldo operates below the rated current, then the v do for that current scales accordingly. the r ds(on) for the TPS7A91 can be calculated using equation 1 : (1) 7.3.3 output voltage accuracy output voltage accuracy specifies minimum and maximum output voltage error, relative to the expected nominal output voltage stated as a percent. the TPS7A91 features an output voltage accuracy of 1% that includes the errors introduced by the internal reference, load regulation, and line regulation variance across the full range of rated load and line operating conditions over temperature, as specified by the electrical characteristics table. output voltage accuracy also accounts for all variations between manufacturing lots. 7.3.4 high power-supply ripple rejection (psrr) psrr is a measure of how well the ldo control loop rejects noise from the input source to make the dc output voltage as noise-free as possible across the frequency spectrum (usually measured from 10 hz to 10 mhz). even though psrr is a loss in noise signal amplitude, the psrr curves in the typical characteristics section are shown as positive values in decibels (db) for convenience. equation 2 gives the psrr calculation as a function of frequency where input noise voltage [v in (f)] and output noise voltage [v out (f)] are the amplitudes of the respective sinusoidal signals. (2) noise that couples from the input to the internal reference voltage is a primary contributor to reduced psrr performance. using a noise-reduction capacitor is recommended to filter unwanted noise from the input voltage, which creates a low-pass filter with an internal resistor to improve psrr performance at lower frequencies. ldos are often employed not only as a step-down regulators, but also to provide exceptionally clean power rails for noise-sensitive components. this usage is especially true for the TPS7A91, which features an innovative circuit to boost the psrr between 200 khz and 1 mhz. this boost circuit helps further filter switching noise from switching-regulators that operate in this region; see figure 1 . to achieve the maximum benefit of this psrr boost circuit, using a capacitor with a minimum impedance in the 100-khz to 1-mhz band is recommended. 7.3.5 low output noise ldo noise is defined as the internally-generated intrinsic noise created by the semiconductor circuits. the TPS7A91 is designed for system applications where minimizing noise on the power-supply rail is critical to system performance. this scenario is the case for phase-locked loop (pll)-based clocking circuits where minimum phase noise is all important, or in test and measurement systems where even small power-supply noise fluctuations can distort instantaneous measurement accuracy. the TPS7A91 includes a low-noise reference ensuring minimal output noise in normal operation. further improvements can be made by adding a noise reduction capacitor (c nr/ss ), a feedforward capacitor (c ff ), or a combination of the two. see the noise-reduction and soft-start capacitor (c nr/ss ) and feed-forward capacitor (c ff ) sections for additional design information. for more information on noise and noise measurement, see the how to measure ldo noise white paper (slyy076). 7.3.6 output soft-start control soft-start refers to the ramp-up characteristic of the output voltage during ldo turn-on after the en and uvlo thresholds are exceeded. the noise-reduction capacitor (c nr/ss ) serves a dual purpose of both governing output noise reduction and programming the soft-start ramp during turn-on. larger values for the noise-reduction capacitors decrease the noise but also result in a slower output turn-on ramp rate. in 10 out v (f ) psrr (db) 20 log v (f ) ? ? 1 r = ds(on) v do i rated
14 TPS7A91 sbvs282 ? december 2016 www.ti.com product folder links: TPS7A91 submit documentation feedback copyright ? 2016, texas instruments incorporated feature description (continued) the TPS7A91 features an ss_ctrl pin. when the ss_ctrl pin is grounded, the charging current for the nr/ss pin is 6.2 a (typ); when this pin is connected to in, the charging current for the nr/ss pin is increased to 100 a (typ). the higher current allows the use of a much larger noise-reduction capacitor and maintains a reasonable startup time. figure 36 shows a simplified block diagram of the soft-start circuit. the switch sw is opened to turn off the i nr/ss current source after v fb reaches approximately 97% of v ref . the final 3% of v nr/ss is charged through the noise reduction resistor (r nr ), which creates an rc delay. r nr is approximately 280 k and applications that require the highest accuracy when using a large value c nr/ss must take this rc delay into account. if a noise-reduction capacitor is not used on the nr/ss pin, tying the ss_ctrl pin to the in pin can result in output voltage overshoot of approximately 10%. this overshoot is minimized by either connecting the ss_ctrl pin to gnd or using a capacitor on the nr/ss pin. figure 36. simplified soft-start circuit 7.3.7 power-good function the power-good circuit monitors the voltage at the feedback pin to indicate the status of the output voltage. when the feedback pin voltage falls below the pg threshold voltage (v it(pg) ), the pg pin open-drain output engages and pulls the pg pin close to gnd. when the feedback voltage exceeds the v it(pg) threshold by an amount greater than v hys(pg) , the pg pin becomes high impedance. by connecting a pullup resistor to an external supply, any downstream device can receive power-good as a logic signal that can be used for sequencing. make sure that the external pullup supply voltage results in a valid logic signal for the receiving device or devices. using a pullup resistor from 10 k to 100 k is recommended. using an external reset device such as the tps3890 is also recommended in applications where high accuracy is needed or in applications where microprocessor induced resets are needed. when using a feed-forward capacitor (c ff ), the time constant for the ldo startup is increased whereas the power-good output time constant stays the same, possibly resulting in an invalid status of the power-good output. to avoid this issue and to receive a valid pg output, make sure that the time constant of both the ldo startup and the power-good output are matching, which can be done by adding a capacitor in parallel with the power- good pullup resistor. for more information, see the pros and cons of using a feedforward capacitor with a low- dropout regulator application report (sbva042). the state of pg is only valid when the device is operating above the minimum input voltage of the device and power good is asserted regardless of the output voltage state when the input voltage falls below the uvlo threshold minus the uvlo hysteresis. figure 37 illustrates a simplified block diagram of the power-good circuit. when the input voltage falls below approximately 0.8 v, there is not enough gate drive voltage to keep the open- drain, power-good device turned on and the power-good output is pulled high. connecting the power-good pullup resistor to the output voltage can help minimize this effect. v ref i nr/ss r nr c nr/ss gnd + sw v fb nr/ss control
15 TPS7A91 www.ti.com sbvs282 ? december 2016 product folder links: TPS7A91 submit documentation feedback copyright ? 2016, texas instruments incorporated feature description (continued) figure 37. simplified pg circuit 7.3.8 internal protection circuitry 7.3.8.1 undervoltage lockout (uvlo) the TPS7A91 has an independent undervoltage lockout (uvlo) circuit that monitors the input voltage, allowing a controlled and consistent turn on and off of the output voltage. to prevent the device from turning off if the input drops during turn on, the uvlo has approximately 290 mv of hysteresis. the uvlo circuit responds quickly to glitches on v in and disables the output of the device if this rail starts to collapse too quickly. use an input capacitor that is large enough to slow input transients to less then two volts per microsecond. 7.3.8.2 internal current limit (i cl ) the internal current-limit circuit is used to protect the ldo against transient high-load current faults or shorting events. the ldo is not designed to operate in current limit under steady-state conditions. during an overcurrent event where the output voltage is pulled 10% below the regulated output voltage, the ldo sources a constant current as specified in the electrical characteristics table. when the output voltage falls, the amount of output current is reduced to better protect the device. during a hard short-circuit event, the current is reduced to approximately 1.45 a. see figure 12 in the typical characteristics section for more information about the current-limit foldback behavior. note also that when a current-limit event occurs, the ldo begins to heat up because of the increase in power dissipation. the increase in heat can trigger the integrated thermal shutdown protection circuit. 7.3.8.3 thermal protection the TPS7A91 contains a thermal shutdown protection circuit to turn off the output current when excessive heat is dissipated in the ldo. thermal shutdown occurs when the thermal junction temperature (t j ) of the pass-fet exceeds 160 c (typical). thermal shutdown hysteresis assures that the ldo again resets (turns on) when the temperature falls to 140 c (typical). the thermal time-constant of the semiconductor die is fairly short, and thus the output turns on and off at a high rate when thermal shutdown is reached until power dissipation is reduced. the internal protection circuitry of the TPS7A91 is designed to protect against thermal overload conditions. the circuitry is not intended to replace proper heat sinking. continuously running the TPS7A91 into thermal shutdown degrades device reliability. for reliable operation, limit junction temperature to a maximum of 125 c. to estimate the thermal margin in a given layout, increase the ambient temperature until the thermal protection shutdown is triggered using worst- case load and highest input voltage conditions. for good reliability, thermal shutdown must occur at least 35 c above the maximum expected ambient temperature condition for the application. this configuration produces a worst-case junction temperature of 125 c at the highest expected ambient temperature and worst-case load. gnd v ref + v in v fb gnd v pg en gnd uvlo
16 TPS7A91 sbvs282 ? december 2016 www.ti.com product folder links: TPS7A91 submit documentation feedback copyright ? 2016, texas instruments incorporated (1) all table conditions must be met. (2) the device is disabled when any condition is met. 7.4 device functional modes table 1 provides a quick comparison between the normal, dropout, and disabled modes of operation. table 1. device functional modes comparison operating mode parameter v in en i out t j normal (1) v in > v out(nom) + v do v en > v ih(en) i out < i cl t j < t sd dropout (1) v in < v out(nom) + v do v en > v ih(en) i out < i cl t j < t sd disabled (2) v in < v uvlo v en < v il(en) ? t j > t sd 7.4.1 normal operation the device regulates to the nominal output voltage when all of the following conditions are met. ? the input voltage is greater than the nominal output voltage plus the dropout voltage (v out(nom) + v do ) ? the enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased below the enable falling threshold ? the output current is less than the current limit (i out < i cl ) ? the device junction temperature is less than the thermal shutdown temperature (t j < t sd ) 7.4.2 dropout operation if the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout. in this mode, the output voltage tracks the input voltage. during this mode, the transient performance of the device becomes significantly degraded because the pass device is in a triode state and no longer controls the current through the ldo. line or load transients in dropout can result in large output-voltage deviations. when the device is in a steady dropout state (defined as when the device is in dropout, v in < v out(nom) + v do , right after being in a normal regulation state, but not during startup), the pass-fet is driven as hard as possible. when the input voltage returns to v in v out(nom) + v do , v out can overshoot for a short period of time if the input voltage slew rate is greater than 0.1 v/ s. 7.4.3 disabled the output of the TPS7A91 can be shutdown by forcing the enable pin below 0.4 v. when disabled, the pass device is turned off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal resistor from the output to ground.
17 TPS7A91 www.ti.com sbvs282 ? december 2016 product folder links: TPS7A91 submit documentation feedback copyright ? 2016, texas instruments incorporated 8 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information the TPS7A91 is a linear voltage regulator operating from 1.4 v to 6.5 v on the input and regulates voltages between 0.8 v to 5.0 v within 1% accuracy and a 1-a maximum output current. efficiency is defined by the ratio of output voltage to input voltage because the TPS7A91 is a linear voltage regulator. to achieve high efficiency, the dropout voltage (v in ? v out ) must be as small as possible, thus requiring a very low dropout ldo. successfully implementing an ldo in an application depends on the application requirements. this section discusses key device features and how to best implement them to achieve a reliable design. 8.1.1 adjustable output the output voltage of the TPS7A9101 can be adjusted from 0.8 v to 5.2 v by using a resistor divider network as shown in figure 38 . figure 38. adjustable operation r 1 and r 2 can be calculated for any output voltage range using equation 3 . this resistive network must provide a current greater than or equal to 5 a for optimum noise performance. (3) if greater voltage accuracy is required, take into account the output voltage offset contribution resulting from the feedback pin current (i fb ) and use 0.1%-tolerance resistors. table 2 lists the resistor combination required to achieve a few of the most common rails using commercially- available, 0.1%-tolerance resistors to maximize nominal voltage accuracy and also abiding to the formula given in equation 3 . ref(max) out 1 2 ref 2 v v r = r 1 , where 5 a v r ! p ? ? 1 v out v in out in en TPS7A9101 ss_ctrl nr/ss fb c in c out c nr/ss r 1 r 2 gnd pg copyright ? 2016, texas instruments incorporated
18 TPS7A91 sbvs282 ? december 2016 www.ti.com product folder links: TPS7A91 submit documentation feedback copyright ? 2016, texas instruments incorporated application information (continued) (1) r 1 is connected from out to fb; r 2 is connected from fb to gnd; see figure 38 . table 2. recommended feedback-resistor values v out(target) (v) feedback resistor values (1) calculated output voltage (v) r 1 (k ) r 2 (k ) 0.8 short open 0.800 1.00 2.55 10.2 1.000 1.20 5.9 11.8 1.200 1.50 9.31 10.7 1.496 1.80 1.87 1.5 1.797 1.90 15.8 11.5 1.899 2.50 2.43 1.15 2.490 3.00 3.16 1.15 2.998 3.30 3.57 1.15 3.283 5.00 10.5 2 5.00 8.1.2 start-up 8.1.2.1 enable (en) and undervoltage lockout (uvlo) the TPS7A91 only turns on when en and uvlo are above the respective voltage thresholds. the TPS7A91 has an independent uvlo circuit that monitors the input voltage to allow a controlled and consistent turn on and off. the uvlo has approximately 290 mv of hysteresis to prevent the device from turning off if the input drops during turn on. the en signal allows independent logic-level turn-on and shutdown of the ldo when the input voltage is present. connecting en directly to in is recommended if independent turn-on is not needed. the TPS7A91 has an internal pulldown mosfet that connects a discharge resistor from v out to ground when the device is disabled to actively discharge the output voltage. 8.1.2.2 noise-reduction and soft-start capacitor (c nr/ss ) the c nr/ss capacitor serves a dual purpose of both reducing output noise and setting the soft-start ramp during turn-on. 8.1.2.2.1 noise reduction for low-noise applications, the c nr/ss capacitor forms an rc filter for filtering output noise that is otherwise amplified by the control loop. for low-noise applications, a c nr/ss of between 10 nf to 10 f is recommended. larger values for c nr/ss can be used; however, above 1 f there is little benefit in lowering the output voltage noise for frequencies above 10 hz. 8.1.2.2.2 soft-start and inrush current soft-start refers to the gradual ramp-up characteristic of the output voltage after the en and uvlo thresholds are exceeded. reducing how quickly the output voltage increases during startup also reduces the amount of current needed to charge the output capacitor, referred to as inrush current. inrush current is defined as the current going into the ldo during start-up. inrush current consists of the load current, the current used to charge the output capacitor, and the ground pin current (that contributes very little to inrush current). this current is difficult to measure because the input capacitor must be removed, which is not recommended. however, the inrush current can be estimated by equation 4 : where: ? v out (t) is the instantaneous output voltage of the turn-on ramp ? dv out (t)/dt is the slope of the v out ramp and ? r load is the resistive load impedance (4) out out out out load c dv (t) v (t) i (t) dt r u ? ? ? 1 ? 1
19 TPS7A91 www.ti.com sbvs282 ? december 2016 product folder links: TPS7A91 submit documentation feedback copyright ? 2016, texas instruments incorporated the TPS7A91 features a monotonic, voltage-controlled soft-start that is set by the user with an external capacitor (c nr/ss ). this soft-start helps reduce inrush current, minimizing load transients to the input power bus that can cause potential start-up initialization problems when powering fpgas, digital signal processors (dsps), or other high current loads. to achieve a monotonic start-up, the TPS7A91 error amplifier tracks the voltage ramp of the external soft-start capacitor until the voltage exceeds approximately 97% of the internal reference. the final 3% of v nr/ss is charged through the noise-reduction resistor (r nr ), creating an rc delay. r nr is approximately 280 k and applications that require the highest accuracy when using a large value c nr/ss must take this rc delay into account. the soft-start ramp time depends on the soft-start charging current (i nr/ss ), the soft-start capacitance (c nr/ss ), and the internal reference (v ref ). the approximate soft-start ramp time (t ss ) can be calculated with equation 5 : t ss = (v ref c nr/ss ) / i nr/ss (5) note that the value for i nr/ss is determined by the state of the ss_ctrl pin. when the ss_ctrl pin is connected to gnd, the typical value for the i nr/ss current is 6.2 a. connecting the ss_ctrl pin to in increases the typical soft-start charging current to 100 a. the larger charging current for i nr/ss is useful if shorter start-up times are needed (such as when using a large noise-reduction capacitor). 8.1.3 capacitor recommendation the TPS7A91 is designed to be stable using low equivalent series resistance (esr) ceramic capacitors at the input, output, and noise-reduction pin. multilayer ceramic capacitors have become the industry standard for these types of applications and are recommended, but must be used with good understanding of their limitations. ceramic capacitors that employ x7r-, x5r-, and cog-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of y5v-rated capacitors is discouraged precisely because the capacitance varies so widely. in all cases, ceramic capacitors vary a great deal with operating voltage and temperature and the design engineer must be aware of these characteristics. as a rule of thumb, ceramic capacitors are recommended to be derated by 50%. the input and output capacitors recommended herein account for a capacitance derating of 50%. 8.1.3.1 input and output capacitor requirements (c in and c out ) the TPS7A91 is designed and characterized for operation with ceramic capacitors of 10 f or greater at the input and output. locate the input and output capacitors as near as practical to the input and output pins to minimize the trace inductance from the capacitor to the device. attention must be given to the input capacitance to minimize transient input droop during startup and load current steps. note that simply using very large ceramic input capacitances can cause unwanted ringing at the output if the input capacitor (in combination with the wire-lead inductance) creates a high-q peaking effect during transients, which is why short, well-designed interconnect traces to the upstream supply are needed to minimize ringing. damping of unwanted ringing can be accomplished by using a tantalum capacitor, with a few hundred milliohms of esr, in parallel with the ceramic input capacitor. the uvlo circuit responds quickly to glitches on v in and disables the output of the device if this rail starts to collapse too quickly. use an input capacitor that is large enough to slow input transients to less then two volts per microsecond. 8.1.3.1.1 load-step transient response the load-step transient response is the output voltage response by the ldo to a step change in load current. the depth of charge depletion immediately after the load step is directly proportional to the amount of output capacitance. however, although larger output capacitances decrease any voltage dip or peak occurring during a load step, the control-loop bandwidth is also decreased, thereby slowing the response time. the ldo cannot sink charge, therefore when the output load is removed or greatly reduced, the control loop must turn off the pass-fet and wait for any excess charge to deplete. 8.1.3.2 feed-forward capacitor (c ff ) although a feed-forward capacitor (c ff ), from the fb pin to the out pin is not required to achieve stability, a 10- nf, feed-forward capacitor improves the noise and psrr performance. a higher capacitance c ff can be used; however, the startup time is longer and the power-good signal can incorrectly indicate that the output voltage has settled. for a detailed description, see the pros and cons of using a feedforward capacitor with a low-dropout regulator application report (sbva042).
20 TPS7A91 sbvs282 ? december 2016 www.ti.com product folder links: TPS7A91 submit documentation feedback copyright ? 2016, texas instruments incorporated 8.1.4 power dissipation (p d ) circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit on the printed circuit board (pcb), and correct sizing of the thermal plane. the pcb area around the regulator must be as free as possible of other heat-generating devices that cause added thermal stresses. to first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference and load conditions. p d can be calculated using equation 6 : p d = (v in ? v out ) i out (6) an important note is that power dissipation can be minimized, and thus greater efficiency achieved, by proper selection of the system voltage rails. for the lowest power dissipation use the minimum input voltage necessary for proper output regulation. the primary heat conduction path for the dsk package is through the thermal pad to the pcb. solder the thermal pad to a copper pad area under the device. this pad area should contain an array of plated vias that conduct heat to additional copper planes for increased heat dissipation. the maximum power dissipation determines the maximum allowable ambient temperature (t a ) for the device. power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance ( ja ) of the combined pcb and device package and the temperature of the ambient air (t a ), according to equation 7 . (7) unfortunately, the thermal resistance ( ja ) is highly dependent on the heat-spreading capability built into the particular pcb design, and therefore varies according to the total copper area, copper weight, and location of the planes. the ja recorded in the thermal information table is determined by the jedec standard, pcb, and copper-spreading area and is only used as a relative measure of package thermal performance. 8.1.5 estimating junction temperature the jedec standard now recommends the use of psi ( ) thermal metrics to estimate the junction temperatures of the ldo when in-circuit on a typical pcb board application. these metrics are not strictly speaking thermal resistances, but rather offer practical and relative means of estimating junction temperatures. these psi metrics are determined to be significantly independent of the copper-spreading area. the key thermal metrics ( jt and jb ) are given in the thermal information table and are used in accordance with equation 8 . where: ? p d is the power dissipated as explained in equation 6 ? t t is the temperature at the center-top of the device package and ? t b is the pcb surface temperature measured 1 mm from the device package and centered on the package edge (8) for a more detailed discussion on thermal metrics and how to use them, see the semiconductor and ic package thermal metrics application report (spra953). y y y jt j t jt d : t = t + p y jb j b jb d : t = t + p t = t + ( p j a ja d q )
21 TPS7A91 www.ti.com sbvs282 ? december 2016 product folder links: TPS7A91 submit documentation feedback copyright ? 2016, texas instruments incorporated 8.2 typical application this section discusses the implementation of the TPS7A91 to regulate from a 2-v input voltage to a 1.2-v output voltages for noise-sensitive loads. the schematic for this application circuit is provided in figure 39 . figure 39. application example 8.2.1 design requirements for the design example shown in figure 39 , use the parameters listed in table 3 as the input parameters. table 3. design parameters parameter application requirements design results input voltages (v in ) 2 v, 3%, provided by the dc-dc converter switching at 750 khz 1.4 v to 6.5 v maximum ambient operating temperature 55 c 101 c junction temperature output voltages (v out ) 1.2 v, 1% 1.2 v, 1% output currents (i out ) 1.0 a (max), 10 ma (min) 1.0 a (max), 5 ma (min) rms noise < 5 v rms , bandwidth = 10 hz to 100 khz 4.7 v rms , bandwidth = 10 hz to 100 khz psrr at 750 khz > 40 db 49 db startup time < 2 ms 800 s (typ) 1.48 s (max) 8.2.2 detailed design procedure the output voltage can be set to 1.2 v by selecting the correct values for r 1 and r 2 ; see equation 3 . input and output capacitors are selected in accordance with the capacitor recommendation section. ceramic capacitances of 10 f for both input and output are selected to help balance the charge needed during startup when charging the output capacitor, thus reducing the input voltage drop. to satisfy the required startup time (t ss ) and still maintain low-noise performance, a 0.1- f c nr/ss is selected for with ss_ctrl connected to v in . this value is calculated with equation 9 . using the i nr/ss(max) and the smallest c nr/ss capacitance resulting from manufacturing variance (often 20%) provides the fastest startup time, whereas using the i nr/ss(min) and the largest c nr/ss capacitance resulting from manufacturing variance provides the slowest startup time. t ss = (v ref c nr/ss ) / i nr/ss (9) with a 1.0-a maximum load, the internal power dissipation is 800 mw, corresponding to a 46 c junction temperature rise. with an 55 c maximum ambient temperature, the junction temperature is at 101 c. to minimize noise, a feed-forward capacitance (c ff ) of 10 nf is selected. see the layout section for an example of how to layout the TPS7A91 to achieve best psrr and noise. 1.2 v 2.0 v out pg in en TPS7A91 ss_ctrl nr/ss fb c in 10 p f c out 10 f c nr/ss 0.1 p f r 1 r 2 11.8 k : 5.9 k : v out r pg 20 k : pg gnd c ff 10 nf copyright ? 2016, texas instruments incorporated
22 TPS7A91 sbvs282 ? december 2016 www.ti.com product folder links: TPS7A91 submit documentation feedback copyright ? 2016, texas instruments incorporated 8.2.3 application curves figure 40. psrr vs frequency figure 41. output noise vs frequency 9 power supply recommendations the input of the TPS7A91 is designed to operate from an input voltage range between 1.4 v and 6.5 v and with an input capacitor of 10 f. the input voltage range must provide adequate headroom in order for the device to have a regulated output. this input supply must be well regulated. if the input supply is noisy, additional input capacitors can be used to improve the output noise performance. 10 layout 10.1 layout guidelines general guidelines for linear regulator designs are to place all circuit components on the same side of the circuit board and as near as practical to the respective ldo pin connections. place ground return connections to the input and output capacitors, and to the ldo ground pin as close to each other as possible, connected by a wide, component-side, copper surface. the use of vias and long traces to create ldo circuit connections is strongly discouraged and negatively affects system performance. 10.1.1 board layout to maximize the ac performance of the TPS7A91, following the layout example illustrated in figure 42 is recommended. this layout isolates the analog ground (agnd) from the noisy power ground. components that must be connected to the quiet analog ground are the noise reduction capacitor (c nr/ss ) and the lower feedback resistor (r 2 ). these components must have a separate connection back to the power pad of the device for optimal output noise performance. connect the gnd pin directly to the thermal pad and not to any external plane. to maximize the output voltage accuracy, the connection from the output voltage back to top output divider resistors (r 1 ) must be made as close as possible to the load. this method of connecting the feedback trace eliminates the voltage drop from the device output to the load. to improve thermal performance, use an array of thermal vias to connect the thermal pad to the ground planes. larger ground planes improve the thermal performance of the device and lowering the operating temperature of the device. frequency (hz) noise ( p v ? hz) 0.001 0.01 0.1 1 10 10 100 1k 10k 100k 1m 10m c nr 100 nf, 4.7 p v rms frequency (hz) power-supply rejection ratio (db) 0 10 20 30 40 50 60 70 80 90 10 100 1k 10k 100k 1m 10m v in 2.0 v
23 TPS7A91 www.ti.com sbvs282 ? december 2016 product folder links: TPS7A91 submit documentation feedback copyright ? 2016, texas instruments incorporated 10.2 layout example figure 42. TPS7A91 example layout out en in nr/ss fb ss_ctrl in out gnd 1 5 2 4 3 10 6 9 7 8 c in c out c nr/ss r 1 ground plane for thermal relief and signal ground v in v out pg r 2 c ff to pg pullup supply pg output to v in power ground plane denotes vias used for application purposes
24 TPS7A91 sbvs282 ? december 2016 www.ti.com product folder links: TPS7A91 submit documentation feedback copyright ? 2016, texas instruments incorporated (1) for the most current package and ordering information see the package option addendum at the end of this document, or see the device product folder at www.ti.com . 11 device and documentation support 11.1 device support 11.1.1 development support 11.1.1.1 evaluation modules an evaluation module (evm) is available to assist in the initial circuit performance evaluation using the TPS7A91. the summary information for this fixture is shown in table 4 . table 4. design kits and evaluation modules (1) name part number TPS7A91 low-dropout voltage regulator evaluation module TPS7A91evm-831 (1) for the most current package and ordering information see the package option addendum at the end of this document, or see the device product folder at www.ti.com . the evm can be requested at the texas instruments web site through the TPS7A91 product folder. 11.1.1.2 spice models computer simulation of circuit performance using spice is often useful when analyzing the performance of analog circuits and systems. a spice model for the TPS7A91 is available through the TPS7A91 product folder under simulation models. 11.1.2 device nomenclature table 5. ordering information (1) product description TPS7A91 xxyyyz xx represents the output voltage. 01 is the adjustable output version. yyy is the package designator. z is the package quantity. 11.2 documentation support 11.2.1 related documentation tps3890 low quiescent current, 1% accurate supervisor with programmable delay (slvsd65) TPS7A91evm user ' s guide (sbvu036) pros and cons of using a feedforward capacitor with a low-dropout regulator (sbva042) how to measure ldo noise (slyy076) semiconductor and ic package thermal metrics (spra953) 11.3 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document.
25 TPS7A91 www.ti.com sbvs282 ? december 2016 product folder links: TPS7A91 submit documentation feedback copyright ? 2016, texas instruments incorporated 11.4 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 11.5 trademarks e2e is a trademark of texas instruments. all other trademarks are the property of their respective owners. 11.6 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.7 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
package option addendum www.ti.com 18-dec-2016 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples TPS7A9101dskr active son dsk 10 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 19gp TPS7A9101dskt active son dsk 10 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 19gp (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release.
package option addendum www.ti.com 18-dec-2016 addendum-page 2 in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.

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