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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. lp873222-q1 snvsat3 ? june 2017 lp873222-q1 dual high-current buck converter and dual linear regulator 1 1 features 1 ? qualified for automotive applications ? aec-q100 qualified with the following results: ? device temperature grade 1: ? 40 c to +125 c ambient operating temperature ? input voltage: 2.8 v to 5.5 v ? two high-efficiency step-down dc-dc converters: ? output voltage: 0.7 v to 3.36 v ? maximum output current 2 a ? programmable output-voltage slew rate from 0.5 mv/ s to 10 mv/ s ? 2-mhz switching frequency ? spread-spectrum mode and phase interleaving for emi reduction ? two linear regulators: ? input voltage: 2.5 v to 5.5 v ? output voltage: 0.8 v to 3.3 v ? maximum output current 300 ma ? configurable general-purpose output signals (gpo, gpo2) ? interrupt function with programmable masking ? programmable power-good signal (pgood) ? output short-circuit and overload protection ? overtemperature warning and protection ? overvoltage protection (ovp) and undervoltage lockout (uvlo) ? 28-pin, 5-mm 5-mm vqfn package with wettable flanks simplified schematic 2 applications ? automotive head unit and cluster ? surround view system ecu ? radar system ecu ? automotive camera module ? automotive display 3 description the lp873222-q1 is designed to meet the power management requirements in automotive applications. the device contains two step-down dc- dc converters and two linear regulators and general- purpose digital-output signals. the device is controlled by an i 2 c-compatible serial interface and by an enable signal. the automatic pwm/pfm (auto mode) operation gives high efficiency over a wide output-current range. the lp873222-q1 supports remote voltage sensing to compensate ir drop between the regulator output and the point-of-load (pol) thus improving the accuracy of the output voltage. in addition the switching clock can be forced to pwm mode and also synchronized to an external clock to minimize the disturbances. the lp873222-q1 device supports programmable start-up and shutdown delays and sequences including gpo signals synchronized to the enable signal. during start-up and voltage change, the device controls the output slew rate to minimize output voltage overshoot and the in-rush current. device information part number package body size (nom) lp873222-q1 vqfn (28) 5.00 mm 5.00 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. dc-dc efficiency vs output current output current (a) efficiency (%) 0.001 0.01 0.1 1 2 50 60 70 80 90 100 d002 vin=3.7v, vout=1.0v vin=3.7v, vout=1.8v vin=3.7v, vout=2.5v sw_b0 vin_b0 vin_b1 vana vin fb_b0 vout_b0 load sda scl nint clkin (gpo2) gnds en gpo sw_b1 fb_b1 vout_b1 load pgood vout_ldo1 vout_ldo0 vin_ldo0 vin_ldo1 vout_ldo0 vout_ldo1 copyright ? 2017, texas instruments incorporated productfolder ordernow technical documents tools & software support &community
2 lp873222-q1 snvsat3 ? june 2017 www.ti.com product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 5 6.1 absolute maximum ratings ...................................... 5 6.2 esd ratings ............................................................ 5 6.3 recommended operating conditions ....................... 5 6.4 thermal information .................................................. 6 6.5 electrical characteristics ........................................... 6 6.6 i 2 c serial bus timing parameters .......................... 11 6.7 typical characteristics ............................................ 13 7 detailed description ............................................ 14 7.1 overview ................................................................. 14 7.2 functional block diagram ....................................... 15 7.3 feature description ................................................ 15 7.4 device functional modes ........................................ 33 7.5 programming ........................................................... 34 7.6 register maps ......................................................... 37 8 application and implementation ........................ 55 8.1 application information ............................................ 55 8.2 typical application .................................................. 55 9 power supply recommendations ...................... 63 10 layout ................................................................... 63 10.1 layout guidelines ................................................. 63 10.2 layout example .................................................... 65 11 device and documentation support ................. 66 11.1 device support ...................................................... 66 11.2 receiving notification of documentation updates 66 11.3 community resources .......................................... 66 11.4 trademarks ........................................................... 66 11.5 electrostatic discharge caution ............................ 66 11.6 glossary ................................................................ 66 12 mechanical, packaging, and orderable information ........................................................... 66 4 revision history date revision notes june 2017 * initial release
3 lp873222-q1 www.ti.com snvsat3 ? june 2017 product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) a: analog pin, d: digital pin, g: ground pin, p: power pin, i: input pin, o: output pin 5 pin configuration and functions rhd package 28-pin vqfn top view pin functions pin type (1) description number name 1 vout_ldo0 p/o ldo0 output. if ldo0 is not used, leave the pin floating. 2 fb_b0 a output voltage feedback (positive) for buck 0 3 fb_b1 a output voltage feedback (positive) for buck 1 4 agnd g ground 5 vana p/i supply voltage for analog and digital blocks. must be connected to same node with vin_bx. 6 en d/i programmable enable signal for regulators and gpos. if the pin is not used, leave the pin floating. 7 vout_ldo1 p/o ldo1 output. if ldo1 is not used, leave the pin floating. 8 vin_ldo1 p/i power input for ldo1. if ldo1 is not used, connect the pin to vana. 9 nint d/o open-drain interrupt output. active low. if the pin is not used, connect the pin to ground. 10 clkin d/i/o external clock input. alternative function is general-purpose digital output (gpo2). if the pin is not used, leave the pin floating. 11, 12 vin_b1 p/i input for buck 1. the separate power pins vin_bx are not connected together internally - vin_bx pins must be connected together in the application and be locally bypassed. 13, 14 sw_b1 p/o buck 1 switch node. if the buck 1 is not used, leave the pin floating. 15, 16 pgnd_b1 p/g power ground for buck 1 17 scl d/i serial interface clock input for i 2 c access. connect a pullup resistor. if the i 2 c interface is not used, connect the pin to ground. 18 sda d/i/o serial interface data input and output for i 2 c access. connect a pullup resistor. if the i 2 c interface is not used, connect the pin to ground. 19 sgnd g ground 20, 21 pgnd_b0 p/g power ground for buck 0 8 9 10 11 12 13 14 2 3 4 5 6 1 7 20 19 18 17 16 21 15 28 27 26 25 24 23 22 vin_ldo1 nint clkin vin_b1 vin_b1 sw_b1 sw_b1 pgnd_b1 pgnd_b1 scl sda sgnd pgnd_b0 pgnd_b0 vout_ldo1 en vana agnd fb_b1 fb_b0 vout_ldo0 sw_b0 sw_b0 vin_b0 vin_b0 gpo pgood vin_ldo0 thermal pad
4 lp873222-q1 snvsat3 ? june 2017 www.ti.com product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated pin functions (continued) pin type (1) description number name 22, 23 sw_b0 p/o buck 0 switch node. if the buck 0 is not used, leave the pin floating. 24, 25 vin_b0 p/i input for buck 0. the separate power pins vin_bx are not connected together internally - vin_bx pins must be connected together in the application and be locally bypassed. 26 gpo d/o general-purpose digital output. if the pin is not used, leave the pin floating. 27 pgood d/o power-good indication signal. if the pin is not used, leave the pin floating. 28 vin_ldo0 p/i power input for ldo0. if ldo0 is not used, connect the pin to vana. thermal pad ? ? connect to pcb ground plane using multiple vias for good thermal performance.
5 lp873222-q1 www.ti.com snvsat3 ? june 2017 product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltage values are with respect to network ground. 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) (2) min max unit vin_bx, vana voltage on power connections (must use the same input supply) ? 0.3 6 v vin_ldox voltage on power connections ? 0.3 6 v sw_bx voltage on buck switch nodes ? 0.3 (vin_bx + 0.3 v) with 6-v maximum v fb_bx voltage on buck voltage sense nodes ? 0.3 (vana + 0.3 v) with 6-v maximum v vout_ldox voltage on ldo output -0.3 (vin_ldox + 0.3 v) with 6-v maximum v sda, scl, nint, en voltage on logic pins (input or output pins) ? 0.3 6 v pgood, gpo, clkin (gpo2) voltage on logic pins (input or output pins) ? 0.3 (vana + 0.3 v) with 6-v maximum v t j-max junction temperature ? 40 150 c t stg storage temperature ? 65 150 maximum lead temperature (soldering, 10 seconds) 260 (1) aec q100-002 indicates that hbm stressing shall be in accordance with the ansi/esda/jedec js-001 specification. 6.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per aec q100-002 (1) 2000 v charged-device model (cdm), per aec q100-011 all pins 500 corner pins (1, 7, 8, 14, 15, 21, 22, 28) 750 6.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) min max unit input voltage vin_bx, vana voltage on power connections (must use the same input supply) 2.8 5.5 v vin_ldox voltage on ldo inputs 2.5 5.5 v en, nint voltage on logic pins (input or output pins) 0 5.5 v clkin voltage on logic pins (input pin) 0 vana with 5.5-v maximum v pgood, gpo, gpo2 voltage on logic pins (output pins) 0 vana v scl, sda voltage on i2c interface, standard (100 khz), fast (400 khz), fast+ (1 mhz), and high-speed (3.4 mhz) modes 0 1.95 v voltage on i2c interface, standard (100 khz), fast (400 khz), and fast+ (1 mhz) modes 0 vana with 3.6-v maximum v temperature t j junction temperature ? 40 140 c t a ambient temperature ? 40 125 c
6 lp873222-q1 snvsat3 ? june 2017 www.ti.com product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application note. 6.4 thermal information thermal metric (1) lp873222-q1 unit rhd (vqfn) 28 pins r ja junction-to-ambient thermal resistance 36.7 c/w r jctop junction-to-case (top) thermal resistance 26.6 c/w r jb junction-to-board thermal resistance 8.9 c/w jt junction-to-top characterization parameter 0.4 c/w jb junction-to-board characterization parameter 8.8 c/w r jcbot junction-to-case (bottom) thermal resistance 2.2 c/w (1) all voltage values are with respect to network ground. (2) minimum (min) and maximum (max) limits are specified by design, test, or statistical analysis. typical (typ) numbers are not verified, but do represent the most likely norm. (3) the maximum output current can be limited by the forward current limit i lim fwd . the power dissipation inside the die increases the junction temperature and limits the maximum current depending of the length of the current pulse, efficiency, board and ambient temperature. 6.5 electrical characteristics limits apply over the junction temperature range ? 40 c t j +140 c, specified v vana , v vin_bx , v vin_ldox , v vout_bx , v vout_ldox and i out range, unless otherwise noted. typical values are at t j = 25 c, v vana = v vin_bx = v vin_ldox = 3.7 v, and v out = 1 v, unless otherwise noted (1) (2) . parameter test conditions min typ max unit external components c in_buck input filtering capacitance for buck regulators effective capacitance, connected from vin_bx to pgnd_bx 1.9 10 f c out_buc k output filtering capacitance for buck regulators effective capacitance 10 22 500 f c pol_buc k point-of-load (pol) capacitance for buck regulators optional pol capacitance 22 f c out- total_bu ck buck output capacitance, total (local and pol) total output capacitance 500 f c in_ldo input filtering capacitance for ldo regulators effective capacitance, connected from vin_ldox to agnd. c in_ldo must be at least two times larger than c out_ldo 0.6 2.2 f c out_ldo output filtering capacitance for ldo regulators effective capacitance 0.4 1 2.7 f esr c input and output capacitor esr [1-10] mhz 2 10 m l inductor inductance of the inductor 0.47 h -30% 30% dcr l inductor dcr 25 m buck regulators v (vin_bx) , v (vana) input voltage range vin_bx and vana pins must be connected to the same supply line 2.8 3.7 5.5 v v out_bx output voltage programmable voltage range 0.7 1 3.36 v step size, 0.7 v v out < 0.73 v 10 mv step size, 0.73 v v out < 1.4 v 5 step size, 1.4 v v out 3.36 v 20 i out_bx output current output current 2 (3) a
7 lp873222-q1 www.ti.com snvsat3 ? june 2017 product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated electrical characteristics (continued) limits apply over the junction temperature range ? 40 c t j +140 c, specified v vana , v vin_bx , v vin_ldox , v vout_bx , v vout_ldox and i out range, unless otherwise noted. typical values are at t j = 25 c, v vana = v vin_bx = v vin_ldox = 3.7 v, and v out = 1 v, unless otherwise noted (1) (2) . parameter test conditions min typ max unit (4) the slew-rate can be limited by the current limit (forward or negative current limit), output capacitance and load current. (5) the final pfm-to-pwm and pwm-to-pfm switchover current varies slightly and is dependent on the output voltage, input voltage and the inductor current level. input and output voltage difference minimum voltage between v (vin_bx) and v out to fulfill the electrical characteristics 0.8 v v out_bx_ dc dc output voltage accuracy, includes voltage reference, dc load and line regulations, process and temperature force pwm mode, v out < 1 v ? 20 20 mv force pwm mode, v out 1 v ? 2% 2% pfm mode, v out < 1 v, the average output voltage level is increased by max. 20 mv ? 20mv 40mv mv pfm mode, v out 1 v, the average output voltage level is increased by max. 20 mv ? 2% 2% + 20 mv ripple voltage pwm mode, l = 0.47 h 10 mv p-p pfm mode, l = 0.47 h 25 dc lnr dc line regulation i out = 1 a 0.05 %/v dc ldr dc load regulation in pwm mode v out_bx = 1 v, i out from 0 to i out(max) 0.3% t ldsr transient load step response i out = 0.1 a to 2 a, t r = t f = 400 ns, pwm mode 55 mv t lnsr transient line response v (vin_bx) stepping 3 v ? 3.5 v, t r = t f = 10 s, i out = i out(max) 10 mv i lim fwd forward current limit for both bucks (peak for every switching cycle) programmable range 1.5 3 a step size 0.5 accuracy, v (vin_bx) 3 v, i lim = 3 a ? 5% 7.5% 20% accuracy, 2.8 v v (vin_bx) < 3 v, i lim = 3 a ? 20% 7.5% 20% i lim neg negative current limit 1.6 2.0 3.0 a r ds(on) hs fet on-resistance, high-side fet each phase, between vin_bx and sw_bx pins (i = 1 a) 50 110 m r ds(on) ls fet on-resistance, low-side fet each phase, between sw_bx and pgnd_bx pins (i = 1 a) 45 90 m ? sw switching frequency pwm mode 1.8 2 2.2 mhz start-up time (soft start) from enx to v out_bx = 0.35 v (slew-rate control begins) 120 s output voltage slew- rate (4) slew_ratex[2:0] = 010, c out-total_buck < 80 f ? 15% 10 15% mv/ s slew_ratex[2:0] = 011, c out-total_buck < 130 f 7.5 slew_ratex[2:0] = 100, c out-total_buck < 250 f 3.8 slew_ratex[2:0] = 101, c out-total_buck < 500 f 1.9 slew_ratex[2:0] = 110, c out-total_buck < 500 f 0.94 slew_ratex[2:0] = 111, c out-total_buck < 500 f 0.47 i pfm-pwm pfm-to-pwm - current threshold (5) 550 ma i pwm-pfm pwm-to-pfm - current threshold (5) 290 ma r dis_bx output pull-down resistance regulator disabled 150 250 350
8 lp873222-q1 snvsat3 ? june 2017 www.ti.com product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated electrical characteristics (continued) limits apply over the junction temperature range ? 40 c t j +140 c, specified v vana , v vin_bx , v vin_ldox , v vout_bx , v vout_ldox and i out range, unless otherwise noted. typical values are at t j = 25 c, v vana = v vin_bx = v vin_ldox = 3.7 v, and v out = 1 v, unless otherwise noted (1) (2) . parameter test conditions min typ max unit output voltage monitoring for pgood pin and for powergood interrupt v (vin_bx) and v (vana) fixed 3.7 v overvoltage threshold (compared to dc output voltage level, v vout_bx_dc ) 39 50 64 mv undervoltage threshold (compared to dc output voltage level, v vout_bx_dc ) ? 53 ? 40 ? 29 deglitch time during operation and after voltage change 4 15 s gating time for pgood signal after regulator enable or voltage change pgood_mode = 0 800 s ldo regulators v in_ldox input voltage range for ldo power inputs v in_ldox can be higher or lower than v (vana) 2.5 3.7 5.5 v v out_ldo x output voltage programmable voltage range 0.8 3.3 v step size 0.1 i out_ldox output current 300 ma dropout voltage v (vin_ldox) ? v (vout_ldox) , i out = i out(max) , programmed output voltage is higher than v (vin_ldox) 200 mv v out_ldo _dc dc output voltage accuracy, includes voltage reference, dc load and line regulations, process, temperature v out < 1 v ? 20 20 mv v out 1 v ? 2% 2% dc lnr dc line regulation i out = 1 ma 0.1 %/v dc ldr dc load regulation i out = 1 ma to i out(max) 0.8% t ldsr transient load step response i out = 1 ma to 300 ma, t r = t f = 1 s ? 50/+40 mv t lnsr transient line response v (vin_ldox) stepping 3 v ? 3.5 v, t r = t f = 10 s, i out = i out(max) 7 mv psrr power supply ripple rejection ? = 10 khz, i out = i out(max) 53 db noise 10 hz < f < 100 khz, i out = i out(max) 82 v rms i short(ld ox) ldo current limit v out = 0 v 400 500 600 ma start-up time from enable to valid output voltage 300 s slew rate during start-up 15 mv/ s r dis_ldox output pulldown resistance regulator disabled 150 250 350 output voltage monitoring for pgood pin and for power-good interrupt overvoltage monitoring, voltage rising (compared to dc output voltage level, v out_ldo_dc ) 106% 108% 110% overvoltage monitoring, hysteresis 3% 3.5% 4% undervoltage monitoring, voltage falling (compared to dc output voltage level, v out_ldo_dc ) 90% 92% 94% undervoltage monitoring, hysteresis 3% 3.5% 4% deglitch time during operation and after voltage change 4 15 s gating time for pgood signal after regulator enable or voltage change pgood_mode = 0 800 s
9 lp873222-q1 www.ti.com snvsat3 ? june 2017 product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated electrical characteristics (continued) limits apply over the junction temperature range ? 40 c t j +140 c, specified v vana , v vin_bx , v vin_ldox , v vout_bx , v vout_ldox and i out range, unless otherwise noted. typical values are at t j = 25 c, v vana = v vin_bx = v vin_ldox = 3.7 v, and v out = 1 v, unless otherwise noted (1) (2) . parameter test conditions min typ max unit (6) the external clock frequency must be selected so that buck switching frequency is above 1.7 mhz. external clock and pll f ext_clk external input clock (6) nominal frequency 1 24 mhz nominal frequency step size 1 required accuracy from nominal frequency ? 30% 10% external clock detection delay for missing clock detection 1.8 s delay and debounce for clock detection 20 clock change delay (internal to external) delay from valid clock detection to use of external clock 600 s pll output clock jitter cycle to cycle 300 ps, p-p protection functions thermal warning temperature rising, tdie_warn_level = 0 115 125 135 c temperature rising, tdie_warn_level = 1 127 137 147 hysteresis 20 thermal shutdown temperature rising 140 150 160 c hysteresis 20 vana ovp vana overvoltage voltage rising 5.6 5.8 6.1 v voltage falling 5.45 5.73 5.96 hysteresis 40 mv vana uvl o vana undervoltage lockout voltage rising 2.51 2.63 2.75 v voltage falling 2.5 2.6 2.7 buck short-circuit detection threshold 280 360 440 mv ldo short-circuit detection threshold 190 300 450 mv load current measurement for buck regulators current measurement range maximum code 10.22 a resolution lsb 20 ma measurement accuracy i out > 1 a < 10% measurement time pfm mode (automatically changing to pwm mode for the measurement) 45 s pwm mode 4 current consumption standby current consumption, regulators disabled 9 a active current consumption, one buck regulator enabled in auto mode, internal rc oscillator, pgood monitoring enabled i out_bx = 0 ma, not switching 58 a
10 lp873222-q1 snvsat3 ? june 2017 www.ti.com product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated electrical characteristics (continued) limits apply over the junction temperature range ? 40 c t j +140 c, specified v vana , v vin_bx , v vin_ldox , v vout_bx , v vout_ldox and i out range, unless otherwise noted. typical values are at t j = 25 c, v vana = v vin_bx = v vin_ldox = 3.7 v, and v out = 1 v, unless otherwise noted (1) (2) . parameter test conditions min typ max unit active current consumption, two buck regulators enabled in auto mode, internal rc oscillator, pgood monitoring enabled i out_bx = 0 ma, not switching 100 a active current consumption during pwm operation, one buck regulator enabled i out_bx = 0 ma 15 ma active current consumption during pwm operation, two buck regulators enabled i out_bx = 0 ma 30 ma ldo regulator enabled additional current consumption per ldo, i out_ldox = 0 ma 86 a pll and clock detector current consumption f ext_clk = 1 mhz, additional current consumption when enabled 2 ma digital input signals en, scl, sda, clkin v il input low level 0.4 v v ih input high level 1.2 v hys hysteresis of schmitt trigger inputs 10 80 200 mv en/clkin pulldown resistance en_pd/clkin_pd = 1 500 k digital output signals nint, sda v ol output low level nint: i source = 2 ma 0.4 v sda: i source = 20 ma 0.4 v r p external pullup resistor for nint to vio supply 10 k ? digital output signals pgood, gpo, gpo2 v ol output low level i source = 2 ma 0.4 v v oh output high level, configured to push-pull i sink = 2 ma v vana ? 0.4 v vana v v pu supply voltage for external pull-up resistor, configured to open-drain v vana v r pu external pull-up resistor, configured to open-drain 10 k ? all digital inputs i leak input current all logic inputs over pin voltage range ? 1 1 a
11 lp873222-q1 www.ti.com snvsat3 ? june 2017 product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) c b refers to the capacitance of one bus line. 6.6 i 2 c serial bus timing parameters these specifications are ensured by design. unless otherwise noted, v in_bx = 3.7 v. see (1) and figure 1 . min max unit f scl serial clock frequency standard mode 100 khz fast mode 400 fast mode+ 1 mhz high-speed mode, c b = 100 pf 3.4 high-speed mode, c b = 400 pf 1.7 t low scl low time standard mode 4.7 s fast mode 1.3 fast mode+ 0.5 high-speed mode, c b = 100 pf 0.16 high-speed mode, c b = 400 pf 0.32 t high scl high time standard mode 4 s fast mode 0.6 fast mode+ 0.26 high-speed mode, c b = 100 pf 0.06 high-speed mode, c b = 400 pf 0.12 t su;dat data setup time standard mode 250 ns fast mode 100 fast mode+ 50 high-speed mode 10 t hd;dat data hold time standard mode 10 3450 ns fast mode 10 900 fast mode+ 10 high-speed mode, c b = 100 pf 10 70 high-speed mode, c b = 400 pf 10 150 t su;sta setup time for a start or a repeated start condition standard mode 4.7 s fast mode 0.6 fast mode+ 0.26 high-speed mode 0.16 t hd;sta hold time for a start or a repeated start condition standard mode 4 s fast mode 0.6 fast mode+ 0.26 high-speed mode 0.16 t buf bus free time between a stop and start condition standard mode 4.7 s fast mode 1.3 fast mode + 0.5 t su;sto setup time for a stop condition standard mode 4 s fast mode 0.6 fast mode+ 0.26 high-speed mode 0.16 t rda rise time of sda signal standard mode 1000 ns fast mode 20 300 fast mode+ 120 high-speed mode, c b = 100 pf 10 80 high-speed mode, c b = 400 pf 20 160
12 lp873222-q1 snvsat3 ? june 2017 www.ti.com product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated i 2 c serial bus timing parameters (continued) these specifications are ensured by design. unless otherwise noted, v in_bx = 3.7 v. see (1) and figure 1 . min max unit t fda fall time of sda signal standard mode 300 ns fast mode 20 (v dd / 5.5 v) 300 fast mode+ 20 (v dd / 5.5 v) 120 high-speed mode, c b = 100 pf 10 80 high-speed mode, c b = 400 pf 30 160 t rcl rise time of scl signal standard mode 1000 ns fast mode 20 300 fast mode+ 120 high-speed mode, c b = 100 pf 10 40 high-speed mode, c b = 400 pf 20 80 t rcl1 rise time of scl signal after a repeated start condition and after an acknowledge bit high-speed mode, c b = 100 pf 10 80 ns high-speed mode, c b = 400 pf 20 160 t fcl fall time of a scl signal standard mode 300 ns fast mode 20 (v dd / 5.5 v) 300 fast mode + 20 (v dd / 5.5 v) 120 high-speed mode, c b = 10 ? 100 pf 10 40 high-speed mode, c b = 400 pf 20 80 c b capacitive load for each bus line (scl and sda) 400 pf t sp pulse width of spike suppressed (scl and sda spikes that are less then the indicated width are suppressed) standard mode, fast mode, and fast mode+ 50 ns high-speed mode 10 figure 1. i 2 c timing scl sda t low t rcl t hd;dat t high t fcl t su;dat t su;sta t su;sto start repeated start stop t hd;sta start t sp t rda t buf t fda t hd;sta
13 lp873222-q1 www.ti.com snvsat3 ? june 2017 product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 6.7 typical characteristics unless otherwise specified: v (vin_bx) = v (vin_ldox) = v (vana) = 3.7 v, v out_bx = 1 v, v out_ldo = 1 v, t a = 25 c, l = 0.47 h (toko dfe252012pd-r47m), c out_buck = 22 f, c pol_buck = 22 f, and c out_ldo = 1 f. regulators disabled figure 2. standby current consumption vs input voltage v out_bx = 1 v load = 0 ma figure 3. active state current consumption vs input voltage, one buck regulator enabled in pfm mode v out_bx = 1 v load = 0 ma figure 4. active state current consumption vs input voltage, one buck regulator enabled in forced pwm mode v out_ldox = 1 v load = 0 ma figure 5. active state current consumption vs input voltage, one ldo regulator enabled input voltage (v) input current ( p a) 2.5 3 3.5 4 4.5 5 5.5 80 82 84 86 88 90 92 94 96 98 100 d104 input voltage (v) input current ( p a) 2.5 3 3.5 4 4.5 5 5.5 5 6 7 8 9 10 11 12 13 14 15 d101 input voltage (v) input current ( p a) 2.5 3 3.5 4 4.5 5 5.5 50 52 54 56 58 60 62 64 66 68 70 d102 input voltage (v) input current (ma) 2.5 3 3.5 4 4.5 5 5.5 4 6 8 10 12 14 16 18 20 22 24 d103
14 lp873222-q1 snvsat3 ? june 2017 www.ti.com product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 7 detailed description 7.1 overview the lp873222-q1 is a high-efficiency, high-performance flexible power supply device with two step-down dc- dc converter cores (buck0 and buck1) and two low-dropout (ldo) linear regulators (ldo0 and ldo1) for automotive applications. table 1 lists the output characteristics of the regulators. table 1. supply specification supply output v out range (v) resolution (mv) i max maximum output current (ma) buck0 0.7 to 3.36 10 (0.7 v to 0.73 v) 5 (0.73 v to 1.4 v) 20 (1.4 v to 3.36 v) 2000 buck1 0.7 to 3.36 10 (0.7 v to 0.73 v) 5 (0.73 v to 1.4 v) 20 (1.4 v to 3.36 v) 2000 ldo0 0.8 to 3.3 100 300 ldo1 0.8 to 3.3 100 300 the lp873222-q1 also supports switching clock synchronization to an external clock (clkin pin). the nominal frequency of the external clock can be from 1 mhz to 24 mhz with 1-mhz steps. additional features include: ? soft-start ? input voltage protection: ? undervoltage lockout ? overvoltage protection ? output voltage monitoring and protection: ? overvoltage monitoring ? undervoltage monitoring ? overload protection ? thermal warning ? thermal shutdown the lp873222-q1 has one dedicated general purpose digital output (gpo) signal. clkin pin can be programmed as a second gpo signal (gpo2) if external clock is not needed. the output type (open-drain or push-pull) is programmable for the gpos.
15 lp873222-q1 www.ti.com snvsat3 ? june 2017 product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.2 functional block diagram 7.3 feature description 7.3.1 dc-dc converters 7.3.1.1 overview the lp873222-q1 includes two step-down dc-dc converter cores. the cores are designed for flexibility; most of the functions are programmable, thus giving a possibility to optimize the regulator operation for each application. the buck regulators deliver 0.7-v to 3.36-v regulated voltage rails from a 2.8-v to 5.5-v supply voltage. the lp873222-q1 has the following features: ? dvs support with programmable slew rate ? automatic mode control based on the loading (pfm or pwm mode) ? forced pwm mode option ? optional external clock input to minimize crosstalk ? optional spread-spectrum technique to reduce emi ? phase control for optimized emi ? synchronous rectification ? current mode loop with pi compensator ? soft start ? power good flag with maskable interrupt ? power good signal (pgood) with selectable sources uvlo sw reset digital logic registers i2c enable/ disable, delay control slew-rate control interrupts nint sda scl en vana otp eprom thermal monitor oscillator buck0 ilim det pwrgood det overload and sc det buck1 ldo0 ldo1 ilim det pwrgood det overload and sc det ilim det pwrgood det overload and sc det ilim det pwrgood det overload and sc det ref & bias iload adc iload adc clkin (gpo2) pgood gpo copyright ? 2016, texas instruments incorporated
16 lp873222-q1 snvsat3 ? june 2017 www.ti.com product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated feature description (continued) ? average output current sensing (for pfm entry and load current measurement) the following parameters can be programmed via registers, the default values are set by otp bits: ? output voltage ? forced pwm operation ? switch current limit ? output voltage slew rate ? enable and disable delays there are two modes of operation for the buck converter, depending on the output current required: pulse-width modulation (pwm) and pulse-frequency modulation (pfm). the converter operates in pwm mode at high load currents of approximately 600 ma or higher. lighter output current loads cause the converter to automatically switch into pfm mode for reduced current consumption when forced pwm mode is disabled. the forced pwm mode can be selected to maintain fixed switching frequency at all load current levels. a block diagram of a single core is shown in figure 6 . figure 6. detailed block diagram showing one core 7.3.1.2 transition between pwm and pfm modes pwm mode operation optimizes efficiency at mid to full load at the expense of light-load efficiency. the lp873222-q1 converter operates in pwm mode at load current of about 600 ma or higher. at lighter load current levels the device automatically switches into pfm mode for reduced current consumption when forced pwm mode is disabled (auto mode operation). by combining the pfm and the pwm modes a high efficiency is achieved over a wide output-load current range. 7.3.1.3 buck converter load current measurement buck load current can be monitored via i 2 c registers. the monitored buck converter is selected with the load_current_buck_select bit in sel_i_load register. a write to this selection register starts a current measurement sequence. the regulator is automatically forced to pwm mode for the measurement period. the measurement sequence is 50 s long, maximum. lp873222-q1 can be configured to give out an interrupt (i_meas_int bit in int_top_1 register) after the load current measurement sequence is finished. load current measurement interrupt can be masked with i_meas_mask bit (top_mask_1 register). the measurement result can be read from registers i_load_1 and i_load_2. register i_load_1 bits buck_load_current[7:0] give out the lsb bits and register i_load_2 bit buck_load_current[8] the msb bit. the measurement result buck_load_current[8:0] lsb is 20 ma, and maximum code value of the measurement corresponds to 10.22 a. fb + - + - power good loop comp ramp generator hs fet current sense ls fet current sense gate control iadc vdac error amp gnd neg current limit zero cross detect sw -+ pos current limit vin v out control block programmable parameters slave interface voltage setting slew rate control master interface copyright ? 2016, texas instruments incorporated
17 lp873222-q1 www.ti.com snvsat3 ? june 2017 product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated feature description (continued) 7.3.1.4 spread-spectrum mode systems with periodic switching signals may generate a large amount of switching noise in a set of narrowband frequencies (the switching frequency and its harmonics). the usual solution to reduce noise coupling is to add emi-filters and shields to the boards. the lp873222-q1 has register selectable spread-spectrum mode which minimizes the need for output filters, ferrite beads, or chokes. in spread spectrum mode, the switching frequency varies around the center frequency, reducing the emi emissions radiated by the converter and associated passive components and pcb traces (see figure 7 ). this feature is available only when internal rc oscillator is used (en_pll bit is 0 in pll_ctrl register), and it is enabled with the en_spread_spec bit in config register, and it affects both buck cores. where a fixed frequency converter exhibits large amounts of spectral energy at the switching frequency, the spread spectrum architecture of the lp873222-q1 spreads that energy over a large bandwidth. figure 7. spread-spectrum modulation 7.3.2 sync clock functionality the lp873222-q1 device contains a clkin input to synchronize the switching clock of the buck regulators with the external clock. the block diagram of the clocking and pll module is shown in figure 8 . depending on the en_pll bit in pll_ctrl register and the external clock availability, the external clock is selected and interrupt is generated as shown in table 2 . the interrupt can be masked with sync_clk_mask bit in top_mask_1 register. the nominal frequency of the external input clock is set by ext_clk_freq[4:0] bits in pll_ctrl register, and it can be from 1 mhz to 24 mhz with 1-mhz steps. the external clock must be inside accuracy limits ( ? 30%/+10%) of the selected frequency for valid clock detection. the sync_clk_int interrupt in int_top_1 register is also generated in cases where the external clock is expected but it is not available. these cases are start-up (read otp-to-standby transition) when en_pll is 1 and buck regulator enable (standby-to-active transition) when en_pll is 1. power spectrum is spread and lowered frequency radiaded energy
18 lp873222-q1 snvsat3 ? june 2017 www.ti.com product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated feature description (continued) figure 8. clock and pll module table 2. pll operation device operation mode en_pll pll and clock detector state interrupt for external clock clock standby 0 disabled no internal rc active 0 disabled no internal rc standby 1 enabled when external clock appears or disappears automatic change to external clock when available active 1 enabled when external clock appears or disappears automatic change to external clock when available 7.3.3 low-dropout linear regulators (ldos) the lp873222-q1 device includes two identical linear regulators, ldo0 and ldo1, targeting analog loads with low noise requirements. the ldo regulators deliver 0.8-v to 3.3-v regulated voltage rails from a 2.5-v to 5.5-v input voltage. both regulators have dedicated inputs which can be higher or lower than the device system voltage v (vana) to minimize the power dissipation. 7.3.4 power-up the power-up sequence for the lp873222-q1 is as follows: ? vana (and vin_bx) reach minimum recommended levels (v vana > vana uvlo ). this initiates power-on-reset (por), otp reading, and enables the system i/o interface. the i 2 c host should allow at least 1.2 ms before writing or reading data to the lp873222-q1. ? device enters standby mode. ? the host can change the default register setting by i 2 c if needed. ? the regulators can be enabled/disabled and the gpo signals can be controlled by en pin and by i 2 c interface. transitions between the operating modes are shown in modes of operation . 7.3.5 regulator control 7.3.5.1 enabling and disabling regulators the regulators can be enabled when the device is in standby or active state. there are two ways for enable and disable the buck regulators: ? using buckx_en bit in buckx_ctrl_1 register (buckx_en_pin_ctrl bit is 0 in buckx_ctrl_1 register) ? using en control pin (buckx_en bit is 1 and buckx_en_pin_ctrl bit is 1) 24mhz rc oscillator clkin divider (;7 _clk_ )5(4 pll divider 24 clkin detector clock select logic internal 24mhz clock 1mhz 1mhz (1 _ 3// 24mhz
19 lp873222-q1 www.ti.com snvsat3 ? june 2017 product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated similarly there are two ways to enable and disable the ldo regulators: ? using ldox_en bit in ldox_ctrl register (ldox_en_pin_ctrl bit is 0 in ldox_ctrl register) ? using en control pin (ldox_en bit is 1 and ldox_en_pin_ctrl bit is 1) if the en control pin is used for enable and disable then the delay from the control signal rising edge to start-up is set by buckx_startup_delay[3:0] bits in buckx_delay register and ldox_startup_delay[3:0] bits in ldox_delay register and the delay from control signal falling edge to shutdown is set by buckx_shutdown_delay[3:0] bits in buckx_delay register and ldox_shutdown_delay[3:0] bits in ldox_delay register. the delays are valid only for en signal transitions and not for control with i 2 c writings to buckx_en and ldox_en bits. the control of the regulator (with 0-ms delays) is shown in table 3 . table 3. regulator control buckx_en / ldox_en buckx_en_pin_ctrl / ldox_en_pin_ctrl en pin buckx output voltage / ldox output voltage enable/disable control with buckx_en/ldox_en bit 0 don't care don't care disabled 1 0 don't care buckx_vset[7:0] / ldox_vset[4:0] enable/disable control with en pin 1 1 low disabled 1 1 high buckx_vset[7:0] / ldox_vset[4:0] the buck regulator is enabled by the en pin or by i 2 c writing as shown in figure 9 . the soft-start circuit limits the in-rush current during start-up. when the output voltage rises to a 0.35-v level, the output voltage becomes slew- rate controlled. if there is a short circuit at the output, and the output voltage does not increase above the 0.35-v level in 1 ms or the output voltage drops below 0.35-v level during operation (for minimum of 1 ms), the regulator is disabled, and buckx_sc_int interrupt in int_buck register is set. when the output voltage reaches the power-good threshold level the buckx_pg_int interrupt flag in int_buck register is set. the power-good interrupt flag when reaching valid output voltage can be masked using buckx_pgr_mask bit in buck_mask register. the power-good interrupt flag can be also generated when the output voltage becomes invalid. the interrupt mask for invalid output voltage detection is set by buckx_pgf_mask bit in buck_mask register. a buckx_pg_stat bit in buck_stat register shows always the validity of the output voltage: 1 means valid and 0 means invalid output voltage. a pgood_window_buck bit in pgood_ctrl_1 register sets the detection method for the valid buck output voltage, either undervoltage detection or undervoltage and overvoltage detection.
20 lp873222-q1 snvsat3 ? june 2017 www.ti.com product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 9. buck regulator enable and disable the ldo regulator is enabled by the en pin or by i 2 c writing as shown in figure 10 . the soft-start circuit limits the in-rush current during start-up. output voltage increase rate is less than 100 mv/ sec during soft-start. if there is a short circuit at the output, and the output voltage does not increase above the 0.3-v level in 1 ms or the output voltage drops below 0.3-v level during operation (for minimum of 1 ms), the regulator is disabled, and ldox_sc_int interrupt in int_ldo register is set. when the output voltage reaches the power-good threshold level the ldox_pg_int interrupt flag in int_ldo register is set. the power-good interrupt flag when reaching valid output voltage can be masked using ldox_pgr_mask bit in ldo_mask register. the power-good interrupt flag can be also generated when the output voltage becomes invalid. the interrupt mask for invalid output voltage detection is set by ldox_pgf_mask bit in ldo_mask register. a ldox_pg_stat bit in ldo_stat register shows always the validity of the output voltage; 1 means valid, and 0 means invalid output voltage. a pgood_window_ldo bit in pgood_ctrl_1 register sets the detection method for the valid ldo output voltage, either undervoltage detection or undervoltage and overvoltage detection. 0.6v enable time voltage soft start ramp buckx_ctrl_2(buckx_slew_rate[2:0]) resistive pull-down (if enabled) buckx_vset[7:0] int_buck(buckx_pg_int) nint powergood buck_stat(buckx_pg_stat) 0.35v voltage decrease because of load buck_stat(buckx_stat) buck_mask(buckx_pgf_mask) = 0 buck_mask(buckx_pgr_mask) = 0 host clears interrupts powergood interrupts 0 0 1 0 0 1 0 1 1 0 0 1 0 1 0 1 0
21 lp873222-q1 www.ti.com snvsat3 ? june 2017 product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 10. ldo regulator enable and disable the en input pin have an integrated pulldown resistor. the pulldown resistor is controlled with en_pd bit in config register. 7.3.5.2 changing output voltage the output voltage of the regulator can be changed by writing to the buckx_vout / ldox_vout register. the voltage change for buck regulator is always slew-rate controlled, and the slew-rate is defined by the buckx_slew_rate[2:0] bits in buckx_ctrl_2 register. during voltage change the forced pwm mode is used automatically. when the programmed output voltage is achieved, the mode becomes the one defined by load current, and the buckx_fpwm bit in buckx_ctrl_1 register. the voltage change and power-good interrupts are shown in figure 11 . enable time voltage resistive pull-down (if enabled) ldox_vset[4:0] int_ldo(ldox_pg_int) nint host clears interrupts powergood interrupts powergood ldo_stat(ldox_pg_stat) 0 0 1 voltage decrease because of load ldo_stat(ldox_stat) 0 0 1 0 1 1 0 0 1 0 1 0 ldo_mask(ldox_pgf_mask) = 0 ldo_mask(ldox_pgr_mask) = 0 1 0
22 lp873222-q1 snvsat3 ? june 2017 www.ti.com product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 11. regulator output voltage change during an ldo voltage change the internal reference for the power-good detection is also changed. for this reason the power good may toggle during the ldo voltage change can indicate valid output even when the output voltage is changing. this period takes less than 100 s and after that time the power good gives correct value. 7.3.6 enable and disable sequences the lp873222-q1 device supports start-up and shutdown sequencing with programmable delays for different regulator outputs using single en control signal. the buck regulator is selected for delayed control with: ? buckx_en = 1 in buckx_ctrl_1 register ? buckx_en_pin_ctrl = 1 in buckx_ctrl_1 register ? buckx_vset[7:0] bits in buckx_vout register defines the voltage when en pin is high ? the delay from rising edge of en pin to the regulator enable is set by buckx_startup_delay[3:0] bits in buckx_delay register and ? the delay from falling edge of en pin to the regulator disable is set by buckx_shutdown_delay[3:0] bits in buckx_delay register. time voltage ramp for buck buckx_ctrl2(slew_ratex[2:0]) buckx_vset / ldox_vset int_buck(buckx_pg_int) / int_ldo(ldox_pg_int) nint host clears interrupt powergood interrupt powergood buck_stat(buckx_stat) / ldo_stat(ldox_stat) 1 powergood buck_stat(buckx_pg_stat) / ldo_stat(ldox_pg_stat) host clears interrupt powergood interrupt 1 0 1 0 1 0 1 0 1 0 buck_mask(buckx_pgf_mask)=0 buck_mask(buckx_pgr_mask)=0 ldo_mask(ldox_pgf_mask)=0 ldo_mask(ldox_pgr_mask)=0
23 lp873222-q1 www.ti.com snvsat3 ? june 2017 product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated in the same way the ldo regulator is selected for delayed control with: ? ldox_en = 1 in ldox_ctrl register ? ldox_en_pin_ctrl = 1 in ldox_ctrl register ? ldox_vset[4:0] bits in ldox_vout register defines the voltage when en pin is high ? the delay from rising edge of en pin to the regulator enable is set by ldox_startup_delay[3:0] bits in ldox_delay register and ? the delay from falling edge of en pin to the regulator disable is set by ldox_shutdown_delay[3:0] bits in ldox_delay register. the gpo (and gpo2) digital output signals can be also controlled as a part of start-up and shutdown sequencing with the following settings: ? gpox_en = 1 in gpo_ctrl register ? gpox_en_pin_ctrl = 1 in gpo_ctrl register ? the delay from rising edge of en pin to the rising edge of gpo/gpo2 signal is set by gpox_startup_delay[3:0] bits in gpox_delay register and ? the delay from falling edge of en pin to the falling edge of gpo/gpo2 signal is set by gpox_shutdown_delay[3:0] bits in gpox_delay register. an example of the start-up and shutdown sequences for the buck regulators are shown in figure 12 . the start-up and shutdown delays for the buck0 regulator are 1 ms and 4 ms; for the buck1 regulator start-up and shutdown delays are 3 ms and 1 ms. the delay settings are used only for enable/disable control with en signal. figure 12. start-up and shutdown sequencing 7.3.7 device reset scenarios there are three reset methods implemented on the lp873222-q1: ? software reset with sw_reset bit in reset register en en_buck0 en 1ms 3ms en_buck1 1ms 4ms en_buck0 en_buck1 3ms 1ms 1ms 4ms typical sequence sequence with short en low and high periods startup cntr shutdown cntr 0 0 1 0 0 1 0 1 2 3 4 5 6 0 0 1 2 0 1 2 3 4 5
24 lp873222-q1 snvsat3 ? june 2017 www.ti.com product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated ? undervoltage lockout (uvlo) reset from vana supply an sw reset occurs when sw_reset bit is written 1. the bit is automatically cleared after writing. this event disables all the regulators immediately, drives gpo and gpo2 signals low, resets all the register bits to the default values and otp bits are loaded (see figure 18 ). i 2 c interface is not reset during software reset. if vana supply voltage falls below the uvlo threshold level then all the regulators are disabled immediately, gpo and gpo2 signals are driven low, and all the register bits are reset to the default values. when the vana supply voltage transition above uvlo threshold level an internal por occurs. otp bits are loaded to the registers and a startup is initiated according to the register settings. 7.3.8 diagnosis and protection features the lp873222-q1 is capable of providing four levels of protection features: ? information of valid regulator output voltage which sets interrupt or pgood signal; ? warnings for diagnosis which sets interrupt; ? protection events which are disabling the regulators; and ? faults which are causing the device to shutdown. the lp873222-q1 sets the flag bits indicating what protection or warning conditions have occurred, and the nint pin is pulled low. nint is released again after a clear of flags is complete. the nint signal stays low until all the pending interrupts are cleared. when a fault is detected or software requested reset, it is indicated by a reset_reg_int interrupt flag in int_top_2 register after next start-up. if the reset_reg_mask is set to masked in the otp, the interrupt is not generated. the mask bit change with i 2 c does not affect, because the reset_reg_mask bit is loaded from otp during reset sequence. table 4. summary of interrupt signals event outcome interrupt bit interrupt mask bit status bit recovery/interrupt clear buck current limit triggered no effect buck_int buckx_ilim_int buckx_ilim_mask buckx_ilim_stat write 1 to buckx_ilim_int bit interrupt is not cleared if current limit is active ldo current limit triggered no effect ldo_int ldox_ilim_int ldox_ilim_mask ldox_ilim_stat write 1 to ldox_ilim_int bit interrupt is not cleared if current limit is active buck short circuit (v vout < 0.35 v at 1 ms after enable) or overload (v vout decreasing below 0.35 v during operation, 1- ms debounce) regulator disable buck_int buckx_sc_int n/a n/a write 1 to buckx_sc_int bit ldo short circuit (v vout < 0.3 v at 1 ms after enable) or overload (v vout decreasing below 0.3 v during operation, 1-ms debounce) regulator disable ldo_int ldox_sc_int n/a n/a write 1 to ldox_sc_int bit thermal sarning no effect tdie_warn_int tdie_warn_mask tdie_warn_stat write 1 to tdie_warn_int bit interrupt is not cleared if temperature is above thermal warning level thermal shutdown all regulators disabled immediately and gpo and gpo2 are set to low tdie_sd_int n/a tdie_sd_stat write 1 to tdie_sd_int bit interrupt is not cleared if temperature is above thermal shutdown level vana overvoltage (vana ovp ) all regulators disabled immediately and gpo and gpo2 are set to low ovp_int n/a ovp_stat write 1 to ovp_int bit interrupt is not cleared if vana voltage is above vana ovp level buck power good, output voltage becomes valid no effect buck_int buckx_pg_int buckx_pgr_mask buckx_pg_stat write 1 to buckx_pg_int bit buck power good, output voltage becomes invalid no effect buck_int buckx_pg_int buckx_pgf_mask buckx_pg_stat write 1 to buckx_pg_int bit ldo power good, output voltage becomes valid no effect ldo_int ldox_pg_int ldox_pgr_mask ldox_pg_stat write 1 to ldox_pg_int bit
25 lp873222-q1 www.ti.com snvsat3 ? june 2017 product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated table 4. summary of interrupt signals (continued) event outcome interrupt bit interrupt mask bit status bit recovery/interrupt clear (1) pgood_stat bit is 1 when the pgood pin shows valid voltages. pgood_pol bit in pgood_ctrl_1 register affects only pgood pin polarity, not power good and pgood_int interrupt polarity. (2) interrupt is generated during clock-detector operation and if clock is not available when clock detector is enabled. ldo power good, output voltage becomes invalid no effect ldo_int ldox_pg_int ldox_pgf_mask ldox_pg_stat write 1 to ldox_pg_int bit pgood pin changing from active to inactive state (1) no effect pgood_int pgood_mask pgood_stat write 1 to pgood_int bit external clock appears or disappears no effect to regulators sync_clk_int (2) sync_clk_mask sync_clk_stat write 1 to sync_clk_int bit load current measurement ready no effect i_meas_int i_meas_mask n/a write 1 to i_meas_int bit supply voltage vana uvlo triggered (vana falling) immediate shutdown, registers reset to default values n/a n/a n/a n/a supply voltage vana uvlo triggered (vana rising) startup, registers reset to default values and otp bits loaded reset_reg_int reset_reg_mask n/a write 1 to reset_reg_int bit software requested reset immediate shutdown followed by power up, registers reset to default values reset_reg_int reset_reg_mask n/a write 1 to reset_reg_int bit 7.3.8.1 power-good information (pgood pin) in addition to the interrupt-based indication of the current limit and the power-good level the lp873222-q1 device supports monitoring with pgood signal: ? regulator output voltage, ? input supply overvoltage, ? thermal warning and ? thermal shutdown. regulator output voltage monitoring (not current limit monitoring) can be selected for pgood indication. this selection is individual for both buck regulators and both ldo regulators and is set by en_pgood_buckx bits in pgood_ctrl_1 register and en_pgood_ldox bits in pgood_ctrl_1 register. when a regulator is disabled, the monitoring is automatically masked to prevent it forcing pgood inactive. a thermal warning can be also selected for pgood indication with en_pgood_twarn bit in pgood_ctrl_2 register. the monitoring from all the output rails, thermal warning (tdie_warn_stat), input overvoltage interrupt (ovp_int), and thermal shutdown interrupt (tdie_sd_int) are combined, and pgood pin is active only if all the selected sources shows a valid status. the type of output voltage monitoring for pgood signal is selected by pgood_window_x bits in pgood_ctrl_1 register. if the bit is 0, only undervoltage is monitored; if the bit is 1, both undervoltage and overvoltage are monitored. the polarity and the output type (push-pull or open-drain) are selected by the pgood_pol and pgood_od bits in the pgood_ctrl_1 register. pgood is only active or asserted when all enabled power resource output voltages are within specified tolerance for each requested/programmed output voltage. pgood is inactive or de-asserted if any enabled power resource output voltages is outside specified tolerance for each requested/programmed output voltage. the device otp setting selects either gated (that is, unusual ) or continuous (that is, invalid ) mode of operation. 7.3.8.1.1 pgood pin gated mode the gated (or unusual ) mode of operation is selected by setting pgood_mode bit to 0 in pgood_ctrl_2 register. for the gated mode of operation, pgood behaves as follows: ? pgood is set to active or asserted state upon exiting otp configuration as an initial default state.
26 lp873222-q1 snvsat3 ? june 2017 www.ti.com product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated ? pgood status is suspended or unchanged during an 800- s gated time period, thereby gating-off the status indication. ? during normal power-up sequencing and requested voltage changes, pgood state is not changed during an 800- s gated time period. it typically remains active or asserted for normal conditions. ? during an abnormal power-up sequencing and requested voltage changes, pgood status could change to inactive or de-asserted after an 800- s gated time period if any output voltage is outside of regulation range. ? using the gated mode of operation could allow the pgood signal to initiate an immediate power shutdown sequence if the pgood signal is wired-or with signal connected to en input. this type of circuit configuration provides a smart porz function for processor that eliminates the need for additional components to generate porz upon start-up and to monitor voltage levels of key voltage domains. the fault sets corresponding fault bit 1 in pg_fault register. the detected fault must be cleared to continue the pgood monitoring. the overvoltage and thermal shutdown are cleared by writing 1 to the ovp_int and tdie_sd_int interrupt bits in int_top_1 register. the regulator fault is cleared by writing 1 to the corresponding register bit in pg_fault register. the interrupts can be also cleared with vana uvlo by toggling the input supply. an example of pgood pin operation in gated mode is shown in figure 13 . figure 13. pgood pin operation in gated mode 7.3.8.1.2 pgood pin continuous mode the continuous (or unvalid ) mode of operation is selected by setting pgood_mode bit to 1 in pgood_ctrl_2 register. for the continuous mode of operation, pgood behaves as follows: ? pgood is set to active or asserted state upon exiting otp configuration. ? pgood is set to inactive or de-asserted as soon as regulator is enabled. ? pgood status begins indicating output voltage regulation status immediately and continuously. ? during power-up sequencing and requested voltage changes, pgood will toggle between inactive or de- asserted while output voltages are outside of regulation ranges and active or asserted when inside of regulation ranges. v (vana) vana_uvlo state shut down read otp standby pgood pin en pin vout (buck1) vout (ldo0) buck1 internal powergood ldo0 internal powergood active 800us timer buck internal enable 800us timer ldo0 internal enable 4ms 2ms clear fault
27 lp873222-q1 www.ti.com snvsat3 ? june 2017 product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated the pg_fault register bits are latched and maintain the fault information until host clears the fault bit by writing 1 to the bit. the pgood signal indicates also a thermal shutdown and input overvoltage interrupts, which are cleared by clearing the interrupt bits. when regulator voltage is transitioning from one target voltage to another, the pgood signal is set inactive. when the pgood signal becomes inactive, the source for the fault can be read from pg_fault register. if the invalid output voltage becomes valid again the pgood signal becomes active. thus the pgood signal shows all the time if the monitored output voltages are valid. the block diagram for this operation is shown in figure 14 and an example of operation is shown in figure 15 . the pgood signal can be also configured so that it maintains inactive state even when the monitored outputs are valid but there are pg_fault_x bits in pg_fault register pending clearance. this type of operation is selected by setting pgfault_gates_pgood bit to 1 in pgood_ctrl_2 register. figure 14. pgood block diagram (continuous mode) buck0 power good en_pgood _buck0 buck1 pgood active high en_pgood _buck1 ldo0 en_pgood _ldo0 ldo1 en_pgood _ldo1 tdie_sd_int ovp_int power good power good power good copyright ? 2016, texas instruments incorporated tdie_warn_stat en_pgood _twarn
28 lp873222-q1 snvsat3 ? june 2017 www.ti.com product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 15. pgood pin operation in continuous mode 7.3.8.2 warnings for diagnosis (interrupt) 7.3.8.2.1 output power limit the buck regulators have programmable output peak current limits. the limits are individually programmed for both regulators with buckx_ilim[2:0] bits in buckx_ctrl_2 register. if the load current is increased so that the current limit is triggered, the regulator continues to regulate to the limit current level (peak current regulation). the voltage may decrease if the load current is higher than limit current. if the current regulation continues for 20 s, the lp873222-q1 device sets the buckx_ilim_int bit in int_buck register and pulls the nint pin low. the host processor can read buckx_ilim_stat bits in buck_stat register to see if the regulator is still in peak current regulation mode and the interrupt is cleared by writing 1 to buckx_ilim_int bit. the current limit interrupt can be masked by setting buckx_ilim_mask bit in buck_mask register to 1. the buck overload situation is shown in figure 16 . v (vana) vana_uvlo state shut down read otp standby pgood pin en pin vout (buck1) vout (ldo0) buck1 internal powergood ldo0 internal powergood active buck1 internal enable ldo0 internal enable 4ms 2ms
29 lp873222-q1 www.ti.com snvsat3 ? june 2017 product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 16. buck regulator overload situation the ldo regulators include also current limit circuitry. if the load current is increased so that the current limit is triggered, the regulator limits the output current to the threshold level. the voltage may decrease if the load current is higher than the current limit. if the current regulation continues for 20 s, the lp873222-q1 device sets the ldox_ilim_int bit in int_ldo register and pulls the nint pin low. the host processor can read ldox_ilim_stat bits in ldo_stat register to see if the regulator is still in current regulation mode and the interrupt is cleared by writing 1 to ldox_ilim_int bit. the current limit interrupt can be masked by setting ldox_ilim_mask bit in ldo_mask register to 1. the ldo overload situation is shown in figure 17 . time voltage voutx 350mv time current ilimx int_buck(buckx_ilim_int) 20 p s nint buck_stat(buckx_stat) 1 resistive pull-down 1 regulator disabled by digital host clearing the interrupt by writing to flags new startup if enable is valid 1ms 0 1 0 0 int_buck(buckx_sc_int) 0 1 0
30 lp873222-q1 snvsat3 ? june 2017 www.ti.com product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 17. ldo regulator overload situation 7.3.8.2.2 thermal warning the lp873222-q1 device includes a protection feature against overtemperature by setting an interrupt for host processor. the threshold level of the thermal warning is selected with tdie_warn_level bit in config register. if the lp873222-q1 device temperature increases above thermal warning level the device sets tdie_warn_int bit in int_top_1 register and pulls the nint pin low. the status of the thermal warning can be read from tdie_warn_stat bit in top_stat register, and the interrupt is cleared by writing 1 to tdie_warn_int bit. the thermal warning interrupt can be masked by setting tdie_warn_mask bit in top_mask_1 register to 1. 7.3.8.3 protection (regulator disable) if the regulator is disabled because of protection or fault (short-circuit protection, overload protection, thermal shutdown, input overvoltage protection, or uvlo), the output power fets are set to high-impedance mode, and the output pulldown resistor is enabled (if enabled with buckx_rdis_en bit in buckx_ctrl_1 register and ldox_rdis_en bit in ldox_ctrl register). the turnoff time of the output voltage is defined by the output capacitance, load current, and the resistance of the integrated pull-down resistor. the pulldown resistors are active as long as vana voltage is above approximately a 1.2-v level. 7.3.8.3.1 short-circuit and overload protection a short-circuit protection feature allows the lp873222-q1 to protect itself and external components against short circuit at the output or against overload during start-up. for buck and ldo regulators the fault thresholds are about 350 mv (buck) and 300 mv (ldo), and the protection is triggered and the regulator is disabled if the output voltage is below the threshold level 1 ms after the regulator is enabled. time voltage voutx 300 mv time current ilimx int_ldo(ldox_ilim_int) 20 p s nint ldo_stat(ldox_stat) 1 resistive pull-down 1 regulator disabled by digital host clearing the interrupt by writing to flags new startup if enable is valid 1ms 0 1 0 0 int_ldo(ldox_sc_int) 0 1 0
31 lp873222-q1 www.ti.com snvsat3 ? june 2017 product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated in a similar way the overload situation is protected during normal operation. if the output voltage falls below 0.35 v and 0.3 v and remains below the threshold level for 1 ms the regulator is disabled. in buck regulator short-circuit and overload situations the buckx_sc_int bit in int_buck register and the int_buckx bit in int_top_1 register are set to 1, the buckx_stat bit in buck_stat register is set to 0, and the nint signal is pulled low. in ldo regulator short-circuit and overload situations the ldox_sc_int bit in int_ldo register and the int_ldox bit in int_top_1 register are set to 1, the ldox_stat bit in ldo_stat register is set to 0, and the nint signal is pulled low. the host processor clears the interrupt by writing 1 to the buckx_sc_int or to the ldox_sc_int bit. upon clearing the interrupt the regulator makes a new start-up attempt if the regulator is in an enabled state. 7.3.8.3.2 overvoltage protection the lp873222-q1 device monitors the input voltage from the vana pin in standby and active operation modes. if the input voltage rises above vana ovp voltage level, all the regulators are disabled immediately (without switching ramp, no shutdown delays), pulldown resistors discharge the output voltages if they are enabled (buckx_rdis_en = 1 in buckx_ctrl_1 register and ldox_rdis_en = 1 in ldox_ctrl register), gpos are set to logic low level, nint signal is pulled low, ovp_int bit in int_top_1 register is set to 1, and buckx_stat bit in buck_stat register and ldox_stat bit in ldo_stat register are set to 0. the host processor clears the interrupt by writing 1 to the ovp_int bit. if the input voltage is above overvoltage detection level the interrupt is not cleared. the host can read the status of the overvoltage from the ovp_stat bit in top_stat register. regulators cannot be enabled as long as the input voltage is above overvoltage detection level or the overvoltage interrupt is pending. 7.3.8.3.3 thermal shutdown the lp873222-q1 has an overtemperature protection function that operates to protect itself from short-term misuse and overload conditions. when the junction temperature exceeds around 150 c, the regulators are disabled immediately (without switching ramp, no shutdown delays), the tdie_sd_int bit in int_top_1 register is set to 1, the nint signal is pulled low, and the device enters standby. nint is cleared by writing 1 to the tdie_sd_int bit. if the temperature is above thermal shutdown level the interrupt is not cleared. the host can read the status of the thermal shutdown from the tdie_sd_stat bit in top_stat register. regulators cannot be enabled as long as the junction temperature is above thermal shutdown level or the thermal shutdown interrupt is pending. 7.3.8.4 fault (power down) 7.3.8.4.1 undervoltage lockout when the input voltage falls below vana uvlo at the vana pin, the buck and ldo regulators are disabled immediately (without switching ramp, no shutdown delays), and the output capacitor is discharged using the pulldown resistor, and the lp873222-q1 device enters shutdown. when v (vana) voltage is above vana uvlo threshold level, the device powers up to standby state. if the reset interrupt is unmasked by default (otp bit for reset_reg_mask is 0 in top_mask_2 register) the reset_reg_int interrupt bit in int_top_2 register indicates that the device has been in shutdown. the host processor must clear the interrupt by writing 1 to the reset_reg_int bit. if the host processor reads the reset_reg_int interrupt bit after detecting an nint low signal, it knows that the input supply voltage has been below vana uvlo level (or the host has requested reset with sw_reset bit in reset register), and the registers are reset to default values. 7.3.9 operation of the gpo signals the lp873222-q1 device supports up to 2 general purpose output signals, gpo and gpo2. the gpo2 signal is multiplexed with clkin signal. the selection between clkin and gpo2 pin function is set with clkin_pin_sel bit in config register. the gpo pins are configured with the following bits: ? gpox_od bit in gpo_ctrl register defines the type of the output, either push-pull with v (vana) level or open drain the logic level of the gpox pin is set by en_gpox bit in gpo_ctrl register.
32 lp873222-q1 snvsat3 ? june 2017 www.ti.com product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) no glitch filtering, only synchronization. the control of the gpos can be included to start-up and shutdown sequences. the gpo control for a sequence with en pin is selected by gpox_en_pin_ctrl bit in gpo_ctrl register. for start-up and shutdown sequence control see enable and disable sequences . 7.3.10 digital signal filtering the digital signals have a debounce filtering. the signal or supply is sampled with a clock signal and a counter. this results as an accuracy of one clock period for the debounce window. table 5. digital signal filtering event signal/supply rising edge falling edge length length enable/disable for buckx, ldox or gpox en 3 s (1) 3 s (1) vana uvlo vana 3 s (1) (vana voltage rising) immediate (vana voltage falling) vana overvoltage vana 1 s (vana voltage rising) 20 s (vana voltage falling) thermal warning tdie_warn_int 20 s 20 s thermal shutdown tdie_sd_int 20 s 20 s current limit voutx_ilim 20 s 20 s overload fb_b0, fb_b1, vout_ldo0, vout_ldo1 1 ms n/v pgood pin and power-good interrupt pgood / fb_b0, fb_b1, vout_ldo0, vout_ldo1 6 s 6 s
33 lp873222-q1 www.ti.com snvsat3 ? june 2017 product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.4 device functional modes 7.4.1 modes of operation shutdown: the v (vana) voltage is below vana uvlo threshold level. all switch, reference, control, and bias circuitry of the lp873222-q1 device are turned off. read otp: the main supply voltage v (vana) is above vana uvlo level. the regulators are disabled, and the reference and bias circuitry of the lp873222-q1 are enabled. the otp bits are loaded to registers. standby: the main supply voltage v (vana) is above vana uvlo level. the regulators are disabled, and the reference, control and bias circuitry of the lp873222-q1 are enabled. all registers can be read or written by the host processor via the system serial interface. the regulators can be enabled if needed. active: the main supply voltage v (vana) is above vana uvlo level. at least one regulator is enabled. all registers can be read or written by the host processor via the system serial interface. the operating modes and transitions between the modes are shown in figure 18 . figure 18. device operation modes shutdown standby active regulator enabled read otp reg reset i 2 c reset from any state except shutdown regulator(s) disabled v( vana) < vana uvlo v( vana) > vana uvlo
34 lp873222-q1 snvsat3 ? june 2017 www.ti.com product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.5 programming 7.5.1 i 2 c-compatible interface the i 2 c-compatible synchronous serial interface provides access to the programmable functions and registers on the device. this protocol uses a two-wire interface for bidirectional communications between the ic's connected to the bus. the two interface lines are the serial data line (sda), and the serial clock line (scl). every device on the bus is assigned a unique address and acts as either a master or a slave depending on whether it generates or receives the serial clock scl. the scl and sda lines must each have a pullup resistor placed on the line and remain high even when the bus is idle. the lp873222-q1 supports standard mode (100 khz), fast mode (400 khz), fast mode plus (1 mhz), and high-speed mode (3.4 mhz). 7.5.1.1 data validity the data on the sda line must be stable during the high period of the clock signal (scl). in other words, the state of the data line can only be changed when clock signal is low. figure 19. data validity diagram 7.5.1.2 start and stop conditions the lp873222-q1 is controlled via an i 2 c-compatible interface. start and stop conditions classify the beginning and end of the i 2 c session. a start condition is defined as sda transitions from high to low while scl is high. a stop condition is defined as sda transition from low to high while scl is high. the i 2 c master always generates the start and stop conditions. figure 20. start and stop sequences the i 2 c bus is considered busy after a start condition and free after a stop condition. during data transmission the i 2 c master can generate repeated start conditions. a start and a repeated start condition are equivalent function-wise. the data on sda must be stable during the high period of the clock signal (scl). in other words, the state of sda can only be changed when scl is low. figure 21 shows the sda and scl signal timing for the i 2 c-compatible bus. see the figure 1 for timing values. sda start condition stop condition scl s p scl sda data change allowed data valid data change allowed data valid data change allowed
35 lp873222-q1 www.ti.com snvsat3 ? june 2017 product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated programming (continued) figure 21. i 2 c-compatible timing 7.5.1.3 transferring data every byte put on the sda line must be eight bits long, with the most significant bit (msb) being transferred first. each byte of data has to be followed by an acknowledge bit. the acknowledge related clock pulse is generated by the master. the master releases the sda line (high) during the acknowledge clock pulse. the lp873222-q1 pulls down the sda line during the 9th clock pulse, signifying an acknowledge. the lp873222-q1 generates an acknowledge after each byte has been received. there is one exception to the acknowledge after every byte rule. when the master is the receiver, it must indicate to the transmitter an end of data by not-acknowledging ( negative acknowledge ) the last byte clocked out of the slave. this negative acknowledge still includes the acknowledge clock pulse (generated by the master), but the sda line is not pulled down. note if the v (vana) voltage is below vana uvlo threshold level during i 2 c communication the lp873222-q1 device does not drive sda line. the ack signal and data transfer to the master is disabled at that time. after the start condition, the bus master sends a chip address. this address is seven bits long followed by an eighth bit which is a data direction bit (read or write). for the eighth bit, a 0 indicates a write, and a 1 indicates a read. the second byte selects the register to which the data will be written. the third byte contains data to write to the selected register. figure 22. write cycle (w = write; sda = 0). example device address = 0x60 start msb chip addr lsb w ack msb register addr lsb ack msb data lsb ack stop ack from slave ack from slave ack from slave scl sda start id = 60h w ack addr = 40h ack ack address 40h data stop scl sda t low t rcl t hd;dat t high t fcl t su;dat t su;sta t su;sto start repeated start stop t hd;sta start t sp t rda t buf t fda t hd;sta
36 lp873222-q1 snvsat3 ? june 2017 www.ti.com product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated programming (continued) when read function is to be accomplished, a write function must precede the read function as shown above. figure 23. read cycle (r = read; sda = 1). example device address = 0x60 7.5.1.4 i 2 c-compatible chip address note the device address for the lp873222-q1 is 0x61. after the start condition, the i 2 c master sends the 7-bit address followed by an eighth bit, read or write (r/w). r/w = 0 indicates a write and r/w = 1 indicates a read. the second byte following the device address selects the register address to which the data is written. the third byte contains the data for the selected register. here in an example with device address of 1100000bin = 60hex. figure 24. device address example 7.5.1.5 auto-increment feature the auto-increment feature allows writing several consecutive registers within one transmission. every time an 8- bit word is sent to the lp873222-q1, the internal address index counter is incremented by one and the next register is written. table 6 shows writing sequence to two consecutive registers. note that auto increment feature does not work for read. table 6. auto-increment example master action start device addres s = 0x61 write register address data data stop lp87322 2-q1 ack ack ack ack r/w bit 0 0 bit 1 0 bit 2 0 bit 3 0 bit 4 0 bit 5 1 bit 7 1 bit 6 msb lsb i 2 c slave address (chip address) ack from slave start msb chip addr lsb scl ack from slave w msb register addr lsb rs r msb data lsb stop ack from slave nack from master repeated start data from slave sda start id =60h w ack address = 3fh ack rs r ack address 3fh data nack stop msb chip address lsb id = 60h
37 lp873222-q1 www.ti.com snvsat3 ? june 2017 product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6 register maps 7.6.1 register descriptions the lp873222-q1 is controlled by a set of registers through the i 2 c-compatible interface. the device registers, their addresses and their abbreviations are listed in table 7 . a more detailed description is given in the dev_rev to i_load_1 sections. the asterisk (*) marking indicates register bits which are updated from otp memory during read otp state. note this register map describes the default values for a device with orderable code of lp873222rhdrq1. for other device versions the default values read from otp memory can be different. table 7. summary of lp873222-q1 control registers addr register read / write d7 d6 d5 d4 d3 d2 d1 d0 0x00 dev_rev r device_id[1:0] reserved 0x01 otp_rev r otp_id[7:0] 0x02 buck0_ ctrl_1 r/w reserved buck0_fp wm buck0_rdi s_en buck0_ en_pin_ct rl buck0_en 0x03 buck0_ ctrl_2 r/w reserved buck0_ilim[2:0] buck0_slew_rate[2:0] 0x04 buck1_ ctrl_1 r/w reserved buck1_fp wm buck1_rdi s_en buck1_ en_pin_ct rl buck1_en 0x05 buck1_ ctrl_2 r/w reserved buck1_ilim[2:0] buck1_slew_rate[2:0] 0x06 buck0_ vout r/w buck0_vset[7:0] 0x07 buck1_ vout r/w buck1_vset[7:0] 0x08 ldo0_ ctrl r/w reserved ldo0_rdis _en ldo0_ en_pin_ct rl ldo0_en 0x09 ldo1_ ctrl r/w reserved ldo1_rdis _en ldo1_ en_pin_ct rl ldo1_en 0x0a ldo0_ vout r/w reserved ldo0_vset[4:0] 0x0b ldo1_ vout r/w reserved ldo1_vset[4:0] 0x0c buck0_ delay r/w buck0_shutdown_delay[3:0] buck0_startup_delay[3:0] 0x0d buck1_ delay r/w buck1_shutdown_delay[3:0] buck1_startup_delay[3:0] 0x0e ldo0_ delay r/w ldo0_shutdown_delay[3:0] ldo0_startup_delay[3:0] 0x0f ldo1_ delay r/w ldo1_shutdown_delay[3:0] ldo1_startup_delay[3:0] 0x10 gpo_ delay r/w gpo_shutdown_delay[3:0] gpo_startup_delay[3:0] 0x11 gpo2_ delay r/w gpo2_shutdown_delay[3:0] gpo2_startup_delay[3:0] 0x12 gpo_ ctrl r/w reserved gpo2_od gpo2_ en_pin_ct rl gpo2_en reserved gpo_od gpo_ en_pin_ct rl gpo_en 0x13 config r/w reserved startup_ delay_se l shutdow n_delay_ sel clkin_pin _sel clkin_pd en_pd tdie _warn _level en_ spread _spec 0x14 pll_ctrl r/w reserved en_pll reserved ext_clk_freq[4:0]
38 lp873222-q1 snvsat3 ? june 2017 www.ti.com product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated register maps (continued) table 7. summary of lp873222-q1 control registers (continued) addr register read / write d7 d6 d5 d4 d3 d2 d1 d0 0x15 pgood_ct rl_1 r/w pgood_p ol pgood_o d pgood_wi ndow_ld o pgood_wi ndow_bu ck en_pgood _ldo1 en_pgood _ldo0 en_pgood _buck1 en_pgood _buck0 0x16 pgood_ct rl_2 r/w reserved en_pgood _twarn pg_fault _gates_p good pgood_m ode 0x17 pg_fault r reserved pg_fault _ldo1 pg_fault _ldo0 pg_fault _buck1 pg_fault _buck0 0x18 reset r/w reserved sw_ reset 0x19 int_top_1 r/w pgood_ int int_ ldo int_ buck sync_ clk_int tdie_sd_i nt tdie_ warn_int ovp_int i_meas_ int 0x1a int_top_2 r/w reserved reset_ reg_int 0x1b int_buck r/w reserved buck1_ pg_int buck1_ sc_int buck1_ ilim_int reserved buck0_ pg_int buck0_ sc_int buck0_ ilim_int 0x1c int_ldo r/w reserved ldo1_ pg_int ldo1_ sc_int ldo1_ ilim_int reserved ldo0_ pg_int ldo0_ sc_int ldo0_ ilim_int 0x1d top_ stat r pgood_st at reserved sync_clk _stat tdie_sd _stat tdie_ warn_ stat ovp_ stat reserved 0x1e buck_sta t r buck1_ stat buck1_ pg_stat reserved buck1_ ilim_stat buck0_ stat buck0_ pg_stat reserved buck0_ ilim_stat 0x1f ldo_stat r ldo1_ stat ldo1_ pg_stat reserved ldo1_ ilim_stat ldo0_ stat ldo0_ pg_stat reserved ldo0_ ilim_stat 0x20 top_ mask_1 r/w pgood_ int_mask reserved sync_clk _mask reserved tdie_war n_mask reserved i_meas_ mask 0x21 top_ mask_2 r/w reserved reset_ reg_mask 0x22 buck_mas k r/w buck1_pg f_mask buck1_pg r_mask reserved buck1_ ilim_ mask buck0_pg f_mask buck0_pg r_mask reserved buck0_ ilim_ mask 0x23 ldo_mask r/w ldo1_pgf _mask ldo1_pgr _mask reserved ldo1_ ilim_ mask ldo0_pgf _mask ldo0_pgr _mask reserved ldo0_ ilim_ mask 0x24 sel_i_ load r/w reserved load_cur rent_ buck_sel ect 0x25 i_load_2 r reserved buck_loa d_curren t[8] 0x26 i_load_1 r buck_load_current[7:0]
39 lp873222-q1 www.ti.com snvsat3 ? june 2017 product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.1 dev_rev address: 0x00 d7 d6 d5 d4 d3 d2 d1 d0 device_id[1:0] reserved bits field type default description 7:6 device_id[1:0] r 0x1* device specific id code. 5:0 reserved r 00 0010 7.6.1.2 otp_rev address: 0x01 d7 d6 d5 d4 d3 d2 d1 d0 otp_id[7:0] bits field type default description 7:0 otp_id[7:0] r 0x22* identification code of the otp eprom version. 7.6.1.3 buck0_ctrl_1 address: 0x02 d7 d6 d5 d4 d3 d2 d1 d0 reserved buck0_fpwm buck0_rdis_ en buck0_en_pi n_ctrl buck0_en bits field type default description 7:4 reserved r/w 0000 3 buck0_fpwm r/w 1 * buck0 mode selection: 0 - automatic transitions between pfm and pwm modes (auto mode) 1 - forced to pwm operation. 2 buck0_rdis_en r/w 1 enable output discharge resistor (r dis_bx ) when buck0 is disabled: 0 - discharge resistor disabled 1 - discharge resistor enabled. 1 buck0_en_pin _ctrl r/w 1 * enable control for buck0: 0 - only buck0_en bit controls buck0 1 - buck0_en bit and en pin control buck0. 0 buck0_en r/w 1 * enable buck0 regulator: 0 - buck0 regulator is disabled 1 - buck0 regulator is enabled. 7.6.1.4 buck0_ctrl_2 address: 0x03 d7 d6 d5 d4 d3 d2 d1 d0 reserved buck0_ilim[2:0] buck0_slew_rate[2:0]
40 lp873222-q1 snvsat3 ? june 2017 www.ti.com product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated bits field type default description 7:6 reserved r/w 00 5:3 buck0_ilim[2:0] r/w 0x3* sets the switch current limit of buck0. can be programmed at any time during operation: 0x0 - 1.5 a 0x1 - 2.0 a 0x2 - 2.5 a 0x3 - 3.0 a 0x4 - reserved 0x5 - reserved 0x6 - reserved 0x7 - reserved 2:0 buck0_slew_ra te[2:0] r/w 0x4* sets the output voltage slew rate for buck0 regulator (rising and falling edges): 0x0 - reserved 0x1 - reserved 0x2 - 10 mv/ s 0x3 - 7.5 mv/ s 0x4 - 3.8 mv/ s 0x5 - 1.9 mv/ s 0x6 - 0.94 mv/ s 0x7 - 0.47 mv/ s 7.6.1.5 buck1_ctrl_1 address: 0x04 d7 d6 d5 d4 d3 d2 d1 d0 reserved buck1_fpwm buck1_rdis_ en buck1_en_pi n_ctrl buck1_en bits field type default description 7:4 reserved r/w 0000 3 buck1_fpwm r/w 1 * buck1 mode selection: 0 - automatic transitions between pfm and pwm modes (auto mode) 1 - forced to pwm operation. 2 buck1_rdis_en r/w 1 enable output discharge resistor (r dis_bx ) when buck1 is disabled: 0 - discharge resistor disabled 1 - discharge resistor enabled. 1 buck1_en_pin _ctrl r/w 1 * enable control for buck1: 0 - only buck1_en bit controls buck1 1 - buck1_en bit and en pin control buck1. 0 buck1_en r/w 1 * enable buck1 regulator: 0 - buck1 regulator is disabled 1 - buck1 regulator is enabled. 7.6.1.6 buck1_ctrl_2 address: 0x05 d7 d6 d5 d4 d3 d2 d1 d0 reserved buck1_ilim[2:0] buck1_slew_rate[2:0]
41 lp873222-q1 www.ti.com snvsat3 ? june 2017 product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated bits field type default description 7:6 reserved r/w 00 5:3 buck1_ilim[2:0] r/w 0x3* sets the switch current limit of buck1. can be programmed at any time during operation: 0x0 - 1.5 a 0x1 - 2.0 a 0x2 - 2.5 a 0x3 - 3.0 a 0x4 - reserved 0x5 - reserved 0x6 - reserved 0x7 - reserved 2:0 buck1_slew_ra te[2:0] r/w 0x4* sets the output voltage slew rate for buck1 regulator (rising and falling edges): 0x0 - reserved 0x1 - reserved 0x2 - 10 mv/ s 0x3 - 7.5 mv/ s 0x4 - 3.8 mv/ s 0x5 - 1.9 mv/ s 0x6 - 0.94 mv/ s 0x7 - 0.47 mv/ s 7.6.1.7 buck0_vout address: 0x06 d7 d6 d5 d4 d3 d2 d1 d0 buck0_vset[7:0] bits field type default description 7:0 buck0_vset[7:0] r/w 0xff* sets the output voltage of buck0 regulator reserved, do not use 0x00 ... 0x13 0.7 v - 0.73 v, 10 mv steps 0x14 - 0.7v ... 0x17 - 0.73 v 0.73 v - 1.4 v, 5 mv steps 0x18 - 0.735 v ... 0x9d - 1.4 v 1.4 v - 3.36 v, 20 mv steps 0x9e - 1.42 v ... 0xff - 3.36 v 7.6.1.8 buck1_vout address: 0x07 d7 d6 d5 d4 d3 d2 d1 d0 buck1_vset[7:0]
42 lp873222-q1 snvsat3 ? june 2017 www.ti.com product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated bits field type default description 7:0 buck1_vset[7:0] r/w 0xa4* sets the output voltage of buck0 regulator reserved, do not use 0x00 ... 0x13 0.7 v - 0.73 v, 10 mv steps 0x14 - 0.7v ... 0x17 - 0.73 v 0.73 v - 1.4 v, 5 mv steps 0x18 - 0.735 v ... 0x9d - 1.4 v 1.4 v - 3.36 v, 20 mv steps 0x9e - 1.42 v ... 0xff - 3.36 v 7.6.1.9 ldo0_ctrl address: 0x08 d7 d6 d5 d4 d3 d2 d1 d0 reserved ldo0_rdis_e n ldo0_en_pin _ctrl ldo0_en bits field type default description 7:3 reserved r/w 0 0000 2 ldo0_rdis_en r/w 1 enable output discharge resistor (r dis_ldox ) when ldo0 is disabled: 0 - discharge resistor disabled 1 - discharge resistor enabled. 1 ldo0_en_pin _ctrl r/w 1 * enable control for ldo0: 0 - only ldo0_en bit controls ldo0 1 - ldo0_en bit and en pin control ldo0. 0 ldo0_en r/w 1 * enable ldo0 regulator: 0 - ldo0 regulator is disabled 1 - ldo0 regulator is enabled. 7.6.1.10 ldo1_ctrl address: 0x09 d7 d6 d5 d4 d3 d2 d1 d0 reserved ldo1_rdis_e n ldo1_en_pin _ctrl ldo1_en bits field type default description 7:3 reserved r/w 0 0000 2 ldo1_rdis_en r/w 1 enable output discharge resistor (r dis_ldox ) when ldo1 is disabled: 0 - discharge resistor disabled 1 - discharge resistor enabled. 1 ldo1_en_pin _ctrl r/w 0 * enable control for ldo1: 0 - only ldo1_en bit controls ldo1 1 - ldo1_en bit and en pin control ldo1. 0 ldo1_en r/w 0 * enable ldo1 regulator: 0 - ldo1 regulator is disabled 1 - ldo1 regulator is enabled.
43 lp873222-q1 www.ti.com snvsat3 ? june 2017 product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.11 ldo0_vout address: 0x0a d7 d6 d5 d4 d3 d2 d1 d0 reserved ldo0_vset[4:0] bits field type default description 7:5 reserved r/w 000 4:0 ldo0_vset[4:0] r/w 0x19* sets the output voltage of ldo0 regulator 0.8 v - 3.3 v, 100 mv steps 0x00 - 0.8v ... 0x19 - 3.3 v reserved, do not use 0x1a ... 0x1f 7.6.1.12 ldo1_vout address: 0x0b d7 d6 d5 d4 d3 d2 d1 d0 reserved ldo1_vset[4:0] bits field type default description 7:5 reserved r/w 000 4:0 ldo1_vset[4:0] r/w 0x02* sets the output voltage of ldo1 regulator 0.8 v - 3.3 v, 100 mv steps 0x00 - 0.8v ... 0x19 - 3.3 v reserved, do not use 0x1a ... 0x1f 7.6.1.13 buck0_delay address: 0x0c d7 d6 d5 d4 d3 d2 d1 d0 buck0_shutdown_delay[3:0] buck0_startup_delay[3:0] bits field type default description 7:4 buck0_ shutdown_ delay[3:0] r/w 0x0* shutdown delay of buck0 from falling edge of en signal: 0x0 - 0 ms 0x1 - 0.5 ms (1 ms if shutdown_delay_sel=1 in config register) ... 0xf - 7.5 ms (15 ms if shutdown_delay_sel=1 in config register) 3:0 buck0_ startup_ delay[3:0] r/w 0x0* startup delay of buck0 from rising edge of en signal: 0x0 - 0 ms 0x1 - 0.5 ms (1 ms if startup_delay_sel=1 in config register) ... 0xf - 7.5 ms (15 ms if startup_delay_sel=1 in config register) 7.6.1.14 buck1_delay address: 0x0d d7 d6 d5 d4 d3 d2 d1 d0 buck1_shutdown_delay[3:0] buck1_startup_delay[3:0]
44 lp873222-q1 snvsat3 ? june 2017 www.ti.com product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated bits field type default description 7:4 buck1_ shutdown_ delay[3:0] r/w 0x0* shutdown delay of buck1 from falling edge of en signal: 0x0 - 0 ms 0x1 - 0.5 ms (1 ms if shutdown_delay_sel=1 in config register) ... 0xf - 7.5 ms (15 ms if shutdown_delay_sel=1 in config register) 3:0 buck1_ startup_ delay[3:0] r/w 0x0* startup delay of buck1 from rising edge of en signal: 0x0 - 0 ms 0x1 - 0.5 ms (1 ms if startup_delay_sel=1 in config register) ... 0xf - 7.5 ms (15 ms if startup_delay_sel=1 in config register) 7.6.1.15 ldo0_delay address: 0x0e d7 d6 d5 d4 d3 d2 d1 d0 ldo0_shutdown_delay[3:0] ldo0_startup_delay[3:0] bits field type default description 7:4 ldo0_ shutdown_ delay[3:0] r/w 0x0* shutdown delay of ldo0 from falling edge of en signal: 0x0 - 0 ms 0x1 - 0.5 ms (1 ms if shutdown_delay_sel=1 in config register) ... 0xf - 7.5 ms (15 ms if shutdown_delay_sel=1 in config register) 3:0 ldo0_ startup_ delay[3:0] r/w 0x0* startup delay of ldo0 from rising edge of en signal: 0x0 - 0 ms 0x1 - 0.5 ms (1 ms if startup_delay_sel=1 in config register) ... 0xf - 7.5 ms (15 ms if startup_delay_sel=1 in config register) 7.6.1.16 ldo1_delay address: 0x0f d7 d6 d5 d4 d3 d2 d1 d0 ldo1_shutdown_delay[3:0] ldo1_startup_delay[3:0] bits field type default description 7:4 ldo1_ shutdown_ delay[3:0] r/w 0x0* shutdown delay of ldo1 from falling edge of en signal: 0x0 - 0 ms 0x1 - 0.5 ms (1 ms if shutdown_delay_sel=1 in config register) ... 0xf - 7.5 ms (15 ms if shutdown_delay_sel=1 in config register) 3:0 ldo1_ startup_ delay[3:0] r/w 0x0* startup delay of ldo1 from rising edge of en signal: 0x0 - 0 ms 0x1 - 0.5 ms (1 ms if startup_delay_sel=1 in config register) ... 0xf - 7.5 ms (15 ms if startup_delay_sel=1 in config register) 7.6.1.17 gpo_delay address: 0x10 d7 d6 d5 d4 d3 d2 d1 d0 gpo_shutdown_delay[3:0] gpo_startup_delay[3:0] bits field type default description 7:4 gpo_ shutdown_ delay[3:0] r/w 0x0* delay for gpo falling edge from falling edge of en signal: 0x0 - 0 ms 0x1 - 0.5 ms (1 ms if shutdown_delay_sel=1 in config register) ... 0xf - 7.5 ms (15 ms if shutdown_delay_sel=1 in config register)
45 lp873222-q1 www.ti.com snvsat3 ? june 2017 product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated bits field type default description 3:0 gpo_ startup_ delay[3:0] r/w 0x0* delay for gpo rising edge from rising edge of en signal: 0x0 - 0 ms 0x1 - 0.5 ms (1 ms if startup_delay_sel=1 in config register) ... 0xf - 7.5 ms (15 ms if startup_delay_sel=1 in config register) 7.6.1.18 gpo2_delay address: 0x11 d7 d6 d5 d4 d3 d2 d1 d0 gpo2_shutdown_delay[3:0] gpo2_startup_delay[3:0] bits field type default description 7:4 gpo2_ shutdown_ delay[3:0] r/w 0x0* delay for gpo2 falling edge from falling edge of en signal: 0x0 - 0 ms 0x1 - 0.5 ms (1 ms if shutdown_delay_sel=1 in config register) ... 0xf - 7.5 ms (15 ms if shutdown_delay_sel=1 in config register) 3:0 gpo2_ startup_ delay[3:0] r/w 0x0* delay for gpo2 rising edge from rising edge of en signal: 0x0 - 0 ms 0x1 - 0.5 ms (1 ms if startup_delay_sel=1 in config register) ... 0xf - 7.5 ms (15 ms if startup_delay_sel=1 in config register) 7.6.1.19 gpo_ctrl address: 0x12 d7 d6 d5 d4 d3 d2 d1 d0 reserved gpo2_od gpo2_en_pin _ctrl gpo2_en reserved gpo_od gpo_en_pin_ ctrl gpo_en bits field type default description 7 reserved r 0 6 gp02_od r/w 1 * gpo2 signal type when configured as general purpose output (clkin pin): 0 - push-pull output (vana level) 1 - open-drain output 5 gpo2_en_pin_c trl r/w 0 * control for gpo2: 0 - only gpo2_en bit controls gpo2 1 - gpo2_en bit and en pin control gpo2. 4 gpo2_en r/w 0 * output level of gpo2 signal (when configured as general purpose output): 0 - logic low level 1 - logic high level 3 reserved r 0 2 gpo_od r/w 1 * gpo signal type: 0 - push-pull output (vana level) 1 - open-drain output 1 gpo_en_pin_ct rl r/w 0 * control for gpo: 0 - only gpo_en bit controls gpo 1 - gpo_en bit and en pin control gpo. 0 gpo_en r/w 0 * output level of gpo signal: 0 - logic low level 1 - logic high level
46 lp873222-q1 snvsat3 ? june 2017 www.ti.com product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.20 config address: 0x13 d7 d6 d5 d4 d3 d2 d1 d0 reserved startup_de lay_sel shutdown_ delay_sel clkin_pin_se l clkin_pd en2_pd tdie_warn_ level en_spread _spec bits field type default description 7 reserved r/w 0 6 startup_delay _sel r/w 0 * startup delay range from en signals. 0 - 0 ms - 7.5 ms with 0.5 ms steps 1 - 0 ms - 15 ms with 1 ms steps 5 shutdown_del ay_sel r/w 0 * shutdown delay range from en signals. 0 - 0 ms - 7.5 ms with 0.5 ms steps 1 - 0 ms - 15 ms with 1 ms steps 4 clkin_pin_sel r/w 1 * clkin pin function: 0 - gpo2 1 - clkin 3 clkin_pd r/w 1 * selects the pull down resistor on the clkin input pin. (valid also when selected as gpo2) 0 - pull-down resistor is disabled. 1 - pull-down resistor is enabled. 2 en_pd r/w 1 * selects the pull down resistor on the en input pin. 0 - pull-down resistor is disabled. 1 - pull-down resistor is enabled. 1 tdie_warn_ level r/w 1 * thermal warning threshold level. 0 - 125 c 1 - 137 c. 0 en_spread _spec r/w 1 * enable spread spectrum feature: 0 - disabled 1 - enabled 7.6.1.21 pll_ctrl address: 0x14 d7 d6 d5 d4 d3 d2 d1 d0 reserved en_pll reserved ext_clk_freq[4:0] bits field type default description 7 reserved r/w 0 6 en_pll r/w 0 * selection of external clock and pll operation: 0 - forced to internal rc oscillator. pll disabled. 1 - pll is enabled in standby and active modes. automatic external clock use when available, interrupt generated if external clock appears or disappears. 5 reserved r/w 0 this bit must be set to '0'. 4:0 ext_clk_freq[4 :0] r/w 0x01* frequency of the external clock (clkin): 0x00 - 1 mhz 0x01 - 2 mhz 0x02 - 3 mhz ... 0x16 - 23 mhz 0x17 - 24 mhz 0x18...0x1f - reserved see electrical specification for input clock frequency tolerance.
47 lp873222-q1 www.ti.com snvsat3 ? june 2017 product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.22 pgood_ctrl_1 address: 0x15 d7 d6 d5 d4 d3 d2 d1 d0 pgood_pol pgood_od pgood_ window_ldo pgood_ window_buc k en_pgood_l do1 en_pgood_l do0 en_pgood_b uck1 en_pgood_b uck0 bits field type default description 7 pgood_pol r/w 0 * pgood signal polarity. 0 - pgood signal high when monitored outputs are valid 1 - pgood signal low when monitored outputs are valid 6 pgood_od r/w 1 * pgood signal type: 0 - push-pull output (vana level) 1 - open-drain output 5 pgood_ window_ldo r/w 1 * ldo output voltage monitoring method for pgood signal: 0 - only undervoltage monitoring 1 - overvoltage and undervoltage monitoring. 4 pgood_ window_buck r/w 1 * buck output voltage monitoring method for pgood signal: 0 - only undervoltage monitoring 1 - overvoltage and undervoltage monitoring. 3 en_pgood_ldo 1 r/w 0 * pgood signal source control from ldo1 0 - ldo1 is not monitored 1 - ldo1 power-good threshold voltage monitored 2 en_pgood_ldo 0 r/w 0 * pgood signal source control from ldo0 0 - ldo0 is not monitored 1 - ldo0 power-good threshold voltage monitored 1 en_pgood_buc k1 r/w 0 * pgood signal source control from buck1 0 - buck1 is not monitored 1 - buck1 power-good threshold voltage monitored 0 en_pgood_buc k0 r/w 0 * pgood signal source control from buck0 0 - buck0 is not monitored 1 - buck0 power-good threshold voltage monitored 7.6.1.23 pgood_ctrl_2 address: 0x16 d7 d6 d5 d4 d3 d2 d1 d0 reserved en_pgood_t warn pg_fault_g ates_pgood pgood_mod e bits field type default description 7:3 reserved r/w 0 0000 2 en_pgood_twa rn r/w 0 * thermal warning control for pgood signal: 0 - thermal warning not monitored 1 - pgood inactive if thermal warning flag is active. 1 pg_fault_gate s_pgood r/w 0 * type of operation for pgood signal: 0 - indicates live status of monitored voltage outputs. 1 - indicates status of pg_fault register, inactive when at least one pg_fault_x bit is inactive. 0 pgood_mode r/w 1 * operating mode for pgood signal: 0 - gated mode 1 - continuous mode 7.6.1.24 pg_fault address: 0x17 d7 d6 d5 d4 d3 d2 d1 d0 reserved pg_fault_ld o1 pg_fault_ld o0 pg_fault_bu ck1 pg_fault_bu ck0
48 lp873222-q1 snvsat3 ? june 2017 www.ti.com product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated bits field type default description 7:4 reserved r/w 0000 3 pg_fault_ldo1 r/w 0 source for pgood inactive signal: 0 - ldo1 has not set pgood signal inactive. 1 - ldo1 is selected for pgood signal and it has set pgood signal inactive. this bit can be cleared by writing '1' to this bit when ldo1 output is valid. 2 pg_fault_ldo0 r/w 0 source for pgood inactive signal: 0 - ldo0 has not set pgood signal inactive. 1 - ldo0 is selected for pgood signal and it has set pgood signal inactive. this bit can be cleared by writing '1' to this bit when ldo0 output is valid. 1 pg_fault_buck 1 r/w 0 source for pgood inactive signal: 0 - buck1 has not set pgood signal inactive. 1 - buck1 is selected for pgood signal and it has set pgood signal inactive. this bit can be cleared by writing '1' to this bit when buck1 output is valid. 0 pg_fault_buck 0 r/w 0 source for pgood inactive signal: 0 - buck0 has not set pgood signal inactive. 1 - buck0 is selected for pgood signal and it has set pgood signal inactive. this bit can be cleared by writing '1' to this bit when buck0 output is valid. 7.6.1.25 reset address: 0x18 d7 d6 d5 d4 d3 d2 d1 d0 reserved sw_reset bits field type default description 7:1 reserved r/w 000 0000 0 sw_reset r/w 0 software commanded reset. when written to 1, the registers will be reset to default values, otp memory is read, and the i 2 c interface is reset. the bit is automatically cleared. 7.6.1.26 int_top_1 address: 0x19 d7 d6 d5 d4 d3 d2 d1 d0 pgood_int ldo_int buck_int sync_clk_in t tdie_sd_int tdie_warn_i nt ovp_int i_meas_int bits field type default description 7 pgood_int r/w 0 latched status bit indicating that the pgood pin has changed from active to inactive. write 1 to clear interrupt. 6 ldo_int r 0 interrupt indicating that ldo1 and/or ldo0 have a pending interrupt. the reason for the interrupt is indicated in int_ldo register. this bit is cleared automatically when int_ldo register is cleared to 0x00. 5 buck_int r 0 interrupt indicating that buck1 and/or buck0 have a pending interrupt. the reason for the interrupt is indicated in int_buck register. this bit is cleared automatically when int_buck register is cleared to 0x00. 4 sync_clk_int r/w 0 latched status bit indicating that the external clock has appeared or disappeared. write 1 to clear interrupt. 3 tdie_sd_int r/w 0 latched status bit indicating that the die junction temperature has exceeded the thermal shutdown level. the regulators have been disabled if they were enabled and gpo and gpo2 signals are driven low. the regulators cannot be enabled if this bit is active. the actual status of the thermal shutdown is indicated by tdie_sd_stat bit in top_stat register. write 1 to clear interrupt. 2 tdie_warn_int r/w 0 latched status bit indicating that the die junction temperature has exceeded the thermal warning level. the actual status of the thermal warning is indicated by tdie_warn_stat bit in top_stat register. write 1 to clear interrupt.
49 lp873222-q1 www.ti.com snvsat3 ? june 2017 product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated bits field type default description 1 ovp_int r/w 0 latched status bit indicating that the input voltage has exceeded the over-voltage detection level. the regulators have been disabled if they were enabled and gpo and gpo2 signals are driven low. the actual status of the over-voltage is indicated by ovp_stat bit in top_stat register. write 1 to clear interrupt. 0 i_meas_int r/w 0 latched status bit indicating that the load current measurement result is available in i_load_1 and i_load_2 registers. write 1 to clear interrupt. 7.6.1.27 int_top_2 address: 0x1a d7 d6 d5 d4 d3 d2 d1 d0 reserved reset_reg_i nt bits field type default description 7:1 reserved r/w 000 0000 0 reset_reg_int r/w 0 latched status bit indicating that either vana supply voltage has been below undervoltage threshold level or the host has requested a reset using sw_reset bit in reset register. the regulators have been disabled, and registers are reset to default values and the normal startup procedure is done. write 1 to clear interrupt. 7.6.1.28 int_buck address: 0x1b d7 d6 d5 d4 d3 d2 d1 d0 reserved buck1_pg _int buck1_sc _int buck1_ilim _int reserved buck0_pg _int buck0_sc _int buck0_ilim _int bits field type default description 7 reserved r/w 0 6 buck1_pg_int r/w 0 latched status bit indicating that buck1 power-good event has been detected. write 1 to clear. 5 buck1_sc_int r/w 0 latched status bit indicating that the buck1 output voltage has been over 1 ms below short-circuit threshold level. write 1 to clear. 4 buck1_ilim_int r/w 0 latched status bit indicating that the buck1 output current limit has been active. write 1 to clear. 3 reserved r/w 0 2 buck0_pg_int r/w 0 latched status bit indicating that buck0 power-good event has been detected. write 1 to clear. 1 buck0_sc_int r/w 0 latched status bit indicating that the buck0 output voltage has been over 1 ms below short-circuit threshold level. write 1 to clear. 0 buck0_ilim_int r/w 0 latched status bit indicating that the buck0 output current limit has been active. write 1 to clear. 7.6.1.29 int_ldo address: 0x1c d7 d6 d5 d4 d3 d2 d1 d0 reserved ldo1_pg _int ldo1_sc _int ldo1_ilim _int reserved ldo0_pg _int ldo0_sc _int ldo0_ilim _int
50 lp873222-q1 snvsat3 ? june 2017 www.ti.com product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated bits field type default description 7 reserved r/w 0 6 ldo1_pg_int r/w 0 latched status bit indicating that ldo1 power-good event has been detected. write 1 to clear. 5 ldo1_sc_int r/w 0 latched status bit indicating that the ldo1 output voltage has been over 1 ms below short-circuit threshold level. write 1 to clear. 4 ldo1_ilim_int r/w 0 latched status bit indicating that the ldo1 output current limit has been active. write 1 to clear. 3 reserved r/w 0 2 ldo0_pg_int r/w 0 latched status bit indicating that ldo0 power-good event has been detected. write 1 to clear. 1 ldo0_sc_int r/w 0 latched status bit indicating that the ldo0 output voltage has been over 1 ms below short-circuit threshold level. write 1 to clear. 0 ldo0_ilim_int r/w 0 latched status bit indicating that the ldo0 output current limit has been active. write 1 to clear. 7.6.1.30 top_stat address: 0x1d d7 d6 d5 d4 d3 d2 d1 d0 pgood_stat reserved sync_clk _stat tdie_sd _stat tdie_warn _stat ovp_stat reserved bits field type default description 7 pgood_stat r 0 status bit indicating the status of pgood pin: 0 - pgood pin is inactive 1 - pgood pin is active 6:5 reserved r 00 4 sync_clk_stat r 0 status bit indicating the status of external clock (clkin): 0 - external clock frequency is valid 1 - external clock frequency is not valid. 3 tdie_sd_stat r 0 status bit indicating the status of thermal shutdown: 0 - die temperature below thermal shutdown level 1 - die temperature above thermal shutdown level. 2 tdie_warn _stat r 0 status bit indicating the status of thermal warning: 0 - die temperature below thermal warning level 1 - die temperature above thermal warning level. 1 ovp_stat r 0 status bit indicating the status of input overvoltage monitoring: 0 - input voltage below overvoltage threshold level 1 - input voltage above overvoltage threshold level. 0 reserved r 0 7.6.1.31 buck_stat address: 0x1e d7 d6 d5 d4 d3 d2 d1 d0 buck1_stat buck1_pg _stat reserved buck1_ilim _stat buck0_stat buck0_pg _stat reserved buck0_ilim _stat bits field type default description 7 buck1_stat r 0 status bit indicating the enable/disable status of buck1: 0 - buck1 regulator is disabled 1 - buck1 regulator is enabled. 6 buck1_pg_stat r 0 status bit indicating buck1 output voltage validity (raw status) 0 - buck1 output voltage is valid. 1 - buck1 output voltage is invalid.
51 lp873222-q1 www.ti.com snvsat3 ? june 2017 product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated bits field type default description 5 reserved r 0 4 buck1_ilim _stat r 0 status bit indicating buck1 current limit status (raw status) 0 - buck1 output current is below current limit level 1 - buck1 output current limit is active. 3 buck0_stat r 0 status bit indicating the enable/disable status of buck0: 0 - buck0 regulator is disabled 1 - buck0 regulator is enabled. 2 buck0_pg_stat r 0 status bit indicating buck0 output voltage validity (raw status) 0 - buck0 output voltage is valid. 1 - buck0 output voltage is invalid. 1 reserved r 0 0 buck0_ilim _stat r 0 status bit indicating buck0 current limit status (raw status) 0 - buck0 output current is below current limit level 1 - buck0 output current limit is active. 7.6.1.32 ldo_stat address: 0x1f d7 d6 d5 d4 d3 d2 d1 d0 ldo1_stat ldo1_pg _stat reserved ldo1_ilim _stat ldo0_stat ldo0_pg _stat reserved ldo0_ilim _stat bits field type default description 7 ldo1_stat r 0 status bit indicating the enable/disable status of ldo1: 0 - ldo1 regulator is disabled 1 - ldo1 regulator is enabled. 6 ldo1_pg_stat r 0 status bit indicating ldo1 output voltage validity (raw status) 0 - ldo1 output voltage is valid. 1 - ldo1 output voltage is invalid. 5 reserved r 0 4 ldo1_ilim _stat r 0 status bit indicating ldo1 current limit status (raw status) 0 - ldo1 output current is below current limit level 1 - ldo1 output current limit is active. 3 ldo0_stat r 0 status bit indicating the enable/disable status of ldo0: 0 - ldo0 regulator is disabled 1 - ldo0 regulator is enabled. 2 ldo0_pg_stat r 0 status bit indicating ldo0 output voltage validity (raw status) 0 - ldo0 output voltage is valid. 1 - ldo0 output voltage is invalid. 1 reserved r 0 0 ldo0_ilim _stat r 0 status bit indicating ldo0 current limit status (raw status) 0 - ldo0 output current is below current limit level 1 - ldo0 output current limit is active. 7.6.1.33 top_mask_1 address: 0x20 d7 d6 d5 d4 d3 d2 d1 d0 pgood_int_ mask reserved sync_clk _mask reserved tdie_warn _mask reserved i_load_ ready_mask bits field type default description 7 pgood_int _mask r/w 1 * masking for power-good interrupt (pgood_int in int_top_1 register): 0 - interrupt generated 1 - interrupt not generated. this bit does not affect pgood_stat status bit in top_stat register. 6:5 reserved r/w 00
52 lp873222-q1 snvsat3 ? june 2017 www.ti.com product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated bits field type default description 4 sync_clk _mask r/w 1 * masking for external clock detection interrupt (sync_clk_int in int_top_1 register): 0 - interrupt generated 1 - interrupt not generated. this bit does not affect sync_clk_stat status bit in top_stat register. 3 reserved r/w 0 2 tdie_warn _mask r/w 0 * masking for thermal warning interrupt (tdie_warn_int in int_top_1 register): 0 - interrupt generated 1 - interrupt not generated. this bit does not affect tdie_warn_stat status bit in top_stat register. 1 reserved r/w 0 0 i_meas _mask r/w 1 * masking for load current measurement ready interrupt (meas_int in int_top_1 register). 0 - interrupt generated 1 - interrupt not generated. 7.6.1.34 top_mask_2 address: 0x21 d7 d6 d5 d4 d3 d2 d1 d0 reserved reset_reg _mask bits field type default description 7:1 reserved r/w 000 0000 0 reset_reg _mask r/w 1 * masking for register reset interrupt (reset_reg_int in int_top_2 register): 0 - interrupt generated 1 - interrupt not generated. this change of this bit by i 2 c writing has no effect because it will be read from otp memory during reset. 7.6.1.35 buck_mask address: 0x22 d7 d6 d5 d4 d3 d2 d1 d0 buck1_pgf _mask buck1_pgr _mask reserved buck1_ilim _mask buck0_pgf _mask buck0_pgr _mask reserved buck0_ilim _mask bits field type default description 7 buck1_pgf_mas k r/w 1 * masking of power good invalid detection for buck1 power good interrupt (buck1_pg_int in int_buck register): 0 - interrupt generated 1 - interrupt not generated. this bit does not affect buck1_pg_stat status bit in buck_stat register. 6 buck1_pgr_mas k r/w 1 * masking of power good valid detection for buck1 power good interrupt (buck1_pg_int in int_buck register): 0 - interrupt generated 1 - interrupt not generated. this bit does not affect buck1_pg_stat status bit in buck_stat register. 5 reserved r 0 4 buck1_ilim _mask r/w 1 * masking for buck1 current limit detection interrupt (buck1_ilim_int in int_buck register): 0 - interrupt generated 1 - interrupt not generated. this bit does not affect buck1_ilim_stat status bit in buck_stat register. 3 buck0_pgf_mas k r/w 1 * masking of power good invalid detection for buck0 power good interrupt (buck0_pg_int in int_buck register): 0 - interrupt generated 1 - interrupt not generated. this bit does not affect buck0_pg_stat status bit in buck_stat register.
53 lp873222-q1 www.ti.com snvsat3 ? june 2017 product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated bits field type default description 2 buck0_pgr_mas k r/w 1 * masking of power good valid detection for buck0 power good interrupt (buck0_pg_int in int_buck register): 0 - interrupt generated 1 - interrupt not generated. this bit does not affect buck0_pg_stat status bit in buck_stat register. 1 reserved r 0 0 buck0_ilim _mask r/w 1 * masking for buck0 current limit detection interrupt (buck0_ilim_int in int_buck register): 0 - interrupt generated 1 - interrupt not generated. this bit does not affect buck0_ilim_stat status bit in buck_stat register. 7.6.1.36 ldo_mask address: 0x23 d7 d6 d5 d4 d3 d2 d1 d0 ldo1_pgf _mask ldo1_pgr _mask reserved ldo1_ilim _mask ldo0_pgf _mask ldo0_pgr _mask reserved ldo0_ilim _mask bits field type default description 7 ldo1_pgf_mask r/w 1 * masking of power good invalid detection for ldo1 power good interrupt (ldo1_pg_int in int_ldo register): 0 - interrupt generated 1 - interrupt not generated. this bit does not affect ldo1_pg_stat status bit in ldo_stat register. 6 ldo1_pgr_mask r/w 1 * masking of power good valid detection for ldo1 power good interrupt (ldo1_pg_int in int_ldo register): 0 - interrupt generated 1 - interrupt not generated. this bit does not affect ldo1_pg_stat status bit in ldo_stat register. 5 reserved r 0 4 ldo1_ilim _mask r/w 1 * masking for ldo1 current limit detection interrupt (ldo1_ilim_int in int_ldo register): 0 - interrupt generated 1 - interrupt not generated. this bit does not affect ldo1_ilim_stat status bit in ldo_stat register. 3 ldo0_pgf_mask r/w 1 * masking of power good invalid detection for ldo0 power good interrupt (ldo0_pg_int in int_ldo register): 0 - interrupt generated 1 - interrupt not generated. this bit does not affect ldo0_pg_stat status bit in ldo_stat register. 2 ldo0_pgr_mask r/w 1 * masking of power good valid detection for ldo0 power good interrupt (ldo0_pg_int in int_ldo register): 0 - interrupt generated 1 - interrupt not generated. this bit does not affect ldo0_pg_stat status bit in ldo_stat register. 1 reserved r 0 0 ldo0_ilim _mask r/w 1 * masking for ldo0 current limit detection interrupt (ldo0_ilim_int in int_ldo register): 0 - interrupt generated 1 - interrupt not generated. this bit does not affect ldo0_ilim_stat status bit in ldo_stat register. 7.6.1.37 sel_i_load address: 0x24 d7 d6 d5 d4 d3 d2 d1 d0 reserved load_curre nt_buck _select
54 lp873222-q1 snvsat3 ? june 2017 www.ti.com product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated bits field type default description 7:1 reserved r/w 000 0000 0 load_current_ buck_select r/w 0 start the current measurement on the selected regulator: 0 - buck0 1 - buck1 the measurement is started when register is written. 7.6.1.38 i_load_2 address: 0x25 d7 d6 d5 d4 d3 d2 d1 d0 reserved buck_load_ current[8] bits field type default description 7:1 reserved r 000 0000 0 buck_load_ current[8] r 0 this register describes the msb bit of the average load current on selected regulator with a resolution of 20 ma per lsb and maximum 10.22-a current. 7.6.1.39 i_load_1 address: 0x26 d7 d6 d5 d4 d3 d2 d1 d0 buck_load_current[7:0] bits field type default description 7:0 buck_load_ current[7:0] r 0000 0000 this register describes 8 lsb bits of the average load current on selected regulator with a resolution of 20 ma per lsb and maximum 10.22-a current.
55 lp873222-q1 www.ti.com snvsat3 ? june 2017 product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information the lp873222-q1 is a power management unit including two step-down regulators, two linear regulators, and two general-purpose digital output signals. 8.2 typical application figure 25. lp873222-q1 typical application 8.2.1 design requirements 8.2.1.1 inductor selection the inductors l 0 and l 1 are shown in the typical application . the inductance and dcr of the inductor affects the control loop of the buck regulator. ti recommends using inductors similar to those listed in table 8 . pay attention to the saturation current and temperature rise current of the inductor. check that the saturation current is higher than the peak current limit and the temperature rise current is higher than the maximum expected rms output current. minimum effective inductance to ensure good performance is 0.22 h at maximum peak output current over the operating temperature range. dc resistance of the inductor must be less than 0.05 for good efficiency at high-current condition. the inductor ac loss also affects conversion efficiency. higher q factor at switching frequency usually gives better efficiency at light load to middle load. shielded inductors are preferred as they radiate less noise. sw_b0 vin_b0 vin_b1 vana v in fb_b0 v out_b0 load sda scl nint clkin (gpo2) gnds en gpo sw_b1 fb_b1 v out_b1 load pgood vout_ldo1 vout_ldo0 vin_ldo0 vin_ldo1 v out_ldo0 v out_ldo1 copyright ? 2017, texas instruments incorporated c out_buck0 c out_buck1 c out_ldo1 c out_ldo0 c in_ldo1 c in_ldo0 c in_buck0 c in_buck1 c ana l 0 l 1
56 lp873222-q1 snvsat3 ? june 2017 www.ti.com product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated typical application (continued) (1) operating temperature range is up to 125 c including self temperature rise. table 8. recommended inductors manufacture r part number value dimensions l w h (mm) rated dc current i sat maximum (typical) / i temp maximum (typical) (a) dcr typical / maximum (m ? ) toko dfe252012pd-r47m 0.47 h (20%) 2.5 2 1.2 5.2 ( ? ) / 4 ( ? ) (1) ? / 27 tayo yuden mdmk2020tr47mmv 0.47 h (20%) 2 2 1.2 4.2 (4.8) / 2.3 (2.45) 40 / 46 8.2.1.2 buck input capacitor selection the input capacitors c in_buck0 and c in_buck1 are shown in the typical application . a ceramic input bypass capacitor of 10 f is required for each phase of the regulator. place the input capacitor as close as possible to the vin_bx pin and pgnd_bx pin of the device. a larger value or higher voltage rating improves the input voltage filtering. use x7r type of capacitors, not y5v or f. also the dc bias characteristics capacitors must be considered. minimum effective input capacitance to ensure good performance is 1.9 f per buck input at maximum input voltage including tolerances, ambient temperature range and aging. this is assuming that there are at least 22 f of additional capacitance common for all the power input pins on the system power rail. see table 9 . the input filter capacitor supplies current to the high-side fet switch in the first half of each cycle and reduces voltage ripple imposed on the input power source. a ceramic capacitor's low esr provides the best noise filtering of the input voltage spikes due to this rapidly changing current. select an input filter capacitor with sufficient ripple current rating. in addition ferrite can be used in front of the input capacitor to reduce the emi. table 9. recommended buck input capacitor (x7r dielectric) manufacturer part number value case size dimensions l w h (mm) voltage rating murata gcm21br71a106ke22 10 f (10%) 0805 2 1.25 1.25 10 v 8.2.1.3 buck output capacitor selection the output capacitor c out_buck0 and c out_buck1 are shown in typical application . a ceramic local output capacitor of 22 f is required per phase. use ceramic capacitors, x7r type; do not use y5v or f. dc bias voltage characteristics of ceramic capacitors must be considered. the output filter capacitor smooths out current flow from the inductor to the load, helps maintain a steady output voltage during transient load changes and reduces output voltage ripple. these capacitors must be selected with sufficient capacitance and sufficiently low esr and esl to perform these functions. minimum effective output capacitance to ensure good performance is 10 f per phase including the dc voltage roll-off, tolerances, aging, and temperature effects. the output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its r esr . the r esr is frequency dependent (as well as temperature dependent); make sure the value used for selection process is at the switching frequency of the part. see table 10 . pol capacitors can be used to improve load transient performance and to decrease the ripple voltage. a higher output capacitance improves the load step behavior and reduces the output voltage ripple as well as decreases the pfm switching frequency. however, output capacitance higher than 150 f per phase is not necessarily of any benefit. note that the output capacitor may be the limiting factor in the output voltage ramp, see specifications for maximum output capacitance for different slew-rate settings. for large output capacitors, the output voltage might be slower than the programmed ramp rate at voltage transitions, because of the higher energy stored on the output capacitance. also at start-up, the time required to charge the output capacitor to target value might be longer. at shutdown the output voltage is discharged to 0.6 v level using forced-pwm operation. this can increase the input voltage if the load current is small and the output capacitor is large compared to input capacitor. below 0.6 v level the output capacitor is discharged by the internal discharge resistor and with large capacitor more time is required to settle v out down as a consequence of the increased time constant.
57 lp873222-q1 www.ti.com snvsat3 ? june 2017 product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated table 10. recommended buck output capacitors (x7r dielectric) manufacturer part number value case size dimensions l w h (mm) voltage rating murata gcm31cr71a226ke02 22 f (10%) 1206 3.2 1.6 1.6 10 v 8.2.1.4 ldo input capacitor selection the input capacitors c in_ldo0 and c in_ldo1 are shown in the figure 25 . a ceramic input capacitor of 2.2 f, 6.3 v is sufficient for most applications. place the input capacitor as close as possible to the vin_ldox pin and agnd pin of the device. a larger value or higher voltage rating improves the input voltage filtering. use x7r type of capacitors, not y5v or f. dc bias characteristics of capacitors must be considered, minimum effective input capacitance to ensure good performance is 0.6 f per ldo input at maximum input voltage including tolerances, ambient temperature range and aging. see table 11 . table 11. recommended ldo input capacitors (x7r dielectric) manufacturer part number value case size dimensions l w h (mm) voltage rating murata gcm188r70j225ke22 2.2 f (10%) 0603 1.6 0.8 0.8 6.3 v murata gcm21br71c475ka73 4.7 f (10%) 0805 2 1.25 1.25 16 v 8.2.1.5 ldo output capacitor selection the output capacitors c out_ldo0 and c out_ldo1 are shown in the typical application . a ceramic output capacitor of minimum 1.0 f is required. place the output capacitor as close to the vout_ldox pin and agnd pin of the device as possible. use x7r type of capacitors, not y5v or f. dc bias characteristics of capacitors must be considered, minimum effective output capacitance to ensure good performance is 0.4 f per ldo input at maximum input voltage including tolerances, ambient temperature range and aging. see table 12 . the output capacitance must be smaller than the input capacitance in order to ensure the stability of the ldo. with a 1- f output capacitor it is recommended to use at least 2.2- f input capacitor; with a 2.2- f output capacitor at least 4.7- f input capacitance. the vana input is used to supply analog and digital circuits in the device. see table 13 for recommended components from for vana input supply filtering. table 12. recommended ldo output capacitors (x7r dielectric) manufacturer part number value case size dimensions l w h (mm) voltage rating murata gcm188r71c105ka64 1 f (10%) 0603 1.6 0.8 0.8 16 v murata gcm188r70j225ke22 2.2 f (10%) 0603 1.6 0.8 0.8 6.3 v table 13. recommended supply filtering components manufacturer part number value case size dimensions l w h (mm) voltage rating murata gcm155r71c104ka55 100 nf (10%) 0402 1 0.5 0.5 16 v murata gcm188r71c104ka37 100 nf (10%) 0603 1.6 0.8 0.8 16 v 8.2.2 detailed design procedure the performance of the lp873222-q1 device depends greatly on the care taken in designing the printed circuit board (pcb). the use of low-inductance and low serial-resistance ceramic capacitors is strongly recommended, while proper grounding is crucial. attention must be given to decoupling the power supplies. decoupling capacitors must be connected close to the device and between the power and ground pins to support high peak currents being drawn from system power rail during turnon of the switching mosfets. keep input and output traces as short as possible, because trace inductance, resistance, and capacitance can easily become the performance limiting items. the separate buck regulator power pins vin_bx are not connected together internally. connect the vin_bx power connections together outside the package using power plane construction.
58 lp873222-q1 snvsat3 ? june 2017 www.ti.com product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.2.3 application curves unless otherwise specified: v (vin_bx) = v (vin_ldox) = v (vana) = 3.7 v, v out_bx = 1 v, v out_ldox = 1 v, t a = 25 c, l = 0.47 h (toko dfe252012pd-r47m), c out_buck = 22 f, and c pol_buck = 22 f, c out_ldo = 1 f. measurements are done using connections in the figure 25 . v out = 1.8 v figure 26. buck efficiency in pfm/pwm and forced pwm mode v in = 3.3 v figure 27. buck efficiency in forced pwm mode v in = 5 v figure 28. buck efficiency in forced pwm mode v out = 1 v figure 29. buck output voltage vs load current in forced pwm mode figure 30. buck output voltage vs load current in pfm/pwm mode v out = 1 v load = 1 a figure 31. buck output voltage vs input voltage in pwm mode output current (a) output voltage (v) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0.98 0.985 0.99 0.995 1 1.005 1.01 1.015 1.02 d019 vin=3.3v, auto vin=5.0v, auto input voltage (v) output voltage (v) 2.5 3 3.5 4 4.5 5 5.5 0.98 0.984 0.988 0.992 0.996 1 1.004 1.008 1.012 1.016 1.02 d021 output current (a) efficiency (%) 0.001 0.01 0.1 1 2 40 50 60 70 80 90 100 d012 vout=1v vout=1.8v vout=2.5v output current (a) output voltage (v) 0 0.5 1 1.5 2 0.98 0.984 0.988 0.992 0.996 1 1.004 1.008 1.012 1.016 1.02 d016 vin=3.3v, fpwm vin=5.0v, fpwm output current (a) efficiency (%) 0.001 0.01 0.1 1 2 40 50 60 70 80 90 100 d004 vin=5v, auto vin=3.3v, auto vin=5v, fpwm vin=3.3v, fpwm output current (a) efficiency (%) 0.001 0.01 0.1 1 2 40 50 60 70 80 90 100 d008 vout=1v vout=1.8v vout=2.5v
59 lp873222-q1 www.ti.com snvsat3 ? june 2017 product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated load = 1 a (pwm) and 0.1 a (pfm) figure 32. buck output voltage vs temperature i load = 0 a slew-rate = 10 mv/ s figure 33. buck start-up with en1, forced pwm mode r load = 1 slew-rate = 10 mv/ s figure 34. buck startup with en1, forced pwm mode r load = 1 slew-rate = 10 mv/ s figure 35. buck shutdown with en1, forced pwm mode i out = 10 ma figure 36. buck output voltage ripple, pfm mode i out = 200 ma figure 37. buck output voltage ripple, forced pwm mode temperature ( q c) output voltage (v) -40 -20 0 20 40 60 80 100 120 140 0.98 0.985 0.99 0.995 1 1.005 1.01 1.015 1.02 d023 pfm pwm
60 lp873222-q1 snvsat3 ? june 2017 www.ti.com product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 38. buck transient from pfm-to-pwm mode figure 39. buck transient from pwm-to-pfm mode i out = 0.1 a 2 a 0.1 a t r = t f = 400 ns figure 40. buck transient load step response, auto mode i out = 0.1 a 2 a 0.1 a t r = t f = 400 ns figure 41. buck transient load step response, forced pwm mode figure 42. buck v out transition from 0.6 v to 1.4 v with different slew rate settings figure 43. buck v out transition from 1.4 v to 0.6 v with different slew rate settings v out (200mv/div) time (400 s/div) v out (200mv/div) time (400 s/div)
61 lp873222-q1 www.ti.com snvsat3 ? june 2017 product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 44. buck start-up with short on output v out = 1 v figure 45. ldo output voltage vs load current v out = 1 v load = 200 ma figure 46. ldo output voltage vs input voltage v out = 1 v load = 200 ma figure 47. ldo output voltage vs temperature i load = 0 a figure 48. ldo start-up r load = 3.3 figure 49. ldo start-up temperature ( q c) output voltage (v) -40 -20 0 20 40 60 80 100 120 140 0.98 0.985 0.99 0.995 1 1.005 1.01 1.015 1.02 d052 output current (ma) output voltage (v) 0 50 100 150 200 250 300 0.98 0.985 0.99 0.995 1 1.005 1.01 1.015 1.02 d050 vin=3.3v vin=5v input voltage (v) output voltage (v) 2.5 3 3.5 4 4.5 5 5.5 0.98 0.985 0.99 0.995 1 1.005 1.01 1.015 1.02 d051
62 lp873222-q1 snvsat3 ? june 2017 www.ti.com product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated i load = 0 a figure 50. ldo shutdown i out = 0 a 0.3 a 0 a t r = t f = 1 s figure 51. ldo transient load step response figure 52. ldo v out transition from 1.8 v to 1.2 v figure 53. ldo v out transition from 1.2 v to 1.8 v start-up delay is 500 s figure 54. ldo start-up with short on output
63 lp873222-q1 www.ti.com snvsat3 ? june 2017 product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 9 power supply recommendations the device is designed to operate from an input voltage supply range between 2.8 v and 5.5 v. the vana input and vin_bx buck inputs must be connected together and they must use the same input supply. this input supply must be well regulated and able to withstand maximum input current and maintain stable voltage without voltage drop even at load transition condition. the resistance of the input supply rail must be low enough that the input current transient does not cause too high a drop in the lp873222-q1 supply voltage that can cause false uvlo fault triggering. if the input supply is located more than a few inches from the lp873222-q1 additional bulk capacitance may be required in addition to the ceramic bypass capacitors. the vin_ldox ldo input supply voltage range is 2.5 v to 5.5 v and can be higher or lower than vana supply voltage. 10 layout 10.1 layout guidelines the high frequency and large switching currents of the lp873222-q1 make the choice of layout important. good power supply results only occur when care is given to proper design and layout. layout affects noise pickup and generation and can cause a good design to perform with less-than-expected results. with a range of output currents from milliamps to several amps, good power supply layout is much more difficult than most general pcb design. use the following steps as a reference to ensure the device is stable and maintains proper voltage and current regulation across its intended operating voltage and current range. 1. place c in as close as possible to the vin_bx pin and the pgnd_bx pin. route the v in trace wide and thick to avoid ir drops. the trace between the positive node of the input capacitor and the vin_bx pin(s) of lp873222-q1, as well as the trace between the negative node of the input capacitor and power pgnd_bx pin(s), must be kept as short as possible. the input capacitance provides a low-impedance voltage source for the switching converter. the inductance of the connection is the most important parameter of a local decoupling capacitor ? parasitic inductance on these traces must be kept as small as possible for proper device operation. the parasitic inductance can be reduced by using a ground plane as close as possible to top layer by using thin dielectric layer between top layer and ground plane. 2. the output filter, consisting of l and cout, converts the switching signal at sw_bx to the noiseless output voltage. it must be placed as close as possible to the device keeping the switch node small, for best emi behavior. route the traces between the output capacitors of the lp873222-q1 and the input capacitors of the load direct and wide to avoid losses due to the ir drop. 3. input for analog blocks (vana and agnd) must be isolated from noisy signals. connect vana directly to a quiet system voltage node and agnd to a quiet ground point where no ir drop occurs. place the decoupling capacitor as close as possible to the vana pin.
64 lp873222-q1 snvsat3 ? june 2017 www.ti.com product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated layout guidelines (continued) 4. if remote voltage sensing can be used for the load, connect the lp873222-q1 feedback pins fb_bx to the respective sense pins on the load capacitor. the sense lines are susceptible to noise. they must be kept away from noisy signals such as pgnd_bx, vin_bx, and sw_bx, as well as high bandwidth signals such as the i 2 c. avoid both capacitive and inductive coupling by keeping the sense lines short and direct, and close to each other. run the lines in a quiet layer. isolate them from noisy signals by a voltage or ground plane if possible. if series resistors are used for load current measurement, place them after connection of the voltage feedback. 5. pgnd_bx, vin_bx and sw_bx must be routed on thick layers. they must not surround inner signal layers which are not able to withstand interference from noisy pgnd_bx, vin_bx and sw_bx. 6. ldo performance (psrr, noise and transient response) depend on the layout of the pcb. best performance is achieved by placing cin and cout as close to the lp873222-q1 device as practical. the ground connections for cin and cout must be back to the lp873222-q1 agnd with as wide and as short of a copper trace as is practical and with multiple vias if routing is done on other layer. avoid connections using long trace lengths, narrow trace widths, or connection through small via. these add parasitic inductances and resistance that results in inferior performance especially during transient conditions. due to the small package of this converter and the overall small solution size, the thermal performance of the pcb layout is important. many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power dissipation limits of a given component. proper pcb layout, focusing on thermal performance, results in lower die temperatures. wide power traces come with the ability to sink dissipated heat. this can be improved further on multi-layer pcb designs with vias to different planes. this results in reduced junction-to-ambient (r ja ) and junction-to-board (r jb ) thermal resistances, thereby reducing the device junction temperature, t j . ti strongly recommends performance of a careful system-level 2d or full 3d dynamic thermal analysis at the beginning product design process by using a thermal modeling analysis software.
65 lp873222-q1 www.ti.com snvsat3 ? june 2017 product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 10.2 layout example figure 55. lp873222-q1 board layout agnd 1 29 vout_ldo0 2 fb_b0 3 fb_b1 7 vout_ldo1 4 agnd 5 vana 6 en 15 pgnd_b1 16 pgnd_b1 17 scl 21 pgnd_b0 18 sda 19 sgnd 20 pgnd_b0 22 sw_b0 23 sw_b0 24 vin_b0 28 vin_ldo0 25 vin_b0 26 gpo 27 pgood 8 vin_ldo1 9 nint 10 clkin 14 sw_b1 11 vin_b1 12 vin_b1 13 sw_b1 agnd agnd agnd agnd agnd vout0 vout1 vout2 vout3 vin vin vin gnd vin gnd vin c in0 c in1 c in2 c in3 l0 l1 c out0 c out1 c out2 c out3 c ana gnd
66 lp873222-q1 snvsat3 ? june 2017 www.ti.com product folder links: lp873222-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 11 device and documentation support 11.1 device support 11.1.1 third-party products disclaimer ti's publication of information regarding third-party products or services does not constitute an endorsement regarding the suitability of such products or services or a warranty, representation or endorsement of such products or services, either alone or in combination with any ti product or service. 11.2 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 11.3 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 11.4 trademarks e2e is a trademark of texas instruments. all other trademarks are the property of their respective owners. 11.5 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 11.6 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
package option addendum www.ti.com 21-jun-2017 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples lp873222rhdrq1 preview vqfn rhd 28 3000 green (rohs & no sb/br) cu sn level-2-260c-1 year -40 to 125 lp8732 22rhdq1 LP873222RHDTQ1 preview vqfn rhd 28 250 green (rohs & no sb/br) cu sn level-2-260c-1 year -40 to 125 lp8732 22rhdq1 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
package option addendum www.ti.com 21-jun-2017 addendum-page 2
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant LP873222RHDTQ1 vqfn rhd 28 250 180.0 12.4 5.25 5.25 1.1 8.0 12.0 q2 package materials information www.ti.com 21-jun-2017 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) LP873222RHDTQ1 vqfn rhd 28 250 220.0 205.0 50.0 package materials information www.ti.com 21-jun-2017 pack materials-page 2

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