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| this is information on a product in full production. march 2013 docid023065 rev 3 1/31 31 lnbh29 lnb supply and control ic wit h step-up and i2c interface datasheet - production data features ? complete interface between lnb and i2c bus ? built-in dc-dc converter for single 12 v supply operation and high efficiency (typ. 93% @ 0.5 a) ? selectable output current limit by external resistor ? compliant with main sate llite receiver output voltage specifications ? accurate built-in 22 khz tone generator suits widely accepted standards ? extm pin, auxiliary 22 khz modulation input (lnbh29e) extends design flexibility ? 22 khz tone waveform integrity guaranteed also at no load condition ? low-drop post regulator and high efficiency step-up pwm with integrated power n-mos allowing low power losses ? overload and overtemperature internal protection with i2c diagnostic bits ? lnb short-circuit dynamic protection ? +/- 4 kv esd tolerant on output power pins applications ? stb satellite receivers ? tv satellite receivers ? pc card satellite receivers description intended for analog and digital satellite receivers/sat-tv and sat- pc cards, the lnbh29 series is a monolithic voltage regulator and interface ic, assembled in qfn16 (3x3) and qfn16 (4x4) specifically designed to provide the 13 / 18 v power supply and the 22 khz tone signaling to the lnb down-converter in the antenna dish or to the multi-switch box. in this application field, it offers a complete solution with extremely low component count, low power dissipation together with a simple design and i2c standard interfacing. qfn16 (4x4) / (3x3) table 1. device summary order codes packages packaging lnbh29ptr qfn16 (3x3) tape and reel lnbh29eptr qfn16 (3x3) tape and reel LNBH29QTR qfn16 (4x4) tape and reel lnbh29eqtr qfn16 (4x4) tape and reel www.st.com
contents lnbh29 2/31 docid023065 rev 3 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 diseqc? data encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 lnbh29: data encoding by ex ternal diseqc envelope control through the dsqin pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.3 lnbh29e: diseqc data encodi ng by external 22 khz signal connected to the extm pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.4 output current limit selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.5 output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.6 diagnostic and protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.7 surge protection and tvs diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.8 vmon: output voltage diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.9 pdo: overcurrent detection on output pull-down stage . . . . . . . . . . . . . . . 6 2.10 power-on i2c interface reset and undervoltage lockout . . . . . . . . . . . . . . . 6 2.11 png: input voltage minimum detection . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.12 comp: boost capacitors and inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.13 olf: overcurrent and short-circuit protection and diagnostic . . . . . . . . . . . 7 2.14 otf: thermal protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 typical application circ uits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 i2c bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.1 data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.2 start and stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.3 byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.4 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.5 transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 docid023065 rev 3 3/31 lnbh29 contents 7 i2c interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.1 write mode transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.2 read mode transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.3 data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.4 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 block diagram lnbh29 4/31 docid023065 rev 3 1 block diagram figure 1. block diagram 1. dsqin pin available only on the lnbh29. 2. extm pin available only on the lnbh29e. am11889v1 vup sda scl isel addr isense pwm ctrl pgnd dac drop control tone ctrl diagnostics protections i2c digital core lx voltage reference vcc gnd byp current limit selection vout gate ctrl linear regulator r1 r3 r2 extm (2) dsqin (1) docid023065 rev 3 5/31 lnbh29 application information 2 application information this ic has a built-in dc-dc step -up converter that, from a single source from 9 v to 17.5 v, generates the voltages (v up ) that allow the linear post-regulator to work with a minimum dissipated power of 0.5 w typ. @ 500 ma load (the linear post-regulator drop voltage is internally kept at v up - v out = 1 v typ.). the ic is also provided with an undervoltage lockout circuit that disables the whole circuit when the supplied v cc drops below a fixed threshold (4.7 v typically). the step-up converter is provided with a soft-start function which reduces the inrush current during startup. the ss time is internally fixed at 4 ms typ. to switch from 0 to 13 v and 6 ms ty p. to switch from 0 to 18 v. 2.1 diseqc? data encoding the lnbh29 series includes two versions wit h different diseqc control pin solutions: lnbh29 with dsqin pin and lnbh29e with extm pin. the lnbh29 is provided with the dsqin logic in put pin (ttl compatible) to be controlled by an external diseqc data envelope source which activates the internal 22 khz tone generator factory trimmed. this guarantees t he tone output waveform in accordance with the diseqc standards. the lnbh29e is provided with the extm analogic modulation input pin to be connected to an external 22 khz diseqc tone source. the tone output waveform depends on the characteristics of an external signal injected by means of the extm pin. 2.2 lnbh29: data encoding by e xternal diseqc envelope control through the dsqin pin if an external diseqc code envelope source is av ailable, it is possible to use the internal 22 khz generator activated during the tone tr ansmission by connecting the diseqc envelope source to the dsqin pin (see section 5: typical application circuits ). in this way, the internal 22 khz signal is superimposed to the v out dc voltage to generate the lnb output 22 khz tone. during the period in which the dsqin is kept high, the internal control circuit activates the 22 khz tone output. the 22 khz tone on the v out pin is activated with about 6 s delay from the dsqin ttl signal rising edge, and it stops with a delay time in the range of 15 s to 60 s after the 22 khz ttl signal on dsqin has expired (refer to figure 2 ). figure 2. tone enable and disa ble timing (using en velope signal) am10427v1 ~ 6 s 15 s ~ 60 s dsqin tone output application information lnbh29 6/31 docid023065 rev 3 2.3 lnbh29e: diseqc data encodi ng by external 22 khz signal connected to the extm pin in order to improve desi gn flexibility, an analogic modulatio n input pin is available (extm) to generate the 22 khz tone superimposed to the v out dc output voltage. an appropriate dc blocking capacitor must be used to coupl e the 22 khz modulating signal source to the extm pin. the extm pin modulates the v out voltage through the series decoupling capacitor, so that: v out (ac) = vextm(ac) x gextm where v out (ac) and vextm(ac) are, re spectively, the peak-to- peak ac voltage on the v out pin and on the extm pin, while gextm is the voltage gain between the extm voltage and v out signal. 2.4 output current limit selection the linear regulator current limit threshold can be set by an external resistor connected to the isel pin. the resistor value defines the output current limit by the equation: equation 1 where r sel is the resistor connected between isel and gnd expressed in k ? and i max (typ.) is the typical current limit threshold expressed in ma. i max can be set up to 550 ma. 2.5 output voltage selection the linear regulator output voltage level can be easily programmed in order to accomplish application specific requirements, using 3 bits of the internal data register (see section 7.1: write mode transmission and table 7 for exact programmable values). register writing is accessible via the i2c bus. 2.6 diagnostic and pr otection functions the lnbh29 series has 5 diagnostic internal f unctions provided via the i2c bus, by reading 5 bits on the status register (in read mode). all the diagnostic bits are, in normal operation, set to low. two diagnostic bits are dedicated to the overtemperature and overload protection status (otf and olf) while the remaining 3 bits are dedicated to the output voltage level (vmon), to external voltage source presence on the v out pin (pdo) and to the input voltage power not good functi on (png). once the olf (or otf or png) bit has been activated (set to ?1?), it is latched to ?1? until the relevant cause is removed and a new register reading operation is done (see table 8 ). 111 . 1 max rsel 13915 .) typ ( i ? docid023065 rev 3 7/31 lnbh29 application information 2.7 surge protection and tvs diodes the lnbh29 series is directly connected to th e antenna cable in a set-top box. atmospheric phenomenon can cause high voltage discharge s on the antenna cable causing damage to the attached devices. surge pulses occur due to direct or indirect lightning strikes to an external (outdoor) circuit. this leads to currents or electromagnetic fields causing high voltage or current transients. transient vo ltage suppressor (tvs) devices are usually placed, as shown in figure 3 , to protect the stb output circuits where the lnbh29 and other devices are electrically connected to the antenna cable. figure 3. surge protection circuit for this purpose the use of lnbtvsxx surge prot ection diodes specifically designed by st is recommended. the selection of the lnbtvs diode should be made based on the maximum peak power dissipation that the dio de is capable of supporting (see the lnbtvs datasheet for further details). 2.8 vmon: output voltage diagnostic when device output voltage is activated (v out pin), its value is internally monitored and, as long as the output voltage level is below the guaran teed limits, the vmon i2c bit is set to ?1?. see table 12 for more details. 2.9 pdo: overcurrent detectio n on output pull-down stage when an overcurrent occurs on the pull-down output stage due to an external voltage source greater than the lnbh29 nominal v out and for a time longer than i sink_time-out (10 ms typ.), the pdo i2c bit is set to ?1?. this may happen due to an external voltage source presence on the lnb output (v out pin). for current threshold and de-glitch time details, see table 9 . 2.10 power-on i2c interface r eset and undervoltage lockout the i2c interface built into the lnbh29 series is automatically reset at power-on. as long as the v cc stays below the undervoltage lockout (uvlo) threshold (4.7 v typ.), the interface does not respond to any i2c command and all data register bits are initialized to zeroes, therefore keeping the power blocks disabled. once the v cc rises above 4.8 v typ. the i2c interface becomes operative and the data registers can be configured by the main microprocessor. application information lnbh29 8/31 docid023065 rev 3 2.11 png: input volt age minimum detection when input voltage (v cc pin) is lower than lpd (low po wer diagnostic) minimum thresholds, the png i2c bit is se t to ?1?. refer to table 9 for threshold details. 2.12 comp: boost capacitors and inductor the dc-dc converter compensation loop can be optimized in order to properly work with both ceramic and electrolytic capacitors (v up pin). for this purpose, one i2c bit in the data register (comp) can be set to ?1? or ?0? as follows: comp=0 for electrolytic capacitors comp=1 for ceramic capacitors for recommended dc-dc capacitor and inductor values refer to section 5: typical application circuits and to the bom in table 5 . 2.13 olf: overcurrent and short-circuit prot ection and diagnostic in order to reduce the total power dissipation during an overload or a short-circuit condition, the device is provided with a dynamic short- circuit protection. the overcurrent protection circuit works dynamically: as soon as an overlo ad is detected, the outpu t current is provided only for t on time (90 ms typ.) and after that, t he output is set in shutdown for a t off time of typically 900 ms. simultaneously, the diagnostic ol f i2c bit of the status register is set to ?1?. after this time has elapsed, the output is resu med for a time t on . at the end of t on , if the overload is still detected, the prot ection circuit cycles again through t off and t on . at the end of a full t on in which no overload is detected, normal operation is resumed and the olf diagnostic bit is reset to low after a register reading is done. typical t on + t off time is 990 ms, determined by an internal timer. this dynamic operation can greatly reduce the power dissipation in short-circuit conditions, while ensuring excellent power-on startup in most conditions. 2.14 otf: thermal prot ection and diagnostic the lnbh29 series is also protected against overheating: when the junction temperature exceeds 150 c (typ.), the step-up converter and the linear regulator are shut off and the diagnostic otf bit in the status register is set to ?1?. as soon as the overtemperature condition is removed, normal operation is au tomatically re-enabled, while the otf bit is reset to ?0? after a register reading operation. docid023065 rev 3 9/31 lnbh29 pin configuration 3 pin configuration figure 4. pin connections qfn16 (3x3) and (4x4) (top view) am11890v1 gnd nc dsqin/ extm vup nc pgnd nc lx sda isel vcc vout nc vbyp addr scl 1 2 3 4 5 6 16 15 14 13 7 8 9 12 11 10 table 2. pin description pin n symbol name pin function 16 lx n-mos drain integrated n-channel power mosfet drain. 2 p-gnd power ground dc-dc converter power ground. to be connected directly to the epad. 5 addr address setting two i2c bus addresses available by setting the address pin level voltage. see table 11 . 6 scl serial clock clock from i2c bus. 7 sda serial data bi-directional data from/to i2c bus. 8 isel current selection the resistor ?rsel? connected between isel and gnd defines the linear regulator current limit threshold. refer to section 2.4 . 9 gnd analog ground analog circuits ground. to be connected directly to the epad. 10 byp bypass capacitor needed for internal pre-regulator filtering. the byp pin is intended only to connect an external ceramic capacitor. any connection of this pin to external current or voltage sources may cause permanent damage to the device. 12 v cc supply input 8 to 17.5 v ic dc-dc power supply. 13 v out lnb output port output of the integrated very low drop linear regulator. see table 7 for voltage selection and description. 14 v up step-up voltage input of the linear post-regulator. the voltage on this pin is monitored by the internal step-up controller to keep a minimum dropout across the linear pass transistor. pin configuration lnbh29 10/31 docid023065 rev 3 pin n symbol name pin function 3 dsqin (lnbh29) diseqc tone envelope input available for lnbh29 version: this pin accepts diseqc envelope codes (ttl compatible) from the main diseqc microcontroller. the lnbh29 uses this code to enable the internally generated 22 khz carrier superimposed to the v out pin dc voltage. see figure 5 . 3 extm (lnbh29e) external 22 khz tone input available for lnbh29e version: the ?external tone modulation? input acts on the integrated linear regu lator loop to superimpose an external 22 khz signal to the v out pin dc voltage. needs dc decoupling to the ac source. see figure 6 . epad epad exposed pad to be connected with power grounds and to the ground layer through vias to dissipate the heat. 1, 4, 11, 15 n.c. not internally connected not internally connected pins. these pins can be connected to gnd to improve thermal performance. table 2. pin description (continued) docid023065 rev 3 11/31 lnbh29 maximum ratings 4 maximum ratings note: absolute maximum ratings ar e those values beyond which damage to the device may occur. these are stress ratings only and functional oper ation of the device at these conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. all voltage values are with respect to the network ground terminal. table 3. absolute maximum ratings symbol parameter value unit v cc dc power supply input voltage pins -0.3 to 20 v v up dc input voltage -0.3 to 40 v i out output current internally limited ma v out dc output pin voltage -0.3 to 40 v v i logic input pins voltage (sda, scl, dsqin, addr pins) -0.3 to 7 v v extm extm pin voltage -0.3 to 2 v lx lx input voltage -0.3 to 30 v v byp internal reference pin voltage -0.3 to 4.6 v isel current selection pin voltage -0.3 to 3.5 v t stg storage temperature range -50 to 150 c t j operating junction temper ature range -25 to 125 c esd esd rating with human body model (hbm) all pins, unless power output pins 2kv esd rating with human body model (hbm) for power output pins 4 table 4. thermal data symbol parameter qfn (3x3) qfn (4x4) unit r thjc thermal resistance junction-case 2 2 c/w r thja thermal resistance junction-ambient with device soldered on 2s2p 4-layer pcb provided with thermal vias below exposed pad 55 40 c/w typical application circuits lnbh29 12/31 docid023065 rev 3 5 typical application circuits figure 5. lnbh29: diseqc tone envelope pin control figure 6. lnbh29e: external 22 khz diseqc pin control am11891v1 d2 c3 vin 12v to lnb lx vup vout c4 lnbh29 d1 c5 isel r1 (rsel) addr c2 c1 vcc dsqin diseqc envelope ttl scl sda 14 16 12 7 6 5 8 byp c6 10 3 13 p-gnd gnd 2 9 d3 l1 am11892v1 d2 l1 c3 vin 12v to lnb lx vup vout c4 lnbh29e d1 c5 isel r1 (rsel) addr c2 c1 vcc extm scl sda 14 16 12 7 6 5 8 byp c6 10 3 13 p-gnd gnd 2 9 d3 diseqc 22khz c7 docid023065 rev 3 13/31 lnbh29 typical appl ication circuits table 5. typical application circuit bill of material component notes r1 (rsel) smd resistor. refer to i max current limit selectio n resistor values ( ta ble 9 ) . c1 > 25 v electrolytic capacitor, 100 f or higher is suitable. or > 25 v ceramic capacitor, 10 f or higher is suitable. c2 with comp=0, > 25 v electrolytic capacitor, 100 f or higher is suitable. or with comp=1, > 35 v ceramic capacitor, 22 f (or 2 x 10 f) or higher is suitable. c3 from 470 nf to 2.2 f ceramic capacitor. higher values allow lower dc-dc noise. c5 from 100 nf to 220 nf ceramic capacitor. higher values allow lower dc-dc noise. c4, c6 220 nf ceramic capacitors. c7 100 nf or higher is suitable. d1 stps130a or similar schottky diode. d3 bat54, bat43, 1n5818, or any low power schottky diode with i f (av) > 0.2 a, vrrm > 25 v, v f < 0.5 v. to be placed as close as possible to v out pin. d2 1n4001-07, s1a-s1m, or any si milar general purpose rectifier. l1 with comp=0, use 10 h inductor with i sat >i peak where i peak is the boost converter peak current. or with comp=1 and c2 = 22 f, use 6.8 h inductor with i sat >i peak where i peak is the boost converter peak current. i2c bus interface lnbh29 14/31 docid023065 rev 3 6 i2c bus interface data transmission from the main microprocessor to the lnbh29 and vice versa takes place through the 2-wire i2c bus interface, consisting of the 2 lines sda and scl (pull-up resistors to positive supply voltage mu st be externally connected). 6.1 data validity as shown in figure 7 , the data on the sda line must be stable during the high semi-period of the clock. the high and low state of th e data line can only change when the clock signal on the scl line is low. 6.2 start and stop condition as shown in figure 8 , a start condition is a high to lo w transition of the sda line while scl is high. the stop conditio n is a low to high transition of the sda line while scl is high. a stop condition must be sent before each start condition. 6.3 byte format every byte transferred to the sda line must cont ain 8 bits. each byte must be followed by an acknowledge bit. the msb is transferred first. 6.4 acknowledge the master (microprocessor) puts a resist ive high level on the sda line during the acknowledge clock pulse (see figure 9 ). the peripheral (lnbh29) that acknowledges must pull down (low) the sda line during the acknowl edge clock pulse, so that the sda line is stable low during this clock pulse. the peripheral which has been addressed must generate an acknowledge after the reception of each byte, otherwise the sda line remains at the high level during the ninth clock pulse time. in this case the master transmitter can generate the stop information in order to abort the transfer. the lnbh29 does not generate an acknowledge if the v cc supply is below the undervoltage lockout threshold (4.7 v typ.). 6.5 transmission without acknowledge if the detection of an acknowledge from the lnbh29 is not required, the microprocessor can use a simpler transmission: it simply waits one clock cycle without checking the slave acknowledging, and sends the new data. this approach is of course less protected from misworking and decreases the noise immunity. docid023065 rev 3 15/31 lnbh29 i2c bus interface figure 7. data validity on the i2c bus figure 8. timing diagram of i2c bus figure 9. acknowledge on the i2c bus i2c interface protocol lnbh29 16/31 docid023065 rev 3 7 i2c interface protocol 7.1 write mode transmission the lnbh29 series interface protocol comprises: ? a start condition (s) ? a chip address byte with the lsb bit r/w = 0 ? a register address (internal address of the first register to be accessed) ? a sequence of data (byte to write in the addressed internal register + acknowledge) ? a stop condition (p). the transfer lasts until a stop bit is encountered ? the lnbh29, as slave, ackno wledges every byte transfer. figure 10. example of writing procedure starting with first data address 0x2 ack = acknowledge s = start p = stop r/w = 1/0, read/write bit x = 0/1, set the values to se lect the chip address (see table 11 for pin selection). note: one only data register address 0x1 is available for the writing procedure. 7.2 read mode transmission in read mode the bytes sequ ence must be as follows: ? a start condition (s) ? a chip address byte with the lsb bit r/w=0 ? the register address byte of the inte rnal first register to be accessed ? a stop condition (p) ? a new master transmission with the chip address byte and the lsb bit r/w=1 ? after the acknowledge the lnbh29 starts to send the addressed register content. as long as the master keeps the acknowledge low, the lnbh29 transmits the next address register byte content. ? the transmission is terminated when the ma ster sets the acknowledge high with a following stop bit. am11893v1 s 000100x r/w = 0 ack 00000001 ack msb lsb chip address msb lsb register address comp vsel2 vsel1 vsel0 ack p msb lsb data add=0x1 n/a n/a n/a n/a docid023065 rev 3 17/31 lnbh29 i2c interface protocol figure 11. example of reading procedure starting with first status address 0x0 (a) ack = acknowledge s = start p = stop r/w = 1/0, read/write bit x = 0/1, set the values to select the chip addr ess (see chip address pin selection table) and to select the register address (0x0 for status register and 0x1 for data register). 7.3 data register the data register can be addressed both in write and read mode. in read mode it returns the last writing byte status receiv ed in the previous write transmission. table 6 provides the data register values with relevant function description of each bit. a. the reading procedure can start from any register addres s (status or data) by simply setting the x values in the register address byte (after the first chip address in figure 11 ). it can be also stopped from the master by sending a stop condition a fter any acknowledge bit. am11894v1 s 000100x r/w = 0 ack 0000000x ack p s 000100x r/w = 1 ack msb lsb chip address msb lsb register address msb lsb chip address n/a n/a n/a pdo png vmon otf olf ack msb lsb data add=0x1 msb lsb status add=0x0 n/a n/a n/a n/a comp vsel2 vsel1 vsel0 ack p i2c interface protocol lnbh29 18/31 docid023065 rev 3 n/a = reserved bit. all bits reset to ?0? at power-on. table 6. data (read/write register. register address = 0x1) bit name value description bit 0 (lsb) vsel0 0/1 output voltage selection bits. (refer to table 7 ) bit 1 vsel1 0/1 bit 2 vsel2 0/1 bit 3 comp 1 dc-dc converter compensation: set to ?1? for using very low e.s.r. capacitors or ceramic caps (v up pin). 0 dc-dc converter compensation: set to ?0? for using standard e.s.r. capacitors (v up pin). bit 4 n/a 0 reserved. keep to ?0? bit 5 n/a 0 reserved. keep to ?0? bit 6 n/a 0 reserved. keep to ?0? bit 7 (msb) n/a 0 reserved. keep to ?0? table 7. output voltage selection table (data register, write mode) vsel2 vsel1 vsel0 v out min. v out pin voltage v out max. function 000 0.000 v out disabled. lnbh29/lnbh29e set in standby mode 0 0 1 12.545 13.000 13.455 0 1 0 12.867 13.333 13.800 0 1 1 13.188 13.667 14.000 1 0 1 17.515 18.150 18.785 1 1 0 17.836 18.483 19.130 1 1 1 18.158 18.817 19.475 docid023065 rev 3 19/31 lnbh29 i2c interface protocol 7.4 status register the status register can be addressed only in read mode and provides the diagnostic functions described in table 8 . n/a = reserved bit. all bits reset to ?0? at power-on. table 8. status (read register. register address = 0x0) bit name value description bit 0 (lsb) olf 1 output short-circuit or v out pin overload protection has been triggered (i out > i max ). 0 no overload protection has been triggered to v out pin (i out < i max ). bit 1 otf 1 junction overtemperature is detected, t j > 150 c. 0 junction overtemperature not detected, t j < 135 c. t j is below thermal protection threshold. bit 2 vmon 1 output voltage (v out pin) lower than vmon specification thresholds. refer to ta ble 1 2 . 0 output voltage (v out pin) is within the vmon specifications. bit 3 png 1 input voltage (v cc pin) lower than lpd minimum thresholds. refer to vlp in table 9 . 0 input voltage (v cc pin) higher than lpd thresholds. refer to vlp in table 9 . bit 4 pdo 1 overcurrent detected on ou tput pull-down stage for a time longer than de-glitch period. this may happen due to an external voltage source present on the lnb output (v out pin). 0 no overcurrent detected on output pull-down stage. bit 5 n/a - reserved bit 6 n/a - reserved bit 7 (msb) n/a reserved electrical characteristics lnbh29 20/31 docid023065 rev 3 8 electrical characteristics refer to the section 5: typical application circuits , t j from 0 to 85 c, data register bits set to ?0? except vsel0 = 1, rsel = 16.2 k ? , dsqin = low, v in = 12 v, i out = 50 ma, unless otherwise stated. typical values are referred to t j = 25 c. v out = v out pin voltage. see software description section for i2 c access to the system register ( section 6 and section 7 ). table 9. electric al characteristic symbol parameter test conditions min. typ. max. unit v in supply voltage (1) 81217.5v i in supply current i out = 0 ma 6 ma 22 khz tone enabled (dsqin=high), i out = 0 ma 10 vsel0=vsel1=vsel2=0 1 v out output voltage total accuracy valid at any v out selected level -3.5 +3.5 % v out line regulation v in = 8 to 17.5 v 40 mv v out load regulation i out from 50 to 500 ma 100 i max output current limiting thresholds rsel = 16.2 k ? rsel = 22 k ? 500 750 ma 350 550 i sc output short-circuit current rsel= 16.2 k ? 400 ma ss soft-start time v out from 0 to 13 v 4 ms ss soft-start time v out from 0 to 18 v 6 ms t13-18 soft transition rise time v out from 13 v to 18 v 1.5 ms t18-13 soft transition fall time v out from 18 v to 13 v 1.5 ms t off dynamic overload protection off-time output shorted 900 ms t on dynamic overload protection on-time output shorted t off / 10 a tone tone amplitude dsqin = ?1? (using internal tone generator) i out from 0 to 500 ma c bus from 0 to 750 nf 0.55 0.675 0.8 v pp f tone tone frequency dsqin = ?1? (using internal tone generator) 20 22 24 khz d tone tone duty cycle 43 50 57 % tr, tf tone rise or fall time (2) 5 8 15 s g extm external modulation gain (3) ? vout / ? vextm , freq. from 10 khz to 30 khz 10 v extm external modulation input voltage (3) extm ac coupling (4) 400 mv pp z extm external modulation impedance (3) 230 w docid023065 rev 3 21/31 lnbh29 electrical characteristics t j from 0 to 85 c, v i = 12 v. symbol parameter test conditions min. typ. max. unit eff dc/dc dc-dc converter efficiency i out = 500 ma 93 % f sw dc-dc converter switching frequency 440 khz uvlo undervoltage lockout thresholds uvlo threshold rising 4.8 v uvlo threshold falling 4.7 v lp low power diagnostic (lpd) thresholds v lp threshold rising 7.2 v v lp threshold falling 6.7 v il dsqin, pin logic low 0.8 v v ih dsqin, pin logic high 2 v i ih dsqin, pin input current v ih = 5 v 15 a i obk output backward current all vselx=0 v, v obk =30 v -3 - 6ma i sink output low-side sink current v out forced at v out_nom + 0.1 v 50 ma i sink_time- out low-side sink current timeout v out forced at v out_nom + 0.1 v pdo i2c bit is set to ?1? after this time has elapsed 10 ms i rev max. reverse current v out forced at v out_nom + 0.1 v, after pdo bit is set to ?1? (i sink_time-out has elapsed) 2ma t shdn thermal shutdown threshold 150 c ? t shdn thermal shutdown hysteresis 15 c 1. in applications where (v cc - v out ) > 1.3 v, the increased power dissipation inside the integrated ldo must be taken into account in the application thermal management design. 2. guaranteed by design. 3. only for type lnbh29e. 4. external signal maximum voltage fo r which the extm function is guaranteed. table 9. electrical characteristic (continued) table 10. i2c electrical characteristics symbol parameter test conditions min. typ. max. unit v il low level input voltage sda, scl 0.8 v v ih high level input voltage sda, scl 2 v i in input current sda, scl, v in = 0.4 to 4.5 v -10 10 a v ol low level output voltage sda (open drain), i ol = 6 ma 0.6 v f max maximum clock frequency scl 400 khz electrical characteristics lnbh29 22/31 docid023065 rev 3 t j from 0 to 85 c, v i = 12 v. refer to section 5: typical application circuits , t j from 0 to 85 c, data register bits set to ?0?, rsel = 16 k ? , dsqin = low, v in = 12 v, i out = 50 ma, unless otherwise stated. typical values are referred to t j = 25 c. v out = v out pin voltage. see software description section for i2c access to the status register. note: if the output voltage is lower than the min. value th e vmon i2c bit is set to 1. if vmon = 0 then v out > 80% of v out typical. if vmon = 1 then v out < 95% of v out typical. table 11. address pin characteristics symbol parameter test condition min. typ. max. unit v addr-1 ?0001000(r/w)? address pin voltage range r/w bit determines the transmission mode: read (r/w=1) write (r/w=0) 00.8v v addr-2 ?0001001(r/w)? address pin voltage range r/w bit determines the transmission mode: read (r/w=1) write (r/w=0) 25v table 12. output voltage diagnostic (vmon bit, status register) characteristics symbol parameter test condition min. typ. max. unit v th-l diagnostic low threshold at v out = 13.0 v vsel0=1, vsel1=vsel2=0 80 90 95 % v th-l diagnostic low threshold at v out = 18.15 v vsel1=0, vsel0=vsel2=1 80 90 95 % docid023065 rev 3 23/31 lnbh29 package mechanical data 9 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions a nd product status are available at: www.st.com . ecopack is an st trademark. table 13. qfn16 (4 x 4 mm.) mechanical data dim. mm min. typ. max. a 0.80 0.90 1.00 a1 0.00 0.02 0.05 a3 0.20 b 0.25 0.30 0.35 d 3.90 4.00 4.10 d2 2.50 2.80 e 3.90 4.00 4.10 e2 2.50 2.80 e0.65 l 0.30 0.40 0.50 package mechanical data lnbh29 24/31 docid023065 rev 3 figure 12. qfn16 (4 x 4 mm) drawing 7571203_a docid023065 rev 3 25/31 lnbh29 package mechanical data table 14. qfn16 (3 x 3 mm) mechanical data dim. mm. min. typ. max. a 0.80 0.90 1.00 a1 0.00 0.05 a3 0.20 b 0.18 0.30 d 2.90 3.00 3.10 d2 1.50 1.80 e 2.90 3.00 3.10 e2 1.50 1.80 e0.50 l 0.30 0.50 package mechanical data lnbh29 26/31 docid023065 rev 3 figure 13. qfn16 (3 x 3 mm) drawing 7509604_c docid023065 rev 3 27/31 lnbh29 package mechanical data dim. mm. inch. min. typ. max. min. typ. max. a 330 12. 99 2 c 12.8 13.2 0.504 0.51 9 d 20.2 0.7 9 5 n 99 101 3.8 9 83. 9 76 t 14.4 0.567 ao 4.35 0.171 bo 4.35 0.171 ko 1.1 0.043 po 4 0.157 p 8 0.315 tape & reel qfnxx/dfnxx (4x4) mechanical data package mechanical data lnbh29 28/31 docid023065 rev 3 dim. mm. inch. min. typ. max. min. typ. max. a 330 12. 99 2 c 12.8 13.2 0.504 0.51 9 d 20.2 0.7 9 5 n 60 2.362 t 18.4 0.724 ao 3.3 0.130 bo 3.3 0.130 ko 1.1 0.043 po 4 0.157 p 8 0.315 tape and reel qfnxx/dfnxx (3x3 mm) mechanical data docid023065 rev 3 29/31 lnbh29 package mechanical data figure 14. qfn16 (4 x 4) footprint recommended data (mm) figure 15. qfn16 (3 x 3) footprint recommended data (mm) 7571203_a 75029604_c revision history lnbh29 30/31 docid023065 rev 3 10 revision history table 15. document revision history date revision changes 03-aug-2012 1 initial release. 01-oct-2012 2 modified: l1 notes table 5 on page 13 . 15-mar-2013 3 modified: maximum clock frequency max. value table 10 on page 21 . docid023065 rev 3 31/31 lnbh29 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not authorized for use in weapons. nor are st products designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com |
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