View APW8715_9000031.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

copyright ? anpec electronics corp. rev. a.5 - apr., 2016 www.anpec.com.tw 1 anpec reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. high input voltage 6a pwm converter with adj. soft start APW8715 features general description adjustable output voltage from +0.8v to +12v - 0.8v reference voltage - + 1% accuracy over temperature operates from an input battery voltage range of +2.7v to +28v power-on-reset monitoring on vcc pin excellent line and load transient responses pfm mode for increased light load efficiency programmable pwm frequency from 100khz to 1000khz integrated 30m w at vcc=5v n-channel mosfet for high side integrated 12m w at vcc=5v n-channel mosfet for low side integrated bootstrap forward p-ch mosfet external adjustable soft-start and soft-stop selectable forced pwm or automatic pfm/pwm mode power good monitoring 70% under-voltage protection 125% over-voltage protection current-limit protection - using sense low-side mosfet s rds(on) over-temperature protection tqfn-23 4mmx4mm package lead free and green device available (rohs compliant) applications notebook mother board table pc hand-held portable aio pc set-top boxes lcd tv the APW8715 is a 6a, synchronous, step-down converter with integrated 30m w n-channel high-side mosfet and 12m w low-side mosfet. the APW8715 steps down high voltage to generate low-voltage chipset or ram sup- plies in notebook computers. the APW8715 provides excellent transient response and accurate dc voltage output in either pfm or pwm mode. in pulse frequency mode (pfm), the APW8715 provides very high efficiency over light to heavy loads with loading- modulated switching frequencies. in pwm mode, the con- verter works nearly at constant frequency for low-noise requirements. the APW8715 is equipped with accurate current-limit, out- put under-voltage, and output over-voltage protections, perfect for various applications. a power-on-reset func- tion monitors the voltage on vcc to prevent wrong operation during power-on. the APW8715 has external adjustable soft-start and built-in an integrated output dis- charge method for soft stop. a soft-start ramps up the output voltage with programmable timing to reduce the start-up current. a soft-stop function actively discharges the output capacitors. the APW8715 is available in tqfn4x4-23 (power pak).
copyright ? anpec electronics corp. rev. a.5 - apr., 2016 www.anpec.com.tw 2 APW8715 simplified application circuit ordering and marking information note: anpec lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with rohs. anpec lead-free products meet or exceed the lead-free requirements of ipc/jedec j - std-020d for msl classification at lead-free peak reflow temperature. anpec defines green to mean lead-free (rohs compliant) and halogen free (br or cl does not exceed 900ppm by weight in homogeneous material and total of br and cl does not exceed 1500ppm by weight). pin configuration = exposed and thermal pad tqfn 4x4 -23 (top view) lx fb 5 ton 6 pok 1 en 2 pfm 3 agnd 4 n c 7 v i n 8 v i n 9 l x 1 0 l x 1 1 17 lx 16 lx 15 pgnd 14 pgnd 13 pgnd 12 pgnd 2 3 s s 2 2 v i n 2 1 v c c 2 0 b o o t 1 9 p g n d 1 8 l x vin v out l out en v in c ss ss c out pfm pok vcc lx vin r pok h / l APW8715 APW8715 handling code temperature range package code package code qb: tqfn4x4-23 operating ambient temperature range i : -40 to 85 c handling code tr : tape & reel lead free code l : lead free device assembly material APW8715 qb : APW8715 xxxxx xxxxx - date code g : halogen and lead free device
copyright ? anpec electronics corp. rev. a.5 - apr., 2016 www.anpec.com.tw 3 APW8715 absolute maximum ratings (note 1) symbol parameter rating unit v vcc vcc supply voltage (vcc to agnd) -0.3 ~ 7 v v in vin supply voltage (vin to agnd) -0.3 ~ 30 v v ton ton supply voltage (ton to agnd) -0.3 ~ 30 v v boot-gnd boot supply voltage (boot to agnd) -0.3 ~ 37 v v boot boot supply voltage (boot to phase) -0.3 ~ 7 v v gnd agnd to pgnd -0.3 ~ +0.3 v all other pins (pok, en, fb, ss and pfm to agnd) -0.3 ~ 7 v v lx lx voltage (lx to pgnd) <50ns pulse width >50ns pulse width -7 ~ 32 -0.3 ~ 30 v t j junction temperature 150 o c t stg storage temperature -65 ~ 150 o c t sdr maximum lead soldering temperature(10 seconds) 260 o c note1: stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom- mended operating conditions" is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal characteristics symbol parameter typical value unit q ja junction-to-ambient resistance in free air (note 2) 50 o c/w note 2: q ja is measured with the component mounted on a high effective thermal conductivity test board in free air. note 3: refer to the application circuit for further information. symbol parameter range unit v vcc vcc supply voltage 4.5 ~ 5.5 v v in converter input voltage 2.7 ~ 28 v v out converter output voltage 0.8 ~ 13.2 v i out converter output current 0 ~ 6 a t a ambient temperature -40 ~ 85 o c t j junction temperature -40 ~ 125 o c recommended operating conditions (note 3)
copyright ? anpec electronics corp. rev. a.5 - apr., 2016 www.anpec.com.tw 4 APW8715 electrical characteristics unless otherwise specified, these specifications apply over v in =12v,v en =5v and t a = -40 to 85 o c. typical values are at t a =25 o c. APW8715 symbol parameter test condition min. typ. max. unit vout and vfb voltage v out output voltage adjustable output range 0.8 13.2 v v ref reference voltage 0.8 v regulation accuracy t a = -40 o c ~ 85 o c -1.0 - +1.0 % i fb fb input bias current fb=0.75v 0.02 - m a t stop output discharge time en go low to output remain below 0.1v - 5*tss - - supply current i vcc_nor mal vcc quiescent supply current en=5v, fb=0.835v, vcc=5v - 0.7 1 m a i vcc_shd n vcc shutdown current en=gnd, vcc=5v - - 25 m a on-time timer and internal soft start t on nominal on time v in =12v, v out =1v, r ton =100k w 170 220 270 ns f sw frequency adjustable range 100 1000 khz t off(min) minimum off time v fb =0.75v, v phase =-0.1v - 250 - ns i ss internal soft start current vss=0v css=0.001uf to 0.1uf 8 10 12 m a gate driver high side mosfet on resistance vin=12v vcc=5v - 30 45 m w low side mosfet on resistance vin=12v vcc=5v - 12 18 m w bootstrap switch v f ron v pvcc C v boot-gnd , i f = 10ma - 0.5 0.7 v i r reverse leakage v boot-gnd = 30v, v phase = 25v, v pvcc = 5v - - 0.5 m a vcc por threshold v lcc_thf falling vcc por threshold voltage 4.25 4.35 4.45 v ldo por hysteresis - 100 - mv control inputs en high-level input voltage 2.5 - - v en low-level input voltage - - 0.5 v en leakage en=0v - 0.1 - m a pfm high-level input voltage 2.5 - - v pfm low-level input voltage - - 0.5 v pfm leakage pfm=0v - 0.1 - m a
copyright ? anpec electronics corp. rev. a.5 - apr., 2016 www.anpec.com.tw 5 APW8715 electrical characteristics unless otherwise specified, these specifications apply over v in =12v,v en =5v and t a = -40 to 85 o c. typical values are at t a =25 o c. APW8715 symbol parameter test condition min. typ. max. unit power-ok indicator pok in from lower (pok goes high) 87 90 93 % v pok pok threshold pok out from normal (pok goes low) 120 125 130 % i pok pok leakage current v pok =5v - 0.1 - m a pok sink current v pok =0.5v 1.25 7.5 - ma pok out debounce time2 when run away 90% - 20 - m s pok enable delay time from en high to pok high - tss - ms current sense i ocp ocp threshold valley current of il 7 - - a zero crossing comparator offset v gnd-lx voltage, pfm=0v -5 0 5 mv protection v uv uvp threshold 65 70 75 % uvp debounce interval 16 m s uvp enable delay en high to uvp workable tss ms v ovr ovp rising threshold1 ovp occur 120 125 130 % ovp propagation delay v fb rising, over voltage=10mv - 3 - m s t otr otp rising threshold (note 5) - 145 - o c otp hysteresis (note 5) - 45 - o c
copyright ? anpec electronics corp. rev. a.5 - apr., 2016 www.anpec.com.tw 6 APW8715 pin description pin no. name function 1 pok power-good output pin of pwm. pok is an open-drain output used to indicate the status of the pwm output voltage. connect the pok in to +5v through a pull-high resistor. 2 en pwm enable. pwm is enabled when en=1. when en=0, pwm is in shutdown. 3 pfm pfm selection input. when the pfm is above high logic level, the device is in force pwm mode. when the pfm is below low logic level, the device is in automatic pfm/pwm mode. 4 agnd signal ground for the ic. 5 fb output voltage feedback pin. this pin is connected to the resistive divider that set the desired output voltage. the pok, uvp, and ovp circuits detect this signal to report output voltage status. 6 ton this pin is allowed to adjust the switching frequency. connect a resistor r ton from ton pin to vin pin. 7 nc no connect. 8, 9, 22 vin battery voltage input pin. vin powers linear regulators and is also used for the constant on-time pwm on-time one-shot circuits. 10, 11, 16~18 lx junction point of the high-side mosfet source, output filter inductor and the low-side mosfet drain for pwm. connect this pin to the source of the high-side mosfet. lx serves as the lower supply rail for the ugate high-side gate driver. lx is the current-sense input for the pwm. 12~15, 19 pgnd power ground of the lgate low-side mosfet drivers. 20 boot supply input for the ugate gate driver and an internal level-shift circuit. connect to an external capacitor to create a boosted voltage suitable to drive a logic-level n-channel mosfet. 21 vcc supply voltage input pin for control circuitry, connect +5v from the vcc pin to the gnd pin. decoupling at least 1 m f of a mlcc capacitor from the vcc pin to the agnd pin. 23 ss soft start output. connect a capacitor to gnd to set the soft start interval.
copyright ? anpec electronics corp. rev. a.5 - apr., 2016 www.anpec.com.tw 7 APW8715 block diagram fb error comparator ov uv 70% v ref 125% v ref v ref por vcc en p w m s i g n a l c o n t r o l l e r thermal shutdown gnd pok lx fault latch logic on-time generator 90% v ref 125% v ref z c lx delay lx pgnd ug gate driver gate driver vcc lg boot vcc v lx vin current limit reference pfm ldo soft - start ss mean value circuit ton pfm
copyright ? anpec electronics corp. rev. a.5 - apr., 2016 www.anpec.com.tw 8 APW8715 typical application circuit when vin=19v, dual power input : ton lx pgnd fb r top 20k r gnd 62k l out 1.0uh APW8715 c in 10uf /25v x 4 (mlcc) 19v v out 1.058v, 6a c out2 22ufx4 ss agnd 5v c vcc 1uf pok vcc en vin 100k boot c out1 150uf c boot 0.1uf pfm mode selection r pok 100k
copyright ? anpec electronics corp. rev. a.5 - apr., 2016 www.anpec.com.tw 9 APW8715 typical application circuit when vin=5v, single power input : ton lx pgnd fb r top 20k r gnd 62k l out 1.0uh APW8715 c in 10uf /12v x 4 (mlcc) 5v v out 1.058v, 6a c out2 22ufx4 ss agnd c vcc 1uf pok r pok 100k vcc en vin 100k boot c out1 150uf c boot 0.1uf pfm mode selection
copyright ? anpec electronics corp. rev. a.5 - apr., 2016 www.anpec.com.tw 10 APW8715 function description constant-on-time pwm controller with input feed- forward the constant on-time control architecture is a pseudo- fixed frequency with input voltage feed-forward. this ar- chitecture relies on the output filter capacitor s effective series resistance (esr) to act as a current-sense resistor, so the output ripple voltage provides the pwm ramp signal. in pfm operation, the high-side switch on-time controlled by the on-time generator is determined solely by a one- shot whose pulse width is inversely proportional to input voltage and directly proportional to output voltage. in pwm operation, the high-side switch on-time is determined by a switching frequency control circuit in the on-time gen- erator block. the switching frequency control circuit senses the switch- ing frequency of the high-side switch and keeps regulat- ing it at a constant frequency in pwm mode. the design improves the frequency variation and is more outstand- ing than a conventional constant on-time controller, which has large switching frequency variation over input voltage, output current and temperature. both in pfm and pwm, the on-time generator, which senses input voltage on vin pin, provides very fast on-time response to input line transients. another one-shot sets a minimum off-time (typical: 250ns). the on-time one-shot is triggered if the error com- parator is high, the low-side switch current is below the current-limit threshold, and the minimum off-time one- shot has timed out. over-current protection of the pwm converter in pfm mode, an automatic switchover to pulse-frequency modulation (pfm) takes place at light loads. this switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current zero crossing. this mechanism causes the threshold between pfm and pwm operation to coincide with the boundary between continuous and discontinuous inductor-current operation (also known as the critical conduction point). the on-time of pfm is given by: where fsw is the nominal switching frequency of the converter in pwm mode. the load current at handoff from pfm to pwm mode is given by: in out sw out in pfm - on out in pwm) to (pfm load v v f 1 2l v - v t l v - v 2 1 i = = in out sw pfm - on v v f 1 t = forced-pwm mode the forced-pwm mode disables the zero-crossing comparator, which truncates the low-side switch on-time at the inductor current zero crossing. this causes the low-side gate-drive waveform to become the complement of the high-side gate-drive waveform. this in turn causes the inductor current to reverse at light loads while ug maintains a duty factor of v out /v in . the benefit of forced- pwm mode is to keep the switching frequency fairly constant. the forced-pwm mode is most useful for re- ducing audio frequency noise, improving load-transient response, and providing sink-current capability for dy- namic output voltage adjustment. when v pfm is above the pfm high threshold (2.5v, minimum), the converter is in forced-pwm mode. when v pfm is below the pfm low threshold (0.5v, maximum), the chip is in automatic pfm/pwm mode. power-on-reset a power-on-reset (por) function is designed to prevent wrong logic controls when the vcc voltage is low. the por function continually monitors the bias supply volt- age on the vcc pin if at least one of the enable pins is set high. when the rising vcc voltage reaches the rising por voltage threshold (4.35v, typical), the por signal goes high and the chip initiates soft-start operations. should this voltage drop lower than 4.25v (typical), the por disables the chip. en pin control when v en is above the en high threshold (2.5v, minimum), the converter is enabled. when v en is below the en low threshold (0.5v, maximum), the chip is in the shutdown and only low leakage current is taken from vcc.
copyright ? anpec electronics corp. rev. a.5 - apr., 2016 www.anpec.com.tw 11 APW8715 function description (cont.) the APW8715 integrates soft-start circuits to ramp up the output voltage of the converter to the programmed regu- lation set point at a predictable slew rate. the slew rate of output voltage is internally controlled to limit the inrush current through the output capacitors during soft- start process. when the en pin is pulled above the rising en threshold voltage, the device initiates a soft-start pro- cess to ramp up the output voltage. during soft-start stage before the pgood pin is ready, the under voltage protection is prohibited. the over volt- age and current limit protection functions are enabled. if the output capacitor has residue voltage before startup, both low-side and high-side mosfets are in off-state until the soft start voltage equal the v fb voltage. this will ensure the output voltage starts from its existing voltage level. in the event of under-voltage, over-voltage, over-tempera- ture or shutdown, the chip enables the soft-stop function. the soft-stop function discharges the output voltages by low side turns mosfet on linearly. power good indicator pok is actively held low in shutdown and soft-start status. in the soft-start process, the pok is an open-drain. when the soft-start is finished, the pok is released. in normal operation, the pok window is from 90% to 125% of the converter reference voltage. when the output voltage has to stay within this window, pok signal will become high. when the output voltage outruns 90% or 125% of the target voltage, pok signal will be pulled low immediately. in order to prevent false pok drop, capacitors need to parallel at the output to confine the voltage deviation with severe load step transient. under-voltage protection (uvp) in the process of operation, if a short circuit occurs, the output voltage will drop quickly. when load current is big- ger than current limit threshold value, the output voltage will fall out of the required regulation range. the under- voltage protection circuit continually monitors the fb volt- age after soft-start is completed. if a load step is strong enough to pull the output voltage lower than the under voltage threshold, the under voltage threshold is 70% of the nominal output voltage, the internal uvp delay counter starts to count. after 16ms de-bounce time, the device turns off both high side and low-side mosefet with latched. toggling enable pin to low, or recycling vin, will clear the latch and bring the chip back to operation. soft-start the APW8715 provides the programmed soft-start func- tion to limit the inrush current. the soft-start time can be programmed by the external capacitor between ss and gnd. typical charge current is 10ua, and the soft-start time can be calculated by the following formula: over-voltage protection (ovp) the over voltage function monitors the output voltage by fb pin. should the fb voltage increase over 125% of the reference voltage due to the high-side mosfet failure or for other reasons, the over voltage protection comparator designed with a 3 m s noise filter will force the low-side mosfet gate driver fully turn on and latch high. this ac- tion actively pulls down the output voltage. this ovp scheme only clamps the voltage overshoot, and does not invert the output voltage when otherwise activated with a continuously high output from low-side mosfet driver. it s a common problem for ovp schemes with a latch. once an over-voltage fault condition is set, it can only be reset by toggling en or vin power-on-reset signal. (nf) c 330 s) ( t ss ss = m current limit the current limit circuit employs a "valley" current-sens- ing algorithm (see figure 1). the APW8715 uses the low-side mosfet s r ds(on) of the synchronous rectifier as a current-sensing element. if the magnitude of the current-sense signal at lx pin is above the current-limit threshold 7a(minimum), the pwm is not allowed to ini- tiate a new cycle. the actual peak current is greater than the current-limit threshold by an amount equal to the in- ductor ripple current. therefore, the exact current-limit char- acteristic and maximum load capability are a function of the sense resistance, inductor value, and input voltage.
copyright ? anpec electronics corp. rev. a.5 - apr., 2016 www.anpec.com.tw 12 APW8715 function description (cont.) figure 1. current limit algorithm time i n d u c t o r c u r r e n t 0 i peak i out i limit i current limit( cont.) the pwm controller uses the low-side mosfets on-re- sistance r ds(on) to monitor the current for protection against shorted outputs. the mosfet s r ds(on) is varied by temperature and gate to source voltage, the user should determine the maximum r ds(on) in manufacture s datasheet. the pcb layout guidelines should ensure that noise and dc errors do not corrupt the current-sense signals at lx. place the hottest power mosefts as close to the ic as possible for best thermal coupling. when combined with the under-voltage protection circuit, this current-limit method is effective in almost every circumstance. over-temperature protection (otp) when the junction temperature increases above the ris- ing threshold temperature t otr , the ic will enter the over temperature protection state that suspends the pwm, which forces the ug and lg gate drivers output low. the thermal sensor allows the converters to start a start-up process and regulate the output voltage again after the junction temperature cools by 45 o c. the otp designed with a 45 o c hysteresis lowers the average t j during con- tinuous thermal overload conditions, which increases life- time of the APW8715. programming the on-time control and pwm switch- ing frequency the APW8715 does not use a clock signal to produce pwm. the device uses the constant on-time control ar- chitecture to produce pseudo-fixed frequency with input voltage feed-forward. the on-time pulse width is propor- tional to output voltage v out and inverse proportional to input voltage v in . in pwm, the on-time calculation is writ- ten as below equation. (v) v ) ( r 10 2 t in ton -12 on w = 3 . 6 where: r ton is the resistor connected from ton pin to vin pin. furthermore, the approximate pwm switching frequency is written as: on in out sw sw on t v v f f d t = = where: f sw is the pwm switching frequency.
copyright ? anpec electronics corp. rev. a.5 - apr., 2016 www.anpec.com.tw 13 APW8715 application information output inductor selection the output voltage is adjustable from 0.8v to 12v with a resistor-divider connected with fb, gnd, and converter | s output. using 1% or better resistors for the resistor-di- vider is recommended. the output voltage is determined by: where 0.8 is the reference voltage, r top is the resistor connected from converter ?| s output to fb, and r gnd is the resistor connected from fb to gnd. suggested r gnd is in the range from 1k to 20k w . to prevent stray pickup, locate resistors r top and r gnd close to APW8715. ) r r (1 0.8 v gnd top out + = output inductor selection the duty cycle (d) of a buck converter is the function of the input voltage and output voltage. once an output voltage is fixed, it can be written as: output capacitor selection output voltage ripple and the transient voltage deviation are factors that have to be taken into consideration when selecting an output capacitor. higher capacitor value and lower esr reduce the output ripple and the load transient drop. therefore, selecting high performance low esr capacitors is recommended for switching regulator applications. in addition to high frequency noise related to mosfet turn-on and turnoff, the output voltage ripple includes the capacitance voltage drop d v cout and esr voltage drop d v esr caused by the ac peak-to-peak inductor s current. these two voltages can be represented by: in out v v d = the inductor value (l) determines the inductor ripple current, i ripple , and affects the load transient response. higher inductor value reduces the inductor | s ripple cur- rent and induces lower output ripple voltage. the ripple current and ripple voltage can be approximated by: in out sw out in ripple v v l f v - v i = where f sw is the switching frequency of the regulator. although the inductor value and frequency are increased and the ripple current and voltage are reduced, a tradeoff exists between the inductor s ripple current and the regu- lator load transient response time. a smaller inductor will give the regulator a faster load transient response at the expense of higher ripple current. increasing the switching frequency (f sw ) also reduces the ripple current and voltage, but it will increase the switching loss of the mosfets and the power dissipa- tion of the converter. the maximum ripple current occurs at the maximum input voltage. a good starting point is to choose the ripple current to be approximately 30% of the maximum output current. once the inductance value has been chosen, selecting an in- ductor that is capable of carrying the required peak cur- rent without going into saturation.in some types of inductors, especially core that is made of ferrite, the ripple current will increase abruptly when it saturates. this re- sults in a larger output ripple voltage. besides, the induc- tor needs to have low dcr to reduce the loss of efficiency. sw out ripple out f c 8 i c = d esr ripple esr r i v = d these two components constitute a large portion of the total output voltage ripple. in some applications, multiple capacitors have to be paralleled to achieve the desired esr value. if the output of the converter has to support another load with high pulsating current, more capacitors are needed in order to reduce the equivalent esr and suppress the voltage ripple to a tolerable level. a small decoupling capacitor (1 m f) in parallel for bypassing the noise is also recommended, and the voltage rating of the output capacitors are also must be considered. to support a load transient that is faster than the switch- ing frequency, more capacitors are needed for reducing the voltage excursion during load step change. another aspect of the capacitor selection is that the total ac cur- rent going through the capacitors has to be less than the rated rms current specified on the capacitors in order to prevent the capacitor from over-heating.
copyright ? anpec electronics corp. rev. a.5 - apr., 2016 www.anpec.com.tw 14 APW8715 application information (cont.) the input capacitor is chosen based on the voltage rating and the rms current rating. for reliable operation, select- ing the capacitor voltage rating to be at least 1.3 times higher than the maximum input voltage. the maximum rms current rating requirement is approximately i out /2, where i out is the load current. during power-up, the input capacitors have to handle great amount of surge current. for low-duty notebook applications, ceramic capacitor is recommended. the capacitors must be connected be- tween the drain of high-side mosfet and the source of low-side mosfet with very low-impedance pcb layout. input capacitor selection sw sw in out ds(on) 2 out upper )f )(t )(v 0.5(i )d tc)(r (1 i p + + = because the APW8715 build-in high-side and low-side mosfet, the heat dissipated may exceed the maximum junction temperature of the part in applications. if the junc- tion temperature reaches approximately 150 o c, both power switches will be turned off and the lx node will become high impedance. to avoid the APW8715 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. the goal of the thermal analysis is to determine whether the power dis- sipated exceeds the maximum junction temperature of the part. the main power dissipated by the part is approximated: thermal consideration d) - )(1 tc)(r (1 i p ds(on) 2 out lower + = i out is the load current tc is the temperature dependency of r ds(on) f sw is the switching frequency t sw is the switching interval d is the duty cycle note that both internal mosfets have conduction losses while the upper mosfet include an additional transition loss. the switching internal, t sw , is the function of the reverse transfer capacitance c rss . the (1+tc) term fac- tors in the temperature dependency of the r ds(on) and can be extracted from the "rds(on) vs. temperature" curve of the power mosfet. in APW8715 case, the r ds(on) is about 30mw from specification table. layout consideration in any high switching frequency converter, a correct lay- out is important to ensure proper operation of the regulator. with power devices switching at higher frequency, the resulting current transient will cause volt- age spike across the interconnecting impedance and parasitic circuit elements. as an example, consider the turn-off transition of the pwm mosfet. before turn-off condition, the mosfet is carrying the full load current. during turn-off, current stops flowing in the mosfet and is freewheeling by the low side mosfet and parasitic diode. any parasitic inductance of the circuit generates a large voltage spike during the switching interval. in general, using short and wide printed circuit traces should minimize interconnecting impedances and the magni- tude of voltage spike. besides, signal and power grounds are to be kept separate and finally combined using ground plane construction or single point grounding. the best tie-point between the signal ground and the power ground is at the negative side of the output capacitor on each channel, where there is less noise. noisy traces beneath the ic are not recommended. below is a checklist for your layout: - keep the switching nodes (boot and lx) away from sensitive small signal nodes since these nodes are fast moving signals. therefore, keep traces to these nodes as short as possible and there should be no other weak signal traces in parallel with theses traces on any layer. - the large layout plane between the drain of the mosfets (vin and lx nodes) can get better heat sinking. - the current sense resistor should be close to ocset pin to avoid parasitic capacitor effect and noise coupling. - decoupling capacitors, the resistor-divider, and boot capacitor should be close to their pins. - the output bulk capacitors should be close to the loads. the input capacitor s ground should be close to the grounds of the output capacitors. - locate the resistor-divider close to the fb pin to mini- mize the high impedance trace. in addition, fb pin traces can t be close to the switching signal traces (boot and lx).
copyright ? anpec electronics corp. rev. a.5 - apr., 2016 www.anpec.com.tw 15 APW8715 application information (cont.) recommended minimum footprint 0.5 0.3 0.4 4mm * just recommend tqfn4x4-23 0.2 * 4mm thermalvia diameter 0.3mm x 12 2 . 7 - 1.35 0.4 0.25 0.95 0.25 0.25 2 . 9 5 0.25 0.5 unit:mm 0.2 0.05 0.13 0.02
copyright ? anpec electronics corp. rev. a.5 - apr., 2016 www.anpec.com.tw 16 APW8715 package information tqfn4x4-23 e d pin 1 b a a1 a3 nx aaa c e 1 pin 1 corner d1 d2 e 2 k l e 0.124 d2 2.95 3.15 0.116 0.057 e1 1.24 1.44 0.049 0.70 0.041 0.028 0.002 0.50 bsc 0.020 bsc k 0.20 0.008 3.90 4.10 0.154 0.161 3.90 4.10 0.154 0.161 0.08 aaa 0.003 s y m b o l min. max. 0.80 0.00 0.20 0.30 2.58 2.78 0.05 0.85 a a1 b d d1 e e2 e l millimeters a3 0.20 ref tqfn4x4-23 0.35 0.45 1.05 0.008 ref min. max. inches 0.032 0.000 0.008 0.012 0.102 0.109 0.033 0.014 0.018
copyright ? anpec electronics corp. rev. a.5 - apr., 2016 www.anpec.com.tw 17 APW8715 devices per unit carrier tape & reel dimensions package type unit quantity tqfn4x4 tape & reel 3000 h t1 a d a e 1 a b w f t p0 od0 b a0 p2 k0 b 0 section b-b section a-a od1 p1 application a h t1 c d d w e1 f 330.0 2.00 50 min. 12.4+2.00 - 0.00 13.0+0.50 -0.20 1.5 min. 20.2 min. 12.0 0.30 1.75 0.10 5.50 0.05 p0 p1 p2 d0 d1 t a0 b0 k0 tqfn4x4 4.00 0.10 8.00 0.10 2.00 0.05 1.5+0.10 -0.00 1.5 min. 0.6+0.00 -0.40 4.30 0.20 4.30 0.20 1.00 0.20 (mm)
copyright ? anpec electronics corp. rev. a.5 - apr., 2016 www.anpec.com.tw 18 APW8715 classification profile taping direction information tqfn4x4 user direction of feed
copyright ? anpec electronics corp. rev. a.5 - apr., 2016 www.anpec.com.tw 19 APW8715 classification reflow profiles profile feature sn-pb eutectic assembly pb-free assembly preheat & soak temperature min (t smin ) temperature max (t smax ) time (t smin to t smax ) (t s ) 100 c 150 c 60-120 seconds 150 c 200 c 60-120 seconds average ramp-up rate (t smax to t p ) 3 c/second max. 3 c/second max. liquidous temperature (t l ) time at liquidous (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak package body temperature (t p )* see classification temp in table 1 see classification temp in table 2 time (t p )** within 5 c of the specified classification temperature (t c ) 20** seconds 30** seconds average ramp-down rate (t p to t smax ) 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. * tolerance for peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. ** tolerance for time at peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. table 2. pb-free process C classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 350-2000 volume mm 3 >2000 <1.6 mm 260 c 260 c 260 c 1.6 mm C 2.5 mm 260 c 250 c 245 c 3 2.5 mm 250 c 245 c 245 c table 1. snpb eutectic process C classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 3 350 <2.5 mm 235 c 220 c 3 2.5 mm 220 c 220 c test item method description solderability jesd-22, b102 5 sec, 245 c holt jesd-22, a108 1000 hrs, bias @ tj=125 c pct jesd-22, a102 168 hrs, 100 % rh, 2atm, 121 c tct jesd-22, a104 500 cycles, -65 c~150 c hbm mil-std-883-3015.7 vhbm R 2kv mm jesd-22, a115 vmm R 200v latch-up jesd 78 10ms, 1 tr R 100ma reliability test program
copyright ? anpec electronics corp. rev. a.5 - apr., 2016 www.anpec.com.tw 20 APW8715 customer service anpec electronics corp. head office : no.6, dusing 1st road, sbip, hsin-chu, taiwan, r.o.c. tel : 886-3-5642000 fax : 886-3-5642050 taipei branch : 2f, no. 11, lane 218, sec 2 jhongsing rd., sindian city, taipei county 23146, taiwan tel : 886-2-2910-3838 fax : 886-2-2917-3838

▲Up To Search▲

Price & Availability of APW8715

	To Download APW8715 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .