cystech electronics corp. spec. no. : c 02 4 fp issued date : 20 18 . 0 5 . 1 5 revised date : page no. : 1 / 8 mte 0 1 4 n1 5 rfp cyste k product specification n - channel enhancement mode power mosfet mte 0 1 4 n1 5 rfp features ? low on resistance ? simple drive requirement ? low gate charge ? fast switching characteristic ? rohs compliant package symbol outline o rdering inf ormation device package shipping mte 0 14 n1 5 rfp - 0 - ub - s t o - 220 fp (rohs compliant) 50 pcs/tube, 20 tubes/box, 4 boxes / carton mte 0 1 4 n1 5 rfp to - 220fp g gate d drain s source bv dss 1 5 0v i d @v gs =10v, t c =25 c 5 2 a i d @v gs =10v, t a =25 c 7 . 3 a r ds(on) @v gs =10v, i d = 2 0a 1 4 m (typ) environment friendly grade : s for rohs compliant products, g for rohs compliant and green compound products packing spec, ub : 50 pcs / tube, 20 tubes/box product ran k, zero for no rank products product name g d s
cystech electronics corp. spec. no. : c 02 4 fp issued date : 20 18 . 0 5 . 1 5 revised date : page no. : 2 / 8 mte 0 1 4 n1 5 rfp cyste k product specification absolute maximum ra tings (t c =25 ? c) parameter symbol limits unit drain - sour c e voltage (note 1) v ds 1 5 0 v gate - source voltage v gs 20 continuous drain current @t c =25 ? c , v gs =10v (note 1) i d 5 2 * a continuous drain current @t c =1 00 ? c , v gs =10v (note 1) 3 6.8 * continuous drain current @t a =25 ? c , v gs =10v (note 2) i dsm 7 .3 continuous drain current @t a =70 ? c , v gs =10v (note 2) 5 .8 pulsed drain current @ v gs =10v i dm 2 10 * avalanche current @ l=100 h i as 8 0 single pulse avalanche energy @ l=1mh, i d = 3 6 a, v dd = 2 5 v (note 4) e as 6 48 mj repetitive avalanche energy (note 3) e ar 25 power dissipation t c =25 ? c (note 1) p d 125 w t c =100 ? c (note 1) 62.5 t a =25 ? c (note 2) p dsm 2.1 t a =70 ? c (note 2) 1.4 maximum temperature for soldering @ lead at 0.063 in(1.6mm) from case for 10 seconds t l 300 ? c maximum temperature for soldering @ package body for 10 seconds t pkg 260 operating junction and storage temperature tj, tstg - 55~+1 75 *drain current limited by maximum junction temperature thermal data parameter symbol value unit thermal resistance, junction - to - case, max r jc 1. 2 ? c /w thermal resistance, junction - to - ambient, max (note 2) r ja 58 note : 1 . the power dissipation p d is based on t j(max) =175 c, using junction - to - case thermal resistance, and is more useful in setting the upper dissipation limit for cases where additional heatsinking is used. 2 . the value of r ja is measured with the device mounted on 1 in 2 fr - 4 board with 2 oz. copper, in a still air environment with t a =25 c. the power dissipation p dsm is based on r ja and the maximum allowed junction temperature of 150 c. the value in any given application depends on the user s specific board design, and the maximum temperature of 175 c may be used if the pcb allows it. 3 . repetitive rating, pulse width li mited by junction temperature t j(max) =175 c. ratings are based on low frequency and low duty cycles to keep initial t j =25 c. 4. 100% tested by condition of l=0.1mh, i as = 1 2 a, v gs =10v, v dd = 2 5 v.
cystech electronics corp. spec. no. : c 02 4 fp issued date : 20 18 . 0 5 . 1 5 revised date : page no. : 3 / 8 mte 0 1 4 n1 5 rfp cyste k product specification characteristics (t j =25 ? symbol min. typ. max. unit test conditions static bv dss 1 5 0 - - v v gs = 0v , i d = 250 a ? bv dss / ? tj - 0 .14 - v/ ? c reference to 25 ? c , i d =250 a v gs(th) 2 - 4 v v ds = v gs , i d = 250 a *g fs - 3 0.2 - s v ds = 10v , i d = 20a i gss - - 100 n a v g s = 20v, v ds =0v i dss - - 1 a v ds = 1 2 0v, v gs =0v - - 25 v ds = 1 2 0v, v gs =0v, tj=125 ? c *r ds ( on ) - 1 4 1 8 m v gs = 10v , i d = 2 0a dynamic *qg - 6 3 .4 8 2 nc v ds = 7 5 v, i d = 2 0a, v gs =10v *qgs - 1 6.3 2 5 *qgd - 1 5 .9 2 4 *t d(on) - 2 9.6 - ns v ds = 7 5 v, i d =20a, v gs =10v, r gs = 1 *tr - 1 1 .8 - *t d(off) - 5 3 .2 - *t f - 1 3 .2 - ciss 3430 3 820 6375 pf v gs =0v, v ds = 7 5 v, f=1mhz co ss - 2 48 - crss - 2 8 - rg - 1 .4 - f=1mhz source - drain diode *i s - - 5 2 a *i sm - - 2 10 *v sd - 0. 7 8 1 .2 v i s = 1 0a, v gs =0v *trr - 7 2 - ns v gs =0v, i f = 1 0a, di f /dt=100a/ s *qrr - 2 06 - nc *pulse test : pulse width ? 3 0 0s, duty cycle ? 2%
cystech electronics corp. spec. no. : c 02 4 fp issued date : 20 18 . 0 5 . 1 5 revised date : page no. : 4 / 8 mte 0 1 4 n1 5 rfp cyste k product specification typical characteristics typical output characteristics 0 40 80 120 160 200 0 2 4 6 8 10 v ds , drain-source voltage(v) i d , drain current(a) 10v,9v,8v,7v v gs =4v 5v 4.5v 6v brekdown voltage vs ambient temperature 0.4 0.6 0.8 1 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 200 tj, junction temperature( c) bv dss , normalized drain-source breakdown voltage i d =250 a, v gs =0v static drain-source on-state resistance vs drain current 10 100 0.1 1 10 100 i d , drain current(a) r ds(on) , static drain-source on-state resistance(m) in descending order v gs = 6v 7v 10v reverse drain current vs source-drain voltage 0.2 0.4 0.6 0.8 1.0 1.2 0 5 10 15 20 i dr , reverse drain current(a) v sd , source-drain voltage(v) tj=25 c tj=150 c static drain-source on-state resistance vs gate-source voltage 0 5 10 15 20 25 30 35 40 45 50 0 2 4 6 8 10 v gs , gate-source voltage(v) r ds(on) , static drain-source on- state resistance(m) i d =20a drain-source on-state resistance vs junction tempearture 0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 -75 -50 -25 0 25 50 75 100 125 150 175 200 tj, junction temperature( c) r ds(on) , normalized static drain- source on-state resistance v gs =10v, i d =20a r ds(on) @tj=25c : 14m typ.
cystech electronics corp. spec. no. : c 02 4 fp issued date : 20 18 . 0 5 . 1 5 revised date : page no. : 5 / 8 mte 0 1 4 n1 5 rfp cyste k product specification typical characteristics (cont.) capacitance vs drain-to-source voltage 1 10 100 1000 10000 0 10 20 30 40 50 60 70 80 90 100 v ds , drain-source voltage(v) capacitance---(pf) c oss ciss crss threshold voltage vs junction tempearture 0.2 0.4 0.6 0.8 1.0 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 200 tj, junction temperature( c) v gs(th) , normalized threshold voltage i d =250 a i d =1ma forward transfer admittance vs drain current 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 100 i d , drain current(a) g fs , forward transfer admittance(s) pulsed ta=25c v ds =15v v ds =10v gate charge characteristics 0 2 4 6 8 10 0 10 20 30 40 50 60 70 qg, total gate charge(nc) v gs , gate-source voltage(v) i d =20a v ds =30v, 75v, 120v from left to right maximum safe operating area 0.1 1 10 100 1000 0.1 1 10 100 1000 v ds , drain-source voltage(v) i d , drain current(a) dc 10 0 ms 10 s 1 0 ms 100 s 1m s r ds(on) limited t c =25c, tj=175c v gs =10v,r jc =1.2c/w single pulse maximum drain current vs case temperature 0 10 20 30 40 50 60 25 50 75 100 125 150 175 200 t c , case temperature(c) i d , maximum drain current(a) v gs =10v,r jc =1.2c/w
cystech electronics corp. spec. no. : c 02 4 fp issued date : 20 18 . 0 5 . 1 5 revised date : page no. : 6 / 8 mte 0 1 4 n1 5 rfp cyste k product specification typical characteristics (cont.) typical transfer characteristics 0 50 100 150 200 0 2 4 6 8 10 v gs , gate-source voltage(v) i d , drain current (a) v ds =10v single pulse power rating, junction to case (note on page 2) 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 0.0001 0.001 0.01 0.1 1 10 pulse width(s) power (w) t j(max) =175c t c =25c r jc =1.2c/w transient thermal response curves 0.001 0.01 0.1 1 1.e-05 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 t 1 , square wave pulse duration(s) r(t), normalized effective transient thermal resistance single pulse 0.01 0.02 0.05 0.1 0.2 d=0.5 1.r jc (t)=r(t)*r jc 2.duty factor, d=t 1 /t 2 3.t jm -t a =p dm *r jc (t) 4.r jc =1.2c/w
cystech electronics corp. spec. no. : c 02 4 fp issued date : 20 18 . 0 5 . 1 5 revised date : page no. : 7 / 8 mte 0 1 4 n1 5 rfp cyste k product specification recommended wave soldering condition product peak temperature soldering time pb - free devices 260 +0/ - 5 ? c 5 + 1/ - 1 seconds recommended temperature profile for ir reflow profile feature sn - pb eutectic assembly pb - free assembly average ramp - up rate (tsmax to tp) 3 ? c /second max. 3 ? c /second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? tim e(ts min to ts max ) 100 ? c 150 ? c 60 - 120 seconds 150 ? c 200 ? c 60 - 180 seconds time maintained above: ? temperature (t l ) ? time (t l ) 183 ? c 60 - 150 seconds 217 ? c 60 - 150 seconds peak temperature(t p ) 240 +0/ - 5 ? c 260 +0/ - 5 ? c time within 5 ? c of actual peak temperature(tp) 10 - 30 seconds 20 - 40 seconds ramp down rate 6 ? c /second max. 6 ? c /second max. time 25 ? c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of the package, measured on the package body surface.
cystech electronics corp. spec. no. : c 02 4 fp issued date : 20 18 . 0 5 . 1 5 revised date : page no. : 8 / 8 mte 0 1 4 n1 5 rfp cyste k product specification to - 220fp dimension *typical dim inches millimeters dim inches millimeters min. max. min. max. min. max. min. max. a 0.1 71 0.18 3 4.3 5 4. 65 g 0.246 0.258 6.25 6.55 a1 0.051 ref 1.300 ref h 0.138 ref 3.50 ref a2 0.11 2 0.12 4 2.8 5 3. 15 h1 0.055 re f 1.40 ref a3 0. 102 0.11 0 2. 6 0 2. 8 0 h2 0.256 0.272 6.50 6.90 b 0.020 0.030 0.50 0.75 j 0.031 ref 0.80 ref b1 0.0 31 0.0 41 0.8 0 1. 0 5 k 0.020 0.50 ref b2 0.0 47 ref 1. 20 ref l 1.102 1.118 28.00 28.40 c 0.020 0.030 0.500 0.750 l1 0.0 43 0.05 1 1. 1 0 1. 3 0 d 0.39 6 0.40 4 10.06 10. 2 6 l2 0.0 36 0.0 4 3 0 .9 2 1 .0 8 e 0.583 0.598 14.80 15.20 m 0.067 ref 1.70 ref e 0.100 * 2.54 * n 0.012 ref 0.30 ref f 0.106 ref 2.70 ref notes: 1. controlling dimension: millimeters. 2 . maximum lead thickness includes le ad finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing specification or packing method, please contact your local cystek sales office. material: ? lead: pure tin pla ted. ? mold com pound: epoxy resin family, flammability solid burning class: ul94v - 0 . important notice: ? ? ? semiconductor products are not warranted to be suitable for use in life - support applications, or systems. ? style: pin 1. gate 2. drain 3. source 3 - lead to - 220fp plastic package cystek package code: fp marking: date code device name e 0 14 n1 5 r
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