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1 for more information www.linear.com/LT8362 description typical application features low i q boost/sepic/ inverting converter with 2a, 60v switch the lt ? 8362 is a current mode dc/dc converter with a 60v, 2a switch operating from a 2.8v to 60v input. with a unique single feedback pin architecture it is capable of boost, sepic or inverting configurations. burst mode operation consumes as low as 9a quiescent current to maintain high efficiency at very low output currents, while keeping typical output ripple below 15mv. an external compensation pin allows optimization of loop bandwidth over a wide range of input and output volt - ages and programmable switching frequencies between 300khz and 2mhz. a sync/mode pin allows synchroni - zation to an external clock. it can also be used to select between burst or pulse-skipping modes of operation with or without spread spectrum frequency modulation for low emi. for increased efficiency, a bias pin can accept a second input to supply the intv cc regulator. additional features include frequency foldback and programmable soft-start to control inductor current during start-up. the LT8362 is available in a thermally enhanced 10-lead 3mm 3mm dfn package or a thermally enhanced 16-lead msop package with four pins removed. 2mhz, 48v output boost converter applications n wide input voltage range: 2.8v to 60v n ultralow quiescent current and low ripple burst?mode ? operation: i q = 9a n 2a, 60v power switch n positive or negative output voltage programming with a single feedback pin n programmable frequency (300khz to 2mhz) n synchronizable to an external clock n spread spectrum frequency modulation for low emi n bias pin for higher efficiency n programmable undervoltage lockout (uvlo) n thermally enhanced 10-lead 3mm 3mm dfn and 16-lead msop packages n industrial and automotive n telecom n medical diagnostic equipment n portable electronics all registered trademarks and trademarks are the property of their respective owners. efficiency and power loss LT8362 8362fa en/uvlo LT8362 v in 8v to 38v v out 48v 200ma at v in = 8v 320ma at v in = 12v 700ma at v in = 24v 6.8h 1m sync/mode fbx bias ss 8362 ta01a gnd v c 4.7f 4.7f rt intv cc 10nf 4.7pf efficiency power loss 34.8k v in = 12v v in = 24v load current (a) 0 0.1 0.2 0.3 0.4 0.5 0.6 57.6k 0.7 0.8 0 10 20 30 40 50 60 70 150pf 80 90 100 0 0.2 0.4 0.6 0.8 1.0 1.2 20k 1.4 1.6 1.8 2.0 efficiency (%) power loss (w) 8362 ta01b 1f v in sw
2 for more information www.linear.com/LT8362 sw ............................................................................ 6 0v v in , en/uvlo ............................................................ 60v bias .......................................................................... 40v en/uvlo pin above v in pin, sync ............................. 6v intv cc ............................................................... ( note 2) v c ............................................................................... 4v order information lead free finish tape and reel part marking* package description temperature range LT8362emse#pbf LT8362emse#trpbf 8362 16-lead plastic msop with 4 pins removed C40c to 125c LT8362imse#pbf LT8362imse#trpbf 8362 16-lead plastic msop with 4 pins removed C40c to 125c LT8362hmse#pbf LT8362hmse#trpbf 8362 16-lead plastic msop with 4 pins removed C40c to 150c LT8362edd#pbf LT8362edd#trpbf lgwz 10-lead (3mm 3mm) plastic dfn C40c to 125c LT8362idd#pbf LT8362idd#trpbf lgwz 10-lead (3mm 3mm) plastic dfn C40c to 125c LT8362hdd#pbf LT8362hdd#trpbf lgwz 10-lead (3mm 3mm) plastic dfn C40c to 150c consult ltc ? marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on nonstandard lead based finish parts. for more information on lead free part marking, go to : http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 3 6 8 6 2 2 6 2 6 ja = 45c/w, jc = 10c/w exposed pad (pin 17) is pgnd and gnd, must be soldered to pcb top view dd package 10-lead (3mm 3mm) plastic dfn 10 9 6 7 8 4 5 3 2 1 sw sync/mode ss rt fbx en/uvlo v in intv cc bias v c 11 pgnd, gnd ja = 43c/w exposed pad (pin 11) is pgnd and gnd, must be soldered to pcb pin configuration absolute maximum ratings (note 1) fbx ........................................................................... 4v operating junction temperature (note 3) lt 8362 e, LT8362 i ............................... C 40 c to 125 c lt 8362 h ............................................. C 40 c to 150 c storage temperature range ................... C 65 c to 150 c http://www.linear.com/product/LT8362#orderinfo LT8362 8362fa
3 for more information www.linear.com/LT8362 parameter conditions min typ max units v in operating voltage range l 2.8 60 v v in quiescent current at shutdown v en/uvlo = 0.2v l 1 1 2 15 a a v en/uvlo = 1.5v l 2 2 5 25 a a v in quiescent current sleep mode (not switching) sync = 0v l 9 9 15 30 a a active mode (not switching) sync = 0v or intv cc , bias = 0v l 1200 1200 1600 1850 a a sync = 0v or intv cc , bias = 5v l 22 22 40 65 a a bias threshold rising, bias can supply int v cc falling, bias cannot supply intv cc 4.4 4 4.65 4.25 v v v in falling threshold to supply intv cc bias = 12v bias C 2v v bias falling threshold to supply intv cc v in = 12v v in v fbx regulation fbx regulation voltage fbx > 0v fbx < 0v l l 1.568 C0.820 1.6 C0.80 1.632 C0.780 v v fbx line regulation fbx > 0v, 2.8v < v in < 60v fbx < 0v, 2.8v < v in < 60v 0.005 0.005 0.015 0.015 %/v %/v fbx pin current fbx = 1.6v, C0.8v l C10 10 na oscillator switching frequency (f osc ) r t = 165k r t = 45.3k r t = 20k l l l 273 0.92 1.85 300 1 2 327 1.08 2.15 khz mhz mhz ssfm maximum frequency deviation ( ?f/f osc ) ? 100, r t = 20k 14 20 25 % minimum on-time burst mode, v in = 24v (note 6) pulse-skip mode, v in = 24v (note 6) 70 60 90 85 ns ns minimum off-t ime l 50 75 ns sync/mode, mode thresholds (note 5) high (rising) low (falling) l l 0.14 1.3 0.2 1.7 v v sync/mode, clock thresholds (note 5) rising falling l l 0.4 1.3 0.8 1.7 v v f sync /f osc allowed ratio r t = 20k 0.95 1 1.25 khz/khz sync pin current sync = 2v sync = 0v, current out of pin 10 10 25 25 a a switch maximum switch current limit threshold l 2 2.5 3.1 a switch over current threshold discharges ss pin 3.75 a switch r ds(on) i sw = 0.5a 165 m switch leakage current v sw = 60v 0.1 1 a electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 12v, en/uvlo = 12v unless otherwise noted. LT8362 8362fa
4 for more information www.linear.com/LT8362 electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 12v, en/uvlo = 12v unless otherwise noted. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: intv cc cannot be externally driven. no additional components or loading is allowed on this pin. note 3: the LT8362e is guaranteed to meet performance specifications from 0c to 125c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the LT8362i is guaranteed over the full C40c to 125c operating junction temperature range. the LT8362h is guaranteed over the full C40c to 150c operating junction temperature range. note 4: the ic includes overtemperature protection that is intended to protect the device during overload conditions. junction temperature will exceed 150c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature will reduce lifetime. note 5: for sync/mode inputs required to select modes of operation see the pin functions and applications information sections. note 6: the ic is tested in a boost converter configuration with the output voltage programmed for 24v. parameter conditions min typ max units en/uvlo logic en/uvlo pin threshold (rising) start switching l 1.576 1.68 1.90 v en/uvlo pin threshold (falling) stop switching l 1.555 1.6 1.645 v en/uvlo pin current v en/uvlo = 1.6v l C50 50 na soft-start soft-start charge current ss = 0.5v 2 a soft-start pull-down resistance fault condition, ss = 0.1v 220 error amplifier error amplifier transconductance fbx = 1.6v fbx = C0.8v 75 60 a/v a/v error amplifier v oltage gain fbx = 1.6v fbx = C0.8v 185 145 v/ v v/v error amplifier max sour ce current v c = 1.1v, current out of pin 7 a error amplifier max sink current v c = 1.1v 7 a LT8362 8362fa
5 for more information www.linear.com/LT8362 typical performance characteristics switching frequency vs temperature switching frequency vs v in normalized switching frequency vs fbx voltage switch current limit vs duty cycle switch minimum on-time vs temperature switch minimum off-time vs temperature fbx positive regulation voltage vs temperature fbx negative regulation voltage vs temperature en/uvlo pin thresholds vs temperature LT8362 8362fa 125 0 5 10 15 20 25 30 35 40 45 150 50 55 60 1.90 1.92 1.94 1.96 1.98 2.00 2.02 175 2.04 2.06 2.08 2.10 switching frequency (mhz) 8362 g05 voltage (v) ?0.8 ?0.4 0.0 1.568 0.4 0.8 1.2 1.6 0 25 50 75 100 125 1.576 normalized switching frequency (%) 8362 g06 v in = 12v duty cycle (%) 0 10 20 30 40 50 1.584 60 70 80 90 100 2.0 2.1 2.2 2.3 2.4 1.592 2.5 2.6 2.7 2.8 2.9 3.0 switch current limit (a) 8362 g07 v in = 12v junction temperature (c) 1.600 ?50 ?25 0 25 50 75 100 125 150 175 1.608 0 10 20 30 40 50 60 70 80 90 1.616 100 minimum on time (ns) 8362 g08 v in = 12v v in = 12v junction temperature (c) ?50 ?25 0 25 junction temperature (c) 1.624 50 75 100 125 150 175 0 10 20 30 1.632 40 50 60 70 80 90 100 minimum off time (ns) 8362 g09 fbx voltage (v) 8362 g01 v in = 12v junction temperature (c) ?50 ?25 0 25 ?50 50 75 100 125 150 175 ?0.820 ?0.815 ?0.810 ?0.805 ?25 ?0.800 ?0.795 ?0.790 ?0.785 ?0.780 fbx voltage (v) 8362 g02 v in = 12v en/uvlo rising (turn?on) en/uvlo falling (turn?off) 0 junction temperature (c) ?50 ?25 0 25 50 75 100 125 150 25 175 1.54 1.56 1.58 1.60 1.62 1.64 1.66 1.68 1.70 50 1.72 1.74 en/uvlo pin voltage (v) 8362 g03 junction temperature (c) ?50 ?25 0 25 50 75 75 100 125 150 175 1.90 1.92 1.94 1.96 1.98 100 2.00 2.02 2.04 2.06 2.08 2.10 switching frequency (mhz) 8362 g04 v in = 12v v in (v)
6 for more information www.linear.com/LT8362 typical performance characteristics switching waveforms (in ccm) switching waveforms (in dcm/light burst mode) switching waveforms (in deep burst mode) burst frequency vs load current v out transient response: load current transients from 160ma to 320ma to 160ma v out transient response: load current transients from 80ma to 320ma to 80ma v in pin current (sleep mode, not switching) vs temperature v in pin current (active mode, not switching, bias = 0v) vs temperature v in pin current (active mode, not switching, bias = 5v) vs temperature LT8362 8362fa 50 8362 g15 v in = 12v v out = 48v front page application 100s/div v out 500mv/div i out 200ma/div 8362 g16 75 v in = 12v v out = 48v front page application 100s/div v out 500mv/div i out 200ma/div 8362 g17 load current (ma) 100 0 10 20 30 40 50 0 0.5 1.0 1.5 125 2.0 2.5 switching frequency (mhz) 8362 g18 v in = 12v v out = 48v front page application 150 175 0 3 6 9 v in = 12v 12 15 18 21 24 27 30 v in pin current (a) 8362 g10 v in = 12v v bias = 0v v bias = 0v v sync_mode = float junction temperature (c) ?50 ?25 0 25 50 75 100 v sync_mode = 0v 125 150 175 0 0.2 0.4 0.6 0.8 1.0 1.2 junction temperature (c) 1.4 1.6 1.8 2.0 v in pin current (ma) 8362 g11 v in = 12v v bias = 5v v sync_mode = float junction temperature (c) ?50 ?50 ?25 0 25 50 75 100 125 150 175 ?25 10 14 18 22 26 30 34 38 42 46 0 50 v in pin current (a) 8362 g12 1s/div v sw 20v/div i l 500ma/div 8362 g13 1s/div 25 v sw 20v/div i l 500ma/div 8362 g14 1s/div v sw 20v/div i l 500ma/div
7 for more information www.linear.com/LT8362 pin functions en/uvlo: shutdown and undervoltage detect pin. the LT8362 is shut down when this pin is low and active when this pin is high. below an accurate 1.6v threshold, the part enters undervoltage lockout and stops switching. this allows an undervoltage lockout (uvlo) threshold to be programmed for system input voltage by resistively dividing down system input voltage to the en/uvlo pin. an 80mv pin hysteresis ensures part switching resumes when the pin exceeds 1.68v. en/uvlo pin voltage below 0.2v reduces v in current below 1a . if shutdown and uvlo features are not required, the pin can be tied directly to system input. v in : input supply. this pin must be locally bypassed. be sure to place the positive terminal of the input capacitor as close as possible to the v in pin, and the negative terminal as close as possible to the exposed pad pgnd copper (near en/uvlo). intv cc : regulated 3.2v supply for internal loads. the intv cc pin must be bypassed with a 1f low esr ceramic capacitor to gnd. no additional components or loading is allowed on this pin. intv cc draws power from the bias pin if 4.4v bias v in , otherwise intv cc is powered by the v in pin. nc: no internal connection. leave this pin open. bias: second input supply for powering intv cc . removes the majority of intv cc current from the v in pin to improve efficiency when 4.4v bias v in . if unused, tie the pin to gnd. v c : error amplifier output pin. tie external compensation network to this pin. fbx: voltage regulation feedback pin for positive or negative outputs. connect this pin to a resistor divider between the output and the exposed pad gnd copper (near fbx). fbx reduces the switching frequency during start-up and fault conditions when fbx is close to 0v. rt : a resistor from this pin to the exposed pad gnd cop - per (near fbx) programs switching frequency. ss : soft-start pin. connect a capacitor from this pin to gnd copper (near fbx) to control the ramp rate of induc - tor current during converter start-up. ss pin charging current is 2a . an internal 220 mosfet discharges this pin during shutdown or fault conditions. sync/mode: this pin allows five selectable modes for optimization of performance. sync/mode pin input capable mode(s) of operation (1) gnd or <0.14v burst (2) external clock pulse-skip/sync (3) 100k resistor to gnd burst/ssfm (4) float (pin open) pulse-skip (5) intv cc or >1.7v pulse-skip/ssfm where the selectable modes of operation are, burst = low i q , low output ripple operation at light loads pulse-skip = skipped pulse(s) at light load (aligned to clock) sync = switching frequency synchronized to external clock ssfm = spread spectrum frequency modulation for low emi sw1, sw2 (sw): output of the internal power switch. minimize the metal trace area connected to these pins to reduce emi. pgnd,gnd: power ground and signal ground for the ic. the package has an exposed pad underneath the ic which is the best path for heat out of the package. the pin should be soldered to a continuous copper ground plane under the device to reduce die temperature and increase the power capability of the LT8362 . connect power ground components to the exposed pad copper exiting near the en/uvlo and sw pins. connect signal ground components to the exposed pad copper exiting near the v c and fbx pins. LT8362 8362fa
8 for more information www.linear.com/LT8362 block diagram 8362 bd ? + ? + a7 ? + ? + a6 ? + ? + ? + a2 ? + r4 opt v bias (+) v bias ? 2v(?) 4.4v(+) 4.0v(?) 3.2v regulator sw oscillator a6 error amp select frequency foldback intv cc uvlo switch logic burst detect slope driver m1 intv cc t j > 170c 1.68v(+) 1.6v(?) internal reference uvlo c in sw bias r3 opt v in c out c vcc d l v out uvlo rt sync/mode over- current a7 overcurrent ? + a1 pgnd/gnd error amp error amp slope 1.6v fbx v out r2 r1 ?0.8v max i limit 1.5 max i limit r sense pwm comparator q1 r5 a3 a5 i ss 2a m2 ss c ss r c v c c c en/uvlo v in uvlo a4 LT8362 8362fa
9 for more information www.linear.com/LT8362 operation the LT8362 uses a fixed frequency, current mode con - trol scheme to provide excellent line and load regula- tion. operation can be best understood by referring to the block diagram. an oscillator (with frequency programmed by a resistor at the rt pin) turns on the internal power switch at the beginning of each clock cycle. current in the inductor then increases until the current comparator trips and turns off the power switch. the peak inductor current at which the switch turns off is controlled by the voltage on the v c pin. the error amplifier servos the v c pin by comparing the voltage on the fbx pin with an internal reference voltage (1.60v or C 0.80v , depending on the chosen topology). when the load current increases it causes a reduction in the fbx pin voltage relative to the internal reference. this causes the error amplifier to increase the v c pin voltage until the new load current is satisfied. in this manner, the error amplifier sets the correct peak switch current level to keep the output in regulation. the LT8362 is capable of generating either a positive or negative output voltage with a single fbx pin. it can be configured as a boost or sepic converter to generate a positive output voltage, or as an inverting converter to generate a negative output voltage. when configured as a boost converter, as shown in the block diagram, the fbx pin is pulled up to the internal bias voltage of 1.60v by a voltage divider (r1 and r2) connected from v out to gnd. amplifier a2 becomes inactive and amplifier a1 performs (inverting) amplification from fbx to v c . when the LT8362 is in an inverting configuration, the fbx pin is pulled down to C0.80v by a voltage divider from v out to gnd. amplifier a1 becomes inactive and amplifier a2 performs (non-inverting) amplification from fbx to v c . if the en/uvlo pin voltage is below 1.6v , the LT8362 enters undervoltage lockout (uvlo), and stops switching. when the en/uvlo pin voltage is above 1.68v (typical), the LT8362 resumes switching. if the en/uvlo pin volt - age is below 0.2v, the LT8362 draws less than 1a from v in . for the sync/mode pin tied to ground or < 0.14v , the LT8362 will enter low output ripple burst mode opera- tion for ultra low quiescent current during light loads to maintain high efficiency. for a 100k resistor from sync/ mode pin to gnd, the LT8362 uses burst mode opera - tion for improved efficiency at light loads but seamlessly transitions to spread-spectrum modulation of switch - ing frequency for low emi at heavy loads. for the sync/ mode pin floating (left open), the LT8362 uses pulse- skipping mode, at the expense of hundreds of microamps, to maintain output voltage regulation at light loads by skipping switch pulses. for the sync/mode pin tied to intv cc or >1.7v , the LT8362 uses pulse-skipping mode and performs spread-spectrum modulation of switching frequency. for the sync/mode pin driven by an external clock, the converter switching frequency is synchronized to that clock and pulse-skipping mode is also enabled. see the pin functions section for sync/mode pin. the LT8362 includes a bias pin to improve efficiency across all loads. the LT8362 intelligently chooses between the v in and bias pins to supply the intv cc for best efficiency. the intv cc supply current can be drawn from the bias pin instead of the v in pin for 4.4v bias v in . protection features ensure the immediate disable of switching and reset of the ss pin for any of the following faults: internal reference uvlo, intv cc uvlo, switch cur - rent > 1.5 maximum limit, en/uvlo < 1.6v or junction temperature > 170c. LT8362 8362fa
10 for more information www.linear.com/LT8362 applications information figure 1. burst frequency vs load current achieving ultralow quiescent current to enhance efficiency at light loads the LT8362 uses a low ripple burst mode architecture. this keeps the out - put capacitor charged to the desired output voltage while minimizing the input quiescent current and output ripple. in burst mode operation, the LT8362 delivers single small pulses of current to the output capacitor followed by sleep periods where the output power is supplied by the output capacitor. while in sleep mode, the LT8362 consumes only 9a. as the output load decreases, the frequency of single cur - rent pulses decreases (see figure 1) and the percentage of time the LT8362 is in sleep mode increases, resulting in much higher light load efficiency than for typical convert - ers. to optimize the quiescent current performance at light loads, the current in the feedback resistor divider must be minimized as it appears to the output as load current. in addition, all possible leakage currents from the output should also be minimized as they all add to the equiva - lent output load. the largest contributor to leakage current can be due to the reverse biased leakage of the schottky diode (see diode selection in the applications information section). while in burst mode operation, the current limit of the switch is approximately 500ma resulting in the output voltage ripple shown in figure 2. increasing the output capacitance will decrease the output ripple proportionally. as the output load ramps upward from zero the switching frequency will increase but only up to the fixed frequency figure 2. burst mode operation defined by the resistor at the rt pin as shown in figure?1. the output load at which the LT8362 reaches the fixed frequency varies based on input voltage, output voltage, and inductor choice. programming input turn-on and turn-off thresholds with en/uvlo pin the en/uvlo pin voltage controls whether the LT8362 is enabled or is in a shutdown state. a 1.6v reference and a comparator a6 with built-in hysteresis (typical 80mv) allow the user to accurately program the system input voltage at which the ic turns on and off (see the block diagram). the typical input falling and rising threshold voltages can be calculated by the following equations: v in(falling,uvlo(?)) = 1.60 ? r3 + r4 r4 v in(rising, uvlo(+)) = 1.68 ? r3 + r4 r4 v in current is reduced below 1a when the en/uvlo pin voltage is less than 0.2v. the en/uvlo pin can be con - nected directly to the input supply v in for always-enabled operation. a logic input can also control the en/uvlo pin. when operating in burst mode operation for light load currents, the current through the r3 and r4 network can easily be greater than the supply current consumed by the LT8362. therefore, r3 and r4 should be large enough to minimize their effect on efficiency at light loads. LT8362 8362fa 0.5 1.0 1.5 2.0 2.5 switching frequency (mhz) 8362 f01 v in = 12v v out = 48v front page application load current (ma) 10s/div i l 500ma/div v out 10mv/div 8362 f02 0 10 20 30 40 50 0
11 for more information www.linear.com/LT8362 applications information intv cc regulator a low dropout (ldo) linear regulator, supplied from v in , produces a 3.2v supply at the intv cc pin. a minimum 1f low esr ceramic capacitor must be used to bypass the intv cc pin to ground to supply the high transient cur - rents required by the internal power mosfet gate driver. no additional components or loading is allowed on this pin. the intv cc rising threshold (to allow soft-start and switching) is typically 2.65v . the intv cc falling threshold (to stop switching and reset soft-start) is typically 2.5v . to improve efficiency across all loads, the majority of intv cc current can be drawn from the bias pin ( 4.4v bias v in ) instead of the v in pin. for sepic applications with v in often greater than v out , the bias pin can be directly connected to v out . if the bias pin is connected to a supply other than v out , be sure to bypass the pin with a local ceramic capacitor. programming switching frequency the LT8362 uses a constant frequency pwm architecture that can be programmed to switch from 300khz to 2mhz by using a resistor tied from the rt pin to ground. a table showing the necessary r t value for a desired switching frequency is in table 1. the r t resistor required for a desired switching frequency can be calculated using: r t = 51.2 f osc ? 5.6 where r t is in k and f osc is the desired switching fre - quency in mhz. table 1. sw frequency vs r t value f osc (mhz) r t (k) 0.3 165 0.45 107 0.75 63.4 1 45.3 1.5 28.7 2 20 synchronization and mode selection to select low ripple burst mode operation, for high effi - ciency at light loads, tie the sync/mode pin below 0.14v (this can be ground or a logic low output). to synchronize the LT8362 oscillator to an external fre - quency connect a square wave (with 20% to 80% duty cycle) to the sync pin. the square wave amplitude should have valleys that are below 0.4v and peaks above 1.7v (up to 6v). the LT8362 will not enter burst mode opera - tion at low output loads while synchronized to an external clock, but instead will pulse skip to maintain regulation. the LT8362 may be synchronized over a 300khz to 2mhz range. the r t resistor should be chosen to set the LT8362 switching frequency equal to or below the lowest synchro - nization input. for example, if the synchronization signal will be 500khz and higher, the r t should be selected for 500khz. for some applications it is desirable for the LT8362 to operate in pulse-skipping mode, offering two major differ - ences from burst mode operation. firstly, the clock stays awake at all times and all switching cycles are aligned to the clock. secondly, the full switching frequency is main - tained at lower output load than in burst mode operation. these two differences come at the expense of increased quiescent current. t o enable pulse-skipping mode, float the sync pin. to improve emi/emc, the LT8362 can provide spread spectrum frequency modulation (ssfm). this feature var - ies the clock with a triangle frequency modulation of 20%. for example, if the LT8362 's frequency was programmed to switch at 2mhz, spread spectrum mode will modulate the oscillator between 2mhz and 2.4mhz. the 20% modu - lation will occur at a frequency: f osc /256 where f osc is the switching frequency programmed using the rt pin. the LT8362 can also be configured to operate in pulse- skipping/ssfm mode by tying the sync/mode pin above 1.7v. the LT8362 can also be configured for burst mode operation at light loads (for improved efficiency) and ssfm at heavy loads (for low emi) by tying a 100k from the sync/mode pin to gnd. LT8362 8362fa
12 for more information www.linear.com/LT8362 duty cycle consideration the LT8362 minimum on-time, minimum off-time and switching frequency (f osc ) define the allowable minimum and maximum duty cycles of the converter (see minimum on-time, minimum off-time, and switching frequency in the electrical characteristics table). minimum allowable duty cycle = minimum on-time (max) ? f osc(max) maximum allowable duty cycle = 1 ? minimum off-time (max) ? f osc(max) the required switch duty cycle range for a boost converter operating in continuous conduction mode (ccm) can be calculated as: d min = 1 ? v in(max) v out + v d d max = 1 ? v in(min) v out + v d where v d is the diode forward voltage drop. if the above duty cycle calculations for a given application violate the minimum and/or maximum allowed duty cycles for the LT8362 , operation in discontinuous conduction mode?(dcm) might provide a solution. for the same v in and v out levels, operation in dcm does not demand as low a duty cycle as in ccm. dcm also allows higher duty cycle operation than ccm. the additional advantage of dcm is the removal of the limitations to inductor value and duty cycle required to avoid sub-harmonic oscilla - tions and the right half plane zero (rhpz). while dcm provides these benefits, the trade-off is higher inductor peak current, lower available output power and reduced efficiency. setting the output voltage the output voltage is programmed with a resistor divider from the output to the fbx pin. choose the resistor values for a positive output voltage according to: r1 = r2 ? v out 1.60v ? 1 ? ? ? ? ? ? choose the resistor values for a negative output voltage according to: r1 = r2 ? |v out | 0.80v ? 1 ? ? ? ? ? ? the locations of r1 and r2 are shown in the block diagram. 1% resistors are recommended to maintain output voltage accuracy. higher-value fbx divider resistors result in the lowest input quiescent current and highest light-load efficiency. fbx divider resistors r1 and r2 are usually in the range from 25k to 1m. soft-start the LT8362 contains several features to limit peak switch currents and output voltage (v out ) overshoot during start-up or recovery from a fault condition. the primary purpose of these features is to prevent damage to external components or the load. high peak switch currents during start-up may occur in switching regulators. since v out is far from its final value, the feedback loop is saturated and the regulator tries to charge the output capacitor as quickly as possible, resulting in large peak currents. a large surge current may cause inductor saturation or power switch failure. the LT8362 addresses this mechanism with a programma - ble soft-start function. as shown in the block diagram, the soft-start function controls the ramp of the power switch current by controlling the ramp of v c through q1. this allows the output capacitor to be charged gradually toward its final value while limiting the start-up peak currents. figure 3 shows the output voltage and supply current for the first page typical application. it can be seen that both the output voltage and supply current come up gradually. applications information LT8362 8362fa
13 for more information www.linear.com/LT8362 figure 3. soft-start waveforms applications information fault protection an inductor overcurrent fault ( > 3.75a ) and/or intv cc undervoltage (intv cc < 2.5v ) and/or thermal lockout (t j ? >? 170 c ) will immediately prevent switching, will reset the ss?pin and will pull down v c . once all faults are removed, the LT8362 will soft-start v c and hence inductor peak current. frequency foldback during start-up or fault conditions in which v out is very low, extremely small duty cycles may be required to main - tain control of inductor peak current. the minimum on- time limitation of the power switch might prevent these low duty cycles from being achievable. in this scenario inductor current rise will exceed inductor current fall during each cycle, causing inductor current to walk up beyond the switch current limit. the LT8362 provides protection from this by folding back switching frequency whenever fbx or ss pins are close to gnd (low v out levels or start-up). this frequency foldback provides a larger switch-off time, allowing inductor current to fall enough each cycle (see normalized switching frequency vs fbx voltage in the typical performance characteristics section). thermal lockout if the LT8362 die temperature reaches 170 c (typical), the part will stop switching and go into thermal lockout. when the die temperature has dropped by 5c (nominal), the part will resume switching with a soft-started inductor peak current. compensation loop compensation determines the stability and transient performance. the LT8362 uses current mode control to regulate the output which simplifies loop compensation. the optimum values depend on the converter topology, the component values and the operating conditions (including the input voltage, load current, etc.). to compensate the feedback loop of the LT8362 , a series resistor-capacitor network is usually connected from the v c pin to gnd. the block diagram shows the typical v c compensation network. for most applications, the capacitor should be in the range of 100pf to 10nf , and the resistor should be in the range of 5k to 100k. a small capacitor is often connected in parallel with the rc compensation network to attenuate the v c voltage ripple induced from the out- put voltage ripple through the internal error amplifier. the parallel capacitor usually ranges in value from 2.2pf to 22pf. a practical approach to designing the compensa - tion network is to start with one of the circuits in this data sheet that is similar to your application, and tune the com - pensation network to optimize the performance. stability should then be checked across all operating conditions, including load current, input voltage and temperature. application note 76 is a good reference. thermal considerations care should be taken in the layout of the pcb to ensure good heat sinking of the LT8362 . both packages have an exposed pad underneath the ic which is the best path for heat out of the package. the exposed pad should be soldered to a continuous copper ground plane under the device to reduce die temperature and increase the power capability of the LT8362 . the ground plane should be connected to large copper layers to spread heat dissi - pated by the LT8362. power dissipation within the LT8362 (p diss_LT8362 ) can be estimated by subtracting the induc - tor and schottky diode power losses from the total power losses calculated in an efficiency measurement. the junc- tion temperature of LT8362 can then be estimated by: t j (LT8362) = t a + ja ? p diss_LT8362 LT8362 8362fa 500s/div v out 20v/div i l 1a/div 8362 f03
14 for more information www.linear.com/LT8362 applications information application circuits the LT8362 can be configured for different topologies. the first topology to be analyzed will be the boost con - verter, followed by the sepic and inverting converters. boost converter : switch duty cycle the LT8362 can be configured as a boost converter for the applications where the converter output voltage is higher than the input voltage. remember that boost con - verters are not short-circuit protected. under a shorted output condition, the inductor current is limited only by the input supply capability. for applications requiring a step- up converter that is short-circuit protected, please refer to the applications information section covering sepic converters. the conversion ratio as a function of duty cycle is: v out v in = 1 1 ? d in continuous conduction mode (ccm). for a boost converter operating in ccm, the duty cycle of the main switch can be calculated based on the output voltage (v out ) and the input voltage (v in ). the maximum duty cycle (d max ) occurs when the converter has the minimum input voltage: d max = v out ? v in(min) v out discontinuous conduction mode (dcm) provides higher conversion ratios at a given frequency at the cost of reduced efficiencies, higher switching currents, and lower available output power. boost converter: maximum output current capability and inductor selection for the boost topology, the maximum average inductor current is: i l(max)(ave) = i o(max) ? 1 1 ? d max ? 1 where m (< 1.0) is the converter efficiency. due to the current limit of its internal power switch, the LT8362 should be used in a boost converter whose maxi - mum output current (i o(max) ) is: i o(max) v in(min) v out ? 2a ? 0.5 ? i sw ( ) ? minimum possible inductor value and switching frequency should also be considered since they will increase inductor ripple current ?i sw . the inductor ripple current ?i sw has a direct effect on the choice of the inductor value and the converter s maximum output current capability. choosing smaller values of ?i sw increases output current capability, but requires large inductances and reduces the current loop gain (the converter will approach voltage mode). accepting larger values of ?i sw provides fast transient response and allows the use of low inductances, but results in higher input current ripple and greater core losses, and reduces output current capability. it is recommended to choose a ?i sw of approximately 0.75a. given an operating input voltage range, and having cho - sen the operating frequency and ripple current in the inductor, the inductor value of the boost converter can be determined using the following equation: l = v in(min) i sw ? f osc ? d max the peak inductor current is the switch current limit (max - imum 3.1a ), and the rms inductor current is approxi - mately equal to i l(max)(ave) . choose an inductor that can handle at least 3.1a without sat - urating, and ensure that the inductor has a low dcr (copper- wire resistance) to minimize i 2 r power losses. note that in some applications, the current handling requirements of the inductor can be lower, such as in the sepic topology where each inductor only carries one-half of the total switch cur - rent. for better efficiency, use similar valued inductors with a larger volume. many different sizes and shapes are available from various manufacturers (see table 2). choose a core material that has low losses at the programmed switching LT8362 8362fa
15 for more information www.linear.com/LT8362 frequency, such as a ferrite core. the final value chosen for the inductor should not allow peak inductor currents to exceed 2a in steady state at maximum load. due to toler - ances, be sure to account for minimum possible inductance value, switching frequency and converter efficiency. for inductor current operation in ccm and duty cycles above 50%, the LT8362's internal slope compensa- tion prevents sub-harmonic oscillations provided the inductor value exceeds a minimum value given by : l > v in ?14 ?d 2 + 21?d ? 5 ( ) ? f osc ( ) ? 2 ?d ? 1 ( ) 1?d ( ) lower l values are allowed if the inductor current oper - ates in dcm or duty cycle operation is below 50%. table 2. inductor manufacturers sumida (847) 956-0666 www.sumida.com tdk (847) 803-6100 www.tdk.com murata (714) 852-2001 www.murata.com coilcraft (847) 639-6400 www.coilcraft.com wurth (605) 886-4385 www.we-online.com boost converter: input capacitor selection bypass the input of the LT8362 circuit with a ceramic capacitor of x7r or x5r type placed as close as pos - sible to the v in and gnd pins. y5v types have poor performance over temperature and applied voltage, and should not be used. a 4.7f to 10f ceramic capacitor is adequate to bypass the LT8362 and will easily handle the ripple current. if the input power source has high imped - ance, or there is significant inductance due to long wires or cables, additional bulk capacitance may be necessar y. this can be provided with a low performance electrolytic capacitor. a precaution regarding the ceramic input capacitor con - cerns the maximum input voltage rating of the LT8362. a ceramic input capacitor combined with trace or cable inductance forms a high quality (under damped) tank cir - cuit. if the LT8362 circuit is plugged into a live supply, the input voltage can ring to twice its nominal value, possibly exceeding the LT8362s voltage rating. this situation is easily avoided (see application note 88). boost converter: output capacitor selection low esr (equivalent series resistance) capacitors should be used at the output to minimize the output ripple volt - age. multilayer ceramic capacitors are an excellent choice, as they are small and have extremely low esr. use x5r or x7r types. this choice will provide low output ripple and good transient response. a 4.7f to 47f output capacitor is sufficient for most applications, but systems with very low output currents may need only a 1f or 2.2f out - put capacitor. solid tantalum or os-con capacitor can be used, but they will occupy more board area than a ceramic and will have a higher esr. always use a capacitor with a sufficient voltage rating. contributions of esr (equivalent series resistance), esl (equivalent series inductance) and the bulk capacitance must be considered when choosing the correct output capacitors for a given output ripple voltage. the effect of these three parameters (esr, esl and bulk c) on the out - put voltage ripple waveform for a typical boost converter is illustrated in figure 4. figure 4. the output ripple waveform of a boost converter v out (ac) t on v esr ringing due to total inductance (board + cap) v cout 8362 f04 t off applications information LT8362 8362fa
16 for more information www.linear.com/LT8362 the choice of component(s) begins with the maximum acceptable ripple voltage (expressed as a percentage of the output voltage), and how this ripple should be divided between the esr step ?v esr and the charging/discharg - ing ? v cout . for the purpose of simplicity, we will choose 2% for the maximum output ripple, to be divided equally between ?v esr and ?v cout . this percentage ripple will change, depending on the requirements of the application, and the following equations can easily be modified. for a 1% contribution to the total ripple voltage, the esr of the output capacitor can be determined using the following equation: esr cout 0.01 ? v out i d(peak) for the bulk c component, which also contributes 1% to the total ripple: c out i o(max) 0.01 ? v out ? f osc the output capacitor in a boost regulator experiences high rms ripple currents, as shown in figure 4. the rms ripple current rating of the output capacitor can be deter - mined using the following equation: i rms(cout) i o(max) ? d max 1 ? d max multiple capacitors are often paralleled to meet esr requirements. typically, once the esr requirement is sat - isfied, the capacitance is adequate for filtering and has the required rms current rating. additional ceramic capaci - tors in parallel are commonly used to reduce the effect of parasitic inductance in the output capacitor, which reduces high frequency switching noise on the converter output. ceramic capacitors ceramic capacitors are small, robust and have very low esr. however, ceramic capacitors can cause problems when used with the LT8362 due to their piezoelectric applications information nature. when in burst mode operation, the LT8362 s switching frequency depends on the load current, and at very light loads the LT8362 can excite the ceramic capacitor at audio frequencies, generating audible noise. since the LT8362 operates at a lower current limit during burst mode operation, the noise is typically very quiet to a casual ear. if this is unacceptable, use a high performance tantalum or electrolytic capacitor at the output. low noise ceramic capacitors are also available. table 3. ceramic capacitor manufacturers taiyo yuden (408) 573-4150 www.t-yuden.com avx (803) 448-9411 www.avxcorp.com murata (714) 852-2001 www.murata.com boost converter: diode selection a schottky diode is recommended for use with the LT8362. low leakage schottky diodes are necessary when low quiescent current is desired at low loads. the diode leak - age appears as an equivalent load at the output and should be minimized. choose schottky diodes with sufficient reverse voltage ratings for the target applications. table 4. recommended schottky diodes part number average forward current (a) reverse voltage (v) reverse current (a) manufacturer dfls260 2 60 20 diodes, inc. pmeg2020ej 2 20 100 nxp pmeg3020 epa 2 30 80 nxp boost converter: layout hints the high speed operation of the LT8362 demands careful attention to board layout. careless layout will result in per - formance degradation. figure 5 shows the recommended component placement for a boost converter. note the vias under the exposed pad. these should connect to a local ground plane for better thermal performance. LT8362 8362fa
17 for more information www.linear.com/LT8362 applications information sepic converter applications the LT8362 can be configured as a sepic (single-ended primary inductance converter), as shown in figure 6. this topology allows for the input to be higher, equal, or lower than the desired output voltage. the conversion ratio as a function of duty cycle is: v out + v d v in = d 1 ? d in continuous conduction mode (ccm). in a sepic converter, no dc path exists between the input and output. this is an advantage over the boost converter for applications requiring the output to be disconnected from the input source when the circuit is in shutdown. figure 5. suggested boost converter layout (a) msop (b) dfn 1 3 5 6 7 8 en v in intv cc nc bias v c 16 14 12 11 10 9 sw1 sw2 sync ss rt fbx pgnd gnd v out sw v out v out pgnd pgnd v in sw 8362 f05 sw en bias gnd v in v c intv cc sync ss rt fbx v in sw 10 9 8 7 6 1 2 3 4 5 v out figure 6. LT8362 configured in a sepic topology LT8362 8362fa LT8362 v in v cc int d1 c in c out c dc 8362 f06 l1 l2 v out v in sw fbx gnd en/uvlo
18 for more information www.linear.com/LT8362 applications information sepic converter: switch duty cycle and frequency for a sepic converter operating in ccm, the duty cycle of the main switch can be calculated based on the output voltage (v out ), the input voltage (v in ) and the diode for - ward voltage (v d ). the maximum duty cycle (d max ) occurs when the con - verter operates at the minimum input voltage: d max = v out + v d v in(min) + v out + v d conversely, the minimum duty cycle (d min ) occurs when the converter operates at the maximum input voltage: d min = v out + v d v in(max) + v out + v d be sure to check that d max and d min obey: d max < 1 ? minimum off-time (max) ? f osc(max) and d min > minimum on-time (max) ? f osc(max) where minimum off-time, minimum on-time and f osc are specified in the electrical characteristics table. sepic converter: the maximum output current capability and inductor selection as shown in figure 6, the sepic converter contains two inductors: l1 and l2. l1 and l2 can be independent, but can also be wound on the same core, since identical volt - ages are applied to l1 and l2 throughout the switching cycle. for the sepic topology, the current through l1 is the converter input current. based on the fact that, ideally, the output power is equal to the input power, the maximum average inductor currents of l1 and l2 are: i l1(max)(avg) = i in(max)(avg) = i o(max) ? d max 1 ? d max i l2(max)(avg) = i o(max) in a sepic converter, the switch current is equal to i l1 + i l2 when the power switch is on, therefore, the maximum average switch current is defined as: i sw(max)(avg) = i l1(max)(avg) + i l2(max)(avg) = i o(max) ? 1 1 ? d max and the peak switch current is: i sw(peak) = 1 + 2 ? ? ? ? ? ? ? i o(max) ? 1 1 ? d max the constant c in the preceding equations represents the percentage peak-to-peak ripple current in the switch, relative to i sw(max)(avg) , as shown in figure 7. then, the switch ripple current ?i sw can be calculated by: ? i sw = ? i sw(max)(avg) the inductor ripple currents ?i l1 and ?i l2 are identical: ? i l1 = ? i l2 = 0.5 ? ? i sw 8362 f07 ?i sw = ? ? i sw(max)(avg) i sw t dt s i sw(max)(avg) t s figure 7. the switch current waveform of the sepic converter the inductor ripple current has a direct effect on the choice of the inductor value. choosing smaller values of ?i l requires large inductances and reduces the current loop gain (the converter will approach voltage mode). accepting larger values of ?i l allows the use of low inductances, but results in higher input current ripple and greater core losses. it is recommended that c falls in the range of 0.5 to 0.8. LT8362 8362fa
19 for more information www.linear.com/LT8362 due to the current limit of its internal power switch, the LT8362 should be used in a sepic converter whose maxi - mum output current (i o(max) ) is: i o(max) < (1 ? d max ) ? (2a ? 0.5 ? ? i sw ) ? where ( < 1.0) is the converter efficiency. minimum possible inductor value and switching frequency should also be considered since they will increase inductor ripple current ?i sw . given an operating input voltage range, and having cho - sen ripple current in the inductor, the inductor value ( l1 and l2 are independent) of the sepic converter can be determined using the following equation: l1 = l2 = v in(min) 0.5 ? i sw ? f osc ? d max for most sepic applications, the equal inductor values will fall in the range of 2.2h to 100h. by making l1 = l2, and winding them on the same core, the value of inductance in the preceding equation is replaced by 2l, due to mutual inductance: l = v in(min) i sw ? f osc ? d max this maintains the same ripple current and energy storage in the inductors. the peak inductor currents are: i l1(peak) = i l1(max) + 0.5 ? ? i l1 i l2(peak) = i l2(max) + 0.5 ? ? i l2 the maximum rms inductor currents are approximately equal to the maximum average inductor currents. based on the preceding equations, the user should choose the inductors having sufficient saturation and rms cur - rent ratings. similar to boost converters, the sepic converter also needs slope compensation to prevent subharmonic oscillations while operating in ccm. the equation presented in the boost converter section defines the minimum inductance value to avoid sub-harmonic oscillations when coupled inductors are used. for uncoupled inductors, the minimum inductance requirement is doubled. sepic converter: output diode selection to maximize efficiency, a fast switching diode with a low forward drop and low reverse leakage is desirable. the average forward current in normal operation is equal to the output current. it is recommended that the peak repetitive reverse voltage rating v rrm is higher than v out + v in(max) by a safety margin (a 10v safety margin is usually sufficient). the power dissipated by the diode is: p d = i o(max) ? v d where v d is diode s forward voltage drop, and the diode junction temperature is: t j = t a + p d ? r ja the r ja used in this equation normally includes the r jc for the device, plus the thermal resistance from the board, to the ambient temperature in the enclosure. t j must not exceed the diode maximum junction temperature rating. sepic converter: output and input capacitor selection the selections of the output and input capacitors of the sepic converter are similar to those of the boost converter. applications information LT8362 8362fa
20 for more information www.linear.com/LT8362 applications information sepic converter: selecting the dc coupling capacitor the dc voltage rating of the dc coupling capacitor (c dc , as shown in figure 6) should be larger than the maximum input voltage: v cdc > v in(max) c dc has nearly a rectangular current waveform. during the switch off-time, the current through c dc is i in , while approx - imately Ci o flows during the on-time. the rms rating of the coupling capacitor is determined by the following equation: i rms(cdc) > i o(max) ? v out + v d v in(min) a low esr and esl, x5r or x7r ceramic capacitor works well for c dc . inverting converter applications the LT8362 can be configured as a dual-inductor invert - ing topology, as shown in figure 8. the v out to v in ratio is: v out ? v d v in = ? d 1 ? d in continuous conduction mode (ccm). inverting converter: switch duty cycle and frequency for an inverting converter operating in ccm, the duty cycle of the main switch can be calculated based on the negative output voltage (v out ) and the input voltage (v in ). the maximum duty cycle (d max ) occurs when the con - verter has the minimum input voltage: d max = v out ? v d v out ? v d ? v in(min) conversely, the minimum duty cycle (d min ) occurs when the converter operates at the maximum input voltage : d min = v out ? v d v out ? v d ? v in(max) be sure to check that d max and d min obey : d max < 1 ? minimum off-time (max) ? f osc(max) and d min > minimum on-time (max) ? f osc(max) where minimum off-time, minimum on-time and f osc are specified in the electrical characteristics table. inverting converter: inductor, output diode and input capacitor selections the selections of the inductor, output diode and input capacitor of an inverting converter are similar to those of the sepic converter. please refer to the corresponding sepic converter sections. figure 8. a simplified inverting converter c dc v in c in l1 d1 c out v out 8362 f10 + gnd LT8362 sw l2 + ? + ? + LT8362 8362fa
21 for more information www.linear.com/LT8362 applications information inverting converter: output capacitor selection the inverting converter requires much smaller output capacitors than those of the boost, flyback and sepic converters for similar output ripples. this is due to the fact that, in the inverting converter, the inductor l2 is in series with the output, and the ripple current flowing through the output capacitors are continuous. the output ripple voltage is produced by the ripple current of l2 flow - ing through the esr and bulk capacitance of the output capacitor: v out(p?p) = i l2 ? esr cout + 1 8 ? f osc ? c out ? ? ? ? ? ? after specifying the maximum output ripple, the user can select the output capacitors according to the preceding equation. the esr can be minimized by using high quality x5r or x7r dielectric ceramic capacitors. in many applications, ceramic capacitors are sufficient to limit the output volt - age ripple. the rms ripple current rating of the output capacitor needs to be greater than: i rms(cout) > 0.3 ? ? i l2 inverting converter: selecting the dc coupling capacitor the dc voltage rating of the dc coupling capacitor (c dc , as shown in figure 8) should be larger than the maximum input voltage minus the output voltage (negative voltage): v cdc > v in(max) + | v out | c dc has nearly a rectangular current waveform. during the switch off-time, the current through c dc is i in , while approximately Ci o flows during the on-time. the rms rating of the coupling capacitor is determined by the fol- lowing equation: i rms(cdc) > i o(max) ? d max 1 ? d max a low esr and esl, x5r or x7r ceramic capacitor works well for c dc . LT8362 8362fa
22 for more information www.linear.com/LT8362 typical applications 2mhz, 8v to 38v input, 48v boost converter 2mhz, 2.8v to 9v input, 12v boost converter efficiency efficiency LT8362 8362fa 1f v in = 9v load current (a) 0 0.2 0.4 0.6 0.8 1.0 1.2 50 r3 55 60 65 70 75 80 85 90 95 100 20k efficiency (%) 8362 ta03a v in = 12v v in = 24v load current (a) 0.001 0.01 0.1 1 50 c5 60 70 80 90 100 efficiency (%) 8362 ta02a 10nf c4 150pf r4 57.6k l1 d1 6.8h c3 4.7f 50v 1210 v out 48v 200ma at v in = 8v 320ma at v in = 12v 700ma at v in = 24v v in fbx bias gnd r1 1m en/uvlo LT8362 8362 ta02 v in 8v to 38v sw sync/mode intv cc r t ss c6 4.7pf v c d1: diodes inc. dfls260 l1: wurth elektronik lhmi 7050 74437349068 c3: murata grm32er71h475k d1 8362 ta03 r1 1m c1 4.7f r2 c1 154k c6 4.7pf c2 1f r3 20k c5 10nf c4 680pf 4.7f r4 36.5k l1 2.2h c3 10f v out 12v 300ma at v r2 in = 2.8v 600ma at v in = 5v 1.1a at v in = 9v v in bias fbx 34.8k gnd en/uvlo LT8362 v in 2.8v to 9v d1: nxp pmeg2020ej sw sync/mode intv c2 cc r t ss v c l1: wurth elektronik lhmi 7050 74437349022 c3: murata grm31cr71e106ka12l v in = 2.8v v in = 5v
23 for more information www.linear.com/LT8362 typical applications 2mhz, 4v to 19v input, 24v boost converter 2mhz, 2.8v to 6v input, 48v boost converter in dcm efficiency efficiency LT8362 8362fa 1f v in = 8v v in = 12v v in = 19v load current (a) 0 0.2 0.4 0.6 0.8 1.0 r3 1.2 1.4 50 55 60 65 70 75 80 85 20k 90 95 100 efficiency (%) 8362 ta04a v in = 2.8v v in = 5v v in = 6v load current (ma) 0 c5 5 10 15 20 25 30 0 10 20 30 10nf 40 50 60 70 80 90 100 efficiency (%) 8362 ta05a c4 330pf r4 36.5k l1 d1 4.7h c3 4.7f 1210 v out 24v 500ma at v in = 8v 700ma at v r1 1m in = 12v 1.24a at v in = 19v v in fbx bias gnd en/uvlo LT8362 c6 4.7pf v in 4v to 19v d1: nxp pmeg3020epa sw sync/mode intv cc r t c1 ss v c l1: wurth elektronik lhmi 7050 74437349047 c3: murata grm32er71h475k 8362 ta04 d1 r1 1m c6 4.7pf c1 4.7f 4.7f r2 34.8k c2 1f r3 20k c5 10nf c4 r2 680pf r4 36.5k l1 0.33h c3 1f 100v 1210 v out 48v 20ma at v in = 2.8v 71.5k 22ma at v in = 5v 25ma at v in = 6v v in fbx bias gnd 8362 ta05 en/uvlo LT8362 v in c2 2.8v to 6v d1: diodes inc. dfls260 sw sync/mode intv cc r t ss v c l1: wurth elektronik lhmi 7050 744373490033 c3: murata grm32cr72a105ka35l
24 for more information www.linear.com/LT8362 typical applications 2mhz, 2.8v to 28v input, 5v sepic converter efficiency 2mhz, 2.8v to 42v input, 12v sepic converter efficiency LT8362 8362fa 10nf c3: murata grm31cr71e106ka12l c6: murata grm31cr72a105k v out v in = 2.8v v in = 5v v in = 12v v in = 28v load current (a) 0 0.2 0.4 c4 0.6 0.8 1.0 1.2 1.4 50 55 60 65 70 680pf 75 80 85 90 95 100 efficiency (%) 8362 ta06a v in = 5v v in = 12v r4 v in = 24v v in = 42v load current (a) 0 0.2 0.4 0.6 0.8 1.0 1.2 36.5k 50 55 60 65 70 75 80 85 90 95 c3 22f 100 efficiency (%) 8362 ta07a l1 2.2h c6 1f d1 l2 2.2h r1 1m c7 4.7pf c1 4.7f v out 5v 500ma at v in = 2.8v 750ma at v in = 5v r2 1a at v in = 12v 1.2a at v in = 28v v in fbx bias gnd 8362 ta06 en/uvlo LT8362 v in 464k 2.8v to 28v d1: diodes inc. dfls260 sw sync/mode intv cc r t ss v c l1, l2: wurth elektronik we-dd smd 1260 744871220 c3: taiyo yuden tmk325b7226mmhp c6: murata grm31cr72a105k c2 v out d1 c1 4.7f r2 154k c2 1f r3 20k 1f c5 10nf c4 680pf r4 36.5k c3 10f l1 4.7h r3 c6 1f l2 4.7h r1 1m c7 4.7pf v out 12v 125ma at v in = 2.8v 460ma at v in = 5v 20k 760ma at v in = 12v 1a at v in = 24v 1a at v in = 42v v in fbx bias gnd 8362 ta07 en/uvlo LT8362 c5 v in 2.8v to 42v d1: diodes inc. dfls260 sw sync/mode intv cc r t ss v c l1, l2: wurth elektronik we-dd smd 1260 744871470
25 for more information www.linear.com/LT8362 typical applications 2mhz, 4.5v to 30v input, 24v sepic converter 2mhz, 2.8v to 28v input, C5v inverting converter efficiency efficiency LT8362 8362fa 10nf sync/mode intv cc r t ss v c l1, l2: wurth elektronik we-dd smd 1260 744871220 c3: taiyo yuden tmk325b7226mmhp c6: murata grm31cr72a105k c4 v in = 5v v in = 12v v in = 24v v in = 30v load current (a) 0 0.1 0.2 0.3 0.4 680pf 0.5 0.6 0.7 0.8 50 55 60 65 70 75 r4 80 85 90 95 100 efficiency (%) 8362 ta08a v in = 2.8v v in = 5v v in = 12v 36.5k v in = 28v load current (a) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 l1 50 55 60 65 70 75 80 85 90 95 6.8h 100 efficiency (%) 8362 ta09a c6 1f l2 d1 6.8h r1 1m c7 4.7pf c3 10f c1 4.7f v out 24v 260ma at v in = 5v 700ma at v in = 24v r2 500ma at v in = 12v 700ma at v in = 30v v in fbx bias gnd 8362 ta08 en/uvlo LT8362 v in 71.5k 4.5v to 30v d1: diodes inc. dfls260 sw sync/mode intv cc r t ss v c l1, l2: wurth elektronik we-dd smd 744870006 c3: murata grm31cr71e106ka12l c6: murata grm31cr72a105k c2 v out d1 r2 191k c2 1f r3 20k c5 10nf 1f c4 680pf r4 36.5k c3 22f l1 2.2h c6 1f r3 l2 2.2h r1 1m c7 4.7pf c1 4.7f v out ?5v 500ma at v 20k in = 2.8v 750ma at v in = 5v 1a at v in = 12v 1.2a at v in = 28v v in fbx c5 bias gnd 8362 ta09 en/uvlo LT8362 v in 2.8v to 28v d1: diodes inc. dfls260 sw
26 for more information www.linear.com/LT8362 typical applications 2mhz, 2.8v to 42v input, C12v inverting converter 2mhz, 4.5v to 30v input, C24v inverting converter efficiency efficiency LT8362 8362fa 10nf 95 100 efficiency (%) 8362 ta11a d1 r2 34.8k c2 1f r3 c4 20k c5 10nf c4 680pf r4 36.5k c3 10f c7 4.7pf 680pf l1 6.8h c6 1f r1 1m l2 6.8h c1 4.7f r4 v out ?24v 260ma at v in = 5v 700ma at v in = 24v 700ma at v in = 30v 500ma at v in = 12v v in fbx bias gnd 36.5k 8362 ta11 en/uvlo LT8362 v in 4.5v to 30v d1: diodes inc. dfls260 sw sync/mode intv cc r t c3 ss v c l1, l2: wurth elektronik we-dd smd 1280 744870006 c3: murata grm31cr71e106ka12l c6: murata grm31cr72a105k 10f c7 4.7pf l1 4.7h d1 c6 1f r1 1m l2 4.7h c1 4.7f v out ?12v r2 125ma at v in = 2.8v 760ma at v in = 12v 1a at v in = 24v 1a at v in = 42v 460ma at v in = 5v v in fbx bias gnd 8362 ta10 en/uvlo 71.5k LT8362 v in 2.8v to 42v d1: diodes inc. dfls260 sw sync/mode intv cc r t ss v c c2 l1, l2: wurth elektronik we-dd smd 1260 744871470 c3: murata grm31cr71e106ka12l c6: murata grm31cr72a105k v in = 5v v in = 12v v in = 24v v in = 42v load current (a) 0 0.2 0.4 1f 0.6 0.8 1.0 1.2 50 55 60 65 70 75 r3 80 85 90 95 100 efficiency (%) 8362 ta10a v in = 5v v in = 12v v in = 24v 20k v in = 30v load current (a) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 c5 0.8 50 55 60 65 70 75 80 85 90
27 for more information www.linear.com/LT8362 typical applications conducted emi performance (cispr25 class 5 peak) conducted emi performance (cispr25 class 5 average) radiated emi performance (cispr25 class 5 peak) radiated emi performance (cispr25 class 5 average) low i q , low emi, 2mhz, 48v output boost converter with ssfm LT8362 8362fa 20k LT8362 2mhz f sw average emi frequency (mhz) 0 3 6 9 12 15 18 21 c5 24 27 30 ?20 ?10 0 10 20 30 40 10nf 50 60 70 80 amplitude (dbv) 8362 ta12b 12v input to 48v output at 300ma, f sw = 2mhz class 5 peak limit LT8362 2mhz f sw peak emi frequency (mhz) c4 0 100 200 300 400 500 600 700 800 900 1nf 1000 ?20 ?10 0 10 20 30 40 50 60 r4 amplitude (dbv/m) 8362 ta12c 12v input to 48v output at 300ma, f sw = 2mhz class 5 average limit LT8362 2mhz f sw average emi frequency (mhz) 0 100 200 300 22.1k 400 500 600 700 800 900 1000 ?20 ?10 0 l1 10 20 30 40 50 60 amplitude (dbv/m) 8362 ta12d 6.8h c3 d1 0.1f fb2 c7 0.1f r5 100k c8 4.7f c9 10f c1 r1 c11 4.7pf 1m v out 48v v in fbx bias gnd en/uvlo 10f LT8362 v in d1: diodes inc. dfls260 sw sync/mode intv cc r t ss v c l1: wurth elektronik lhmi 74437324068 l2: wurth elektronik 74479876147 fb1: wurth elektronik 742792040 c6: 50ce33pcs r2 input emi filter l2 0.47h output emi filter 50v 1206 c6 + 33f 100v 0402 100v 34.8k 0402 8362 ta12 50v 1210 50v 1206 8v to 38v 300ma at v in = 12v 700ma at v in = 24v c10 0.1f x2 100v 0402 c2 12v input to 48v output at 300ma, f sw = 2mhz class 5 peak limit LT8362 2mhz f sw peak emi frequency (mhz) 0 3 6 9 12 15 1f 18 21 24 27 30 ?20 ?10 0 10 20 r3 30 40 50 60 70 80 amplitude (dbv) 8362 ta12a 12v input to 48v output at 300ma, f sw = 2mhz class 5 average limit
28 for more information www.linear.com/LT8362 typical applications conducted emi performance (cispr25 class 5 peak) conducted emi performance (cispr25 class 5 average) radiated emi performance (cispr25 class 5 peak) radiated emi performance (cispr25 class 5 average) low i q , low emi, 400khz, 48v boost converter with ssfm LT8362 8362fa c2 3 6 9 12 15 18 21 24 27 30 1f ?20 ?10 0 10 20 30 40 50 60 70 r3 80 amplitude (dbv) 8362 ta13b 12v input to 48v output at 300ma, f sw = 400khz class 5 peak limit LT8362 400khz f sw peak emi frequency (mhz) 0 100 200 121k 300 400 500 600 700 800 900 1000 ?20 ?10 c5 0 10 20 30 40 50 60 amplitude (dbv/m) 8362 ta13c 12v input to 48v output at 300ma, f sw = 400khz 10nf class 5 average limit LT8362 400khz f sw average emi frequency (mhz) 0 100 200 300 400 500 600 c4 700 800 900 1000 ?20 ?10 0 10 20 30 1nf 40 50 60 amplitude (dbv/m) 8362 ta13d r4 22.1k d1 l1 22h c6 + 82f fb1 r5 100k c8 4.7f x4 50v 1206 c10 0.1f x2 100v 0402 r1 c11 4.7pf v out 48v v in fbx bias gnd en/uvlo LT8362 v in 1m d1: diodes inc. dfls260 sw sync/mode intv cc r t ss v c l1: wurth elektronik lhmi 74437346220 l2: wurth elektronik 74437324022 fb1: wurth elektronik 742792040 c6: panasonic 35svpf82m input emi filter l2 2.2h output emi filter c1 c3 1f 100v 0402 c7 0.1f 100v 0402 c9 10f 10f 50v 1210 50v 1206 4v to 35v 300ma at v in = 12v 700ma at v in = 24v 12v input to 48v output at 300ma, f sw = 400khz class 5 peak limit LT8362 400khz f sw peak emi r2 frequency (mhz) 0 3 6 9 12 15 18 21 24 34.8k 27 30 ?20 ?10 0 10 20 30 40 50 8362 ta13 60 70 80 amplitude (dbv) 8362 ta13a 12v input to 48v output at 300ma, f sw = 400khz class 5 average limit LT8362 400khz f sw average emi frequency (mhz) 0
29 for more information www.linear.com/LT8362 package description 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.125 typ 2.38 0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dd) dfn rev c 0310 0.25 0.05 2.38 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.50 bsc 0.70 0.05 3.55 0.05 package outline 0.25 0.05 0.50 bsc dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699 rev c) pin 1 notch r = 0.20 or 0.35 45 chamfer please refer to http://www.linear.com/product/LT8362#packaging for the most recent package drawings. LT8362 8362fa
30 for more information www.linear.com/LT8362 package description msop (mse16(12)) 0213 rev d 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ?0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 1.0 (.039) bsc 1.0 (.039) bsc 16 16 14 121110 1 3 5 6 7 8 9 9 1 8 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 6. exposed pad dimension does include mold flash. mold flash on e-pad shall not exceed 0.254mm (.010") per side. 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.10 (.201) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc bottom view of exposed pad option 2.845 0.102 (.112 .004) 2.845 0.102 (.112 .004) 4.039 0.102 (.159 .004) (note 3) 1.651 0.102 (.065 .004) 1.651 0.102 (.065 .004) 0.1016 0.0508 (.004 .002) 3.00 0.102 (.118 .004) (note 4) 0.280 0.076 (.011 .003) ref 4.90 0.152 (.193 .006) detail ?b? detail ?b? corner tail is part of the leadframe feature. for reference only no measurement purpose 0.12 ref 0.35 ref mse package variation: mse16 (12) 16-lead plastic msop with 4 pins removed exposed die pad (reference ltc dwg # 05-08-1871 rev d) please refer to http://www.linear.com/product/LT8362#packaging for the most recent package drawings. LT8362 8362fa
31 for more information www.linear.com/LT8362 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. revision history rev date description page number a 12/17 removed lead temperature line from absolute maximum ratings corrected electrical characteristics table ssfm maximum frequency deviation condition corrected f sync /f osc units corrected soft-start charge current condition to 0.5v inverting converter section: added, + |v out | to equation added efficiency graph to 48v boost converter circuit removed 200ma output current line from schematic corrected conducted emi y axis units on both plots removed 100ma and 200ma output current lines from schematic edited circuit: added lower fb resistor, shorted bias pin to gnd corrected conducted emi y axis units on both plots 2 3 3 4 21 22 27 27 28 28 28 LT8362 8362fa
32 ? analog devices, inc. 2017 lt 1217 rev a ? printed in usa www.linear.com/LT8362 related parts typical application part number description comments lt8300 100v in micropower isolated flyback converter with 150v/260ma switch v in = 6v to 100v, low i q monolithic no-opto flyback, 5-lead tsot - 23 lt8330 60v, 1a, low i q boost/sepic/inverting 2mhz converter v in = 3v to 40v, v out(max) = 60v, i q = 6a (burst mode operation), 6-lead tsot-23, 3mm 2mm dfn packages lt8331 low i q boost/sepic/flyback/inverting converter with 140v/0.5a switch v in = 4.5v to 100v, v out(max) =140v, i q = 6a (burst mode operation), msop-16(12)e lt8335 28v, 2a, low iq boost/sepic/inverting 2mhz converter v in = 3v to 25v, v out(max) = 25v, i q = 6a (burst mode operation), 3mm 2mm dfn package lt8494 70v, 2a boost/sepic 1.5mhz high efficiency step-up dc/dc converter v in = 1v to 60v (2.5v to 32v start-up), v out(max) = 70v, i q = 3a (burst mode operation), i sd = <1a, 20-lead tssop lt8570/lt8570-1 65v, 500ma/250ma boost/inverting dc/dc converter v in(min) = 2.55v, v in(max) = 40v, v out(max) = 60v, i q = 1.2ma, i sd = <1ma, 3mm 3mm dfn-8, msop-8e lt8580 1a (i sw ), 65v, 1.5mhz, high efficiency step-up dc/dc converter v in : 2.55v to 40v, v out(max) = 65v, i q = 1.2ma, i sd = <1a, 3mm 3mm dfn-8, msop-8e 2mhz, low-i q automotive pre-boost application line transient response (pass-through to boosting) LT8362 8362fa c2 1f r3 20k c5 10nf c4 150pf r4 57.6k d1 l1 1.5h c3 22f c6 4.7pf v out 8v (while boosting) 500ma at v in = 2.8v v in r1 fbx bias gnd en/uvlo LT8362 v in 2.8v to 20v d1: nxp pmeg2020ej l1: wurth elektronik lhmi 7050 74437349015 c3: taiyo yuden tmk325b7226mmhp 1m sw sync/mode intv cc r t ss v c v in = 14v to 3v (20v/ms) v out = 8v, i out = 0.5a 100s/div v out c1 5v/div v in 5v/div 8362 ta14a 4.7f r2 250k 8362 ta14

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