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general description the MAXQ3181 is a dedicated electricity measurementfront-end that collects and calculates polyphase volt- age, current, active power and energy, and many other metering parameters of a polyphase load. the comput- ed results can be retrieved by an external master through the on-chip serial peripheral interface (spi?) bus. this bus is also used by the external master to configure the operation of the MAXQ3181 and monitor the status of operations. the MAXQ3181 performs voltage and current measure- ments using an integrated adc that can measure up to seven external differential signal pairs. an eighth differ- ential signal pair is used to measure the die tempera- ture. an internal amplifier automatically adjusts the current channel gain to compensate for low-current channel-signal levels. applications 3-phase active energy electricity meters features ? compatible with 3-phase/3-wire, 3-phase/4-wire,and other 3-phase services ? 0.1% active power and energy linearity error ? 0.5% apparent power and energy linearity error ? 0.5% linearity errors for rms voltage and rmscurrent ? neutral line current measurement ? line frequency (hz) ? power factors ? phase sequence indication ? phase voltage absence detection ? programmable pulse width ? programmable no-load current threshold ? programmable meter constant ? programmable thresholds for undervoltage andovervoltage detection ? programmable threshold for overcurrent detection ? amp-hours in absence of voltage signals ? on-chip digital temperature sensor ? precision internal voltage reference 2.048v(30ppm/? typical), also supports an external voltage reference ? active power and energy of each phase andcombined 3-phase (kwh), positive and negative ? apparent power and energy of each phase andcombined 3-phase ? supports software meter calibration ? up to 3-point multipoint calibration tocompensate for transducer nonlinearity ? power-fail detection ? bidirectional reset input/output ? spi-compatible serial interface with interruptrequest ( irq ) output ? single 3.3v supply, low power (35mw typical) MAXQ3181 low-power, active energy, polyphase afe ________________________________________________________________ maxim integrated products 1 19-4668; rev 1; 12/09 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. note: some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of any device may be simultaneously available through various sales channels. for information about device errata, go to: www.maxim-ic.com/errata . maxq is a registered trademark of maxim integrated products, inc. spi is a trademark of motorola, inc. ordering information + denotes a lead(pb)-free/rohs-compliant package. part temp range pin-package MAXQ3181-ran+ -40 c to +85 c 28 tssop pin configuration and typical application circuit appear at end of data sheet. downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe 2 _______________________________________________________________________________________ absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 metering specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 spi slave mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 analog front-end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 digital signal processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 precision pulse generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 spi peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 power-supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 external high-frequency crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 external high-frequency clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 internal rc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 master communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 spi communications rate and format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 spi communications protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 host software design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 ram-based registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 general operating registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 global status register (status) (0x000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 operating mode register 0 (opmode0) (0x001) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 operating mode register 1 (opmode1) (0x002) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 operating mode register 2 (opmode2) (0x003) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 table of contents downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe _______________________________________________________________________________________ 3 global interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 interrupt request flag register (irq_flag) (0x004) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 interrupt mask register (irq_mask) (0x006) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 meter pulse configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 pulse configurationcfp output (plscfg1) (0x01e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 cfp pulse width (pls1_wd) (0x020) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 cfp pulse threshold (thr1) (0x022) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 calibration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 current gain, phase x = a/b/c/n (x.i_gain) (a: 0x130, b: 0x21c, c: 0x308, n: 0x12e) . . . . . . . . . . . . . . . . . . .34 voltage gain, phase x = a/b/c (x.v_gain) (a: 0x132, b: 0x21e, c: 0x30a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 energy gain, phase x = a/b/c (x.e_gain) (a: 0x134, b: 0x220, c: 0x30c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 phase-angle compensation, high range, phase x = a/b/c (x.pa0) (a: 0x13e, b: 0x22a, c: 0x316) . . . . . . . . .35 phase-angle compensation, medium range, phase x = a/b/c (x.pa1) (a: 0x140, b: 0x22c, c: 0x318) . . . . . .36 phase-angle compensation, low range, phase x = a/b/c (x.pa2) (a: 0x142, b: 0x22e, c: 0x31a) . . . . . . . . .36 limit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 overcurrent level (oclvl) (0x044) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 overvoltage level (ovlvl) (0x046) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 undervoltage level (uvlvl) (0x048) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 no-load level (noload) (0x04a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 phase status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 interrupt flags, phase x = a/b/c (x.flags) (a: 0x144, b: 0x230, c: 0x31c) . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 interrupt mask, phase x = a/b/c (x.mask) (a: 0x145, b: 0x231, c: 0x31d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 energy overflow flags, phase x = a/b/c (x.eover) (a: 0x146, b: 0x232, c: 0x31e) . . . . . . . . . . . . . . . . . . . . .39 measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 line frequency (linefr) (0x062) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 power factor, phase x = a/b/c (x.pf) (a: 0x1c6, b: 0x2b2, c: 0x39e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 rms voltage, phase x = a/b/c (x.vrms) (a: 0x1c8, b: 0x2b4, c: 0x3a0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 rms current, phase x = a/b/c (x.irms) (a: 0x1cc, b: 0x2b8, c: 0x3a4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 energy, real positive, phase x = a/b/c (x.eapos) (a: 0x1e8, b: 0x2d4, c: 0x3c0) . . . . . . . . . . . . . . . . . . . . . .41 energy, real negative, phase x = a/b/c (x.eaneg) (a: 0x1ec, b: 0x2d8, c: 0x3c4) . . . . . . . . . . . . . . . . . . . . .42 energy, apparent, phase x = a/b/c (x.es) (a: 0x1f8, b: 0x2e4, c: 0x3d0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 virtual register conversion coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 voltage units conversion coefficient (volt_cc) (0x014) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 current units conversion coefficient (amp_cc) (0x016) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 power units conversion coefficient (pwr_cc) (0x018) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 energy units conversion coefficient (enr_cc) (0x01a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 table of contents (continued) downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe 4 _______________________________________________________________________________________ virtual registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 real power, phase x = a/b/c/t (pwrp.x) (a: 0x801, b: 0x802, c: 0x804, t: 0x807) . . . . . . . . . . . . . . . . . . .46 apparent power, phase x = a/b/c/t (pwrs.x) (a: 0x821, b: 0x822, c: 0x824, t: 0x827) . . . . . . . . . . . . . . .46 voltage and current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 rms volts, phase x = a/b/c (v.x) (a: 0x831, b: 0x832, c: 0x834) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 rms amps, phase x = a/b/c/n (i.x) (a: 0x841, b: 0x842, c: 0x844, n: 0x840) . . . . . . . . . . . . . . . . . . . . . . .47 power factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 power factor (pf.t) (0x867) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 real energy, phase a/b/c/t (enrp.x) (a: 0x8c1, b: 0x8c2, c: 0x8c4, t: 0x8c7) . . . . . . . . . . . . . . . . . . . . .48 apparent energy, phase a/b/c/t (enrs.x) (a: 0x871, b: 0x872, c: 0x874, t: 0x877) . . . . . . . . . . . . . . . . . .48 theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 analog front-end operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 digital signal processing (dsp) terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 digital processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 per sample operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 per dsp cycle operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 energy accumulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 no-zero-crossing detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 phase sequence status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 power calculation (active and apparent) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 energy accumulation start delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 no-load feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 on demand calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 rms volts, rms amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 power factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 line frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 meter pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 generating pulses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 meter constant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 overvoltage and overcurrent detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 meter units to real units conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 units conversion examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 table of contents (continued) downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe _______________________________________________________________________________________ 5 calibration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 calibration overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 calibrating voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 calibrating current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 calibrating phase offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 interfacing the MAXQ3181 to external hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 connections to the power source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 sensor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 voltage sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 voltage-divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 voltage transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 current sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 current shunt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 current transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 advanced operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 modifying the adc operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 fine-tuning the dsp controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 fine-tuning the line frequency measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 low-power measurement mode (lowpm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 advanced calibrations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 calibrating current offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 calibrating linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 calibrating power/energy gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 multipoint phase offset calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 advanced register configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 analog scan configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 time slot assignmentcurrent channel x = a/b/c (scan_ix) (a: 0x008, b: 0x00c, c: 0x00a) . . . . . . . . . .65 time slot assignmentvoltage channel x = a/b/c (scan_vx) (a: 0x009, b: 0x00d, c: 0x00b) . . . . . . . . .66 time slot assignmentneutral current channel (scan_in) (0x00e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 time slot assignmenttemperature channel (scan_te) (0x00f) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 neutral current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 auxiliary channel configuration (aux_cfg) (0x010) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 dsp system configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 system clock frequency (sys_khz) (0x012) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 cycle count (cycnt) (0x01c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 number of scan frames per dsp cycle (ns) (0x040) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 table of contents (continued) downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe 6 _______________________________________________________________________________________ filter coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 line cycle noise rejection filter (rej_ns) (0x02c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 line cycle averaging filter (avg_ns) (0x02e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 meter measurement averaging filter (avg_c) (0x030) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 meter measurement highpass filter (hpf_c) (0x032) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 zero-cross lowpass filter (zc_lpf) (0x05a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 hardware mirror registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 adc configuration (r_acfg) (0x04c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 adc conversion rate (r_adcrate) (0x04e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 adc settling time (r_adcacq) (0x050) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 spi configuration (r_spicf) (0x052) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 timeouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 zero-crossing timeout (nzx_timo) (0x054) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 communications timeout (com_timo) (0x056) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 energy accumulation timeout (acc_timo) (0x058) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 phase-angle compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 phase offset current threshold 1 (i1thr) (0x05c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 phase offset current threshold 2 (i2thr) (0x05e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 miscellaneous gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 neutral current gain (n.i_gain) (0x12e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 linearity compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 linearity offset, high range, phase x = a/b/c (x.offs_hi) (a: 0x138, b: 0x224, c: 0x310) . . . . . . . . . . . . .77 linearity gain coefficient, low range, phase x = a/b/c (x.gain_lo) (a: 0x13a, b: 0x226, c: 0x312) . . . .77 linearity offset, low range, phase x = a/b/c (x.offs_lo) (a: 0x13c, b: 0x228, c: 0x314) . . . . . . . . . . . .78 measurementsram registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 on-demand rms result (n.irms) (0x11c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 energy accumulated in the last dsp cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 real energy, phase x = a/b/c (x.act) (a: 0x1d0, b: 0x2bc, c: 0x3a8) . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 apparent energy, phase x = a/b/c (x.app) (a: 0x1d8, b: 0x2c4, c: 0x3b0) . . . . . . . . . . . . . . . . . . . . . . . . .79 checksum (chksum) (0x060) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 neutral current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 rms current, neutral (i.n) (0x840) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 special commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 grounds and bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 specific design considerations for MAXQ3181-based systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 additional documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 table of contents (continued) downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe _______________________________________________________________________________________ 7 technical support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 table of contents (continued) figure 1. external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 2. brownout reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 3. simplified clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 4a. spi interface timing (ckpha = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 4b. spi interface timing (ckpha = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 5. read spi transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 6. write spi transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 7. flowchart for reading from MAXQ3181 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 8. flowchart for writing to MAXQ3181 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 9. per sample operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 figure 10. computation of rms values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 figure 11. phase compensation for energy calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 figure 12. apparent energy calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 figure 13. sample voltage input circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 figure 14. sample current input circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 figure 15. offset testing setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 figure 16. phase offset vs. input current calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 table 1. command format for spi register read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 table 2. command format for spi register write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 3. ram register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 table 4. virtual register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 table 5. meter unit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 table 6. virtual register coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 table 7. virtual registers that activate special commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 list of figures list of tables downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe 8 _______________________________________________________________________________________ stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on dvdd relative to dgnd .........-0.3v to +4.0v voltage range on avdd relative to agnd..........-0.3v to +4.0v voltage range on agnd relative to dgnd .........-0.3v to +0.3v voltage range on avdd relative to dvdd ..........-0.3v to +0.3v voltage range on any pin relative to dgnd except vxp, ixn pins..............................-0.3v to +4.0v voltage range on vxp, ixn relative to agnd ......-0.3v to +4.0v operating temperature range ...........................-40c to +85c junction temperature ......................................................+150c storage temperature range .............................-65c to +150c lead soldering temperature .............................refer to the ipc/ jedec j-std-020 specification. parameter conditions min typ max units active energy linearity error dr 1000:1 0.1 % apparent energy linearity error dr 1000:1 0.5 % rms voltage linearity error dr 20:1 0.5 % dr 500:1 1.0 rms current linearity error dr 20:1 0.5 % line frequency error 0.5 % power factor error 1.0 % electrical characteristics(v avdd = v dvdd = v rst to 3.6v, t a = -40c to +85c, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units power-supply specifications digital supply voltage v dvdd v rst 3.6 v power-fail interrupt trip point v pfw active mode, epwrf = 1 2.84 3.13 v power-fail reset trip point v rst active mode 2.70 2.99 v analog supply voltage v avdd v rst 3.6 v analog supply current i avdd f clk = 8mhz 0.9 1.8 ma digital supply current i dvdd f clk = 8mhz 8.5 13 ma low-power measurement mode current i lowpm lowpm = 1 (note 1) 4.2 ma stop-mode current 0.2 12 a digital i/o specifications input high voltage v ih 0.7 x v dvdd v input low voltage v il 0.3 x v dvdd v input hysteresis v ihys v dvdd = 3.3v 500 mv input leakage i l v in = dgnd or v dvdd , pullup off 0.01 1 a metering specifications(v avdd = v dvdd = v rst to 3.6v, current channel dynamic range 1000:1 at t a = +25c, unless otherwise noted.) (note 1) absolute maximum ratings downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe _______________________________________________________________________________________ 9 electrical characteristics (continued)(v avdd = v dvdd = v rst to 3.6v, t a = -40c to +85c, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units input low current i il v in = 0.4v, weak pullup on -50 a reset pullup resistance r reset 50 150 200 k i oh = -4ma v dvdd - 0.4 output high voltage (except reset ) v oh i oh = -6ma v dvdd - 0.5 v i ol = 4ma 0.4 output low voltage v ol i ol = 6ma 0.5 v system clock sources external clock input frequency 0 8.12 mhz external clock input duty cycle 45 55 % external hf crystal frequency fundamental mode 8.12 mhz xtal1, xtal2 internal load capacitance 16 pf internal rc oscillator frequency 7.4 7.6 8.6 mhz internal rc oscillator accuracy 2 % internal rc oscillator current 50 120 a internal rc oscillator startup delay (note 1) 0.45 s analog-to-digital converter input voltage range 0 v ref v common-mode bias v comm 1.14 v offset error 2 mv offset error drift 8 v/ c gain error (g = 1) 0.05 % spurious-free dynamic range sfdr 90 db total harmonic distortion thd 90 db input bandwidth (-3db) (note 1) 7 khz internal voltage reference temperature coefficient (note 1) 30 ppm/ c output voltage v ref 2.048 v internal temperature sensor temperature error (note 1) -4 +4 c spi slave-mode interface timing maximum spi clock rate (note 3) f sys /4 mhz sclk input pulse-width high t sch (note 3) 4 x t sys ns sclk input pulse-width low t scl (note 3) 4 x t sys ns downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe 10 ______________________________________________________________________________________ electrical characteristics (continued)(v avdd = v dvdd = v rst to 3.6v, t a = -40c to +85c, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units ssel low to first sclk edge (slave enable) t se (note 3) 4/t sys ns last sclk edge to ssel high (slave disable) t sd t sys + 5 ns mosi valid to sclk sample edge (mosi setup) t sis 5 ns sclk sample edge to mosi change (mosi hold) t sih t sys + 5 ns sclk shift edge to miso valid (miso hold) t sov 3t sys + 5 ns note 1: specifications guaranteed by design but not production tested. note 2: specifications to -40c are guaranteed by design and are not production tested. note 3: t sys = 1/f sys , where f sys is the system clock frequency, external or internal. spi slave mode timing ssel shift edge sample edge sclk data output data input t sd t se t sov t sih t sis t scl t sch downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe ______________________________________________________________________________________ 11 block diagram MAXQ3181 cfp, cfq counters i/o buffers i/o registers adc cfp v2p i0p v0p vcomm reset vref v1p i1p i2p inp spi i/o buffers i/o registers watchdog timer adc clock prescaler miso mosi sclk ssel xtal1 sysclk adcclk xtal2 i/o buffers i/o registers hf rc osc/8 hf xtal osc por/ brownout monitor 16 x 16 hw multiply 48-bit accumulate irq i2n vn i0n i1n temp sense ref adc control, electricity metering dsp, communications manager downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe 12 ______________________________________________________________________________________ pin description pin name function power pins 17, 22 dvdd digital supply voltage 25 avdd analog supply voltage 18 dgnd digital ground 9 agnd analog ground 23 vcomm voltage bias. this pin can be used to create an input common-mode dc offset for a dc channel conversions. 24 vref voltage reference. reference voltage for the adc. an external reference voltage can be con nected to this pin when extremely high accuracy is required. voltage and current pins 26, 3, 4 v0p, i0p, i0n phase a voltage and current analog inputs 27, 5, 6 v1p, i1p, i1n phase b voltage and current analog inputs 28, 7, 8 v2p, i2p, i2n phase c voltage and current analog inputs 1 vn analog input for common voltage 2 inp analog input for neutral current clock pins 10 xtal2 11 xtal1 high-frequency crystal input/output. when using an external hi gh-frequency crystal, the crystal oscillator circuit s hould be connected between xtal1 and xtal2. when using an externally d riven clock (extclk = 1), the clock should be input at xtal1, with xtal 2 left unconnected. 12 irq interrupt request output. this line is driven low by the device to i ndicate to the master that an unmasked interrupt has occurred. 13 ssel slave select input. this line is the active-low slave select input for the spi interface. 14 sclk slave clock input. this line is the clock input for the spi in terface. 15 mosi master out-slave in input. this line is used by the master to trans mit data to the slave (the MAXQ3181) over the spi interface. 16 miso master in-slave out output. this line is used by the MAXQ3181 (the sla ve) to transmit data back to the master over the spi interface. 19 cfp pulse output. configurable to represent energy or rms voltage or curr ent. 21 reset active-low reset input/output. an external master can reset the ma xq3181 by driving this pin low. this pin includes a weak pullup resistor to allow for a combinat ion of wired-or external reset sources. an rc circuit is not required for power-up, as this fu nction is provided internally. this pin also acts as a reset output when the source of the reset is internal to the device (power-fail, watchdog reset, etc.). in this case, the reset pin is held low by the device until it exits the reset state, the n the reset pin is released. no connection pins 20 n.c. no connection downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe ______________________________________________________________________________________ 13 detailed description the MAXQ3181 contains four major subsections: theanalog front-end, the digital signal processor, the preci- sion pulse generators, and an spi peripheral for com- munication to the host processor. analog front-end the analog front-end (afe) is an 8-channel analog-to-digital converter (adc). it operates autonomously in the standard configuration, assigning three channels to phase a, b, and c voltage; three channels to phase a, b, and c current; one channel to neutral current; and the last channel to a temperature sensor. each channel also contains a programmable-gain amplifier capable of providing a gain of 1, 2, 4, 8, 16, or 32 incoming signals. only the voltage channels permit gain scaling by the host processor. the MAXQ3181 dsp firmware automatically sets the gain on current channels. digital signal processor the dsp code is permanently embedded in maskedrom and accepts raw current and voltage samples for each of three phases and continuously calculates a host of values including rms volts, rms amps, real energy, apparent energy, and power factor. the MAXQ3181 dsp core processes incoming sam- ples from the analog front-end according to user con- figurations. the host sets these operating parameters by specifying addresses within the device ram space. when a calculation cycle is complete, the results are placed back into ram as well. thus, the dsp core uses the ram block as both its input (for operating parame- ters) and output (for calculation results) medium. see the spi peripheral section for how the host writes oper- ating parameters and reads results from the ram.the dsp also calculates certain values such as line fre- quency and active power only when demanded by the host. precision pulse generators the MAXQ3181 includes a precision pulse generatorthat generates a pulse whenever certain conditions are met. in the MAXQ3181, many meter quantities can be selected for conversion to meter pulses including absolute energy, net energy, voltage, and current. the pulse generator is an accumulator. on each dsp cycle, whatever quantity is being measuredreal ener- gy, current, or something elseis added to the pulse accumulator. the pulse accumulator is then tested to determine if the value in the accumulator is greater thanthe threshold. if it is greater, the threshold value is sub- tracted from the accumulator value and the meter pulse starts. spi peripheral the spi controller is a slave-only device that can reador write any location in the data ram. additionally, it can request data from on-demand registers. the MAXQ3181 implements a truly full-duplex commu- nication, rather than the pseudo half-duplex mode used by other spi peripherals. that is, each time a character is received by the MAXQ3181, a meaningful character is returned to the host. often, this is a protocol charac- ter. in this way, the host can be assured that the com- mand has been received and is valid. optional error checking can also be enabled to further guarantee proper operation. operating modes the MAXQ3181 has two basic modes of operation,each of which is described in the following sections. the initialization mode is the default mode upon power- up or following reset; entry to and exit from the other operating modes is only performed as a result of com- mands sent by the master. run mode this mode is the normal operating mode for theMAXQ3181. in this mode, the MAXQ3181 continuously executes the following operations: ? scans analog front-end channels and collects raw voltage and current samples. ? processes voltage and current samples through dsp filters as enabled and configured. ? calculates power, energy, and other required quanti- ties and stores these values in ram registers. ? responds to register write and read commands from the master. ? outputs power pulse on cfp as configured. ? drives irq when an interrupt condition has been detected and the interrupt is not masked. stop mode this mode places the MAXQ3181 into a power-savingstate where it consumes the least possible amount of current. in stop mode, all functions are suspended, including the adc and power and voltage measurement and processing. the MAXQ3181 does not respond to any commands from the master in this operating state. downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe 14 ______________________________________________________________________________________ entry into stop mode only occurs at the request of themaster. to place the MAXQ3181 into stop mode, the master must read the enter stop (0xc02) register. once this register has been read, the MAXQ3181 enters stop mode immediately, before the transmission of the final ack byte by the MAXQ3181. there are three possible ways to bring the MAXQ3181 back out of stop mode. ? power cycle. the MAXQ3181 automatically exits stop mode if a power-on reset occurs. following exitfrom stop mode, all registers are cleared back to their default states, and the MAXQ3181 transitions to initialization mode. ? external reset. the MAXQ3181 exits stop mode if an external reset is triggered by driving reset low. once the reset pin is released and allowed to return to a high state, the MAXQ3181 comes out ofreset and goes into initialization mode. all registers are cleared to their default states when exiting stop mode in this manner. ? external interrupt. driving the ssel pin low causes the MAXQ3181 to exit stop mode without undergoinga reset cycle. when exiting stop mode in this man- ner, all register and configuration settings are retained, and the MAXQ3181 automatically resumes electric-metering functions and sample processing. note that when the master is communicating with the MAXQ3181, the ssel line is normally driven low at the beginning of each spi command. this means that if themaster sends an spi command after the MAXQ3181 enters stop mode, the MAXQ3181 automatically exits stop mode. reset sources there are several different sources that can cause theMAXQ3181 to undergo a reset cycle. for any type of hardware reset, the reset pin is driven low when a reset occurs. external reset this hardware reset is initiated by an external source(such as the master controller or a manual pushbutton press) driving the reset pin on the MAXQ3181 low. the reset line must be held low for at least four cycles of the currently selected clock for the external reset totake effect. once the external reset takes effect, it remains in effect indefinitely as long as reset is held low. once the external reset has been released, theMAXQ3181 clears all registers to their default states and resumes execution in initialization mode. when an external reset occurs outside of stop mode, execution (in initialization mode) resumes after four cycles of the currently selected clock (external high-fre- quency crystal for run mode, 1mhz internal rc oscilla- tor for lowpm mode). as the MAXQ3181 enters initialization mode, the lowpm bit is always cleared clock resetreset sampling internal reset begin running in initialization mode figure 1. external reset downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe ______________________________________________________________________________________ 15 t por v rst1 brownout detection brownout detection (always enabled outside of stop mode) forces reset state. por = 1 brownout detection disabled during stop mode. no reset is generated. brownout detection disabled. por level causes reset. v por internal reset stop mode figure 2. brownout reset to 0, meaning that the MAXQ3181 always switches to the high-frequency clock before it begins accepting commands in initialization mode. when an external reset occurs from stop mode, execu- tion (in initialization mode) resumes after 128 cycles of the internal rc oscillator (or approximately 128s). power-on reset when the MAXQ3181 is first powered up, or when thepower supply, v dvdd , drops below the v rst power-fail trip point (outside of stop mode), the MAXQ3181 isheld in power-on reset. once the power supply rises above the v rst level, the power-on reset state is released and all registers are reset to their defaults andexecution resumes in initialization mode. the high-fre- quency external crystal (lowpm = 0) is always select- ed as the clock source following any power-on or brownout reset. in stop mode brownout detection is disabled, so a power-on reset does not occur until v dvdd drops to a lower level (v por ). from the masters perspective, power-on resets and brownout resets both cause theMAXQ3181 to reset in the same way. watchdog reset the MAXQ3181 includes a hardware watchdog timerthat is armed and periodically reset automatically dur- ing normal operation. under normal circumstances, the MAXQ3181 always resets the watchdog timer often enough to prevent it from expiring. however, if an inter- nal error of some kind causes the MAXQ3181 to lock up or enter an endless execution loop, the watchdog timer expires and triggers an automatic hardware reset. there is no register flag to indicate to the master that a watchdog reset has occurred, but the reset line strobes low briefly. the watchdog timer does not run during stop mode. software reset the master initiates a software reset by setting theswres (opmode0.3) bit to 1. when a software reset occurs, the MAXQ3181 clears all registers to their default states and returns to initialization mode, in the downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe 16 ______________________________________________________________________________________ same manner as if an external reset had taken place.unlike a hardware reset, however, a software reset does not cause the MAXQ3181 to drive the reset line low. power-supply monitoring in addition to the hardware reset provided by thepower-on reset and brownout reset circuits, the MAXQ3181 includes the capability to detect a low power supply on the dvdd pin and alert the master through the interrupt ( irq ) mechanism before a hard- ware reset occurs. this function, which is alwaysenabled outside of stop mode, causes the ram status register flag pwrf (irq_flag.0) to be set to 1 when- ever v dvdd drops below the v pfw trip point. once pwrf has been set to 1 by hardware, it can only becleared by the master (or by a system reset). whenever pwrf = 1, if the epwrf interrupt masking bit is also set to 1, the MAXQ3181 drives irq low to signal to the master that an interrupt condition (in this case, a power-fail warning) exists and requires attention. clock sources all operations including adc sampling and spi com-munications are synchronized to a single system clock. this clock can be obtained from any one of three selec- table sources, as shown in figure 3. external high-frequency crystal the default system clock source for the MAXQ3181 isan external high-frequency crystal oscillator circuit con- nected between xtal1 and xtal2. when clocked with an external crystal, a parallel-resonant, at-cut crystal oscillating in the fundamental mode is required. when using a high-frequency crystal, the fundamental oscillation mode of the crystal operates as inductive reactance in parallel resonance with external capaci- tors c1 and c2. the typical values of these external capacitors vary with the type of crystal being used and should be selected based on the load capacitance as suggested by the crystal manufacturer. since noise at xtal1 and xtal2 can adversely affect device timing, the crystal and capacitors should always be placed as close as possible to the xtal1 and xtal2 pins, with connection traces between the crystal and the device kept as short and direct as possible. in multiple layer boards, avoid running other high-speed digital signals underneath the crystal oscillator circuit if possible, as this could inject unwanted noise into the clock circuit. following power-up or any system reset, the high-fre- quency clock is automatically selected as the system clock source. however, before this clock can be used xtal in ring in system clock extclk stopm por clk enable watchdog reset ring count int/ext crystal startup timer watchdog timer 1mhz internal oscillator hf crystal glitch-free mux enable clock generation figure 3. simplified clock sources downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe ______________________________________________________________________________________ 17 for system execution, a crystal warmup timer mustcount 65,536 cycles of the high-frequency clock. while this warmup time period is in effect, execution contin- ues using the internal 1mhz oscillator. once the 65,536-cycle count completes (which requires approxi- mately 8.2ms at 8mhz), the device automatically switches over to the high-frequency clock. this crystal warmup timer is also activated upon exit from stop mode, since the high-frequency crystal oscillator is shut down during stop mode. external high-frequency clock instead of using a crystal oscillator to generate thehigh-frequency clock, it is also possible to input a high- frequency clock that has been generated by another source (such as a digital oscillator ic) directly into the xtal1 pin of the MAXQ3181. to use an external high-frequency clock as the system clock source, the xtal1 pin should be used as the clock input and the xtal2 pin should be left uncon- nected. the master should also shut down the internal crystal oscillator circuit by setting the extclk bit (opmode0.4) to 1. this bit is only cleared by the MAXQ3181 if a power-on or brownout reset occurs and is unaffected by other resets. when using an external high-frequency clock, the clock signal should be generated by a cmos driver. if the clock driver is a ttl gate, its output must be connected to dvdd through a pullup resistor to ensure that the correct logic levels are generated. to minimize system noise in the clock circuitry, the external clock source must meet the maximum rise and fall times and the minimum high and low times specified for the clock source in the electrical characteristics table. internal rc oscillator when the external high-frequency crystal is warmingup, or when the MAXQ3181 is placed into lowpm mode, the system clock is sourced from an internal rc oscillator. this internal oscillator is designed to provide the system approximately 1mhz, although the exact frequency varies over temperature and supply voltage. if no external crystal circuit or high-frequency clock will be used, the MAXQ3181 can be forced to operate infi- nitely from the internal oscillator by grounding xtal1. this ensures that the crystal warmup count never com- pletes, so the MAXQ3181 runs from the internal oscilla- tor in all active modes. master communications before the MAXQ3181 can begin performing electric-metering operations, the master must initialize a num- ber of configuration parameters. since the MAXQ3181 does not contain internal nonvolatile memory, these parameters (stored in internal registers) must be set by the master each time a power-up or reset cycle occurs, or each time a switch is made between lowpm mode and run mode. the external master communicates with the MAXQ3181 over a standard spi bus, using commands to read and write values to internal registers on the MAXQ3181. these registers include, among many other items: ? operating mode settings (stop mode, lowpm mode, external clock mode, etc.) ? status and interrupt flags (power-supply failure, over- current/overvoltage detection, etc.) ? masking control for interrupts to determine which conditions cause irq to be driven low ? configuration settings for analog channel scanning ? power pulse output configuration ? filter coefficients and configuration ? read-only registers containing accumulated power and energy data as the MAXQ3181 obtains voltage and current mea-surements in run mode or lowpm mode, it accumu- lates, filters, and performs a number of calculations on the collected data. many of these operations (including the various filtering stages) are configured by settings in registers written by the master. the output results can then be read by the master from various read-only registers in parallel with the ongoing measurement and processing operations. spi communications rate and format the spi is an interdevice bus protocol that providesfast, synchronous, full-duplex communications between a designated master device and one or more slave devices. in a MAXQ3181-based design, the MAXQ3181 would be the slave device connected to a designated master microcontroller. the external master initiates all communications trans- fers. the interrupt request line irq , while not technical- ly part of the spi bus interface, is also used formaster/slave communications because it allows the MAXQ3181 to notify the master that an interrupt condi- tion exists. some spi peripherals sacrifice speed in favor of simulating a half-duplex operation. this is not the case with the MAXQ3181; it is truly a full-duplex spi slave. downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe 18 ______________________________________________________________________________________ during an spi transfer, data is simultaneously transmit-ted and received over two serial data lines (miso and mosi) with respect to a single serial shift clock (sclk). the polarity and phase of the serial shift clock are the primary components in defining the spi data transfer format. the polarity of the serial clock corresponds to the idle logic state of the clock line and, therefore, also defines which clock edge is the active edge. to define a serial shift clock signal that idles in a logic-low state (active clock edge = rising), the clock polarity select (ckpol; r_spicf.0) bit should be configured to a 0, while setting ckpol = 1 causes the shift clock to idle in a logic-high state (active clock edge = falling). the phase of the serial clock selects which edge is used to sample the serial shift data. the clock phase select (ckpha; r_spicf.1) bit controls whether the active or inactive clock edge is used to latch the data. whenckpha is set to a logic 1, data is sampled on the inac- tive clock edge (clock returning to the idle state). when ckpha is set to a logic 0, data is sampled on the active clock edge (clock transition to the active state). together, the ckpol and ckpha bits allow four possi- ble spi data transfer formats. transfers over the spi interface always start with the most significant bit and end with the least significant bit. all spi data transfers to and from the MAXQ3181 are always 8 bits (one byte) in length. the MAXQ3181 spi interface does not support 16-bit character lengths. the default format (upon power-up or system reset) for the MAXQ3181 spi interface is represented in figure 4a (ckpol = 0; ckpha = 0). in this format, the sclk cycle # (for reference) sclk (ckpol = 0)sclk (ckpol = 1) mosi (from master) miso (from slave) ssel (to slave) 1 msb 6 5 4 3 2 1 lsb 2 3 4 5 6 7 8 6 msb *not defined but normally msb of character just received. 5 4 3 2 1 lsb * 1 msb 6 5 4 3 2 1 lsb 2 3 4 5 6 7 8 msb * *not defined but normally lsb of previously transmitted character. 6 5 4 3 2 1 lsb sclk cycle # (for reference) sclk (ckpol = 0)sclk (ckpol = 1) mosi (from master) miso (from slave) ssel (to slave) figure 4b. spi interface timing (ckpha = 1) figure 4a. spi interface timing (ckpha = 0) downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe ______________________________________________________________________________________ 19 spi clock idle state is low, and data is shifted in and outon the rising edge of sclk. once spi communication with the MAXQ3181 has been established, it is possible to alter the ckpol and ckpha format settings (as well as changing the ssel signal from active low to active high) if desired by writing to the r_spicf mirror registerand then reading from the special command register upd_sfr to copy the r_spicf value into the internal spi configuration register. whenever the active clock edge is used for sampling (ckpha = 0), the transfer cycle must be started with assertion of the ssel signal. this requirement means that the ssel signal be deasserted and reasserted between successive transfers. conversely, when theinactive edge is used for sampling (ckpha = 1), the ssel signal may remain low through successive transfers, allowing the active clock edge to signal thestart of a new transfer. the clock rate used for the spi interface is determined by the bus master, since the MAXQ3181 always oper- ates as an spi slave device. however, the maximum clock rate is limited by the system clock frequency of the MAXQ3181. for proper communications operation, the spi clock frequency used by the master must be less than or equal to the MAXQ3181s clock frequency divided by 4. for example, when the MAXQ3181 is run- ning at 8mhz, the spi clock frequency must be 2mhz or less. and if the MAXQ3181 is running in lowpm mode (or if the crystal is still warming up), the spi clock frequency must remain at 250khz or less for proper communications operation. in addition to limiting the overall spi bus clock rate, the master must also include a communications delay fol- lowing each byte transmit/receive cycle. this delay, which provides the MAXQ3181 with time to process an adc sample, should be a minimum of 400 system clocks. with default settings and running at 8mhz, this delay time is 50s. reducing the system clock frequen- cy to 1mhz (lowpm mode) would increase this delay period by a factor of 8 to 400s. spi communications protocol all transactions between the master and theMAXQ3181 consist of the master writing to or reading from one of the MAXQ3181s registers. to the host, the MAXQ3181 looks like a memory array that consists of both ram and rom. this is because the rom firmware in the MAXQ3181 reads its operational parameters from ram and places its results in ram. consequently, con- figuring a MAXQ3181 is as simple as performing a block write to its ram locations. some read-only memory locations in the MAXQ3181trigger actions within the device to calculate electricity- metering results on the fly. the specific function and purpose of ram and virtual rom locations are given in the register map. there are several different categories of internal registers on the MAXQ3181. ? ram registers. the values of these registers are stored in the internal ram of the MAXQ3181. somecan be read and written by the master, while others are read-only. ram registers are either 2 or 4 bytes long (16 or 32 bits), although in some registers not all the bits have defined values. read/write registers are generally either status/flag registers (which can be written by either the MAXQ3181 or the master), con- figuration registers (which are written by the master and read by the MAXQ3181 firmware), or data regis- ters (which are read-only and are written by the MAXQ3181 firmware and read by the master). ? virtual registers. these read-only registers are not stored in ram; instead, they contain values that arecalculated on the fly by the MAXQ3181 firmware when the master reads them. these registers are used by the master to obtain values such as phase a, b, and c active and apparent power; power fac- tor; and rms voltage and current, which are calculat- ed from currently collected data on an as-needed basis. most virtual registers are 8 bytes in length. ? hardware registers. these registers control core functions of the MAXQ3181 including the adc andthe spi slave bus controller. each of these registers (r_acfg, r_adcrate, r_adcacq, r_spicf, and opmode0 (bit 4, extclk only)) has a register loca- tion in ram that shadows the value of the hardware register. to read from a hardware register, the mas- ter must first read from the special command register upd_mir (a00h) to copy the values from the hard- ware registers to the mirror registers in ram, and then the mirror register in ram can be read. to write to a hardware register, the master reverses the process by writing to the mirror ram register and then reading from the special command register upd_sfr (900h) to copy the values from the mirror registers to the hardware registers. ? special command registers. these registers (upd_sfr and upd_mir) do not return meaningfuldata when read but instead trigger an operation. reading upd_sfr causes values to be copied from the mirror registers to hardware, and reading upd_mir causes values to be copied from the hard- ware to mirror registers. downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe 20 ______________________________________________________________________________________ every defined register on the MAXQ3181 has a 12-bitaddress (from 0 to 4095). this address is used when addressing the register for either a read or write opera- tion. addresses 0 to 1023 (000h to 3ffh) are used to address ram registers. registers with addresses from 1024 to 4095 (400h to fffh) are used for virtual regis- ters and special command registers. each command consists of a read/write command code, a data length (1, 2, 4, or 8 bytes), a 12-bit regis- ter address, and the specified number of data bytes fol- lowed optionally by a cyclic redundancy check (crc). since spi is a full-duplex interface, the master and slave must both transmit the same number of bytes dur- ing the command. when a multiple-byte register is read or written (2/4/8 byte length), the least significant byte is read or written first in the command. every transaction begins with the master sending 2 bytes that contain the command (read or write), the address to access, and the number of bytes to transfer. every spi peripheral must return 1 byte for every byte it receives. if the master is reading 1 or more bytes from the MAXQ3181, it must send dummy bytes during the cycles when it is receiving a multibyte response to arequest, meeting the send a byte to get a byte require- ment. but the MAXQ3181 could require time to calculate the result, and thus might not have it ready when the master sends the dummy byte. for this reason, the MAXQ3181 always sends zero or more bytes of a nak character (0x4e or ascii n) followed by an ack char- acter (0x41, or ascii a) before sending the data. if the master is writing 1 or more bytes, it sends the data to be written immediately after sending the com- mand. the MAXQ3181 returns ack (0x41) for each data byte. it then returns nak (0x4e) until the write cycle is complete, after which it returns a final ack. immediately after the final ack, the MAXQ3181 is ready to begin the next transaction; there is no need to wait for any other event. it is not even necessary to tog- gle ssel to begin the next transaction. the MAXQ3181 knows that the first transaction is over and is ready forthe next. if, for whatever reason, it is necessary to reset the com- munications between the host and the MAXQ3181 (for table 1. command format for spi register read byte transfers bit description 7:6 command code: 00 read 01 reserved 10 write 11 reserved 5:4 data length: 00 1 byte 01 2 bytes 10 4 bytes 11 8 bytes 1st byte master sends command; slave sends 0xc1 byte 3:0 msb portion of data address. 2nd byte master sends address; slave sends 0xc2 byte 7:0 lsb portion of data address. sync bytes master sends dummy; slave sends ack (0x41) or nack (0x4e) byte 7:0 master sends dummy byte; slave responds with nack if busy, or with ack when processing complete. master must receive ack, then receive data. 3rd byte (1st data byte) master sends dummy; slave sends data 7:0 data, lsb ... ... ... ... nth byte (last data byte) master sends dummy; slave sends data 7:0 data, msb (n + 1) byte master sends dummy; slave sends crc 7:0 optional crc downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe ______________________________________________________________________________________ 21 table 2. command format for spi register write byte transfers bit description 7:6 command code: 00 read 01 reserved 10 write 11 reserved 5:4 data length: 00 1 byte 01 2 bytes 10 4 bytes 11 8 bytes 1st byte master sends command; slave sends 0xc1 byte 3:0 msb portion of data address. 2nd byte master sends address; slave sends 0xc2 byte 7:0 lsb portion of data address. 3rd byte (1st data byte) master sends data; slave sends ack (0x41) 7:0 data, lsb ... ... ... ... nth byte (last data byte) master sends data; slave sends ack (0x41) 7:0 data, msb (n + 1) byte master sends crc; slave sends ack (0x41) 7:0 optional crc sync bytes master sends dummy; slave sends ack (0x41) or nack (0x4e) byte 7:0 master sends dummy byte; slave responds with nack if busy, or with ack when processing complete. master must receive ack before starting the next transaction. example, if synchronization is lost), the host only needsto wait for the spi to time out before restarting commu- nication from the first command byte. spi timeout count starts after receiving the first command byte from the master (after the 8th spi clock of the first byte). the count stops and clears after receiving the last byte of a transaction (after the 8th spi clock of the last byte). if the timeout count expires (exceeds com_timo) before the transaction completes, the MAXQ3181 aban- dons the unfinished transaction and resets the spi logic to be ready for the next transaction. the default spi timeout is 320ms. optionally, a crc byte can be appended to eachtransaction. for write commands, the crc byte is sent by the master, and for read commands the crc byte is sent by the MAXQ3181. the crc mode is enabled when the crcen bit is set to 1 in opmode1 register. otherwise, the MAXQ3181 assumes no crc byte is used. the 8-bit crc is calculated for all bytes in a transaction, from the first command byte sent by the master through the last data byte excluding sync bytes, using the polynomial p = x 8 + x 5 + x 4 + 1. if the trans- mitted crc byte does not match the calculated crcbyte (for a write command), the MAXQ3181 ignores the command. downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe 22 ______________________________________________________________________________________ the length of the transfer is defined by the first com-mand byte and the status of the crcen bit in the opmode1 register. there is no special synchronization mechanism provided in this simple protocol. therefore, the master is responsible for sending/receiving the cor- rect number of bytes. if the master mistakenly sends more bytes than are required by the current command, the extra bytes are either ignored (if the MAXQ3181 is busy processing the previous command) or are inter- preted as the beginning of a new command. if the mas- ter sends fewer bytes than are required by the current command, the MAXQ3181 waits for spi timeout, then drops the transaction and resets the communication channel. the duration of the timeout can be configured through the com_timo register. figures 5 and 6 show typical 2-byte reading and writing transfers (without crc byte). host software design individual message bytes sent through the spi areprocessed in a software routine contained in the rom firmware. for this reason, it is necessary to provide a delay between successive bytes. this byte spacing must be no less than 400 system clocks to ensure that the MAXQ3181 has a chance to read and process the byte before the arrival of the next one. it is strongly rec- ommended that crc be enabled for both read and write to achieve reliable communications. register set data and device command and control information arelocated in internal registers. registers range from 8 to 64 bits in length and are divided into ram-based regis- ters and virtual registers. the ram-based registers contain both operating parameters and measurement results. ssel sclkmosi miso reading data from MAXQ3181 through spi interface 00 01 address dummy dummy dummy dummy 0xc1 0xc2 nack (0x4e) data lsb data msb ack (0x41) ssel sclkmosi miso 10 01 address dummy dummy 0xc1 0xc2 ack (0x41) nack (0x4e) ack (0x41) ack (0x41) writing data to MAXQ3181 through spi interface data lsb data msb figure 6. write spi transfer figure 5. read spi transfer downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe ______________________________________________________________________________________ 23 read MAXQ3181 send command byte 1 get 0xc1?get 0xc2? exit spi timeout (320ms) delay > 400 sysclk send command byte 2 send 0x00 delay > 400 sysclk send 0x00 get data byte delay > 400 sysclk get 0x4e? get 0x41? done? n n n y n write MAXQ3181 send command byte 1 get 0xc1?get 0xc2? exit spi timeout (320ms) delay > 400 sysclk send command byte 2 send data byte delay > 400 sysclk send 0x00 delay > 400 sysclk get 0x4e? get 0x41? done? get 0x41? n n n n y n figure 8. flowchart for writing to MAXQ3181 figure 7. flowchart for reading from MAXQ3181 the virtual registers contain calculated values derivedfrom one or more real registers. they are calculated at the time they are requested, and thus can involve addi- tional time to return a value. most virtual registers are 8bytes in length and are delivered least significant byte first. downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe 24 ______________________________________________________________________________________ table 3. ram register map 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh eh fh 0x00 status op mode1 op mode2 op mode3 irq_flag irq_mask scan _ia scan _va scan _ic scan _vc scan _ib scan _vb scan _in scan _te 0x01 aux_cfg sys_khz volt_cc amp_cc pwr_cc enr_cc cycnt plscfg 1 0x02 pls1_wd thr1 rej_ns avg_ns 0x03 avg_c hpf_c 0x04 ns oclvl ovlvl uvlvl noload r_acfg r_adcrate 0x05 r_adcacq r_ spicf nzx_timo com_timo acc_timo zc_lpf i1thr i2thr 0 x 0 6 c h k s u m l i n e f r 0 x 1 1 n . i r m s 0 x 1 2 n . i _ g a i n phase a configuration and status registers 0x13 a.i_gain a.v_gain a.e_gain a.offs_hi a.gain_lo a.off s_lo a.pa0 0x14 a.pa1 a.pa2 a. flags a. mask a. eover phase b configuration and status registers 0 x 2 1 b . i _ g a i n b . v _ g a i n 0x22 b.e_gain b.offs_hi b.gain_lo b.offs_lo b.pa0 b.pa1 b.pa2 0x23 b. flags b. mask b. eover phase c configuration and status registers 0 x 3 0 c . i _ g a i n c . v _ g a i n c . e _ g a i n 0x31 c.offs_hi c.gain_lo c.offs_lo c.pa0 c.pa1 c.pa2 c. flags c. mask c. eover 0 x 3 2 phase a measurement registers* 0x1c a.pf a.vrms a.irms 0x1d a.act a.app 0x1e a.eapos a.eaneg 0x1f a.es 0x20 phase b measurement registers* 0x2b b.pf b.vrms b.irms b.act 0x2c b.app 0x2d b.eapos b.eaneg 0x2e b.es 0x2f phase c measurement registers* 0x39 c.pf 0x3a c.vrms c.irms c.act 0x3b c.app 0x3c c.eapos c.eaneg 0x3d c.es 0x3e * read-only. downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe ______________________________________________________________________________________ 25 0 1 2 3 4 5 6 7 0x80 pwrp.a pwrp.b pwrp.c pwrp.t 0x81 0x82 pwrs.a pwrs.b pwrs.c pwrs.t 0x83 v.a v.b v.c 0x84 i.n i.a i.b i.c 0x85 0x86 pf.t 0x87 enrs.a enrs.b enrs.c enrs.t 0x88 0x89 0 x 8 a 0 x 8 b 0x8c enrp.a enrp.b enrp.c enrp.t 0 x 8 d 0 x 8 e 0x8f special function registers 0xc0 dspver rawtemp enter stop enter lowpm exit lowpm table 4. virtual register map note: all virtual registers are read-only. downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe 26 ______________________________________________________________________________________ ram-based registers the ram-based registers contain both operating parameters and measurement results. they are divided into a num-ber of categories that are described in the following sections. general operating registers global status register (status) (0x000) this register contains bits that reflect the global status of the device. bit: 7 6 5 4 3 2 1 0 name: croff porf wdtr phseq revcfp reset: 0 0 0 0 0 0 0 0 bit name function 7, 3, 1 reserved. 6 croff when set, the high-frequency crystal has failed and the MAXQ3181 is operat ing from its internal ring oscillator. under these circumsta nces, energy accumulation is not accurate and the spi bus does not operate at full speed. 5 porf when set, the last reset was due to power-on-reset. host s hould clear this bit to allow the next por detection. 4 wdtr when set, the last reset was caused by expired watchdog. the bit shoul d be cleared (set to 0) by the host to allow the next watchdog reset detection. 2 phseq 0 = the sequence of voltages presented to the voltage inputs is (-a-b -c-). 1 = the sequence of voltages presented to the voltage inputs is rever sed (-a-c-b-). this bit is meaningful only for connection systems that include all three v oltages. 0 revcfp 0 = the quantity being output on the cfp pin is positive (direct). 1 = the quantity being output on the cfp pin is negative (reverse). downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe ______________________________________________________________________________________ 27 operating mode register 1 (opmode1) (0x002) bit name function 7:4 reserved. 3 crcen if set, a 1-byte crc is appended to the end of each spi read and is expected at the end of each spi write. see the spi communications protocol section for details about how to use the crc byte for error checking on the spi bus. 2 popol this bit sets the polarity of the output pulse generators. if clear, the pu lse outputs are active low; that is, they remain in the high state until a pulse event occurs, at which time they switch low for one pulse-width interval before reverting to the high state. if set, the pul se outputs are active high; that is, they remain in the low state until a pulse event occurs, at which time they s witch to the high state for one pulse-width interval before reverting to the low state. bit: 7 6 5 4 3 2 1 0 name: crcen popol concfg reset: 0 0 0 0 0 0 0x0 operating mode register 0 (opmode0) (0x001) bit name function 7:5, 0 reserved. 4 extclk when set, the high-frequency crystal osc illator is disabled and the xtal1 pin is configured to be a clock input for the device. this is used when it is desired to operate multiple devices from the same clock source for purposes of maintaining synchronization. 3 swres when set, forces the internal software to restart from the reset vector. this h as the same effect as a power-on reset, but does not specifically reset any hardwar e peripherals. this bit is automatically cleared after the reset. 2 dspdis when set, disables the signal processing software routines. the c pu continues to run at full speed, but only to perform supervisory functions (such as servicing t he spi port). 1 lowpm when set, causes the cpu to switch its clock source from the external crystal to an internal ring osci llator that operates at a nominal frequency of 1mhz. in this mode, the cpu continues to run, but the host must reconfigure the parameters configured for crystal operation (such as filter settings, timeouts, an d pulse widths). bit: 7 6 5 4 3 2 1 0 name: extclk swres dspdis lowpm reset: 0 0 0 0 0 0 0 0 downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe 28 ______________________________________________________________________________________ operating mode register 1 (opmode1) (0x002) (continued) bit name function these bits determine how power is calculated on each of the three phases. 00 p a = i a x v a p b = i b x v b p c = i c x v c use this configuration when the load is connected in a wye arrangement and neutral is connected to MAXQ3181 gr ound, or when the load is connected in a delta arrangement and isolated voltage and current sensors are used. this arrangement measures power in each load branch rather than power in each source branch. 01 p a = i a x v a p b = i b x (-v c ) p c = i c x v c use this configuration when the load is connected in a four-wire delta arrangement. in this arrangement, the bc leg is split and v b-n is expected to be equal to -v c-n . voltages are referenced to neutral. 10 p a = i a x v a p b = i b x (-v a - v c ) p c = i c x v c use this configuration when the load is connected in a four-wire wye arrangement, but only two voltage sensors are available. when connected in this way, phase b is assumed to be ground. 1:0 concfg 11 p a = i a x v a p b = i b x (v a - v c ) p c = i c x v c use this configuration when the load is connected as a three-wire delta and it is desired to measure the voltage and current inside the delta legs, but to calculate the power in each of the source circuits. when connected this way, source phase b is considered ground. v i ii v v i i i v v v i i v v v i v i ii v n v i i v v i downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe ______________________________________________________________________________________ 29 operating mode register 2 (opmode2) (0x003) bit name function 7:4 reserved. 3 linfrm selects the current linearity offset calibration method. see the calibrating current offset section for more information. 0 = irms 2 + offs 1 = irms + offs these bits select the coefficient used in calculating apparent powe r. 00 = 1-phase, 3-wire (1p3w), or 3-phase, 4-wire (3p4w) (c = 1) 01 = 3-phase, 3-wire (3p3w) (c = 3/2) 10 = three voltages, three currents (3v3a) (c = 3/3) 3p3w wiring (01) 2:1 wirsys 3p4w wiring (00) bit: 7 6 5 4 3 2 1 0 name: linfrm wirsys appsel reset: 0 0 0 0 0 0 0 0 i a i c v ab v cb v i a i b i c v n v b downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe 30 ______________________________________________________________________________________ operating mode register 2 (opmode2) (0x003) (continued) bit name function 3v3a (10) 2:1 wirsys 1p3w (00) selects the mechanism to use for calculating apparent power. 0 appsel 0: s = v rms x i rms apparent power is calculated by multiplying, on a per-dsp cycle ba sis, the product of the rms volts and rms amps. this bit must be set to 0. i a i c i b v ab v ac v bc i a n i b v an v bn downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe ______________________________________________________________________________________ 31 the interrupt request flag register contains bits that indicate the reason the irq pin has become active. the active bit must be cleared by the host to avoid continuing firing of the interrupt by the MAXQ3181. bit name function 15 dspor when set, the dsp was unable to complete processing one cycle when a nother cycle was due to begin. this indicates that the r_adcrate is set too low, and that samples are arriving more quickly than they can be processed. increase the value of the r_adcrate regis ter to reduce the load on the dsp. 14 dsprdy when set, the latest dsp cycle has just completed. 13, 7:3 reserved. 12 dcha when set, the direction of real energy flow has changed (that is, from to ward the load to away from the load, or from away from the load to toward the load). 11 nozx when set, the MAXQ3181 has failed to detect zero crossings on one or more vol tage channels for the time defined by the nzx_timo register. 10 uv when set, the absolute instantan eous voltage level in one or more voltage channels failed to exceed the trip level set in the uvlvl (undervoltage level) register for one dsp c ycle. 9 ov when set, the absolute instantan eous voltage level in one or more voltage channels has exceeded the trip level set in the ovlvl (overvoltage level) register. 8 oc when set, the absolute instantan eous current in one or more current channels has exceeded the trip level set in the oclvl (overcurrent level) register. 2 eovf when set, one or more energy accumulators have an msb overflow condition. 1 chsch when set, indicates a change of the chksum. the chksum is compute d over the configuration and calibration data. the host should review a change in chksum becaus e any change in the configuration or calibration data affects the metering operation and accuracy. 0 pwrf when set, a power-supply failure is immi nent and the supervisory processor should begin taking steps to save its state and prepare for a loss of power. global interrupt registers interrupt request flag register (irq_flag) (0x004) bit: 15 14 13 12 11 10 9 8 name: dspor dsprdy dcha nozx uv ov oc reset: 0 0 0 0 0 0 0 0 bit: 7 6 5 4 3 2 1 0 name: eovf chsch pwrf reset: 0 0 0 0 0 0 0 0 downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe 32 ______________________________________________________________________________________ interrupt mask register (irq_mask) (0x006) bit name function 15 edspor when set, the dspor flag causes the irq pin to become active. 14 edsprdy when set, this flag causes the irq pin to become active. 13, 7:3 reserved. 12 edcha when set, this flag causes the irq pin to become active when the direction of real energy flow has been observed to have changed (that is, from toward the load to away from the load, or from away from the load to toward the load). 11 enozx when set, this flag causes the irq pin to become active when the MAXQ3181 has failed to detect zero crossings on one or more voltage channels for at least one dsp cycle. 10 euv when set, this flag causes the irq pin to become active when the absolute instantaneous voltage level in one or more voltage channels failed to exceed the trip level set in the uvlvl (undervoltage level) register for one dsp cycle. 9 eov when set, this flag causes the irq pin to become active when the absolute instantaneous voltage level in one or more voltage channels has exceeded the trip level s et in the ovlvl (overvoltage level) register. 8 eoc when set, this flag causes the irq pin to become active when absolute instantaneous current in one or more current channels has exceeded the trip level set in the oclvl (overcurrent level) register. 2 eeovf when set, this flag causes the irq pin to become active when one or more energy accumulators have an overflow condition from their msb. 1 echsch when set, this flag enables the irq pin to become active when a chksum change is detected. 0 epwrf when set, this flag causes the irq pin to become active when a power-supply failure is imminent and the supervisory processor should begin taking steps to save it s state and prepare for a loss of power. bit: 15 14 13 12 11 10 9 8 name: edspor edsprdy edcha enozx euv eov eoc reset: 0 0 0 0 0 0 0 0 bit: 7 6 5 4 3 2 1 0 name: eeovf echsch epwrf reset: 0 0 0 0 0 0 0 0 downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe ______________________________________________________________________________________ 33 cfp pulse width (pls1_wd) (0x020) this register designates the width of the cfp pulse, that is, the duration of the period that the cfp pulse is in theactive state. this value is given in adc frame times (about 320s). the default value of 0x9c (156 decimal) provides a pulse width of about 50ms. bit: 15 14 13 12 11 10 9 8 name: cfp pulse-width high byte reset: 0x00 bit: 7 6 5 4 3 2 1 0 name: cfp pulse-width low byte reset: 0x9c meter pulse configuration pulse configuration?fp output (plscfg1) (0x01e) this register selects which phases are included in the cfp pulse output and also selects which quantity is accumu-lated to drive the pulse output. bit: 7 6 5 4 3 2 1 0 name: qnsel phasec phaseb phasea reset: 0x0 0 0 0 bit name function 7:3 qnsel cfp pulse output source select. this five-bit field determine s what meter value will be accumulated in each of the phases to produce the cfp pulse output. all other values ar e reserved. 00000 = net real energy 00001 = absolute real energy 00100 = apparent energy 00110 = i rms 00111 = v rms 01000 = real energy delivered to load 01001 = real energy delivered to line 2 phasec cfp phase c inclusion. when this bit is set, phase c is included in cfp pulse generation. 1 phaseb cfp phase b inclusion. when this bit is set, phase b is included in cfp pulse generation. 0 phasea cfp phase a inclusion. when this bit is set, phase a is included in cfp pulse generation. downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe 34 ______________________________________________________________________________________ cfp pulse threshold (thr1) (0x022) this register designates the threshold of the cfp pulse. this value is used to set the meter constant for the cfppulse output. when the cfp pulse accumulator exceeds the value set in this register, the cfp pulse output is acti- vated and the cfp pulse accumulator is reduced by the amount in this register. calibration registers current gain, phase x = a/b/c/n (x.i_gain) (a: 0x130, b: 0x21c, c: 0x308, n: 0x12e) this register contains gain coefficient for phase x current channel. the raw values are taken from the selected mea-surement quantity and scaled by the factor: note: bit 15 of this register must be set to zero for correct operation. xi gain ._ 2 14 bit: 31 30 29 28 27 26 25 24 name: thr1 byte 3 reset: 0x00 bit: 23 22 21 20 19 18 17 16 name: thr1 byte 2 reset: 0x10 bit: 15 14 13 12 11 10 9 8 name: thr1 byte 1 reset: 0x00 bit: 7 6 5 4 3 2 1 0 name: thr1 byte 0 reset: 0x00 bit: 15 14 13 12 11 10 9 8 name: current gain coefficient high byte reset: 0x40 bit: 7 6 5 4 3 2 1 0 name: current gain coefficient low byte reset: 0x00 downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe ______________________________________________________________________________________ 35 voltage gain, phase x = a/b/c (x.v_gain) (a: 0x132, b: 0x21e, c: 0x30a) this register contains gain coefficient for phase x voltage channel. the raw values are taken from the selected mea-surement quantity and scaled by the factor: note: bit 15 of this register must be set to zero for correct operation. energy gain, phase x = a/b/c (x.e_gain) (a: 0x134, b: 0x220, c: 0x30c) this register contains gain coefficient for phase x energy. the raw values are taken from the selected measurementquantity and scaled by the factor: note: bit 15 of this register must be set to zero for correct operation. phase-angle compensation, high range, phase x = a/b/c (x.pa0) (a: 0x13e, b: 0x22a, c: 0x316) this signed register contains the angle as a fraction of one radian to add to the measured phase angle when themeasured current is above the value given in i1thr. this signed value ranges from -0.5 radian (at a value of 0x8000) to +(0.5 - 2 -16 ) radian (at a value of 0x7fff). xe gain ._ 2 14 x v gain ._ 2 14 bit: 15 14 13 12 11 10 9 8 name: voltage gain coefficient high byte reset: 0x40 bit: 7 6 5 4 3 2 1 0 name: voltage gain coefficient low byte reset: 0x00 bit: 15 14 13 12 11 10 9 8 name: energy gain coefficient high byte reset: 0x40 bit: 7 6 5 4 3 2 1 0 name: energy gain coefficient low byte reset: 0x00 bit: 15 14 13 12 11 10 9 8 name: phase-angle offset high byte reset: 0x00 bit: 7 6 5 4 3 2 1 0 name: phase-angle offset low byte reset: 0x00 downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe 36 ______________________________________________________________________________________ phase-angle compensation, medium range, phase x = a/b/c (x.pa1) (a: 0x140, b: 0x22c, c: 0x318) this signed register contains the angle, as a fraction of one radian, to add to the measured phase angle when themeasured current is between the values given in i1thr and i2thr. this signed value ranges from -0.5 radian (at a value of 0x8000) to +(0.5 - 2 -16 ) radian (at a value of 0x7fff). phase-angle compensation, low range, phase x = a/b/c (x.pa2) (a: 0x142, b: 0x22e, c: 0x31a) this signed register contains the angle, as a fraction of one radian, to add to the measured phase angle when themeasured current is below the value given in i2thr. this signed value ranges from -0.5 radian (at a value of 0x8000) to +(0.5 - 2 -16 ) radian (at a value of 0x7fff). limit registers overcurrent level (oclvl) (0x044) this register specifies the fraction of full-scale current that is declared to be an overcurrent condition. when x.irmsexceeds this level for one dsp cycle, the ocf flag in the x.flags register is set. if the ocm flag is set in the x.mask register, setting the ocf flag will cause the interrupt bit oc to be set in the irq_flag register. if the inter- rupt is enabled, the interrupt pin is driven active. full scale is represented by 0x10000. the maximum value for this register is 0xffff. bit: 15 14 13 12 11 10 9 8 name: phase-angle offset high byte reset: 0x00 bit: 7 6 5 4 3 2 1 0 name: phase-angle offset low byte reset: 0x00 bit: 15 14 13 12 11 10 9 8 name: phase-angle offset high byte reset: 0x00 bit: 7 6 5 4 3 2 1 0 name: phase-angle offset low byte reset: 0x00 bit: 15 14 13 12 11 10 9 8 name: overcurrent level high byte reset: 0xff bit: 7 6 5 4 3 2 1 0 name: overcurrent level low byte reset: 0xff downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe ______________________________________________________________________________________ 37 overvoltage level (ovlvl) (0x046) this register specifies the fraction of full-scale voltage that is declared to be an overvoltage condition. when x.vrmsexceeds this level for one dsp cycle, the ovf flag in the x.flags register is set. if the ovm flag is set in the x.mask register, setting the ovf flag will cause the interrupt bit ov to be set in the irq_flag register. if the inter- rupt is enabled, the interrupt pin is driven active. full scale is represented by 0x10000. the maximum value for this register is 0xffff. undervoltage level (uvlvl) (0x048) this register specifies the fraction of full-scale voltage below which an undervoltage condition is declared. whenx.vrms falls below this level for one dsp cycle, the uvf flag in the x.flags register is set. if the uvm flag is set in the x.mask register, setting the uvf flag will cause the interrupt bit uv to be set in the irq_flag register. if the interrupt is enabled, the interrupt pin is driven active. full scale is represented by 0x10000. the maximum value for this register is 0xffff. no-load level (noload) (0x04a) this register specifies the fraction of full-scale current below which a no-load condition is declared. when x.irmsfalls below this level, the MAXQ3181 no longer accumulates power for phase x. full scale is represented by 0x10000. the maximum value for this register is 0xffff. bit: 15 14 13 12 11 10 9 8 name: overvoltage level high byte reset: 0xff bit: 7 6 5 4 3 2 1 0 name: overvoltage level low byte reset: 0xff bit: 15 14 13 12 11 10 9 8 name: undervoltage level high byte reset: 0x00 bit: 7 6 5 4 3 2 1 0 name: undervoltage level low byte reset: 0x00 bit: 15 14 13 12 11 10 9 8 name: no-load level high byte reset: 0x00 bit: 7 6 5 4 3 2 1 0 name: no-load level low byte reset: 0x03 downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe 38 ______________________________________________________________________________________ phase status registers interrupt flags, phase x = a/b/c (x.flags) (a: 0x144, b: 0x230, c: 0x31c) the x.flags register contains condition flags that relate to the function of phase x (a/b/c) measurements. onceset, these bits can be cleared only by the host. bit: 7 6 5 4 3 2 1 0 name: dchaf nozxf uvf ovf ocf reset: 0 0 0 0 0 0 0 0 bit name function 7:5 reserved. 4 dchaf real energy direction change. set when the direction of real power flow changes (fr om toward the load to toward the line, or from toward the line to toward the load). if the dcham bit is set, thi s bit sets the dcha flag in the irq_flag register. 3 nozxf no-zero crossing. set when the voltage waveform in phase x fails to ex hibit a zero crossing during nzx_timo of the adc sample periods. if the nozxm bit is set, this bit sets the nozx flag in the irq_flag register. 2 uvf undervoltage. set when the rms voltage in phase x falls below the undervoltage threshold set in uvlvl. if the uvm bit is set, this bit sets the uv flag in the irq_flag re gister. 1 ovf overvoltage. set when the rms voltage in phase x exceeds the overvol tage threshold set in ovlvl. if the ovm bit is set, this bit sets the ov flag in the irq_flag reg ister. 0 ocf overcurrent. set when the rms current in phase x exceeds the overcurrent thresh old set in oclvl. if the ocm bit is set, this bit sets the oc flag in the irq_flag registe r. downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe ______________________________________________________________________________________ 39 interrupt mask, phase x = a/b/c (x.mask) (a: 0x145, b: 0x231, c: 0x31d) energy overflow flags, phase x = a/b/c (x.eover) (a: 0x146, b: 0x232, c: 0x31e) these bits indicate that an overflow condition has occurred on an energy accumulator. an overflow condition is not an error condition. rather, it simply indicates that the value in the energy accumulator could be smaller than the pre-vious reading due to the overflow in the counter. to obtain the actual energy usage since the previous reading, 0x100000000 must be added to the difference. these bits, once set, can be cleared only by the host. bit: 7 6 5 4 3 2 1 0 name: dir_a dcham nozxm uvm ovm ocm reset: 0 0 0 0 0 0 0 0 bit name function 7, 5 reserved. 6 dir_a active energy direction status 0 = positive 1 = negative 4 dcham real energy direction change mask. if set, a change in real power direction on phase x causes the dcha flag in the irq_flag register to be set. 3 nozxm no-zero crossing mask. if set, a no-zero crossing on phase x causes the nozx flag in the irq_flag register to be set. 2 uvm undervoltage mask. if set, an undervoltage condition on phase x causes the uv flag in the irq_flag register to be set. 1 ovm overvoltage mask. if set, an overvoltage condition on phase x causes the ov flag in the irq_flag register to be set. 0 ocm overcurrent mask. if set, an overcurrent condition on phase x causes the oc flag in the irq_flag register to be set. bit name function 7:5, 3:2 reserved. 4 sov when set, indicates an overflow condition on the apparent energy accum ulator. 1 anov when set, indicates an overflow condition on the real negativ e energy accumulator. 0 apov when set, indicates an overflow condition on the real positi ve energy accumulator. bit: 7 6 5 4 3 2 1 0 name: sov anov apov reset: 0 0 0 0 0 0 0 0 downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe 40 ______________________________________________________________________________________ measurements line frequency (linefr) (0x062) line frequency, lsb = 0.001hz. power factor, phase x = a/b/c (x.pf) (a: 0x1c6, b: 0x2b2, c: 0x39e) power factor of phase a/b/c, lsb = 1/2 14 . note that the power factors are signed integers, and a negative value indicates a reversed power flow direction. rms voltage, phase x = a/b/c (x.vrms) (a: 0x1c8, b: 0x2b4, c: 0x3a0) this register provides the raw rms voltage over the most recent dsp cycle, lsb = v fs /2 24 . bit: 15 14 13 12 11 10 9 8 name: line frequency high byte reset: bit: 7 6 5 4 3 2 1 0 name: line frequency low byte reset: bit: 15 14 13 12 11 10 9 8 name: power factor high byte reset: 0x00 bit: 7 6 5 4 3 2 1 0 name: power factor low byte reset: 0x00 bit: 31 30 29 28 27 26 25 24 name: rms voltage byte 3 bit: 23 22 21 20 19 18 17 16 name: rms voltage byte 2 bit: 15 14 13 12 11 10 9 8 name: rms voltage byte 1 bit: 7 6 5 4 3 2 1 0 name: rms voltage byte 0 downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe ______________________________________________________________________________________ 41 rms current, phase x = a/b/c (x.irms) (a: 0x1cc, b: 0x2b8, c: 0x3a4) this register provides the raw rms current over the most recent dsp cycle, lsb = i fs /2 24 . energy, real positive, phase x = a/b/c (x.eapos) (a: 0x1e8, b: 0x2d4, c: 0x3c0) on every dsp cycle, the contents of the x.act register are tested, and, if positive, are added to this register. whenthis register overflows, the apov bit in the x.eover register is set. bit: 31 30 29 28 27 26 25 24 name: rms current byte 3 bit: 23 22 21 20 19 18 17 16 name: rms current byte 2 bit: 15 14 13 12 11 10 9 8 name: rms current byte 1 bit: 7 6 5 4 3 2 1 0 name: rms current byte 0 bit: 31 30 29 28 27 26 25 24 name: real energy byte 3 bit: 23 22 21 20 19 18 17 16 name: real energy byte 2 bit: 15 14 13 12 11 10 9 8 name: real energy byte 1 bit: 7 6 5 4 3 2 1 0 name: real energy byte 0 downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe 42 ______________________________________________________________________________________ energy, real negative, phase x = a/b/c (x.eaneg) (a: 0x1ec, b: 0x2d8, c: 0x3c4) on every dsp cycle, the contents of the x.act register are tested, and, if negative, absolute values are added tothis register. when this register overflows, the anov bit in the x.eover register is set. energy, apparent, phase x = a/b/c (x.es) (a: 0x1f8, b: 0x2e4, c: 0x3d0) on every dsp cycle, the contents of the x.app register are added to this register. when this register overflows, thesov bit in the x.eover register is set. bit: 31 30 29 28 27 26 25 24 name: real energy byte 3 bit: 23 22 21 20 19 18 17 16 name: real energy byte 2 bit: 15 14 13 12 11 10 9 8 name: real energy byte 1 bit: 7 6 5 4 3 2 1 0 name: real energy byte 0 bit: 31 30 29 28 27 26 25 24 name: apparent energy byte 3 bit: 23 22 21 20 19 18 17 16 name: apparent energy byte 2 bit: 15 14 13 12 11 10 9 8 name: apparent energy byte 1 bit: 7 6 5 4 3 2 1 0 name: apparent energy byte 0 downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe ______________________________________________________________________________________ 43 virtual register conversion coefficients voltage units conversion coefficient (volt_cc) (0x014) this register contains the value by which the raw voltage value in each phase (a.vrms, b.vrms, and c.vrms) ismultiplied before being presented to the virtual rms voltage registers (v.a, v.b, and v.c). to determine the value of volt_cc, a voltage value for the least significant bit (volt_lsb) of the v.x registers must be selected. typical values might range from 1mv to 1nv. to avoid significant conversion loss, volt_lsb should be chosen such that volt_cc is >1000. once volt_lsb is determined, calculate volt_cc from the fol- lowing equation: current units conversion coefficient (amp_cc) (0x016) this register contains the value by which the raw current value in each phase (a.irms, b.irms, c.irms, andn.irms) is multiplied before being presented to the virtual rms current registers (i.a, i.b, i.c, and i.n). to determine the value of amp_cc, a current value for the least significant bit (amp_lsb) of the i.x registers must be selected. typical values might range from 1na to 10a. to avoid significant conversion loss, amp_lsb should be chosen such that amp_cc is >1000. once determined, calculate amp_cc from the following equation: amp cc i amp lsb fs _ _ = 2 24 volt cc v volt lsb fs _ _ = 2 24 bit: 15 14 13 12 11 10 9 8 name: voltage units conversion coefficient high byte reset: 0x00 bit: 7 6 5 4 3 2 1 0 name: voltage units conversion coefficient low byte reset: 0x01 bit: 15 14 13 12 11 10 9 8 name: current units conversion coefficient high byte reset: 0x00 bit: 7 6 5 4 3 2 1 0 name: current units conversion coefficient low byte reset 0x01 downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe 44 ______________________________________________________________________________________ power units conversion coefficient (pwr_cc) (0x018) this register contains the value by which the raw power value in each phase is multiplied before being presented tothe virtual power registers. the table below lists the raw power registers and the corresponding virtual registers. pwr_cc establishes the amount of power represented by one pwr_lsb of the power registers. to avoid significant conversion loss, pwr_lsb should be chosen such that pwr_cc is > 1000. calculate the value of pwr_cc accord- ing to the following formula: pwr cc iv pwr lsb fs fs _ _ = 2 32 bit: 15 14 13 12 11 10 9 8 name: power units conversion coefficient high byte reset: 0x00 bit: 7 6 5 4 3 2 1 0 name: power units conversion coefficient low byte reset: 0x01 description raw virtual real power, phase a a.act pwrp.a real power, phase b b.act pwrp.b real power, phase c c.act pwrp.c real power, total pwrp.t apparent power, phase a a.app pwrs.a apparent power, phase b b.app pwrs.b apparent power, phase c c.app pwrs.c apparent power, total pwrs.t downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe ______________________________________________________________________________________ 45 energy units conversion coefficient (enr_cc) (0x01a) this register contains the value by which the raw accumulated energy value in each phase is multiplied before beingpresented to the virtual energy registers. the table below lists the raw energy accumulators and the corresponding virtual registers. to avoid significant conversion loss, enr_lsb should be chosen such that enr_cc is > 1000. calculate the value of enr_cc according to the following formula: enr cc ivt enr lsb fs fs fr _ _ = 2 16 bit: 15 14 13 12 11 10 9 8 name: energy units conversion coefficient high byte reset: 0x00 bit: 7 6 5 4 3 2 1 0 name: energy units conversion coefficient low byte reset: 0x01 description raw virtual real energy, phase a, positive direction a.eapos real energy, phase a, reverse direction a.eaneg enrp.a* real energy, phase b, positive direction b.eapos real energy, phase b, reverse direction b.eaneg enrp.b* real energy, phase c, positive direction c.eapos real energy, phase c, reverse direction c.eaneg enrp.c* real energy, total enrp.t apparent energy, phase a a.es enrs.a apparent energy, phase b b.es enrs.b apparent energy, phase c c.es enrs.c apparent energy, total enrs.t * these registers represent the algebraic sum of the positive and reverse energy in the two raw registers noted. thus, the energy returned in these virtual registers represents the net energy. downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe 46 ______________________________________________________________________________________ virtual registers the virtual registers are calculated values derived from one or more real registers. they are calculated at the timethey are requested, and thus could involve additional time to return a value. most virtual registers are 8 bytes in length and are delivered least significant byte first. power real power, phase x = a/b/c/t (pwrp.x) (a: 0x801, b: 0x802, c: 0x804, t: 0x807) this signed register contains the real instantaneous power delivered into phase a/b/c or total. power is calculatedfrom the instantaneous energy measurement according to the following equation: the register is 8 bytes long, but the most significant 2 bytes are not used. see the pwr_cc register description for more details. note that the sign bit is bit 47 for all 8-byte signed virtual registers. apparent power, phase x = a/b/c/t (pwrs.x) (a: 0x821, b: 0x822, c: 0x824, t: 0x827) this register contains the apparent instantaneous power delivered into phase a/b/c or total. power is calculatedfrom the instantaneous energy measurement according to the following equation: the register is 8 bytes long, but the most significant 2 bytes are not used. see the pwr_cc register description for more details. pwrs x x app pwr cc ns . ._ = 2 16 pwrp x xact pwr cc ns . ._ = 2 16 byte 7 (msbyte unused) byte 6 (unused) byte 5 byte 4 byte 3 byte 2 byte 1 byte 0 (lsbyte) byte 7 (msbyte unused) byte 6 (unused) byte 5 byte 4 byte 3 byte 2 byte 1 byte 0 (lsbyte) downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe ______________________________________________________________________________________ 47 voltage and current rms volts, phase x = a/b/c (v.x) (a: 0x831, b: 0x832, c: 0x834) this register contains the rms voltage on phase a/b/c. the units are defined by the volt_cc setting such that v.x= x.vrms x volt_cc. in this equation, volt_cc is the conversion coefficient. see the volt_cc register for more information. rms amps, phase x = a/b/c/n (i.x) (a: 0x841, b: 0x842, c: 0x844, n: 0x840) this register contains the rms current on phase a/b/c or the neutral channel. the units are defined by the amp_ccsetting such that i.x = x.irms x amp_cc. in this equation, amp_cc is the conversion coefficient. see the amp_cc register for more information. power factor power factor (pf.t) (0x867) this signed register contains the power factor of the total power. the power factor is calculated as:it is expressed in units of 0.00001; thus, unity power factor is expressed as decimal 100,000 (0x00000000000186a0). this register is presented as a twos complement value, so that a load delivering real power to the line (that is, reverse power) is seen as having a power factor of -1 (0x0000fffffffe7960). pf t a act b act c act a app b app c app . .. . .. . = ++ ++ byte 7 (msbyte unused) byte 6 (unused) byte 5 byte 4 byte 3 byte 2 byte 1 byte 0 (lsbyte) byte 7 (msbyte unused) byte 6 (unused) byte 5 byte 4 byte 3 byte 2 byte 1 byte 0 (lsbyte) byte 7 (msbyte unused) byte 6 (unused) byte 5 byte 4 byte 3 byte 2 byte 1 byte 0 (lsbyte) downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe 48 ______________________________________________________________________________________ energy real energy, phase a/b/c/t (enrp.x) (a: 0x8c1, b: 0x8c2, c: 0x8c4, t: 0x8c7) this signed register contains the real accumulated energy delivered into phase a/b/c or total. the register is calcu-lated according to the following formula: enrp.x = enr_cc x (x.eapos - x.eaneg) apparent energy, phase a/b/c/t (enrs.x) (a: 0x871, b: 0x872, c: 0x874, t: 0x877) this register contains the apparent accumulated energy delivered into phase a/b/c or total. the register is the prod-uct of the enr_cc and x.es registers. byte 7 (msbyte unused) byte 6 (unused) byte 5 byte 4 byte 3 byte 2 byte 1 byte 0 (lsbyte) byte 7 (msbyte unused) byte 6 (unused) byte 5 byte 4 byte 3 byte 2 byte 1 byte 0 (lsbyte) downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe ______________________________________________________________________________________ 49 theory of operation analog front-end operation whenever the MAXQ3181 is in one of the active operat-ing modes (run mode or lowpm mode), the analog front-end operates continuously, scanning up to eight scan slots depending on the selected front-end config- uration. for each analog scan slot that is enabled, one of the eight differential input pairs is measured. the scan_ix and scan_vx (x = a/b/c), scan_in, and scan_te registers contain the settings for each slot, which include whether the slot is enabled and the differential input pair to measure during that scan slot. the logical mapping of the slots is fixed in following order: ? slot 0phase a current (ia) ? slot 1phase a voltage (va) ? slot 2phase c current (ic) ? slot 3phase c voltage (vc) ? slot 4phase b current (ib) ? slot 5phase b voltage (vb) ? slot 6neutral current (in)disabled by default ? slot 7temperature measurementdisabled by default the required time for each analog scan slot measure-ment (t c ) is determined by the MAXQ3181 system clock frequency and the setting of the r_adcratehardware register, as shown below: t c = 1/f clk x (r_adcrate[8:0] + 1) using the default register settings (r_adcrate = 13fh= 319d), the time for each analog slot measurement (t c ) is 40s when the MAXQ3181 is running at 8mhz. since there are eight analog scan slots in the measure-ment frame, the total time for all measurements (t fr ) is t c x 8. using the default settings with the MAXQ3181 running at 8mhz, the entire sequence of measurementstakes 320s to complete, which, in turn, means that 320s will elapse, for example, between one phase a current measurement and the next. even if some of the analog measurement slots (such as neutral current or temperature measurement) are skipped by setting the dadcnv bit in that slots regis- ter to 1, the time period for that slot will remain in the frame, ensuring that the total frame time is always t c x 8, regardless of which individual slots are enabled ordisabled. digital signal processing (dsp) terminology establishing the precise definitions of some of the termsused in this document will assist in understanding how the dsp functions. sample period: the amount of time required to mea- sure a single data element; 40s, by default.adc frame period: the amount of time required for the adc to sample all analog inputs; always equal to 8sample periods. the inverse of this value is the frame rate ; by default 3125 samples per second. this is the rate at which any particular signal is sampled by theMAXQ3181. line cycle: the period of time from one positive-going zero crossing on a voltage channel to the next positive-going zero crossing. at 50hz, this is nominally 20ms; at 60hz, this is nominally 16.67ms. cycle count: the number of line cycles contained in a single dsp cycle. an integer, this is typically set tosome value greater than one to minimize the effect of load variations that may not occur in every line cycle. by default, this value is 16. dsp cycle: the period of time over which line parame- ters are calculated. energy and other parameters areaccumulated once per dsp cycle. one dsp cycle is the time of a line cycle multiplied by the cycle count. ns: this value represents the number of adc frame periods in a dsp cycle. this is a noninteger calculatedvalue. for example, if the cycle count is set to unity, and the line frequency is exactly 50hz, the ns value would be 20ms/320s = 62.5. digital processing as voltage and current samples are collected, theMAXQ3181 performs a variety of digital filtering, accumulation, and processing calculations to arrive at meter-reading values (such as line frequency, rms voltage and current, and active power) that can then be read by the master. the MAXQ3181 calculates and detects values and conditions including the following: ? zero-crossing detection ? line frequency and line period calculation ? rms voltage (phase a, phase b, phase c) ? rms current (phase a, phase b, phase c, neutral current) ? power (active and apparent) for each phase downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe 50 ______________________________________________________________________________________ ? energy accumulation (including energy pulse output function) ? overvoltage detection ? overcurrent detection ? undervoltage detection per sample operations on every adc frame, the input samples are processedas follows: ? the voltage and current samples are read. the cur- rent sample is shifted to account for the gain appliedin the pga. the phase- and gain-corrected samples are passed to the next stage. ? both the current and voltage signals are passed through highpass filters (hpf) specified by thehpf_c variable. ? the current and voltage signals are now split into several components. the first of these components issquared and accumulated to begin the rms current and voltage process. the second is processed and accumulated to begin the real power calculation. the result is a set of accumulated values that representsquared voltage, squared current, and real (active) energy for both the entire usable spectrum and as fil- tered by the peak filter. the real energy at this point does not yet represent real power; to obtain usable power values further processing is required. each of these values is further processed at the end of each dsp cycle. per dsp cycle operations at the end of each dsp cycle, accumulated informationis available that is used to calculate all other opera- tional results in the meter. dsp cycles track the line fre- quency and have a duration of the number of cycles specified in the cycnt register. on each phase, the time required for cycnt cycles to complete is calculat- ed and this value is used to update the duration of one dsp cycle, specified in the ns register. ns contains the number of adc frame periods in a sin- gle dsp cycle. because line frequency varies slightly from cycle to cycle, and because the adc frame clock is not synchronized to the line, the value of ns is not an integer, and varies slightly from dsp cycle to dsp cycle. because the value of ns is so critical to accurate calcu- lation of energy, ensuring that it is correct on every cycle is essential. there are two ways to manage the slight variation of ns from cycle to cycle: first, one could simply replace the old value of ns with the newly calculated value on each dsp cycle. this means that ns (and every other value in the meter, since they depend on ns) would have a significant amount of uncertainty. a better method is to use each newly cal- culated value of ns as an input to a filter. the output of the filter is then the value of ns that is actually used incalculations. in the MAXQ3181, this filter is controlled by the avg_ns register. a second problem with updating ns on every line cycles is the fact that noise impulses that occur at near- ly the same time as the zero crossing can shift the zero current input adc hpf e p i 2 x 2 v 2 x 2 energy processing voltage input hpf gain sel i_gain v_gain adc figure 9. per sample operations downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe ______________________________________________________________________________________ 51 crossing, affecting the accuracy of the energy mea-sured during the preceding period. for this reason, a second register, rej_ns contains a value that specifies how far a particular sample can deviate from the aver- age and still be considered valid. if the period of the newly acquired dsp cycle differs from the previously accumulated average value by more than rej_ns adc frames, ns is not updated with the new period (but the energy is still accumulated). with this discussion in mind, the signal path for the vari- ous reported parameters can be reviewed. rms volts and rms amps: first, the squared voltage accumulation is divided by ns. this accomplishes themean part of the root-mean-square calculation. then, the square root of the result is taken, producing the raw rms calculation value. on the voltage channel, the signal is ready for gain compensation to be applied. but on the current channel, there is an additional twist: depending on the amplitude of the current, there may be a gain factor pre-applied before the raw sample is available. to compensate for inaccuracy in the gain factor for the amplifier and for noise seen in the channel at high gain settings, it may be necessary to provide linearity compensation. there are three registers that manage the linearization of the current signal: the x.offs_hi (x = a/b/c) regis- ter contains a signed value that is added to the raw rms current signal before further processing; the x.offs_lo register contains a signed value that is added to the raw rms current signal when the current signal is below a low current threshold (1/32 of the full scale) value; and the x.gain_lo register contains a gain adjustment that is applied to the current signal when the current signal is below the threshold value. the practical effect of this is to turn what may be asomewhat nonlinear response curve for the current sen- sor to a much more linear response by two-piece approximation. the high current calibration term x.offs_hi is used so long as the instantaneous current exceeds the low- current threshold at some instant during a dsp cycle. as long as this threshold is crossed during a dsp cycle, the value in x.offs_hi controls the offset current. when the input stays below the low-current threshold for one dsp cycle, the x.offs_lo and x.gain_lo are applied. the low-current calibration terms (x.gain_lo and x.offs_lo) remain in effect until the peak of input current waveform exceeds 1/32 of full-scale current at any time during a dsp cycle. as a final step, both voltage and current are passed through an averaging filter that provides smoothing for the signals. the amount of filtering is given in avg_c. energy: current sensors and other external circuitry components could introduce a phase distortion to thecurrent signal, and this phase distortion may not be constant at all current values. consequently, for the most precise measurements, the phase between the voltage and current signals must be compensated. in the MAXQ3181, the energy signals are compensated for phase offset by performing a complex multiplication of the signal with the contents of the appropriate phase offset register. determining which phase offset register is appropriate is a matter of comparing the incoming rms current for the phase with the contents of the i1thr and i2thr regis- ters. it is the responsibility of the administrative software to ensure that i1thr is greater than or equal to i2thr. if the raw rms current is greater than or equal to the con- linearization average avg_c i rms offs_hi gain_lo offs_lo raw_i average avg_c v rms raw_v i 2 ns v 2 ns figure 10. computation of rms values downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe 52 ______________________________________________________________________________________ tents of i1thr, then the angle expressed in pa0 is usedto compensate the phase angle. if the raw rms current is less than i2thr, then the angle expressed in pa2 is used to compensate the phase angle. and if the raw rms current falls between i1thr and i2thr then pa1 is used to compensate the phase angle. in this way, a three-piece stepwise approximation of the phase response of the current sensor is available. to use a constant phase compensation, set i1thr and i2thr to zero and insert the phase compensation value into pa0. apparent energy is calculated as the product of the raw rms volts and amps. line frequency: line frequency can be taken directly from the ns value. recall that ns is the number offrames in a dsp cycle. since each frame is 320s, sim- ply multiply ns by 320s and divide by cycnt to obtain the line period. the reciprocal of this is the line frequency. energy accumulation once real energy over the most recent dsp cycle hasbeen calculated, it is necessary to accumulate the result. the result accumulated during any dsp cycle can be positive (that is, energy is delivered to the load) or neg- ative (that is, energy is driven back into the line). thesevalues are separately accumulated. apparent energy is also accumulated, but since this value is always positive or zero, there is only one apparent energy accumulator. from time to time, the accumulators generate an over- flow. when this occurs, the appropriate bit is set in the overflow status register x.eover. when an overflow occurs, supervisory code running on the host processor must make the appropriate adjust- ments in the reported energy. in many cases, this could simply involve incrementing an overflow counter. the host processor must then clear the overflow indication. no-zero-crossing detection the MAXQ3181 monitors the voltage signal on eachphase for zero-crossing events. if no ascending zero crossings are detected within a specified number (nzx_timo) of analog scan sample periods, the nozxf (x.flags) flag is set by the MAXQ3181 to noti- fy the master of this condition. if the nozxm bit is set, this flag sets the nozx bit in the irq_flag. if the inter- rupt enable bit enozx is set to 1, the interrupt signal irq is driven low by the MAXQ3181 whenever nozx = 1. the master can clear nozxf and nozx back to 0 toremove the interrupt condition. phase sequence status a phase sequence status bit phseq indicates theorder in which zero crossings are detected. when a zero-crossing event occurs on the phase a voltage sig- nal, followed by phase b, phase c, and then phase a pa pa i i thr pa i thr i i thr pa rms rms = > 01 11 2 2 , ,) , ,i i thr rms < ? ? ? ? ? ? ? ? ? ? 2 average avg_c e apparent e_gain appsel = 0 x y raw_i raw_v figure 12. apparent energy calculations phase compensation pa0pa1 pa2 e p real processing linearization average avg_c e real e_raw real offs_hi gain_lo offs_lo e_gain figure 11. phase compensation for energy calculations downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe ______________________________________________________________________________________ 53 again, this bit cleared. if a zero crossing on phase a isthen followed by a zero crossing on phase c, then phase b, this bit set to 1. power calculation (active and apparent) the power, energy, and rms calculation process con-sists of two tasks: continuous accumulation and post- processing triggered every cycnt line cycles. the accumulation task accumulates raw data obtained from the afe during cycnt line cycles. this task is per- formed continuously in the background by the MAXQ3181. when a cycnt line cycles accumulation stage has completed, which is determined by a dedi- cated frame counter exceeding the ns level, the raw integral accumulator values are saved for postprocess- ing and cleared, beginning the next cycle of accumula- tion task. then, the dsp postprocessing is triggered to process saved integrals and calculate energy, power, etc., values. note that the background accumulation task continues while foreground postprocessing is tak- ing place, i.e., both tasks are executed simultaneously sharing cpu time. it is essential that the dsp postpro- cessing calculations be completed before the next dsp trigger to avoid losing accumulated data. the master should allow enough processing time by adjusting the r_adcrate register. default settings provide plenty of cpu time for both tasks. the MAXQ3181 accumulates raw sums and calculates line-cycle integrals for each voltage-current pair sepa- rately. the individual power accumulators are: ? pa = v a x i a ? pb = i b x v b or -i b x v c or -i b x (v a + v c ) or -i b x (v a - v c ) ? pc = v c x i c the pa and pc accumulators always operate in a sin-gle mode: (v a x i a ) for the pa accumulator, (v c x i c ) for the pc accumulator. alternately, the operating mode ofthe pb accumulator is defined by setting the concfg[1:0] bits in the opmode1 register. energy accumulation start delay all filters have a certain settling time before accurateenergy readings can be accumulated. to avoid accu- mulation of invalid data from filters that are still settling, an energy accumulation timeout period can be set in the acc_timo register. when acc_timo > 0, comput- ed energy is not accumulated for acc_timo of dsp cycles. the MAXQ3181 will decrement the acc_timo register every dsp cycle until it becomes 0. when acc_timo reaches 0 value, energy accumulation begins (or resumes, if acc_timo was set to nonzero value by the master). pulse outputs are also disabled when acc_timo > 0. the default value of acc_timois 0x05. no-load feature to avoid meter creep, no energy accumulation shouldtake place when measured current is less than a cer- tain threshold. the noload register can be pro- grammed to enable and configure this feature. if the measured x.irms value for a phase (a, b, or c) falls below the noload threshold, the energy accumulators for this phase are not incremented. setting noload = 0 disables this feature. full scale is represented by 0x10000. on demand calculations so far in this discussion, the values being calculatedand managed in the MAXQ3181 have been based on fundamental units meaningful to the device itself: volt- age as a binary fraction of full-scale voltage; current as a binary fraction of full-scale current, and time as a non- integer multiple of the adc frame time. but a practical electricity meter must report its results in standard units, such as volts, amperes, and watts. the MAXQ3181 contains a mechanism to convert the inter- nal units (meter units) to real world units (display units). this conversion is performed in the conversion constant (cc) registers. for some of these values (voltage, current) the calcula- tion is simple: multiply by the conversion constant. for other values (power, energy) the calculation is more complex. in any case, the value in the cc register affects only the conversion from a meter unit to a dis- play unit; calibration is handled separately in the gain adjustment registers for each recorded value. the results of all on-demand calculations are reported as 8-byte (64-bit) values of which no more than 6 bytes (48 bits) are significant. eight bytes are used as a com- mon length; however, fewer bytes can be requested for those registers known to have smaller maximum values. for example, the power factor virtual register has a maximum value that is expressed in only 3 bytes; con- sequently, the register can be requested with a length of 4 bytes without loss of data. rms volts, rms amps these registers (v.a, v.b, v.c, i.a, i.b, i.c) are calculat-ed by simply multiplying the calculated rms value (a.vrms, b.vrms, c.vrms, a.irms, b.irms, c.irms) by the contents of the volt_cc or amp_cc register. since the rms voltage and rms current are given in 32- bit registers and the conversion coefficients are given in 16-bit registers, the result of the product is 48 bits. downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe 54 ______________________________________________________________________________________ regardless of the internal units used, volt_cc andamp_cc can be tailored so that the lsb of the virtual register can be any value. for example, if one wished to have a 32-bit value representing milliamps, one could multiply by a value that scaled the register such that the lsb was 2 -16 ma. then, discard the low-order 16 bits. the result is milliamps with 32 bits of precision;thus, the maximum current that could be represented would be 4,294,967,296ma, or just over 4ma. the volt_cc and amp_cc values can be calculated from the full-scale voltage or full-scale current and the desired value of one lsb in the display register: example: assume the full-scale current is 102.4a, and that we desire a 1na lsb. the calculation would pro-vide an amp_cc value of: 102.4/(2 24 x 10 -9 ) = 6104 = 0x17d8 power the MAXQ3181 measures energy. but power is justenergy per unit time, and the MAXQ3181 keeps track of the time unit over which energy is accumulated. this is simply the ns value, the fractional number of samples that comprises one dsp cycle. so converting energy to power is as simple as dividing the accumulated energy over one dsp cycle by ns. multiplying by a conversion constant (pwr_cc) gives power in user-established units. the power registers (pwrp.a, pwrp.b, pwrp.c, pwrs.a, pwrs.b, pwrs.c) are calculated by multiply- ing the accumulated energy (a.act, a.app, b.act, b.app, c.act, c.app) by the conversion coefficient (pwr_cc) and then dividing by ns. the result is the 48-bit average power over the most recent dsp cycle, in units established by the conversion coefficient. the pwr_cc value can be calculated from the full- scale voltage, the full-scale current, and the desired value of one lsb in the display register: example: for this example, assume the full-scale cur- rent is 102.4a, the full-scale voltage is 558.1v, and thatthe desired lsb is milliwatts after discarding the 16 lsb; that is, the desired lsb is 2 -16 milliwatts. perform the following calculation: 102.4 x 558.1/(2 32 x 2 -16 x 10 -3 ) = 872 = 0x0368 power factor power factor is calculated as real power divided byapparent power. apparent power is computed as the product of the rms voltage and current measurement. the power factor is multiplied by 2 14 before it is report- ed; thus, unity power factor is given by 16,384 decimal(0x4000). line frequency the line frequency is derived directly from the mean nsvalues over the three phases. it is reported as millihertz; thus, a 50hz line frequency is reported as decimal 50,000 (0xc350). energy energy is read as the net energy directly scaled fromthe appropriate registers. for example, the energy read from the enrp.a register (real energy, phase a) is composed of the difference between the a.eapos (real energy, positive direction, phase a) and a.eaneg (real energy, negative direction, phase a) registers scaled by the enr_cc register. note that the energy registers (enrp.a, enrp.b, enrp.c, enrp.t, enrs.a, enrs.b, enrs.c, enrs.t) represent the energy, in every case, since the last over- flow event. for this reason, software must keep track of overflow and make adjustments accordingly when using this register set. to calculate the enr_cc register value, begin with the full-scale voltage and full-scale current, the frame time, and the desired lsb value for energy. then perform the following calculation: example: it is essential to ensure that the correct units are maintained throughout the calculation. in this exam-ple, assume that the full-scale voltage is 558.1v, the full-scale current is 102.4a, the frame time is the default of 320s, and the desired lsb is 100 milliwatt-hours after the 32 bits are discarded; that is, the lsb is 0.1 x 2 -32 watt-hours. notice, however, that the frame time is given in microseconds and must be converted to hours before the calculation can be performed: 320s is 88.9x 10 -9 hours. so the calculation proceeds as follows: 102.4 x 558.1 x 88.9 x 10 -9 /(2 16 x 0.1 x 2 -32 ) = 3329 = 0x0d01 enr cc ivt enr lsb fs fs fr _ _ = 2 16 pwr cc iv pwr lsb fs fs _ _ = 2 32 volt cc v volt lsb fs _ _ = 2 24 amp cc i amp lsb fs _ _ = 2 24 downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe ______________________________________________________________________________________ 55 meter pulse the purpose of a meter pulse is generally to advance amechanical counter when such a device is used as a display. meter pulses are also used during calibration since time intervals can be measured with great preci- sion. the MAXQ3181 supports one meter pulse output. this output can be configured for either active positive or active negative pulses by means of the popol bit in the opmode1 register. when triggered, the pulse goes to its active state and remains there for a period of time defined by the pls1_wd register, and then returns to the inactive state (unless triggered again). the pls1_wd register contains the time in adc frame periods that the pulses remain in the active state when triggered. by default, this register contains decimal 156 (0x9c) giving, at the default frame rate, a pulse width of 50ms. among the quantities that can be accumulated by the pulse subsystem are the arithmetic active energy (that is, the accumulated positive real energy minus the accumulated negative real energy) and the absolute active energy (that is, accumulated positive real energy plus accumulated negative real energy). other quanti- ties include rms voltage and current, positive and neg- ative real energy. select the desired accumulation value in the qnsel field of the plscfg1 register. also in the pulse configuration registers you can select which phases to include in the accumulation. set any or all the phasea, phaseb, and phasec bits in the plscfg1 register to include them in the accumulation. generating pulses on every dsp cycle, the MAXQ3181 adds the value inthe selected register (or set of registers) to the pulse accumulator. if the value in the pulse accumulator exceeds the value in the associated threshold register (thr1), then a pulse is started and the value in the threshold register is subtracted from the value in the pulse accumulator. meter constant a meter constant is the number of pulses that are gen-erated during a standard measurement interval; for example, a meter might specify a meter constant of 1600 pulses per kilowatt-hour. the thr1 register is used to specify the meter constant according to the fol- lowing formula: in this formula, thr is the value to be written to thethreshold register, k m is the desired meter constant (in pulses per kilowatt hour), i fs and v fs are the full-scale voltage and current, respectively, and t fr is the frame period in units of hours, as in the previous calculation.as an example, assume once again a full-scale voltage value of 558.1v = 0.5581kv, a full-scale current value of 102.4a, a desired meter constant of 1600 pulses per kilowatt hour, and a default frame time of 320s (88.9 x 10 -9 hours). the threshold register value can be calcu- lated as: 65,536/(1600 x 102.4 x 0.5581 x 88.9 x 10 -9 ) = 8,063,071 = 0x7b085f increasing the value of the threshold register reduces the meter constant (that is, there are fewer pulses perkilowatt-hour); reducing the threshold register increases the meter constant (that is, there are more pulses perkilowatt-hour.) interrupts the MAXQ3181 contains an interrupt subsystem torelieve the host processor of the burden of constantly polling the device for status. instead, under certain cir- cumstances, the MAXQ3181 can activate an external pin to alert the host processor that some condition requiring host attention has occurred. interrupts are managed globally by the irq_mask and irq_flag registers. in general, when a bit becomes set in the irq_flag register, an interrupt is generated if the corresponding bit is set in the irq_mask register. interrupts can be configured for the following conditions: pwrf: this flag indicates the v dvdd to the MAXQ3181 has fallen below its nominal operatingthreshold (about 2.85v). this can be taken as an indication that power failure is imminent and that the host processor should begin taking steps to ensure an orderly shutdown. chsch: this flag indicates that the chksum regis- ter changed its value.eovf: energy overflow. this flag indicates that one or more energy accumulators (x.eapos, x.eaneg, etc.)have overflowed. in a traditional meter, the host processor would poll the MAXQ3181 to determine which of the energy accumulators have overflowed and adjust its internal accounting registers accordingly. oc: the rms current value on one or more of the phases over the most recent dsp cycle has exceed-ed the value set in the oclvl register. thr ki v t mfs fs fr = 2 16 downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe 56 ______________________________________________________________________________________ ov: the rms voltage on one or more of the phases over the most recent dsp cycle has exceeded thevalue set in the ovlvl register. uv: the rms voltage on one or more of the phases over the most recent dsp cycle has failed to exceedthe value set in the uvlvl register. nozx: zero crossings were not detected on one or more of the phases. the detection time is defined inthe nzx_timo register. the resolution for the nzx_timo register is the duration of one adc sam- ple time (nominally 40s). dcha: tells the host processor that the direction of net real energy flow on one of the three phases haschanged during the current dsp cycle as compared to the previous dsp cycle. dsprdy: indicates the latest dsp cycle has just completed.dspor: indicates that the processing for the previ- ous dsp cycle had not been completed before thecurrent dsp cycle became available for processing. this overflow indication should never be seen in the default configuration; however, under some condi- tions (faster adc rate, slower cpu clock) the pro- cessing requirements may exceed the number of cpu cycles available for dsp processing. under these circumstances, the clock rate may be increased, the adc rate may be reduced (that is, the r_adcrate register may be increased). note that when dspor becomes set, all dsp calcu- lations as well as the pulse output are invalidated. the appropriate host response is to take the remedi- al action described above and discard the current set of dsp result values. each phase has a local register that contains copies ofthe oc, ov, uv, nozx, and dcha bits. thus, to deter- mine which phase(s) have exception conditions requires four reads: the irq_flag register to deter- mine which conditions are active that are causing the interrupt to occur, and then a read to a.flags, b.flags, and c.flags to determine which of the phases have the indicated condition. finally, each phase has a pair of local registers that contain overflow flags for each energy accumulator. if the eovf bit is set in the irq_flag register, the host should then read the a.eover, b.eover, and c.eover registers to determine which of the phases have overflow conditions. overvoltage and overcurrent detection the MAXQ3181 detects overvoltage and overcurrentevents and can issue interrupt request signals to the master when these events occur. the overvoltage level can be programmed into the ovlvl register, while the overcurrent level is determined by the oclvl register. both ovlvl and oclvl registers represent the bits 23:8 of the vrms or irms registers. any time the MAXQ3181 detects the rms-value exceeding a thresh- old level, the ov or oc interrupt flag is set. if enabled, any of these flags issues an interrupt request. all inter- rupt flags are sticky bitsthe MAXQ3181 never clears them on its own unless a reset occurs. the inter- rupt flags should be cleared by the master by writing the appropriate register. meter units to real units conversion all energy calculations, including various thresholdchecks, are performed internally in fixed format in meter units. therefore, the threshold values must be supplied by the user in meter units as well. this section summa- rizes how to convert real units (v, a, kwh, w, and kah) into meter units and vice versa. the conversion factors are based on the settings of t fr , v fs , and i fs , defined by the users design. t fr is analog scan frame timing. this parameter is defined by the r_adcrate setting and system clockfrequency f sys : t fr = (r_adcrate + 1) x 8/f sys default conditions are r_adcrate = 319, f sys = 8mhz. v fs is full-scale voltage. this is the input voltage that produces full-scale adc output; defined by the hard-ware voltage transducer ratio v tr and adc full-scale input voltage v fsadc : v fs = v fsadc x v tr default conditions are v fsadc = 1.024v. v tr is design dependent.i fs is full-scale current. this is the input current that produces full-scale adc output; defined by the hard-ware current transducer ratio i tr and adc full-scale input voltage v fsadc : i fs = v fsadc x i tr default conditions are v fsadc = 1.024v. i tr is design dependent.meter units are defined with respect to the base para- meters as shown in table 5. downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe ______________________________________________________________________________________ 57 when reading virtual registers, the MAXQ3181 uses theconfigurable conversion coefficients amp_cc, volt_cc, pwr_cc, and enr_cc to return meaningfuldata. table 6 describes how to set the coefficients. table 6. virtual register coefficients virtual register output resolution (1 lsb), defined by user coefficient power: pwrp.x, pwrs.x pwr_lsb pwr_cc = mu_pwr/pwr_lsb voltage: v.x volt_lsb volt_cc = mu_volt/volt_lsb current: i.x amp_lsb amp_cc = mu_amp/amp_lsb energy: enrp.x, enrs.x enr_lsb enr_cc = mu_enr/enr_lsb register or accumulator meter unit (1 lsb) current rms: x.irms pulse output current rms thr1, when pulse output configured to irms mu_amp = i fs /2 24 voltage rms: x.vrms pulse output rms voltage thr1, when pulse output configured to vrms mu_volt = v fs /2 24 energy: x.act, x.app, x.eapos, x.eaneg, x.es pulse output energy: thr1 mu_enr = v fs x i fs x t fr /2 16 power: pwrp.x, pwrs.x mu_pwr = v fs x i fs /2 32 when x.esf contains amp-hours: x.esf mu_ah = i fs x t fr /2 16 oclvl, noload, i1thr, i2thr i fs /2 16 ovlvl, uvlvl v fs /2 16 table 5. meter unit definitions downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe 58 ______________________________________________________________________________________ units conversion examples the conversions from meter units to physical units areillustrated with the simplified input circuits in figures 13 and 14. the voltage input circuit is a voltage-divider. current input is through a current transfer with turn ratio of 2000:1. the voltage transducer ratio (v tr ) = (r1 + r2)/r2 = 545, v fs = 558.1v. the current transducer ratio (i tr ) = ct_n/(2 x r) = 2000/(2 x 10) =100 (a/v), i fs = 102.4a. the input circuits should be designed to avoid gettingtoo close to the adc input full sale at the specified maximum ratings. so for the above circuits, we would specify the maximum input current = 70a (rms) and maximum voltage = 390v (rms), to ensure that peak of sinusoudal waveform never exceeds i fs or v fs . use the default adc timing t fr = 320s, we get the fol- lowing meter unit to physical unit conversion coeffi-cients (these coefficients are not part of the MAXQ3181 registers): mu_amp = i fs /2 24 = 6.1e-6 (a) mu_volt = v fs /2 24 = 33.3e-6 (v) mu_pwr = v fs x i fs /2 32 = 13.3e-6 (w) mu_enr = v fs x i fs x t fr /2 16 = 77.5e-9 (wh) for example, if we get 0x07654af0 from reading0x1cc register (phase a current rms), the current value it represents is 0x07654af0 x mu_amp = 47.33 (a) for some low-end host microcontrollers, doing theabove math multiplication above could be difficult. for this reason, the MAXQ3181 provides conversions for some commonly needed parameters through the volt_cc, amp_cc, pwr_cc, and enr_cc registers. for example, if you want to display current in the reso- lution of 1ma, without having to use a multiplication operation to convert from the meter unit value0x07654af0, you would set amp_cc to 0x0190, and read from virtual register 0x831 (phase a rms current). the output would be 0xb8e45170. dropping the lower 2 bytes (right shifting 16 bits) gives 0xb8e4, or 47332 decimal (47332ma). amp_cc is computed as follows: amp_cc = (i fs /2 24 )/amp_lsb = mu_amp/amp_lsb amp_lsb = 0.001/2 16 (a) i fs = 102.4a amp_cc = (102.4/2 24 )/(0.001/2 16 ) = 400d = 0x0190 calibration procedure calibration overview calibration ensures that the recorded voltage, current,energy, and power are in accordance with the design criteria. before creating a calibration regimen, establish the fundamental units of the meter: the full-scale volt- age and current. then adjust the gain registers using calculated calibration constants to produce the expect- ed reading in the raw current, voltage, energy, and power factor registers. the calibration constants should be stored in non- volatile memory by the host microcontroller. upon any reset or loss of power, the host microcontroller must reload the MAXQ3181 with the constants. calibration always follows a set of fundamental steps: ? apply a known signal (voltage/current/power) to the meter. ? read the meter. ? calculate the correction factor based on the differ- ence between the applied signal level and the meterreading. ? write the correction factor to the appropriate register. MAXQ3181 i0p vcomm ia (ac) i0n r 10 r 10 figure 14. sample current input circuit MAXQ3181 vop va (ac) vn r2 1k r1 544k figure 13. sample voltage input circuit downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe ______________________________________________________________________________________ 59 ? read the meter quantity again to verify the calibra- tion. note that these steps can occur more than once for agiven signal type to verify readings at different signal levels. there are two methods to read the meter in the above second step. the first is to read the raw register associ- ated with the value under calibration, for example, a.vrms for the phase a voltage channel; a.irms for the phase a current channel, and a.act for phase a real power. the second calibration method assigns a pulse output to the value being calibrated and measures the pulse period. in practical use, the method chosen depends on the specific application and the available equip- ment. for example, in some applications the voltage and current are of no concern, but the energy accumu- lation must be very accurate. for these applications, meter calibration sets with built-in pulse measurement facilities can make the most sense. the calibration procedure involves the following gener- al steps: ? calibrate voltage for a given phase by applying a known voltage and adjusting the voltage gain(a.v_gain for phase a) until the rms voltage (a.vrms for phase a) reads the applied voltage in the designated units. ? calibrate current by applying a known current and adjusting the current gain (a.i_gain for phase a)until the rms current (a.irms for phase a) reads the applied current in the designated units. if desired, the current can be calibrated at two points (low range and high range) for more accuracy. ? once the current gain and voltage gain are calibrat- ed, the power/energy should not require any addi-tional adjustment for most situations. although, a separate power gain register is available for further fine-tuning of the power/energy accuracy. one must keep in mind that anytime voltage or current is recali- brated, the power or energy accuracy is naturally affected. so the power gain should be recalibrated to achieve the desired accumulative effect of voltage, current, and power gains. ? calibrate the phase offset by applying a power factor load and adjusting the phase angle offset according-ly. if desired, the phase offset can be calibrated at up to three points for more accuracy. once these elements are calibrated for each phase, allother information (power factor, apparent power, etc.) is also properly calibrated. the descriptions in the follow-ing sections deal specifically with phase a, but the same procedure is followed with phases b and c. calibrating voltage ensure that there is no previous value in the gain regis-ter, a.v_gain, by setting this register to 0x4000. ? apply a known voltage with rms value close to the desired maximum operating voltage (and less thanv fs / 2). ? read the a.vrms register. note the value. ? convert the known value to meter units by dividing it by mu_volt (= v fs /2 24 ). ? divide the applied value (in meter unit) by the value read from the MAXQ3181. the result should be avalue between 0 and 2. if the value falls outside of this range, you have probably miscalculated v fs . ? multiply the calculated value by 2 14 . the result is the gain value to be programmed into a.v_gain. ensurethe most significant bit is 0. when the gain value is programmed, wait for 2 to 3seconds, reread the rms value from a.vrms. check that the measured value is correct by comparing a.vrms against the applied voltage in meter unit. voltage calibration example assumptions: v fs is 558.1v. the applied voltage is 240 vrms. ? convert the applied voltage to meter units. this cal- culation gives 240 x 2 24 /558.1 = 7,214,714 = 0x006e1679. ? read the a.vrms register. you read 0x0708029. this is 7,372,841 decimal. ? divide the applied voltage by the voltage read from the meter. the result is 7,214,714/7,372,841 =0.97855. ? convert to integer by multiplying 2 14 : 16,384 x 0.97855 = 16,033 = 0x3ea1. write this value to thea.v_gain register. calibrating current ensure that there is no previous value in the gain regis-ter, a.i_gain, by setting this register to 0x4000. ? apply a known current with rms value close to the desired maximum operating current (and much lowerthan i fs / 2). ? read the a.irms register. note the value. ? convert the known value to meter units by dividing it by mu_amp (= i fs /2 24 ). downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe 60 ______________________________________________________________________________________ ? divide the applied value (in meter unit) by the value read from the MAXQ3181. the result should be avalue between 0 and 2. if the value falls outside of this range, you have probably miscalculated i fs . ? multiply the calculated value by 2 14 . the result is the gain value to be programmed into a.i_gain. ensurethe most significant bit is 0. when the gain value is programmed, wait for approxi-mately 2 to 3 seconds, then reread the rms value from a.irms. check that the measured value is correct by comparing a.irms against the applied current in meter unit. calibrating phase offset phase offset calibration should be performed after thevoltage and current gains have been calibrated. to cal- ibrate the phase offset, it is first necessary to measure the power reported by the meter at two different phase points. the best way to do this is to rely on the pulse output of the meter; use a precise counter to determine the power reported by the meter by counting the pulse period. a load of power factor 0.5l or 0.5c is a good choice for calibrating phase offset. 1) apply a known pure resistive load to the meter. read the measured power, as p 1.0 . 2) shift the phase of the current by +60 (power factor of 0.5c). read the measured power, as p 0.5c . 3) the phase offset pa 0.5c is computed from the equation: tan(pa 0.5c ) = (1 - 2p 0.5c /p 1.0 )/ if an inductive load (pf = 0.5l) is applied, thephase offset equation becomes: tan(pa 0.5l ) = (2p 0.5l /p 1.0 - 1)/ these equations can be expressed in terms of rela-tive errors, where e 1.0 , e 0.5c , and e 0.5l are the power relative errors at pf = 1.0, 0.5c, and 0.5lrespectively. 4) solve for pa from one of the above equations. 5) convert pa into integer number, by multiplying it by 2 16 . 6) convert to hex value and write to the appropriate register. note that MAXQ3181 supports three offset valuesx.pa2, x.pa1, and x.pa0corresponding to the low, mid, and high range of the input signals, respectively. calibrating at the three loading levels could become necessary if the phase error introduced by the current sensors varies significantly with the input levels. registers i1thr and i2thr define the limits of the ranges. if i1thr and i2thr are left at their default val- ues of 0x0000, x.pa0 is applied to the full input range. phase offset calibration example make sure x.pa0, x.pa1, and x.pa2 are cleared before proceeding with calibrations. assume the phase a has been calibrated for a.vgain and a.igain at ib (= 10a). at pf = 1.0, the active power relative error is e 1.0 = -0.4%. set input to i = ib and pf = 0.5l. the relativeerror reported by the meter tester is e 0.5l = 1.2%. solve for pa 0.5l from the following equation: where pa 0.5l = 0.009274437 (radians) = 0.53 and x.pa0 = 0.009274437 x 2 16 = 607.8095 = 0x0260. write 0x260 to a.pa0 (address 0x13e). if multirangecalibration is required, repeat the above procedure at the desired input levels. the input levels for calibration should be selected based the phase error characteris- tics of the current sensors. interfacing the MAXQ3181 to external hardware the MAXQ3181 has all the internal circuitry that isneeded for a sophisticated electricity meter, but specif- ic external hardware is required when configuring the meter for a particular application. the most critical decision that must be made is how the load will be con- nected to the power source, and how the meter will be connected to measure power consumed in the load. this section covers how to select hardware compo- nents for a MAXQ3181 electricity meter. tan( ) () ./ . . .. . pa ee e l l 05 10 05 10 31 0 4 100 1 = + + = + 2 2 100 1 0 4 100 3 0 009274703 / (./) . = tan( ) () . .. . pa ee e l l 05 10 05 10 31 = + + tan( ) () . .. . pa ee e c c 05 10 05 10 31 = + 3 3 v lab meter v unit under test load line neutral figure 15. offset testing setup downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe ______________________________________________________________________________________ 61 connections to the power source generally, three-phase power as delivered from the util-ity consists of four wires: three voltage phases and a neutral wire. in one typical three-phase delivery system, measuring from neutral to any phase would read 120v, while measuring from any phase to any other phase would read 208v. connecting a load so that load cur- rent is taken from phase lines and returned to neutral is called a wye-connected load. connecting a load so that load current is provided by one phase and returned on another phase is called a delta-connected load. the MAXQ3181 can measure power consumed in either a wye-connected or a delta-connected load. if the load is connected in a wye fashion, the voltage is measured from the neutral lead to each of the phases, and the current measuring device is placed in series with the load, most often in the hot lead. the sensor is not placed in the neutral lead to prevent a customer from defrauding the utility by returning the current to ground rather than neutral. a current sensor placed in the hot lead makes fraud even more difficult. a delta-connected load can have current measured in two possible ways. if it is primarily desirable to know how much power is delivered to the load, one can place the current sensor in the load circuit between two phas- es. but if it is more important to know how much current is being drawn from each supply phase, each current sensor is placed in the line circuit of each single phase. most utilities are only concerned with the total amount of energy being consumed. if individually accounting for the power delivered by each phase is not a require- ment, it is not necessary to measure all three voltages. instead, knowing only two voltages and the three cur- rents is all that is necessary to measure total energy usage. there are several ways of doing this. in a wye arrange- ment, one of the phasesusually phase bCcan be considered the voltage reference point instead of neu- tral. then the voltage measurements can be made from phase a to phase b and from phase c to phase b. by using some simple arithmetic, the power delivered by phase a, phase b, and phase c can be calculated even though only two voltages are available. a second mechanism is to have a delta-connected load, but with one legusually the bc legsplit into two equal loads. the point where the load is split is defined as the reference. in this arrangement, it is only necessary to know the voltage between phase c and the split and phase a and the split, since v c = -v a . finally, there is the connection arrangement in whichthe load is in a delta configuration with the current sen- sor at each load, but it is still desired to determine how much current is in each supply branch. the MAXQ3181 supports all of these connection arrangements. sensor selection the MAXQ3181 supports a variety of voltage and cur-rent sense elements. this section describes the proper- ties of many of these sensing devices. voltage sensors voltage-divider a voltage-divider is an ideal voltage-sensing elementwhen there is no need for voltage isolation. modern resistors have virtually no parasitic capacitance or inductance at the frequencies of interest in an electrici- ty meter and have extremely low variation with tempera- ture. when selecting resistors for a voltage-divider, keep the division ratio high enough so that the peak voltage value cannot exceed the maximum allowable input voltage. in the MAXQ3181, the peak input voltage is about 1v; consequently, a divider in the range of 400:1 to 600:1 is ideal. the second consideration is the total power dissipation and voltage hold-off requirements of the resistor. it is tempting to design a 400:1 divider with a 400k resis- tor in series with a 1k resistor, but that would force the 400k resistor to dissipate about 140mw. this is not an excessive amount of power, but if the design is to usesmall smt parts, it can handle greater than a 1/10w smt resistor. it is better to use a series of several small- er components to improve system reliability. voltage transformer if isolation is required between the meter electronicsand the line, a voltage transformer is required. a volt- age transformer is designed to faithfully transfer an ac voltage applied on the primary side to a sensor on the secondary side. on the primary side, a voltage-divider is used to reduce the voltage to a workable level. on the secondary side, a load resistor is selected so that the current in the transformer windings is safely within the transformers linear operating region. because the impedance seen in the primary side of the transformer is equal to the impedance of the load resis- tor in the secondary circuit plus impedance of the transformer secondary winding at the operating fre- quency, it is easy to calculate the value of the required voltage-divider resistors in the primary side. for exam- ple, assume we want a 500:1 divider ratio and assume downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe 62 ______________________________________________________________________________________ the load resistor is 600 and that the impedance of the transformer secondary is 200 . the resistor required in the primary is (600 + 200) x 500 = 400k often, this resistor is constructed from multipleinstances of a smaller value resistor; in this case, one might use eight 50k resistors. doing so minimizes the voltage requirements for the resistor chain and reducesthe possibility that a single point of failure will cause a catastrophic failure. current sensors current shunt a current shunt is a low-value (approximately 100 to a 100m ) resistor that converts a large-value current into a small voltage. shunts make good current sensorsbecause the output is an extremely linear representa- tion of the measured current, current shunts can have very low temperature coefficients, and they are inex- pensive. the power dissipated by a current shunt is inversely proportional to its resistance and proportional to the square of the output voltage. consequently, there is great incentive to reduce the resistance (and hence, the output voltage) of a shunt. often, full-scale current in a shunt produces only a few millivolts of output, mak- ing a front-end amplifier essential. the MAXQ3181 includes a gain-of-32 amplifier in the current channels that is automatically cycled in and out, depending on the input voltage of the current channels. current shunts operate at line voltage, thus, the afe must be isolated from the line. that means that in a wye-connected meter, the current sensing must be per- formed in the neutral return circuit (so that all voltages into the current-sense amplifiers are referenced to neu- tral). it also means that the use of a shunt is precluded for delta-connected meters; the MAXQ3181 cannot tol- erate the line-voltage differential between channels. current transformer in a current transformer, the primary is usually one turnof thick wire or buss bar and the secondary is often 1000 turns or more of magnet wire. a ferrite core mag- netically couples the two. thus, a large current in the primary turn creates a small current but large voltage in the secondary winding. for example, assume a current transformer with a 1000 turn secondary. a 10a current in the primary winding induces a 10ma current in the secondary. this current is made to flow through a so-called burden resistor, usually 10 to 20 . assuming a 20 burden, our 10a current thus produces a 200mv signal in the secondary. advanced operation modifying the adc operation there are several other registers that directly affect theafe function. these registers directly affect the hard- ware functionality, and should be modified only when it is explicitly required. for example, if the MAXQ3181 is operated at some frequency other than the nominal 8mhz system clock, modification of these registers by supervisory code becomes necessary to maintain a 320s frame time. ? r_acfg: this register contains bits that disable the adc entirely, disable the voltage reference bufferamplifier, and disable the adc interrupt. modifying this register will likely disable or impair operation of the MAXQ3181 internal firmware. ? r_adcrate: modify this register to change the rate at which the MAXQ3181 acquires samples. bydefault, r_adcrate contains 319 decimal, which means that the adc acquires a sample every 320 system clocks. with an 8mhz clock, this translates to 40s. if the system clock is slower, it may be advan- tageous to reduce this value to keep a 40s per sam- ple time constant. ? r_adcacq: modify this register to change the acquisition time. the acquisition time is the time fromadc power-on until conversion starts, and is provid- ed to allow the input amplifiers to settle. by default this is set to 47 decimal, or 6s at an 8mhz system clock. if the system clock rate is changed, then r_adcacq should change so that this value remains about 6s. fine-tuning the dsp controls fine-tuning the line frequency measurement line frequency measurement is based on zero-crossingdetection. for that purpose each voltage signal is passed through a digital lowpass filter, controlled by the zc_lpf register. this register specifies the b 0 coef- ficient of a first-order lpf using following formula:the msb of this register must be zero. for each phase a, b, and c, the MAXQ3181 counts the number of scan frames (ns) between zero crossings within a dsp cycle. each individual phase a, b, or c zero-crossing event contributes the raw ns count that plugs as input to lowpass filter: y n = y n - 1 + (avg_ns/65,536) x (x n - y n - 1 ) b zc lpf 0 16 2 = _ downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe ______________________________________________________________________________________ 63 the filter coefficient is a signed 16-bit value and can beconfigured by master. here y denotes the global ns value, x denotes individual ns measurements pro- duced by zero-crossing events detected on the phase a, b, or c voltage channel. note that if all three phase voltages present, the filter above receives three inputs each dsp cycle. the global ns value is used to gener- ate the trigger for dsp processing. note that the ns value can be configured by the master, which could be necessary if all three voltage signals are lost and no zero-crossings are detected. the line period is then calculated as a product of ns and the scan frame t fr . the reciprocal of this value is the line frequency, whichcan be obtained as a fixed-point value with 1 lsb = 0.001hz by reading the linefr register. low-power measurement mode (lowpm) this mode enables a subset of metering functions whileoperating from the lower frequency internal rc oscilla- tor to conserve power. the actual system clock fre- quency used is the rc oscillator output frequency divided by 8, which results in a system clock frequency of approximately 1mhz. the parameters provided in the lowpm are: ? voltage rms ? current rms ? ampere-hour the ampere-hour value is readable from the x.esf reg- isters (x = a/b/c). entry to lowpm mode only occurs at the request of the master. the master must set the lowpm_e bit (register address 0xc03) to 1 to place the MAXQ3181 into lowpm mode. entering lowpm mode changes the clock frequency, thereby invalidat- ing a number of configuration registers. as a result, the master must immediately reload the configuration regis- ters and filter with new, updated values before metering measurement operations can continue. the master instructs the MAXQ3181 to exit lowpm mode by reading the lowpm_x bit (register address 0xc04). temperature the MAXQ3181 contains a temperature sensor that canbe used by host software for any purpose, including compensating power readings for temperature effects. use the virtual register command (rawtemp, 0xc01) to perform a temperature conversion. the MAXQ3181 returns raw adc reading of voltage produced by the temperature sensor. conversion from the arbitrary units to useful units (such as degrees celsius) requires taking one calibration point and storing a conversion constant in the hostprocessor. the conversion constant is simply the value (in absolute degrees) of one lsb. to calculate the lsb value, take a reading at a known temperature and divide the known temperature by the reading. for example, assume you take a reading at room temperature (23c), and the reading is 0x7f00. the degrees per lsb are then: (23 + 273.15)/0x7f00 = 0.00911k now, assume at a later time you read the temperatureand see it is 0x84f0. to find the temperature in celsius, multiply by the degrees per lsb and subtract 273.15: 0x84f0 x 0.00911 - 273.15 = 36.8 c advanced calibrations calibrating current offset ideal hardware should produce a current reading lin-early proportional to the input current. however, due to noise or other factors, the rms current read by the meter might not be precisely linear. the current offset (x.offs_hi, x = a/b/c) can be used to compensate the current channel nonlinearity. since the MAXQ3181 tracks the input current to deter- mine what linearity compensation factors to use, the user must choose two points (i lo and i hi ) comfortably above the low current threshold, and get the x.irmscurrent readings (r lo and r hi ). then calculate the y-inter- cept of the line drawn between the two points, that is,the offset. to calculate the value for the offset register, use the following formula. if linfrm = 0: if linfrm = 1: in this equation, i hi and r hi are the applied current and the current reading, respectively, in meter units at thehigher of the two reference currents; i lo and r lo are the applied current and the current reading, respectively, inmeter units at the lower of the two reference currents. the gain (x.i_gain) may require recalibration after the offset register updated. calibrating linearity the current channel includes a variable-gain amplifierthat introduces a gain of 32 when the current falls below the low current threshold (about 1/32 of full-scale current i fs ). because the gain of the amplifier cannot offs ri ir ii hi lo hi lo lo hi = () 2 4 offs ri ir ii hi lo hi lo hi lo = 22 22 24 2 2 2( ) downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe 64 ______________________________________________________________________________________ be controlled with arbitrary precision, and becausehigh gain implies increased noise, it may be necessary to calibrate the MAXQ3181 to maintain linearity at the lowest inputs. there are two settings that manage low-current lineari- ty: an offset setting, offs_lo; and a gain setting, gain_lo. setting the offset is simple. ensure no cur- rent is flowing in the current circuit. read x.irms. to calculate offset use following formula: if linfrm = 0: if linfrm = 1: offs = -x.irms program the offs into the offs_lo register.so, if the user reads 0x0113 from the x.irms register and linfrm = 1, program 0xfeed into the offs_lo register. setting the gain_lo register means applying a current below the low-current threshold, reading the value from the MAXQ3181, and adjusting the gain accordingly. note that, unlike offset, the low-end gain is added to the overall gain provided in the i_gain register.apply a known current with peak value less than the low-current threshold. ensure that there is no previous value in the low-current gain register, a.gain_lo, by setting this register to 0x4000. read the a.irms regis- ter (0x1cc). note the value. convert the known value to meter units by multiplying the known value (in amperes) by 2 24 and dividing by i fs . divide the results of this cal- culation by the value read from the MAXQ3181. theresult should be a value between 0 and 2. convert the integer by multiplying 2 14 , and ensure msb is zero. the result is the gain value to be programmed intoa.gain_lo. calibrating power/energy gain once voltage and current have been calibrated, theenergy and power calculation automatically reflects the calibrated voltage and current. however the energy gain factor (x.e_gain, x = a/b/c) can be further tuned to achieve even more accurate power and energy result if necessary. for example, if the voltage and cur- rent calibration sources are not as accurate as the power/energy calibration source, then the additional gain calibration may be necessary. the following pro- cedure for power/energy gain calibration is outlined for phase a. ? apply a precision unity power factor power (applied value) that is close to the desired normal operatingpoint. ? read the pwrp.a register. note the value. ? convert the applied value to meter units by dividing it by mu_pwr. ? divide the applied value (in meter unit) by the value read from the MAXQ3181. the result should be avalue between 0 and 2. if the value falls outside of this range, i fs and/or v fs have probably been mis- calculated. ? multiply the calculated value by 2 14 , and ensure the msb is zero. the result is the gain value to be pro-grammed into a.e_gain. ? when the gain value is programmed, wait for 1 to 2 seconds, then reread the power value from pwrp.a.check that the measured value is correct by compar- ing pwrp.a against the applied power in meter unit. multipoint phase offset calibration to perform the calibration at three current levels, notethe raw current value (x.irms) at each point. label the current values, from highest to lowest, i 0 , i 1 , and i 2 . program x.pa0, x.pa1, and x.pa2 with the phase offsetvalues calculated at i 0 , i 1 , and i 2 , respectively, as described in the calibrating phase offset section. finally, program i1thr with the average of i 0 and i 1 , and program i2thr with the geometric average of i 1 and i 2 . now as the current changes the phase offset is adjusted accordingly. see figure 16. offs xirms = (. ) 2 16 2 0 1 2 i2thr i1thr pa2 i 2 i 1 i 0 pa1 pa0 input current phase offset figure 16. phase offset vs. input current calibration downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe ______________________________________________________________________________________ 65 advanced register configurations analog scan configuration registers time slot assignment?urrent channel x = a/b/c (scan_ix) (a: 0x008, b: 0x00c, c: 0x00a) these registers configure the time slot normally assigned to current channels a/b/c. we recommend leaving theseregisters at their default values. if they must be reassigned, one must ensure that all the current and voltage chan- nels are reassigned properly so that the MAXQ3181 computes the power/energy parameters as intended by your setup. bit: 7 6 5 4 3 2 1 0 name: adcmx dadcnv reset a: 0x3 0 0 0 0 reset b: 0x4 0 0 0 0 reset c: 0x5 0 0 0 0 bit name function 7:4 adcmx analog input select. this four-bit field determines which of the following analog inputs are sampled during this time slot. 0000 = v0p - vn 0001 = v1p - vn 0010 = v2p - vn 0011 = i0p - i0n (phase a current: 0011) 0100 = i1p - i1n (phase b current: 0100) 0101 = i2p - i2n (phase c current: 0101) 0110 = inp - vn 1xxx = temperature all other values are reserved. 3 dadcnv adc disable. when set, disables the adc for this time slot. 2:0 reserved. downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe 66 ______________________________________________________________________________________ time slot assignment?oltage channel x = a/b/c (scan_vx) (a: 0x009, b: 0x00d, c: 0x00b) these registers configure the time slot normally assigned to voltage channels a/b/c. the user may wish to change thepgg settings to match the voltage sensor. however, it is recommended that the user not modify the adcmx settings. bit name function 7:4 adcmx analog input select. this four-bit field determines which of the following analog input s are sampled during this time slot. 0000 = v0p - vn (phase a voltage: 0000) 0001 = v1p - vn (phase b voltage: 0001) 0010 = v2p - vn (phase c voltage: 0010) 0011 = i0p - i0n 0100 = i1p - i1n 0101 = i2p - i2n 0110 = inp - vn 1xxx = temperature 3 dadcnv adc disable. when set, disables the adc for this time slot. 2:0 pgg programmable gain amplifier select. this three-bit field configures the programmable-gain amp lifier at the front-end of the analog input. the field has the following values: 000 = gain of 1 001 = gain of 2 010 = gain of 4 011 = gain of 8 100 = gain of 16 101 = gain of 32 all other values are reserved and can cause unpredictable behavior if selected. bit: 7 6 5 4 3 2 1 0 name: adcmx dadcnv pgg reset a: 0x0 0 0x0 reset b: 0x1 0 0x0 reset c: 0x2 0 0x0 downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe ______________________________________________________________________________________ 67 time slot assignment?eutral current channel (scan_in) (0x00e) this register configures the time slot normally assigned to the neutral current channel. the user can change thedadcnv bit to enable/disable neutral current sampling. it is recommended that the other bits of this register be left at their default values. bit: 7 6 5 4 3 2 1 0 name: adcmx dadcnv reset: 0x6 1 0 0 0 bit name function 7:4 adcmx analog input select. this four-bit field determines which of the following analog inputs are sampled during this time slot. all other values are reserved. by default, this register is se t to 0110. 0000 = v0p - vn 0001 = v1p - vn 0010 = v2p - vn 0011 = i0p - i0n 0100 = i1p - i1n 0101 = i2p - i2n 0110 = inp - vn 1xxx = temperature 3 dadcnv adc disable. when set, disables the adc for this time slot. 2:0 reserved. downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe 68 ______________________________________________________________________________________ time slot assignment?emperature channel (scan_te) (0x00f) this register configures the time slot normally assigned to the temperature measurement device. this register ismanaged by the firmware and should not be modified by the host. changing this register can result in unpredictable results. bit name function 7:4 adcmx analog input select. this four-bit field determines which of the following analog inputs are sampl ed during this time slot. 0000 = v0p - vn 0001 = v1p - vn 0010 = v2p - vn 0011 = i0p - i0n 0100 = i1p - i1n 0101 = i2p - i2n 0110 = inp - vn 0111 = auto-zero adc 1xxx = temperature by default, this register is set to 1000. 3 dadcnv adc disable. when set, disables the adc for this time slot. 2:0 pgg programmable gain amplifier select. this three-bit field configures the programmable-gain amplifier at the front end of the analog input. the field has the following values: 000 = gain of 1 001 = gain of 2 010 = gain of 4 011 = gain of 8 100 = gain of 16 101 = gain of 32 all other values are reserved and can cause unpredictable behavior if selected. this register is managed by the firmware and should not be modified by the host. bit: 7 6 5 4 3 2 1 0 name: adcmx dadcnv pgg reset: 0x8 1 0x2 downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe ______________________________________________________________________________________ 69 neutral current auxiliary channel configuration (aux_cfg) (0x010) the MAXQ3181 can monitor the rms value of one auxiliary channel in addition to its normal processing. theauxiliary channel configuration register selects which input the auxiliary channel processes and what processing is applied to the auxiliary channel. dsp system configuration system clock frequency (sys_khz) (0x012) this register contains the system clock frequency in khz units. because the default frequency is 8mhz, this registerdefaults to 0x1f40. bit: 15 14 13 12 11 10 9 8 name: reset: 0 0 0 0 0 0 0 0 bit: 7 6 5 4 3 2 1 0 name: enaux aux_mux reset: 0 0 0 0 0 0 0 0 bit name function 15:7 reserved. 6 enaux enable auxiliary channel. when set, enables auxiliary channel processing . 2:0 aux_mux auxiliary channel input select. this three-bit field selects the input to be processed by the auxi liary channel. 001 = i n bit: 15 14 13 12 11 10 9 8 name: system clock frequency high byte reset: 0x1f bit: 7 6 5 4 3 2 1 0 name: system clock frequency low byte reset: 0x40 downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe 70 ______________________________________________________________________________________ cycle count (cycnt) (0x01c) this register contains the number of line cycles that will be accumulated in a single dsp cycle. when cycnt linecycles have been accumulated, the dsp performs power, power factor, and energy calculations. by default, the cycle count is 0x10 (16 decimal). number of scan frames per dsp cycle (ns) (0x040) the ns register defines the fundamental timing for the electricity meter. it defines a dsp cycle in terms the period ofthe adc scan frame. generally, this register is calculated and updated automatically by the MAXQ3181 firmware based on the zero-crossing detection, and whether noise rejection (rej_ns) and averaging (avg_ns) are enabled. host code can write to this register in order to set the desired dsp cycle duration. the duration of one scan frame (t fr ) is represented as 0x00010000. bit: 15 14 13 12 11 10 9 8 name: cycle count high byte reset: 0x00 bit: 7 6 5 4 3 2 1 0 name: cycle count low byte reset: 0x10 bit: 31 30 29 28 27 26 25 24 name: integer portion, high byte reset: 0x03 bit: 23 22 21 20 19 18 17 16 name: integer portion, low byte reset: 0xe8 bit: 15 14 13 12 11 10 9 8 name: fractional portion, high byte reset: 0x00 bit: 7 6 5 4 3 2 1 0 name: fractional portion, low byte reset: 0x00 downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe ______________________________________________________________________________________ 71 filter coefficients line cycle noise rejection filter (rej_ns) (0x02c) this register establishes the sensitivity of the ns rejection filter setting. ns is a measure of the line frequency. if a linecycle occurs that is shorter or longer than the line cycle represented in the ns register, this filter determines whether the cycle is used to update the ns value. for more information, see the ns register description. if this register is zero, noise rejection is disabled for the line cycle counter. line cycle averaging filter (avg_ns) (0x02e) this register determines whether the ns value is averaged over previous values or whether the most recently measuredvalue is used directly. if the value of this register is nonzero, the ns value is averaged using the following formula: if the value of this register is zero, ns is not averaged. the msb of this register must be zero. yy a v gn s xy nn nn =+ 1 1 16 2 _ bit: 15 14 13 12 11 10 9 8 name: line cycle noise rejection filter high byte reset: 0x00 bit: 7 6 5 4 3 2 1 0 name: line cycle noise rejection filter low byte reset: 0xc8 bit: 15 14 13 12 11 10 9 8 name: line cycle averaging filter high byte reset: 0x40 bit: 7 6 5 4 3 2 1 0 name: line cycle averaging filter low byte reset: 0x00 downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe 72 ______________________________________________________________________________________ meter measurement averaging filter (avg_c) (0x030) this register determines whether the all other measured values in the electricity meter are averaged over time. if thevalue of this register is nonzero, all measured meter values are averaged using the following formula: if the value of this register is zero, no averaging is performed. the msb of this register must be zero. meter measurement highpass filter (hpf_c) (0x032) this register specifies the b 0 coefficient of a first-order butterworth filter using the following formula: the msb of this register must be zero. zero-cross lowpass filter (zc_lpf) (0x05a) this register specifies the lowpass filter applied for zero-cross detection. the msb of this register must be zero. b hpf c 0 16 2 = _ yy a v gc xy nn nn =+ 1 1 16 2 _ bit: 15 14 13 12 11 10 9 8 name: meter measurement averaging filter high byte reset: 0x40 bit: 7 6 5 4 3 2 1 0 name: meter measurement averaging filter low byte reset: 0x00 bit: 15 14 13 12 11 10 9 8 name: meter measurement highpass filter high byte reset: 0x00 bit: 7 6 5 4 3 2 1 0 name: meter measurement highpass filter low byte reset: 0xc8 bit: 15 14 13 12 11 10 9 8 name: zero-cross lowpass filter high byte reset: 0x0b bit: 7 6 5 4 3 2 1 0 name: zero-cross lowpass filter low byte reset: 0x00 downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe ______________________________________________________________________________________ 73 hardware mirror registers adc configuration (r_acfg) (0x04c) this register is a mirror of a cpu register in the MAXQ3181. this register should not be modified by supervisorycode. adc conversion rate (r_adcrate) (0x04e) this register specifies the number of system clock cycles between consecutive adc conversions. it defaults to0x13f (319 decimal), which specifies 320 cpu clock cycles between conversions. this register is a mirror of a cpu register in the MAXQ3181. bit: 7 6 5 4 3 2 1 0 name: adcasd adcry adccd adcby adcie arbe adce reset: 0 0 0x0 0 1 1 1 bit name function 7 adcasd disable adc automatic shutdown. normally, the adc analog sectio n is powered off following a conversion to conserve power. if this bit is set, the adc leaves the ana log section powered on following a conversion. 6 adcry adc data ready. when a conversion is complete, this bit is set to in dicate that data is available. this bit generates an interrupt if adcie is set. 5:4 adccd adc clock divider. sets the division ratio between the cpu master and a dc clock. 00 = divide by 1 01 = divide by 2 10 = divide by 4 11 = reserved 3 adcby adc busy. when set, a single adc conversion cycle is in progress. t he bit is cleared on the conclusion of the conversion cycle. 2 adcie adc interrupt enable. if set, the adc interrupts the cp u at the completion of a conversion cycle. 1 arbe reference buffer enable. if set, the reference buffer is enabled to driv e the refo pin. 0 adce adc enable. if set, the adc hardware is activated. bit: 15 14 13 12 11 10 9 8 name: adc conversion rate high byte reset: 1 bit: 7 6 5 4 3 2 1 0 name: adc conversion rate low byte reset: 0x3f downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe 74 ______________________________________________________________________________________ adc settling time (r_adcacq) (0x050) this register is a mirror of a cpu register in the MAXQ3181. this register should not be modified by supervisorycode. this register specifies the time, in cpu clocks, that the adc must wait after switching analog mux inputs before beginning its conversion. this register defaults to 0x2f (47 decimal), which specifies a 48 cpu clock-cycle delay from analog mux switching to the start of conversion. spi configuration (r_spicf) (0x052) this register is a mirror of a cpu register in the MAXQ3181. this register configures the spi port of the MAXQ3181. bit: 15 14 13 12 11 10 9 8 name: adc settling time high byte reset: bit: 7 6 5 4 3 2 1 0 name: adc settling time low byte reset: 0x2f bit: 7 6 5 4 3 2 1 0 name: espii sas chr ckpha ckpol reset: 1 0 0 0 0 0 0 0 bit name function 7 espii enable spi interrupt. if set, arrival of a chara cter on the spi bus causes a cpu interrupt. 6 sas spi slave select polarity. if clear, ssel is assumed to be active low; if set, ssel is assumed to be active high. 5:3 reserved. 2 chr spi character length. if clear, characters on the spi bus are assumed to be 8 bits; i f set, characters on the spi bus are assumed to be 16 bits. 1 ckpha spi clock phase. if clear, data is sampled on the leading edge of th e clock (low-to-high if the clock is active high, and high-to-low if the clock is active low). if set, data is sampled on the trailing edge of the clock (high-to-low if the clock is active high, and low-to-high if th e clock is active low). 0 ckpol spi clock polarity. if clear, the clock is assumed to be active high; if set, the clock is assumed to be active low. downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe ______________________________________________________________________________________ 75 timeouts zero-crossing timeout (nzx_timo) (0x054) this register specifies the time in adc sample periods (default 40s) that must elapse following a zero-crossingevent before the MAXQ3181 declares a no-zero crossing fault. when this fault is declared, the nozxf bit in the x.flags register is set. communications timeout (com_timo) (0x056) this register specifies the duration of spi timeout in adc frames (default 320s). energy accumulation timeout (acc_timo) (0x058) this register specifies the time in dsp cycles that the MAXQ3181 waits before accumulating energy. if this register isnonzero, it is decremented on each dsp cycle. if the result of the decrement is nonzero, the results of the dsp cycle are discarded and are not accumulated to the energy registers. this register is useful for delaying the initiation of energy accumulation on startup or after some hardware function has been modified. bit: 15 14 13 12 11 10 9 8 name: zero-crossing timeout high byte reset: 0x23 bit: 7 6 5 4 3 2 1 0 name: zero-crossing timeout low byte reset: 0x28 bit: 15 14 13 12 11 10 9 8 name: communications timeout high byte reset: 0x03 bit: 7 6 5 4 3 2 1 0 name: communications timeout low byte reset: 0xe8 bit: 15 14 13 12 11 10 9 8 name: energy accumulation timeout high byte reset: 0x00 bit: 7 6 5 4 3 2 1 0 name: energy accumulation timeout low byte reset: 0x05 downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe 76 ______________________________________________________________________________________ phase-angle compensation phase offset current threshold 1 (i1thr) (0x05c) this register specifies the fraction of full-scale current that causes the MAXQ3181 to switch from pa0 to pa1 to pro-vide phase-angle compensation. for more information, see the pa0, pa1, and pa2 register descriptions. the full- scale current is represented by 0x10000. phase offset current threshold 2 (i2thr) (0x05e) this register specifies the fraction of full-scale current that causes the MAXQ3181 to switch from pa1 to pa2 to pro-vide phase-angle compensation. for more information, see the pa0, pa1, and pa2 register descriptions. the full- scale current is represented by 0x10000. miscellaneous gain neutral current gain (n.i_gain) (0x12e) this register contains gain compensation coefficient for the neutral current channel measurement. the raw valuesare taken from the selected measurement quantity and scaled by n.i_gain/2 14 . bit: 15 14 13 12 11 10 9 8 name: phase accumulator current threshold 1 high byte reset: 0x00 bit: 7 6 5 4 3 2 1 0 name: phase accumulator current threshold 1 low byte reset: 0x00 bit: 15 14 13 12 11 10 9 8 name: phase accumulator current threshold 2 high byte reset: 0x00 bit: 7 6 5 4 3 2 1 0 name: phase accumulator current threshold 2 low byte reset: 0x00 bit: 15 14 13 12 11 10 9 8 name: compensation coefficient high byte reset: 0x40 bit: 7 6 5 4 3 2 1 0 name: compensation coefficient low byte reset: 0x00 downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe ______________________________________________________________________________________ 77 linearity compensation linearity offset, high range, phase x = a/b/c (x.offs_hi) (a: 0x138, b: 0x224, c: 0x310) this signed register contains the linearity offset for phase x current channel when the programmable gain amplifieris set to unity gain (that is, the measured current is above the low current threshold). the signed value represented by this register is added to the current value according to following formula: if linfrm = 0: if linfrm = 1: x.irms + x.offs_hi x 2 4 linearity gain coefficient, low range, phase x = a/b/c (x.gain_lo) (a: 0x13a, b: 0x226, c: 0x312) this register contains the linearity coefficient for phase x current channel when the programmable gain amplifier isset to gain of 32 (that is, the measured current is below the low current threshold). the effective gain is given by the equation: xgain lo ._ 2 14 xirms x offs hi .. _ 22 4 2 + bit: 15 14 13 12 11 10 9 8 name: linearity offset high byte reset: 0x00 bit: 7 6 5 4 3 2 1 0 name: linearity offset low byte reset: 0x00 bit: 15 14 13 12 11 10 9 8 name: linearity coefficient high byte reset: 0x40 bit: 7 6 5 4 3 2 1 0 name: linearity coefficient low byte reset: 0x00 downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe 78 ______________________________________________________________________________________ linearity offset, low range, phase x = a/b/c (x.offs_lo) (a: 0x13c, b: 0x228, c: 0x314) this signed register contains the linearity offset for phase x current channel when the programmable gain amplifieris set to gain of 32 (that is, the measured current is below the low current threshold). the signed value represented by this register is added to the current value. the total linearity compensation is applied as follows: if linfrm = 0: x.gain_lo/2 14 x if linfrm = 1: x.gain_lo/2 14 x (x.irms + x.offs_lo) measurements?am registers on-demand rms result (n.irms) (0x11c) this register contains the result of the rms calculation on the aux channel. usually, this is the neutral currentchannel. xirms x offs lo .. _ 21 6 2 + bit: 15 14 13 12 11 10 9 8 name: linearity offset high byte reset: 0x00 bit: 7 6 5 4 3 2 1 0 name: linearity offset low byte reset: 0x00 bit: 31 30 29 28 27 26 25 24 name: rms result, byte 3 reset: bit: 23 22 21 20 19 18 17 16 name: rms result, byte 2 reset: bit: 15 14 13 12 11 10 9 8 name: rms result, byte 1 reset: bit: 7 6 5 4 3 2 1 0 name: rms result, byte 0 reset: downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe ______________________________________________________________________________________ 79 energy accumulated in the last dsp cycle real energy, phase x = a/b/c (x.act) (a: 0x1d0, b: 0x2bc, c: 0x3a8) this signed register provides the raw real energy accumulated over the most recent dsp cycle. for each adc sam-ple period, the real instantaneous power calculated from the instantaneous voltage and current is accumulated. at the end of each dsp cycle, the result of the accumulation over the dsp cycle is copied to this register and is accu- mulated in x.eapos or x.eaneg, depending on the sign of the accumulated energy. lsb of the energy registers is v fs x i fs x t fr /2 16 . apparent energy, phase x = a/b/c (x.app) (a: 0x1d8, b: 0x2c4, c: 0x3b0) this signed register provides the raw apparent energy accumulated over the most recent dsp cycle. bit: 31 30 29 28 27 26 25 24 name: real energy byte 3 bit: 23 22 21 20 19 18 17 16 name: real energy byte 2 bit: 15 14 13 12 11 10 9 8 name: real energy byte 1 bit: 7 6 5 4 3 2 1 0 name: real energy byte 0 bit: 31 30 29 28 27 26 25 24 name: apparent energy byte 3 bit: 23 22 21 20 19 18 17 16 name: apparent energy byte 2 bit: 15 14 13 12 11 10 9 8 name: apparent energy byte 1 bit: 7 6 5 4 3 2 1 0 name: apparent energy byte 0 downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe 80 ______________________________________________________________________________________ checksum (chksum) (0x060) this register contains the calculated 16-bit arithmetic checksum over critical configuration and calibration registers.it is updated on every dsp cycle. in use, the administrative processor records the value in the chksum register and then checks it periodically to verify that no configuration or calibration registers have changed. the MAXQ3181 sets the chsch bit when this registers value changes. the registers included in the checksum calculation include the following: bit: 15 14 13 12 11 10 9 8 name: checksum high byte reset: bit: 7 6 5 4 3 2 1 0 name: checksum low byte reset: sys_khz r_adcrate a.i_gain b.i_gain c.i_gain volt_cc rej_ns r_adcacq a.v_gain b.v_gain c.v_gain amp_cc avg_ns r_spicf a.e_gain b.e_gain c.e_gain pwr_cc avg_c nzx_timo enr_cc hpf_c com_timo a.offs_hi b.offs_hi c.offs_hi cycnt acc_timo a.gain_lo b.gain_lo c.gain_lo plscfg1 oclvl i1thr a.offs_lo b.offs_lo c.offs_lo ovlvl i2thr a.pa0 b.pa0 c.pa0 pls1_wd uvlvl zc_lpf a.pa1 b.pa1 c.pa1 thr1 noload a.pa2 b.pa2 c.pa2 r _ a c f g downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe ______________________________________________________________________________________ 81 neutral current rms current, neutral (i.n) (0x840) this register reports the rms current of the neutral currentchannel. the units are defined by the amp_cc setting. special commands table 7 shows the read-only virtual registers that acti-vate special commands when read by the master. some commands return dummy values. applications information grounds and bypassing careful pcb layout significantly minimizes noise on theanalog inputs, resulting in less noise on the digital i/o that could cause improper operation. the use of multi- layer boards is essential to allow the use of dedicated power planes. the area under any digital components should be a continuous ground plane if possible. keep any bypass capacitor leads short for best noise rejec- tion and place the capacitors as close to the leads of the devices as possible. the MAXQ3181 must have separate ground areas for the analog (agnd) and digital (dgnd) portions, con- nected together at a single point. cmos design guidelines for any semiconductor require that no pin be taken above dvdd or below dgnd. violation of this guideline can result in a hard failure (damage to the silicon inside the device) or a soft fail- ure (unintentional modification of memory contents).voltage spikes above or below the devices absolute maximum ratings can potentially cause a devastating ic latchup. microcontrollers commonly experience negative volt- age spikes through either their power pins or general- purpose i/o pins. negative voltage spikes on power pins are especially problematic as they directly couple to the internal power buses. devices such as keypads can conduct electrostatic discharges directly into the microcontroller and seriously damage the device. system designers must protect components against these transients that can corrupt system memory. specific design considerations for MAXQ3181-based systems to reduce the possibility of coupling noise into themicrocontroller, the system should be designed with a crystal or oscillator in a metal case that is grounded to the digital plane. doing so reduces the susceptibility of the design to fast transient noise. because the MAXQ3181 is designed for use in systems where high voltages are present, care must be taken to route all signal paths, both analog and digital, as far away as possible from the high-voltage components. it is possible to construct more elaborate metering designs using multiple MAXQ3181 devices. this can be accomplished by using a single spi bus to connect all name address description data length (bytes) upd_sfr 0x900 reading this register copies the mirror registers (r_adcf, r_adcr ate, r_adcacq, r_spicf) into hardware sfr registers. the read returns du mmy data. 1 upd_mir 0xa00 reading this register copies hardware sfr registers into mirr or registers (r_adcf, r_adcrate, r_adcacq, r_spicf). the read returns dummy data. 1 dspver 0xc00 reading this register returns the dsp firmwar e version number. 2 rawtemp 0xc01 reading this register initiates the sampling and averaging of two int ernal temperature readings. the result in internal temperature units is read from this register lsb first. use the following equation to convert a raw temperatur e reading to celsius: t[c] = t[raw] x tempfactor - 273.15 where tempfactor is a value to be determined by calibration. note that th e final value may be slightly higher than ambient due to internal die heating. 2 enter stop 0xc02 reading this register places the device into stop mode. 1 enter lowpm 0xc03 reading this register places the device into low pm mode. 1 exit lowpm 0xc04 reading this register exits lowpm mode. 1 table 7. virtual registers that activate special commands downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe 82 ______________________________________________________________________________________ the MAXQ3181 devices together but using separateslave select lines to individually select each MAXQ3181. additional documentation designers must ensure they have the latest MAXQ3181errata documents. errata sheets contain deviations from published specifications. a MAXQ3181 errata sheet for any specific device revision is available at www.maxim-ic.com/errata . technical support for technical support, go to https://support.maxim- ic.com/micro . package type package code document no. 28 tssop u28+3 21-0066 top view MAXQ3181 tssop 25 4 avdd i0n 26 3 v0p i0p 27 2 v1p inp 28 1 v2p vn 22 7 dvdd i2p 23 6 vcomm i1n 21 8 reset i2n 20 9 n.c. agnd 19 10 cfp xtal2 18 11 dgnd xtal1 17 12 dvdd irq 16 13 miso ssel 24 5 vref i1p 15 14 mosi sclk pin configuration package information for the latest package outline information and land patterns, goto www.maxim-ic.com/packages . downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe ______________________________________________________________________________________ 83 MAXQ3181 v0p ssel sclk mosi miso r1 r2 v1p r1 r2 v2p vn vcomm r1 r2 i0pi0n r3r3 i1pi1n i2pi2n voltage sense v a v b v c n current transformer l c l b l a r3r3 r3r3 master typical application circuit downloaded from: http:///
MAXQ3181 low-power, active energy, polyphase afe maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 84 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 7/09 initial release. changed the voltage range on vxp, ixn relative to agnd to -0.3v to +4.0v in th e absolute maimum ratings section. 8 1 12/09 added a statement that the crc be enabled for read and write in the host software design section. 22 downloaded from: http:///

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