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a twinc3400 single chip ieee 802.11 b/g/n network controller with integrated bluetooth 4.0 preliminary datasheet de scription the atmel ? ATWINC3400 is a single chip ieee ? 802.11 b/g/n rf/baseband/mac network controller and bluetooth ? low energy (ble) 4.0 optimized for low - power mobile applications. the ATWINC3400 supports single stream 1x1 802.11n mode providing up to 7 2 mbps phy rate. the ATWINC3400 features fully integrated power amplifier, lna, switch , and power management. ATWINC3400 also features an on - chip microcontroller and integrated f lash memory for system software. implemented in 65nm cmos technology, the atwin c3400 offers very low power consumption while simultaneously providing high performance and minimal bill of materials . the ATWINC3400 utilizes highly optimized 802.11 - ble coexistence protocols. the ATWINC3400 provides multiple peripheral interfaces includi ng uart, spi, i 2 c, and sdio. the only external clock sources needed for the ATWINC3400 is a high - speed crystal or oscillator with a wide range of reference clo ck frequencies supported (14 - 40mhz) and a 32.768 khz clock for sleep operation. the ATWINC3400 is available in qfn packaging . features ieee 802.11 ? ieee 802.11 b/g/n 20mhz (1x1) solution ? single spatial stream in 2.4ghz ism band ? integrated pa and t/r switch ? superior sensitivity and range via advanced phy signal processing ? advanced equalization and channel estimation ? advanced carrier and timing synchronization ? wi - fi direct and soft - ap support ? supports ieee 802.11 wep, wpa, and wpa2 security ? supports china wapi security ? superior mac throughput via hardware accelerated two - level a - msdu/a - mpdu frame aggregation and block acknowledgement ? on - chip memory management engine to reduce host load ? spi, sdio, i 2 c, and uart host interfaces ? operating temperature range of - 4 0c to +85c ? fast boot o ptions: C on - chip boot rom (firmware instant boot) C spi flash boot (firmware patches and state variables) C low - leakage on - chip memory for state variables atmel - 42396 c - smartconnect - atw inc3400_preliminary - datasheet _0 7/ 201 5
ATWINC3400 - datasheet [ preliminary datashee t ] atmel - 42396 c - smartconnect - atw inc3400_preliminary - datasheet _0 7 / 201 5 2 2 C fast ap re - association (150ms) ? on - chip network stack to offload mcu: C integrated network ip stack to minimi ze host cpu requirements C network features: tcp, udp, dhcp, arp, http, ssl, and dns ble ? ble 4.0 ? adaptive frequency hopping ? hci (host control interface) via high speed uart ? integrated pa and t/r switch ? superior sensitivity and range ? uart host and audio inter faces
[ preliminary datashee t ] atmel - 42396 c - smartconnect - atw inc3400_preliminary - datasheet _0 7/ 201 5 3 3 tabl e of cont ent s description ................................ ................................ ................................ ....................... 1 features ................................ ................................ ................................ ....................... 1 table of contents ................................ ................................ ................................ ................. 3 1 ordering information and ic marking ................................ ................................ .......... 5 2 block diagram ................................ ................................ ................................ ............... 5 3 pinout and package information ................................ ................................ ................. 5 3.1 pin description ................................ ................................ ................................ ................................ ...... 5 3.2 package description ................................ ................................ ................................ ............................. 8 4 elec trical specifications ................................ ................................ ............................... 9 4.1 absolute ratings ................................ ................................ ................................ ................................ ... 9 4.2 recommended operating conditions ................................ ................................ ................................ . 10 4.3 dc electrical characteristics ................................ ................................ ................................ ............... 10 5 clocking 11 5.1 crystal oscillator ................................ ................................ ................................ ................................ . 11 5.2 low power oscillator ................................ ................................ ................................ ........................... 12 6 cpu and memory subsystems ................................ ................................ .................. 12 6.1 processor ................................ ................................ ................................ ................................ ............ 12 6.2 memory sub system ................................ ................................ ................................ ............................. 12 6.3 non - volatile memory (efuse) ................................ ................................ ................................ ............. 12 7 wlan subsystem ................................ ................................ ................................ ....... 13 7.1 mac ................................ ................................ ................................ ................................ .............. 13 7.1.1 features ................................ ................................ ................................ ................................ . 13 7.1.2 description ................................ ................................ ................................ .............................. 14 7.2 phy ................................ ................................ ................................ ................................ .............. 14 7.2.1 features ................................ ................................ ................................ ................................ . 14 7.2.2 description ................................ ................................ ................................ .............................. 15 7.3 radio ................................ ................................ ................................ ................................ .............. 15 7.3.1 receiver performance ................................ ................................ ................................ ............ 15 7.3.2 transmitter performance ................................ ................................ ................................ ........ 16 8 ble subsystem ................................ ................................ ................................ ........... 16 8.1 ble radio ................................ ................................ ................................ ................................ ........... 17 8.1.1 receiver performance ................................ ................................ ................................ ............ 17 8.1.2 transmitter performance ................................ ................................ ................................ ........ 17 9 external interfaces ................................ ................................ ................................ ...... 18 9.1 i 2 c slave interface ................................ ................................ ................................ .............................. 19 9.2 i 2 c master interface ................................ ................................ ................................ ............................ 20 9.3 spi slave interface ................................ ................................ ................................ .............................. 21 9.4 spi master interface ................................ ................................ ................................ ............................ 23 9.5 sdio slave interface ................................ ................................ ................................ ........................... 24 9.6 uart ................................ ................................ ................................ ................................ .............. 26
ATWINC3400 - datasheet [ preliminary datashee t ] atmel - 42396 c - smartconnect - atw inc3400_preliminary - datasheet _0 7 / 201 5 4 4 9.7 gpios ................................ ................................ ................................ ................................ .............. 27 10 power management ................................ ................................ ................................ ..... 27 10.1 power architecture ................................ ................................ ................................ .............................. 27 10.2 power consumption ................................ ................................ ................................ ............................ 28 10.2.1 description of device states ................................ ................................ ................................ ... 28 10.2.2 current consumption in various device states ................................ ................................ ...... 29 10.2.3 restrictions for power states ................................ ................................ ................................ . 29 10.3 power - up/down sequence ................................ ................................ ................................ ................. 30 10.4 digital i/o pin behavior during power - up sequences ................................ ................................ ........ 31 11 reference design ................................ ................................ ................................ ........ 31 12 refer ence design guidelines ................................ ................................ ..................... 33 13 reference documentation and support ................................ ................................ .... 33 14 revision history ................................ ................................ ................................ .......... 34
[ preliminary datashee t ] atmel - 42396 c - smartconnect - atw inc3400_preliminary - datasheet _0 7/ 201 5 5 5 1 ordering information and ic marking table 1 - 1. ordering details atmel official part number (for ordering) package type ic marking ATWINC3400 - mu - t 6x6 qfn in tape and reel ATWINC3400 2 block diagram figure 2 - 1. ATWINC3400 block diagram 3 pinout and package information 3.1 pin description atwinc 3400 is offered in an exposed pad 40 - pin qfn package. this package has an exposed paddle that must be connected to the system board ground. the qfn package pin assignment is shown in figure 3 - 1 . the color shading is used to indicate the pin type as follows: ? green C power ? red C analog ? blue C digital i/o ? yellow C digital input ? grey C unconnected or reserved the atwinc 3400 pins are described in table 3 - 1 . x x t x d i g i t a l c o r e d p d 8 0 2 . 1 1 b g n i f f t 8 0 2 . 1 1 b g n c o d i n g h o s t i n t e r f a c e m i c r o c o n t r o l l e r d a c a d c r x d i g i t a l c o r e 8 0 2 . 1 1 b g n o f d m c h a n n e l e s t i m a t i o n / e q u a l i z a t i o n 8 0 2 . 1 1 b g n f o r w a r d e r r o r c o r r e c t i o n r a m 8 0 2 . 1 1 b , g , n m a c ~ s d i o s p i x o p m u i 2 c r t c c l o c k v b a t t p l l g f s k d e m o d 8 p s k & q p s k d e m o d w i - f i / b l u e t o o t h c o e x i s t e n c e f r o n t e n d g f s k m o d u l a t o r 8 p s k & q p s k m o d f r o n t e n d b l u e t o o t h 4 . 0 m a c f r o n t e n d f r o n t e n d u a r t p c m a u d i o i n t e r f a c e g p i o w i n c 3 4 0 0 f l a s h
ATWINC3400 - datasheet [ preliminary datashee t ] atmel - 42396 c - smartconnect - atw inc3400_preliminary - datasheet _0 7 / 201 5 6 6 figure 3 - 1. pin assignment table 3 - 1. pin description pin # pin name pin type description 1 vddrf_rx power tuner rf rx supply (see section 10.1 ) 2 vddams power tuner bb supply (see section 10.1 ) 3 vddrf_tx power tuner rf tx supply (see section 10.1 ) 4 vddbatt_ppa/pa power battery supply for pa (see section 10.1 ) 5 rfiop analog wi - fi/ ble pos rf differential i/o 6 rfion analog wi - fi / ble neg rf differential i/o 7 test_mode digital input test mode C customer tie to gnd 8 sdio_spi_cfg digital input tie to vddio for spi, gnd for sdio 9 gpio_38 digital i/o, programmable pull - down gpio_38 10 gpio_39 digital i/o, programmable pull - up gpio_39 11 gpio_40 digital i/o, programmable pull - down gpio_40 12 gpio_42 digital i/o, programmable pull - down gpio_42 13 resetn digital input active - low hard reset 14 gpio_16 digital i/o, programmable pull - up gpio_16/ ble uart transmit data output 15 gpio_15 digital i/o, programmable pull - up gpio_15/ ble uart receive data input 16 gpio_14 digital i/o, programmable pull - up gpio _14/ ble uart rts output/ i 2 c slave data
[ preliminary datashee t ] atmel - 42396 c - smartconnect - atw inc3400_preliminary - datasheet _0 7/ 201 5 7 7 pin # pin name pin type description 17 gpio_13 digital i/o, programmable pull - up gpi o_13/ ble uart cts input/ i 2 c slave clock/ wi - fi uart tx d output 18 vddc power digital core power supply (see section 10.1 ) 19 vddio_0 power digital i/o power supply (see section 10.1 ) 20 gpio_3 digital i/o, programmable pull - up gpio_3/spi flash clock output 21 gpio_4 digital i/o, programmable pull - up gpio_4/spi flash ssn output 22 gpio_5 digital i/o, programmable pull - up gpio_5/ wi - fi uart tx d output /spi flash tx output (mosi) 23 gpio_6 digital i/o, programmable pull - up gpio_6/ wi - fi uart rxd input/spi flash rx input (miso) 24 vbatt_buck power battery supply for dc/dc converter (see section 10.1 ) 25 vsw power switching output of dc/dc converter (see section 10.1 ) 26 vreg_buck power core power from dc/dc converter (see section 10.1 ) 27 chip_en analog pmu enable 28 rtc_clk digital i/o, programmable pull - up rtc clock input/gpio_1/ wi - fi uart rx d input/ wi - fi uart tx d output/bt uart cts input 29 sd_clk digital i/o, programmable pull - up sdio clock/gpio_8/ wi - fi uart rx d input/bt uart cts input 30 sd_cmd/spi_sck digital i/o, programmable pull - up sdio command/spi clock 31 sd_dat0/spi_txd digital i/o, programmable pull - up sdio data0/spi tx data 32 sd_dat1/spi_ssn digital i/o, programmable pull - up sdio data1/spi slave select 33 vddio_1 power digital i/o power supply (see section 10.1 ) 34 sd_dat2/spi_rxd digital i/o, programmable pull - up sdio data2/spi rx data 35 sd_dat3 digital i/o, programmable pull - up sdio data3/gpio_7/ wi - fi uart tx d output/bt uart rts output 36 gpio_17 digital i/o, programmable pull - down gpio_17 37 gpio_18 digital i/o, programmable pull - down gpio_18 38 gpio_19 digital i/o, programmable pull - down gpio_19 39 gpio_20 digital i/o, programmable pull - down gpio_20 40 irqn digital i/o, programmable pull - up host interrupt request output/ wi - fi uart rx d input/bt uart rts output 41 gpio_21 digital i/o, programmable pull - up gpio_21/rtc clock/ wi - fi uart rx d input/ wi - fi uart tx d output/bt uart rts output 42 host_wakeup digital i/o, programmable pull - up sleep mode control/ wi - fi uart tx d output 43 xo_n analog crystal oscillator n 44 xo_p analog crystal oscillator p 45 vdd_sxdig power sx power supply (see section 10.1 ) 46 vdd_vco power vco power supply (see section 10.1 ) 47 vddio_a power tuner vddio power supply (see section 10.1 ) 48 tp_p analog test pin/customer no connect 49 paddle vss power connect to system board ground
ATWINC3400 - datasheet [ preliminary datashee t ] atmel - 42396 c - smartconnect - atw inc3400_preliminary - datasheet _0 7 / 201 5 8 8 3.2 package description the ATWINC3400 qfn package information is provided in table 3 - 2 . table 3 - 2. qfn package information parameter value unit tolerance package size 6x6 mm 0.1mm qfn pad count 48 total thickness 0.85 mm 0.05mm qfn pad pitch 0.40 pad width 0.25 exposed pad size 4.7x4.7 the ATWINC3400 48 qfn package view is shown in figure 3 - 2 . figure 3 - 2. qfn package atwilc3400 qfn package top view atwilc3400 qfn package bottom view atwilc3400 qfn package side view
[ preliminary datashee t ] atmel - 42396 c - smartconnect - atw inc3400_preliminary - datasheet _0 7/ 201 5 9 9 the qfn package is a qualified green package. 4 electrical specifications 4.1 absolute ratings table 4 - 1. absolute maximum ratings characteristic symbol min . max . unit core supply voltage vddc - 0.3 1.5 v i/o supply voltage vddio - 0.3 5.0 battery supply voltage vbatt - 0.3 5.0 digital input voltage v in - 0.3 vddio analog input voltage v ain - 0.3 1.5 esd human body model v esdhbm - 1000, - 2000 (see notes below) +1000, +2000 (see notes below) storage temperature t a - 65 150 o c junction temperature 125 rf input power max 23 dbm notes: 1. v in corresponds to all the digital pins . 2. v ain corresponds to the following analog pins: vdd_rf_rx, vdd_rf_tx, vdd_ams, rfiop, rfion, xo_n, xo_p, vdd_sxdig, and vdd_vco . 3. for v esdhbm , each pin is classified as class 1, or class 2, or both: ? the class 1 pins in clude all the pins (both analog and digital) ? the class 2 pins are all digital pins only ? v esdhbm is 1kv for class1 pins. v esdhbm is 2kv for class2 pins atwilc3400 qfn package notes
ATWINC3400 - datasheet [ preliminary datashee t ] atmel - 42396 c - smartconnect - atw inc3400_preliminary - datasheet _0 7 / 201 5 1 0 10 4.2 recommended operating conditions table 4 - 2. recommended operating conditions characteristic symbol min . typ . max . unit i/o supply voltage 1 vddio 2.7 3.3 3.6 v battery supply voltage 2 vbatt 3.0 3.6 4.2 operating temperature - 40 85 o c notes: 1. i/o supply voltage is applied to the following pins: vddio_a, vddio . 2. battery supply voltage is applied to following pins: vdd_batt_ppa, vdd_batt_pa, vbatt_buck . 3. r efer to section 10.1 and 11 for the details of power connections . 4.3 dc electrical characteristics table 4 - 3 provides the dc characteristics for the atwinc 3400 digital pads . table 4 - 3. dc electrical characteristics characteristic min. max. unit input low voltage v il - 0.30 0.60 v input high voltage v ih vddio - 0.60 vddio+0.30 output low voltage v ol 0.45 output high voltage v oh vddio - 0.50 input low voltage v il - 0.30 0.63 v input high voltage v ih vddio - 0.60 vddio+0.30 output low voltage v ol 0.45 output high voltage v oh vddio - 0.50 input low voltage v il - 0.30 0.65 v input high voltage v ih vddio - 0.60 vddio+0.30 (up to 3.60) output low voltage v ol 0.45 output high voltage v oh vddio - 0.50 output loading 20 pf digital input load 6 pad drive streng t h 8 13.5 ma
[ preliminary datashee t ] atmel - 42396 c - smartconnect - atw inc3400_preliminary - datasheet _0 7/ 201 5 1 1 11 5 clocking 5.1 crystal oscillator table 5 - 1. crystal oscillator parameters parameter min . typ . max . unit crystal resonant frequency 12 26 40 mhz crystal equivalent series resistance 50 150 ? stability C initial offset 1 - 100 100 ppm stability - temperature and aging - 25 25 note 1. initial offset must be calibrated to maintain 25ppm in all operating conditions. this calibration is performed during final production testing . the block diagram in figure 5 - 1 (a) shows how the internal crystal oscillator (xo) is connected to the external crystal. the xo has 5pf internal capacitance on each terminal xo_p and xo_n. to bypass the crystal oscillator with an external reference, an external signal capable of driving 5pf can be applied to the xo_n terminal as shown in figure 5 - 1 (b) . figure 5 - 1. xo connections (a) crystal oscillator is used (b) crystal oscillator is bypassed table 5 - 2 specifies the electrical and performance requirements for the external clock . table 5 - 2. bypass clock specification parameter min . max . unit comments oscillation f requency 12 32 mhz must be able to drive 5pf load @ desired frequency voltage swing 0.5 1.2 v pp must be ac coupled stability C temperature and aging - 25 +25 ppm phase noise - 130 dbc/hz at 10khz offset jitter(rms) <1psec based on integrated phase noise spectrum from 1khz to 1mhz
ATWINC3400 - datasheet [ preliminary datashee t ] atmel - 42396 c - smartconnect - atw inc3400_preliminary - datasheet _0 7 / 201 5 1 2 12 5.2 low power oscillator atwilc3 4 00 requires an external 32.768 khz clock to be used for sleep operation, which is provided through pin 28 or pin 41. the frequency accuracy of the external clock has to be within 200 ppm . 6 cpu an d memory subsystems 6.1 processor atwilc3 4 00 has a cortus aps3 32 - bit processor. this processor performs many of the mac functions, including but not limited to association, authentication, power management, security key management, and msdu aggregation/de - agg regation. in addition, the processor provides flexibility for various modes of operation, such as sta and ap modes . 6.2 memory subsystem the aps3 core uses a 256 kb i nstruction/boot rom (160kb for 802.11 and 96 kb for ble ) along with a 420kb instruction ram (128 kb for 802.11 and 292kb for ble ), and a 128kb data ram (64kb for 802.11 and 64 kb for ble ). in addition, the device uses a 160 kb shared /exchange ram (128kb for 802.11 and 32 kb for ble ), accessible by the processor and mac, which allows the processor to perform various data management tasks on the tx and rx data packets . 6.3 non - volatile memory (e fuse) atwilc3 4 00 has 768 bits of non - volatile efuse memory that can be read by the cpu after device reset. this non - volatile one - time - programmable memory can be used to store customer - specific parameters, such as 802.11 mac address, ble address, and various calibration information, such as tx power, crystal frequency offset, etc., as well as other software - specific configuration parameters. the efuse is partitioned in to six 128 - bit banks. the bit map of the first and last banks is shown in figure 6 - 1 . the purpose of the first 80 bits in bank 0 and the first 56 bits in bank 5 is fixed, and the remaining bits are general - purpose software dependent bits, or reserved for future use. since each bank and each bit can be programmed independently, this allows for several updates of the device parameters fo llowing the initial programming, e .g. , updating 802.11 mac address or ble address (this can be done by invalidating the last programmed bank and programming a new bank). r efer to atwilc3 4 00 programming guide for the efuse programming instructions .
[ preliminary datashee t ] atmel - 42396 c - smartconnect - atw inc3400_preliminary - datasheet _0 7/ 201 5 1 3 13 figure 6 - 1. e fuse bit map 7 wlan subsystem the wlan subsystem is composed of the media access controller (mac) and the physical layer (phy). the following two subsections describe the mac and phy in detail . 7.1 mac 7.1.1 features the atwilc3 4 00 ieee802.11 mac supports the following functions : ? ieee 802.11b/g/n ? ieee 802.11e wmm qos edca/pcf multiple access categories traffic scheduling ? advanced ieee 802.11n features: C transmission and reception of aggregated mpdus (a - mpdu) C transmission and reception of aggregated msdus (a - msdu) C immediat e block acknowledgement C reduced interframe spacing (rifs) ? support for ieee802.11i and wfa security with key management C wep 64/128 C wpa - tkip C 128 - bit wpa2 ccmp (aes) ? support for wapi security ? advanced power management : C standard 802.11 power save mode C wi - fi alliance wmm - ps (u - apsd) b a n k 0 b a n k 1 b a n k 2 b a n k 3 b a n k 4 b a n k 5 f m a c a d d r u s e d i n v a l i d v e r s i o n r e s e r v e d m a c a d d r u s e d f o g 3 1 1 4 1 u s e d t x g a i n c o r r e c t i o n u s e d f r e q . o f f s e t 1 7 4 8 8 8 1 6 1 1 5 1 2 8 b i t s f b t a d d r u s e d b t a d d r i n v a l i d v e r s i o n r e s e r v e d r e s e r v e d b t a d d r 4 8 8 1 1 3 2 1
ATWINC3400 - datasheet [ preliminary datashee t ] atmel - 42396 c - smartconnect - atw inc3400_preliminary - datasheet _0 7 / 201 5 1 4 14 ? rts - cts and cts - self support ? supports either sta or ap mode in the infrastructure basic service set mode ? supports independent basic service set (ibss) 7.1.2 description the atwilc3 4 00 mac is designed to operate at low power while providing high data throughput. the ieee 802.11 mac functions are implemented with a combination of dedicated data path engines, hardwired control logic, and a low - power, high - efficiency microprocessor. the combination of dedicated logic with a programmabl e processor provides optimal power efficiency and real - time response while providing the flexibility to accommodate evolving standards a nd future feature enhancements. dedicated data path engines are used to implement data path functions with heavy computa tional. for example, an fcs engine checks the crc of the transmitting and receiving packets, and a cipher engine performs all the required encryption and decryption operations for the wep, wpa - tkip, wpa2 ccmp - aes, and wapi security requirements. control fu nctions which have real - time requirements are implemented using hardwired control logic modules. these logic modules offer real - time response while maintaining configurability via the processor. examples of hardwired control logic modules are the channel a ccess control module (implements edca/hcca, beacon tx control, interframe spacing, etc.), protocol timer module (responsible for the network access vector, back - off timing, timing synchronization function, and slot management), mpdu handling module, aggreg ation/de - aggregation module, block ack controller (implements the protocol requirements for burst block communication), and tx/rx control fsms (coordinate data movement between phy - mac interface, cipher engine, and the dma interface to the tx/rx fifos). th e mac functions implemented solely in software on the microprocessor have the following characteristics: ? functions with high memory requirements or complex data structures. examples are association table management and power save queuing ? functions with low computational load or without critical real - time requirements. examples are authentication and association ? functions which need flexibility and upgradeability. examples are beacon frame processing and qos scheduling 7.2 phy 7.2.1 features the atwilc3 4 00 ieee802.11 phy supports the following functions: ? single antenna 1x1 stream in 20mhz channels ? supports ieee 802.11b dss s - cck modulation: 1, 2, 5.5, and 11 mbps ? supports ieee 802.11g ofdm modulation: 6, 9, 12,18, 24, 36, 48, and 54 mbps ? supports ieee 802.11n ht modulatio ns mcs0 - 7, 20mhz, 800 and 400ns guard interval: 6.5, 7.2, 13.0, 14.4, 19.5, 21.7, 26.0, 28.9, 39.0, 43. 3, 52.0, 57.8, 58.5, 65.0, and 72.2 mbps ? ieee 802.11n mixed mode operation ? per packet tx power control ? advanced channel estimation/equalization, automatic gain control, cca, carrier/symbol recovery, and frame detection
[ preliminary datashee t ] atmel - 42396 c - smartconnect - atw inc3400_preliminary - datasheet _0 7/ 201 5 1 5 15 7.2.2 description the atwilc3 4 00 wlan phy is designed to achieve reliable and power - efficient physical layer communication specified by ieee 802.11b/g/n in single stream mode with 20mhz bandwidth. advanced algorithms have been employed to achieve maximum throughput in a real world communication environment with impairments and interference. the phy implements all the required functions such as fft, filtering, fec (viterbi decoder), frequency and ti ming acquisition and tracking, channel estimation and equalization, carrier sensing and clear channel assessment, as well as the automatic gain control . 7.3 radio 7.3.1 receiver performance radio performance under typical conditions: vbatt =3.6v; vddio=3.3v; temp erat ure : 25c . table 7 - 1. receiver performance parameter description min . typ . max . unit frequency 2,412 2,484 mhz sensitivity 802.11b 1 mbps dss - 98.0 dbm 2mbps dss - 95.0 5.5mbps dss - 93.0 11 mbps dss - 89.0 sensitivity 802.11g 6 mbps ofdm - 90.6 dbm 9mbps ofdm - 89.0 12mbps ofdm - 87.9 18mbps ofdm - 86.0 24mbps ofdm - 83.0 dbm 36mbps ofdm - 79.8 48mbps ofdm - 76.0 54mbps ofdm - 74.3 sensitivity 802.11n (bw=20mhz) mcs 0 - 89.0 dbm mcs 1 - 86.9 mcs 2 - 84.9 mcs 3 - 82.4 mcs 4 - 79.2 mcs 5 - 75.0 mcs 6 - 73.2 mcs 7 - 71.2 maximum receive signal level 1 - 11 mbps dss - 10 5 dbm 6 - 54 mbps ofdm - 10 - 3 mcs 0 C 7 - 10 - 3 adjacent channel 1 mbps dss (30mhz offset) 50 db
ATWINC3400 - datasheet [ preliminary datashee t ] atmel - 42396 c - smartconnect - atw inc3400_preliminary - datasheet _0 7 / 201 5 1 6 16 parameter description min . typ . max . unit rejection 11 mbps dss (25mhz offset) 43 6mbps ofdm (25mhz offset) 40 54mbps ofdm (25mhz offset) 25 mcs 0 C 20mhz bw (25mhz offset) 40 mcs 7 C 20mhz bw (25mhz offset) 20 7.3.2 transmitter performance radio performance under typical conditions: vbatt =3.6v; vddio=3.3v; temp: 25c . table 7 - 2. transmitter performance parameter description min . typ . max . unit frequency 2,412 2,484 mhz output power 802.11b dsss 1 mbps 20 1 dbm 802. 11b dsss 11 mbps 17 1 802.11g ofdm 6 mbps 16 1 t x power accuracy 1.5 2 db carrier suppression 30.0 dbc harmonic output power 2 nd - 125 dbm /hz 3 rd - 125 notes: 1. measured at 802.11 spec compliant evm/ spectral mask. 2. measured at rf pin assuming 50? differential. 3. rf performance guar anteed for temp range - 30 to 85c . 1db derating in performance at - 40 c . 8 ble subsystem the ble subsystem implements all the mission critical real - time functions. it encodes/decodes hci packets, constructs baseband data packages and manages and monitors connection status, slot usage, data flow, routing, se gmentation, and buffer control. the ble subs ystem performs link control layer management supporting the following states: ? standby ? connection ? page and page scan ? inquiry and inquiry scan ? sniff the ble subsystem supports ble profiles allowing connection to advanced low energy application such as : ? smar t energy ? consumer wellness ? home automation ? security ? proximity detection
[ preliminary datashee t ] atmel - 42396 c - smartconnect - atw inc3400_preliminary - datasheet _0 7/ 201 5 1 7 17 ? entertainment ? sports and fitness ? automotive 8.1 ble radio 8.1.1 receiver performance radio performance under typical conditions: vbatt =3.6v; vddio=3.3v; temp: 25c . table 8 - 1. atwilc3 4 00 ble receiver perfo rmance parameter description min . typ. max . unit frequency 2,402 2,480 mhz sensitivity ideal tx ble (gfsk) - 96 dbm maximum receive signal level ble (gfsk) - 10 0 dbm 8.1.2 transmitter performance radio performance under typical conditions: vbatt =3.6v; vddio=3.3v; temp: 25c . table 8 - 2. atwilc3 4 00 ble transmitter performance parameter description min . typ . max . unit frequency 2,402 2,480 mhz output power ble ( gfsk ) - 3 0 8 10 dbm
ATWINC3400 - datasheet [ preliminary datashee t ] atmel - 42396 c - smartconnect - atw inc3400_preliminary - datasheet _0 7 / 201 5 1 8 18 9 external interfaces ATWINC3400 external interfaces include: spi slave, sdio slave, and uart for 802.11 control and data transfer , uart for ble control and data transfer , i 2 c slave for control , spi master for external flash , i 2 c master for external eepr om, and general purpose input/ output (gpio) pins. with the exception of the spi slave and sdio slave host interfaces, which are selected using the dedicated sdio_spi_cfg pin, the other interfaces can be assigned to various pins by programming the corresponding pin muxing control regist er for each pin to a specific value between 0 and 6.the default values of these registers are 0, which is gpio mode. each digital i/o pin also has a programmable pull - up or pull - down. the summary of the available interfaces and their corresponding pin mux settings is shown in table 9 - 1 . for specific programming instructions refer to ATWINC3400 programming guide . table 9 - 1. pin - mux matrix of external interfaces pin name pin # pu ll mux0 mux1 mux2 mux3 mux4 mux5 mux6 gpio_38 9 down i_wakeup gpio_39 10 up i_wakeup gpio_40 11 down i_wakeup gpio_42 12 down gpio_16 14 up gpio_16 o_bt_uar t1_txd gpio_15 15 up gpio_15 i_bt_uart 1_rxd gpio_14 16 up gpio_14 o_bt_uar t1_rts io_i2c_sda i_wakeup gpio_13 17 up gpio_13 i_bt_uart 1_cts io_i2c_scl o_wifi_ua rt_txd i_wakeup gpio_3 20 up gpio_3 o_spi_sck _flash o_bt_uar t2_txd gpio_4 21 up gpio_4 o_spi_ssn _flash i_bt_uart 2_rxd gpio_5 22 up gpio_5 o_spi_txd _flash o_wifi_ua rt_txd i_wakeup gpio_6 23 up gpio_6 i_spi_rxd_ flash i_wifi_uar t_rxd i_wakeup rtc_clk 28 up gpio_1 i_rtc_clk i_wifi_uar t_rxd o_wifi_ua rt_txd i_bt_uart 1_cts sd_clk/gpi o_8 29 up gpio_8 i_sd_clk i_wifi_uar t_rxd i_bt_uart 1_cts sd_cmd/sp i_sck 30 up io_sd_cm d io_spi_sc k sd_dat0/s pi_txd 31 up io_sd_dat 0 o_spi_txd sd_dat1/s pi_ssn 32 up io_sd_dat 1 io_spi_ss n sd_dat2/s pi_rxd 34 up io_sd_dat 2 i_spi_rxd sd_dat3/g pio_7 35 up gpio_7 io_sd_dat 3 o_wifi_ua rt_txd o_bt_uar t1_rts gpio_17 36 down gpio_17 i_wakeup gpio_18 37 down gpio_18 i_wakeup gpio_19 38 down gpio_19 i_wakeup
[ preliminary datashee t ] atmel - 42396 c - smartconnect - atw inc3400_preliminary - datasheet _0 7/ 201 5 1 9 19 pin name pin # pu ll mux0 mux1 mux2 mux3 mux4 mux5 mux6 gpio_20 39 down gpio_20 i_wakeup irqn 40 up gpio_2 o_irqn i_wifi_uar t_rxd o_bt_uar t1_rts gpio_21 41 up gpio_21 i_rtc_clk i_wifi_uar t_rxd o_wifi_ua rt_txd o_bt_uar t1_rts io_i2c_ma ster_scl host_wak eup 42 up gpio_0 i_wakeup o_wifi_ua rt_txd io_i2c_ma ster_sda 9.1 i 2 c slave interface the i 2 c slave interface, used primarily for control by the host processor, is a two - wire serial interface consisting of a serial data line (sda) on pin 16 (gpio14) and a serial clock line (scl) on pin 17 (gpio13). i 2 c slave responds to the seven bit address value 0x60. the atwilc3 4 00 i 2 c supports i 2 c bus version 2.1 - 2000 and can operate in standard mode (with data rates up to 100 kb/s) and fast mode (with data rates up to 400 kb/s). the i 2 c slave is a synchronous serial interface. the sda line is a bidirectional signal and changes only while the scl line is low, except for stop, start, and restart conditions. the output drivers are open - drain to perform wire - and functions on the bus. the maximum number of devices on the bus is limited by only the maximum c apacitance specification of 400 pf. data is transmitted in byte pac kages. for specific information, refer to the philips specification entitled the i 2 c - bus specification, version 2.1. figure 9 - 1. i 2 c slave timing diagram t h l s d a s c l t h d s t a t w l t w h t s u d a t t p r t h d d a t t p r t p r t l h t h l t l h t s u s t o t b u f t s u s t a f s c l
ATWINC3400 - datasheet [ preliminary datashee t ] atmel - 42396 c - smartconnect - atw inc3400_preliminary - datasheet _0 7 / 201 5 2 0 20 table 9 - 2. i 2 c slave timing parameters parameter symbol min . max . unit remarks scl clock frequency f scl 0 400 khz scl low pulse width t wl 1.3 s scl high pulse width t wh 0.6 scl, sda fall time t hl 300 ns scl, sda rise time t lh 300 this is dictated by external components start setup time t susta 0.6 s start hold time t hdsta 0.6 sda setup time t sudat 100 n s sda hold time t hddat 0 slave and master default 40 master programming option stop setup time t susto 0.6 s bus free time between stop and start t buf 1.3 glitch pulse reject t pr 0 50 ns 9.2 i 2 c master interface atwilc3 4 00 provides an i 2 c bus master, which is intended primarily for accessing an external eeprom memory through a software - defined protocol. the i 2 c master is a two - wire serial interface consisting of a serial data line (sda) and a serial cloc k line (scl). sda can be configured on pin 42 (host_wakeup), and scl can be configured on pin 41 (gpio21). the i 2 c master interface supports three speeds: ? standard mode (100kb/s) ? fast mode (400kb/s) ? high - speed mode (3.4mb/s) the timing diagram of the i 2 c m aster interface is the same as that of the i 2 c slave interface (see figure 9 - 1 ). the timing parameters of i 2 c master are shown in table 9 - 3 . table 9 - 3. i 2 c master timing parameters parameter symbol standard mode fast mode high - speed mode unit min . max . min . max . min . max . scl clock frequency f scl 0 100 0 400 0 3400 khz scl low pulse width t wl 4.7 1.3 0.16 s scl high pulse width t wh 4 0.6 0.06 scl fall time t hlscl 300 300 10 40 ns sda fall time t hlsda 300 300 10 80 scl rise time t lhscl 1000 300 10 40 sda rise time t lhsda 1000 300 10 80
[ preliminary datashee t ] atmel - 42396 c - smartconnect - atw inc3400_preliminary - datasheet _0 7/ 201 5 2 1 21 parameter symbol standard mode fast mode high - speed mode unit min . max . min . max . min . max . start setup time t susta 4.7 0.6 0.16 s start hold time t hdsta 4 0.6 0.16 sda setup time t sudat 250 100 10 ns sda hold time t hddat 5 40 0 70 stop setup time t susto 4 0.6 0.16 s bus free time between stop and start t buf 4.7 1.3 glitch pulse reject t pr 50 ns 9.3 spi slave interface atwilc3 4 00 provides a serial peripheral interface (spi) that operates as a spi slave. the spi slave interface can be used for control and for serial i/o of 802.11 data. the spi slave pins are mapped as shown in table 9 - 4 . the rxd pin is same as master output, slave input (mosi), and the txd pin is same as master input, slave output (miso). the spi slave is a full - duplex slave - synchronous serial interface that is available immediately following reset when pin 12 (sdio_spi_cfg) is tied to vddio . table 9 - 4. spi slave interface pin mapping pin # spi function 12 cfg: must be tied to vddio 32 ssn: active low slave select 30 sck: serial clock 34 rxd: serial data receive (mosi) 31 txd: serial data transmit (miso) when the spi is not selected, i.e., when ssn is high, the spi interface will not interfere with data transfers between the serial - master and other serial - slave devices. when the serial slave is not selected, it s transmitted data output is buffered, resulting in a high impedance drive onto the serial master receive line. the spi slave interface responds to a protocol that allows an external host to read or write any register in the chip as well as initiate dma transfers. for the details of the spi protocol and more specific instructions refer to atwilc3 4 00 programming guide. the spi slave interface supports four standard modes as determined by the clock polarity (cpol) and clock phase (cpha) settings. these mode s are illustrated in table 9 - 5 and figure 9 - 2 . the red lines in figure 9 - 2 correspond to clock phase = 0 and the blue lines correspond to clock phase = 1.
ATWINC3400 - datasheet [ preliminary datashee t ] atmel - 42396 c - smartconnect - atw inc3400_preliminary - datasheet _0 7 / 201 5 2 2 22 table 9 - 5. spi slave modes mode cpol cpha 0 0 0 1 0 1 2 1 0 3 1 1 figure 9 - 2. spi slave clock polarity and clock phase timing the spi slave timing is provided in figure 9 - 3 and table 9 - 6 . figure 9 - 3. spi slave timing diagram table 9 - 6. spi slave timing parameters parameter symbol min . max . unit clock input frequency f sck 48 mhz clock low pulse width t wl 5 ns clock high pulse width t wh 5 clock rise time t lh 5 z z z z s c k c p o l = 0 c p o l = 1 s s n r x d / t x d ( m o s i / m i s o ) c p h a = 0 c p h a = 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 1 8
[ preliminary datashee t ] atmel - 42396 c - smartconnect - atw inc3400_preliminary - datasheet _0 7/ 201 5 2 3 23 parameter symbol min . max . unit clock fall time t hl 5 input setup time t isu 5 input hold time t ihd 5 output delay t odly 0 20 slave select setup time t sussn 5 slave select hold time t hdssn 5 9.4 spi master interface atwilc3 4 00 provides a spi master in terface for accessing external f lash memory. the spi master pins are mapped as shown in table 9 - 7 . the t xd pin is same as master output and slave input (mosi ). t he rxd pin is same as m aster input and slave output (miso). the spi master interface supports all four standard modes of clock polarity and clock phase shown in table 9 - 5 . external spi f lash memory is accessed by a processor programming commands to the spi master interface, which in turn initia tes a spi master access to the f lash. for more specific instructions refer to atwilc3 4 00 programming guide . table 9 - 7. spi master interface pin mapping pin # pin name spi function 20 gpio3 sck: serial clock output 21 gpio4 sck: active low slave select output 22 gpio5 txd: serial data transmit output (mosi) 23 gpio6 rxd: serial data receive input (miso) the spi master timing is provided in figure 9 - 4 and table 9 - 8 . figure 9 - 4. spi master timing diagram table 9 - 8. spi master timing parameters parameter symbol mi n. max. unit clock output frequency f sck 48 mhz f s c k t w h t l h t h l t w l t o d l y t i s u t i h d s c k s s n , t x d r x d
ATWINC3400 - datasheet [ preliminary datashee t ] atmel - 42396 c - smartconnect - atw inc3400_preliminary - datasheet _0 7 / 201 5 2 4 24 parameter symbol mi n. max. unit clock low pulse width t wl 5 ns clock high pulse width t wh 5 clock rise time t lh 5 clock fall time t hl 5 input setup time t isu 5 input hold time t ihd 5 output delay t odly 0 5 9.5 sdio slave interface the atwi n c3 4 00 sdio slave is a full speed interface. the interface supports the 1 - bit/4 - bit sd transfer mode at the clock range of 0 - 50mhz. the host can use this interface to read and write from any register within the chip as well as configure the atwi n c3000 for data dma. to use this interface, pin 12 (sdio_spi_cfg) must be grounded. the sdio slave pins are mapped as shown in table 9 - 9 . table 9 - 9. sdio interface pin mapping pin # spi function 12 cfg: must be tied to ground 35 dat3: data 3 34 dat2: data 2 32 dat1: data 1 31 dat0: data 0 30 cmd: command 29 clk: clock when the sdio card is inserted into an sdio aware host, the detection of the card will be via the means described in sdio specification. during the normal initialization and interrogation of the card by the host, the card will identify itself as an sdio device. the host software will obtain the card information in a tuple (linked list) format and determine if that cards i/o function(s) are acceptable to activate. if the card is acceptable, it will be allowed to power up fully and start the i/o function(s) built int o it. the sd memory card communication is based on an advanced 9 - pin interface (clock, command, and four data and three power lines) designed to operate at maximum operating frequency of 50mhz. the sdio slave interface has the following features: ? meets sdio card specification version 2.0 ? host clock rate variable between 0 and 50mhz ? 1 bit/4 - bit sd bus modes supported ? allows card to interrupt host ? responds to direct read/write (io52) and extended read/write (io53) transactions ? supports suspend/resume opera tion the sdio slave interface timing is provided in figure 9 - 5 and table 9 - 10 .
[ preliminary datashee t ] atmel - 42396 c - smartconnect - atw inc3400_preliminary - datasheet _0 7/ 201 5 2 5 25 figure 9 - 5. sdio slave timing diagram s d _ c l k i n p u t s o u t p u t s f p p t w l t w h t h l t l h t i s u t i h t o d l y ( m a x ) t o d l y ( m i n )
ATWINC3400 - datasheet [ preliminary datashee t ] atmel - 42396 c - smartconnect - atw inc3400_preliminary - datasheet _0 7 / 201 5 2 6 26 table 9 - 10. sdio slave timing parameters parameter symbol min . max . unit clock input frequency f pp 0 50 mhz clock low pulse width t wl 10 ns clock high pulse width t wh 10 clock rise time t lh 10 clock fall time t hl 10 input setup time t isu 5 input hold time t ih 5 output delay t odly 0 14 9.6 uart atwilc3400 provides universal asynchronous receiver/transmitter (uart) interfaces for serial communication. the ble subsystem has two uart interfaces: a 4 - pin interface for control, data transfer, and audio (bt uart1), and a 2 - pin interface for debugging ( bt uart2). the 802.11 subsystem has one 2 - pin uart interface ( wi - fi uart), which can be used for control, data transfer, or debugging. the uart interfaces are compatible with the rs - 232 standard, where atwilc3 4 00 operates as data terminal equipment (dte). the 2 - pin uart has the receive and transmit pins (rxd and txd), and the 4 - pin uart has two additional pins used for flow control/handshaking: request to send (rts) and clear to send (cts). the pins associated with each uart interfaces can be enabled on sev eral alternative pins by program ming their corresponding pin mux control registers (see table 9 - 1 for available options). the uart features programmable baud rate generation with fractional clock division, which allows transmission and reception at a wide variety of standard and non - standard baud rates. the ble uart input clock is selectable between 104mhz, 52mhz, 26mhz, and 13mhz. the clock divider value is progr am mable as 13 integer bits and three fractional bits (with 8.0 being the smallest recommended value for normal operation). this results in the maximum supporte d baud rate of 10mhz/ 8.0 = 13 mbd. the 802.11 uart input clock is selectable between 10mhz, 5mhz, 2. 5mhz, and 1.25mhz. the clock divider value is progr ammable as 13 integer bits and three fractional bits (with 8.0 being the smallest recommended value for normal operation). this results in the maximum supported baud rate of 10mhz/ 8.0 = 1.25 mbd. the uart c an be configured for seven or eight bit operation, with or without parity, with four different parity types (odd, even, mark, or space), and with one or two stop bits. it also has rx and tx fifos, which ensure reliable high speed reception and low software overhead transmission . fifo size is 4 x8 for both rx and tx direction. the uart also has status registers showing the number of received characters available in the fifo and various error conditions, as well the ability to generate interrupts based on the se status bits.an example of uart receiving or transmitting a single packet is shown in figure 9 - 6 . this example shows 7 - bit data (0x45), odd parity, and two stop b its. for more specific instructions refer to atwilc3 4 00 programming guide.
[ preliminary datashee t ] atmel - 42396 c - smartconnect - atw inc3400_preliminary - datasheet _0 7/ 201 5 2 7 27 figure 9 - 6. example of uart rx or tx packet 9.7 gpios 18 general purpose input/ output (gpio) pins, labeled gpio 0 - 8 and 13 - 21, are available to allow for application specific functions. each gpi o pin can be programmed as an input (the value of the pin can be read by the host or internal processor) or as an output (the output values can be programmed by the host or internal processor), where the default mode after power - up is input. gpios 7 and 8 are only available when the host does not use the sdio interface, which shares two of its pins with these gpios. therefore, for sdio - based applications, 16 gpios (0 - 6 and 13 - 21) are available. for more specific usage instructions refer to atwilc3 4 00 progra mming guide . 10 power management 10.1 power architecture atwilc3 4 00 uses an innovative power architecture to eliminate the need for external regulators and reduce the number of off - chip components. this architecture is shown in figure 10 - 1 . the power management unit (pmu) has a dc/dc converter that converts vbatt to the core supply used by the digital and rf/ams blocks. table 10 - 1 shows the typical values for the digital and rf/ams core voltages. the pa and e fuse are supplied by dedicated ldos, and the vco is supplied by a separate ldo structure .
ATWINC3400 - datasheet [ preliminary datashee t ] atmel - 42396 c - smartconnect - atw inc3400_preliminary - datasheet _0 7 / 201 5 2 8 28 figure 10 - 1. power architecture table 10 - 1. pmu output voltages parameter typical rf/ams core voltage (vreg_buck) 1.3v digital core voltage (vddc) 1.1v the power connections in figure 10 - 1 provide a conceptual framework for understanding the atwilc3 4 00 power architecture. r efer to the reference design for an example of power supply connections, including proper isolation of the supplies used by the digital and rf/ams blocks . 10.2 power consumption 10.2.1 description of device states atwilc3 4 00 has several d evices s tates: ? on_wifi_transmit : device is actively transmitting an 802.11 signal ? on_wifi_receive : device is actively receiving an 802.11 signal vbatt _ buck off - chip lc rf / ams core sleep osc rf / ams core voltage vsw vreg _ buck vdd _ ams , vdd _ rf , vdd _ sxdig ldo 1 vddio _ a vdd _ vco ldo 2 ~ vdd _ batt 1 . 2 v 1 . 0 v chip _ en efuse ldo sx digital core dc / dc converter efuse pa pmu rf / ams digital vddc dig core ldo 2 . 5 v pads vddio sleep ldo digital core voltage dcdc _ ena ena vin vout ena ena vbatt vddio
[ preliminary datashee t ] atmel - 42396 c - smartconnect - atw inc3400_preliminary - datasheet _0 7/ 201 5 2 9 29 ? on_bt_transmit : device is actively transmitting a ble signal ? on_bt_receive : device is actively receiving a ble signal ? on_doze : device is on but is neither transmitting nor receiving ? power_down : device core supply off (leakage) the follo wing pins are used to switch between the on and power_down states: ? chip_en : device pin (pin #27) used to enable dc/dc converter ? vddio : i/o supply voltage from external supply in the on states, vddio is on and chip_en is high (at vddio voltage level). to switch between the on states and power_down state chip_en has to change between high and low (gnd) voltage. when vddio is off and chip_en is low, the chip is powered off with no leakage (also see note 1 in table 10 - 2 ). 10.2.2 current consumption in various device states table 10 - 2. current consumption device state code rate output power, dbm power consumption 1,2 i vbatt i vddio on_ wifi_ transmit 802.11b 1mbps 19.2 325 ma 2.7 ma 802.11b 11mbps 20.1 322 ma 2.7 ma 802.11g 6mbps 17.8 318 ma 2.7 ma 802.11g 54mbps 16.2 280 ma 2.7 ma 802.11n mcs 0 19.5 321 ma 2.7 ma 802.11n mcs 7 15.3 276 ma 2.7 ma on_ wifi_ receive 802.11b 1mbps n/a 83.7 ma 2.5 ma 802.11b 11mbps n/a 84.9 ma 2.5 ma 802.11g 6mbps n/a 85.8 ma 2.5 ma 802.11g 54mbps n/a 90.1 ma 2.5 ma 802.11n mcs 0 n/a 86 ma 2.5 ma 802.11n mcs 7 n/a 91.8 ma 2.5 ma on_ bt_ transmit tbd tbd tbd tbd on_ bt_ receive tbd n/a <45ma <2.5ma doze n/a n/a <0.65ma < 7a power_down n/a n/a <0.5a < 3 . 5 a notes: 1. conditions: vbatt @3.6v, vddio @2.8v, 25c 2. power consumption numbers are preliminary 10.2.3 restrictions for power states when no power supplied to the device, i.e., the dc/dc converter output and vddio are both off (at ground potential). in this case, a voltage cannot be applied to the device pins because each pin contains an esd diode from the pin to supply. this diode will turn on when voltage higher than one diode - drop is supplied to the pin.
ATWINC3400 - datasheet [ preliminary datashee t ] atmel - 42396 c - smartconnect - atw inc3400_preliminary - datasheet _0 7 / 201 5 3 0 30 if a voltage must be appl ied to the signal pads while the chip is in a low power state, the vddio supply must be on, so the sleep or power_down state must be used. similarly, to prevent the pin - to - ground diode from turning on, do not apply a voltage that is more than one diode - dro p below ground to any pin. 10.3 power - up/down sequence the power - up/down sequence for atwilc3 4 00 is shown in figure 10 - 2 . the timing parameters are provided in table 10 - 3 . figure 10 - 2. power up/down sequence table 10 - 3. power - up/down sequence timing parameter min . max . unit description notes t a 0 ms vbatt rise to vddio rise vbatt and vddio can rise simultaneously or can be tied together. vddio must not rise be- fore vbatt. t b 0 vddio rise to chip_en rise chip_en must not rise before vddio. chip_en must be driven high or low, not left floating. t c 5 chip_en rise to resetn rise this delay is needed because xo clock must stabilize before resetn removal. resetn must be driven high or low, not left floating. t a 0 vddio fall to vbatt fall vbatt and vddio can fall simultaneously or can be tied together. vbatt must not fall be- fore vddio. t b 0 chip_en fall to vddio fall vddio must not fall before chip_en. chip_en and resetn can fall simultane- ously. t c 0 resetn fall to vddio fall vddio must not fall before resetn. resetn and chip_en can fall simultaneously. v b a t t v d d i o c h i p _ e n r e s e t n t a t b t c x o c l o c k t b ' t a ' t c '
[ preliminary datashee t ] atmel - 42396 c - smartconnect - atw inc3400_preliminary - datasheet _0 7/ 201 5 3 1 31 10.4 digital i/o pin behavior during power - up sequences the following table represents digital i / o pin states corresponding to device power modes. table 10 - 4. digital i/o pin behavior in different device states device state vddio chip_en resetn output driver input driver pull up/down resistor (96k ? power_down: core supply off high low low disabled (hi - z) disabled disabled power - on reset: core supply on, hard reset on high high low disabled (hi - z) disabled enabled power - on default: core supply on, device out of reset but not programmed yet high high high disabled (hi - z) enabled enabled on_doze/ on_transmit/ on_receive: core supply on, device programmed by firm- ware high high high programmed by firmware for each pin: enabled or disa- bled opposite of output driver state programmed by firmware for each pin: enabled or disa- bled 11 reference design the ATWINC3400 reference design schematic is shown in figure 11 - 1 .
ATWINC3400 - datasheet [ preliminary datashee t ] atmel - 42396 c - smartconnect - atw inc3400_preliminary - datasheet _0 7 / 201 5 3 2 32 figure 11 - 1. ATWINC3400 reference schematic
[ preliminary datashee t ] atmel - 42396 c - smartconnect - atw inc3400_preliminary - datasheet _0 7/ 201 5 3 3 33 12 reference design guidelines ? rfiop and rfion pins must be ac coupled ? it is recommended that the balun is located right next to the pins C if this is not poss ible, rfiop and rfion should be routed as 50? differential pair to the balun ? ATWINC3400 provides programmable pull - up resistors on various pins (see table 3 - 1 ) . the purpose of these resistors is to keep any unused input pins from floating which can cause excess current to flow through the input buffer from the vddio supply . any unused pin on the device should leave these pull - up resistors enabled so the pin will not float . the default state at power up is for the pull - up resistor to be enabled. however, any pin which is used should have the pull - up resistor disabled. the reason for this is that if any pins are driven to a low level while the device is in the low power sleep state, current will flow from the vddio supply through the pull - up resistors, increasing the current consumption of the module. since the value of the pull - up resistor is approximately 100k?, the current through any pull - up resistor that is being dr iven low will be vddio/100k. for vddio = 3.3v, the current would be approximately 33 a. pins which are used and have had the programmable pull - up resistor disabled should always be actively driven to either a high or low level and not be allowed to float ? i f sdio interface is used, each sdio pin should use a 70? resistor in series for rf noise filtering ? r efer to ATWINC3400 programming guide for information on enabling/disabling the programmable pull - up resistors 13 reference documentation and support atmel offe rs a set of collateral documentation to ease integration and device ramp. the following list of documents available on atmel web or integrated into development tools. title content datasheet this document design files package user guide, schematic, pcb layout, gerber, bom and system notes on: rf/radio full test report, radiation pattern, design guide lines, temperature performance, esd. platform getting started guide how to use package: out of the box starting guide, hw limitations and notes, sw quick st art guide- lines . hw design guide best practices and recommendations to d esign a board with the product. including: antenna design for wi - fi (layo ut recommendations, types of an tennas, impedance match- ing, using a power amplifier etc . ), spi/uart protocol bet ween wi - fi soc and the host mcu. sw design guide integration guide with clear description of: high level arch, overview on how to write a networking application, list all api, parameters and structures. features of the device, spi/handshake protocol between device and host mcu, with flow/se- quence/state diagram, timing. sw program- mer guide explain in details the flow chart and how to use each api to implement all generic use cases (e.g. start ap, start sta, provisioning, udp, tcp, http, tls, p2p, erro rs management, connection/transf er recovery mechanism/state dia gram) - usage and sample a pp lication note . for a complete listin g of development - support tools and documentation, visit http://www.atmel.com/ , or contact the nearest atmel field representative.
ATWINC3400 - datasheet [ preliminary datashee t ] atmel - 42396 c - smartconnect - atw inc3400_preliminary - datasheet _0 7 / 201 5 3 4 34 14 revision history doc rev. date comments 42396c 0 7 /2015 1. modified sections 10.2.1 and 10.2.2 to add new current consumption numbers, update state names, and correct some typos 2. f ixed typos fo r spi slave interface timing ( table 9 - 6 ) 3. fixed typos for battery supply name: changed from vbat to vbatt 4. c orrected pmu output voltages ( table 10 - 1 ) 5. update d reference schematic drawing ( s ection 11 ) 6. added comment r egarding resistors on sdio pins ( s ection 12 ) 7. replaced bluetooth with ble throughout the document, updated content accordingly 8. removed pcm functionality 9. added ba ck sdio interface description (s ection 9.5 ) 10. updated powe r architecture drawing ( s ection 10.1 ) 1 1 . added pad drive strength in table 4 - 3 and removed the note under table 3 - 1 1 2 . updated operating temperature in the feature list 13. cor rected current in power_down state in table 10 - 2 1 4 . miscellaneous minor formatting and content corrections 42396b 03/2015 ordering information ( table 1 - 1 ) and qfn package information ( table 3 - 2 ) have been corrected. 42396 a 02 /201 5 initial document release.
[ preliminary datashee t ] atmel - 42396 c - smartconnect - atw inc3400_preliminary - datasheet _0 7/ 201 5 3 5 35 atmel corporation 1600 technology drive, san jose, ca 95110 usa t: (+1)(408) 441.0311 f: (+1)(408) 436.4200 www.atmel.com ? 2015 atmel corporation. / rev.: atmel - 42396 c - smartconnect - atw inc3400_preliminary - datasheet _0 7/ 201 5 . atmel ? , atmel logo and combinations thereof, enabling unlimited possibi lities ? , and others are registered trademarks or trademarks of atmel corporation in u.s. and other countries. arm ? , arm connected ? logo, and others are the registered trademarks or trademarks of arm ltd. other terms and product na mes may be trademarks of o thers. disclaimer: the information in this document is provided in connection with atmel products. no license, express or implied, b y estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of a tmel products. except as set forth in the atmel terms and conditions of sales located on the atmel website, atmel assumes no liability whatsoever and disclaims any express, implied or statutory warranty relating to its products including, but not limited t o, the implied warranty of merchantability, fitness for a particular purpose, or non - infringement. in no event shall atmel be liable for any direct, indirect, consequential, punitive, special or incidental damages (including, without li mitation, damages fo r loss and profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atmel has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time without notice. atmel does not make any commitment to update the information contained herein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atme l products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. s afety - critical, military, and automotive applications disclaimer: atmel products are not designed for and will not be used in conne ction with any applications where the failure of such products would reasonably be expected to result in significant personal injury or death (safety - critical applications) without an atmel officer's specific written consent. safety - critical applications include, without limitation, life support devices and systems, equipment or systems for the operation o f nuclear facilities and weapons systems. atmel products are not designed nor intended for use in military or aerospace applications or environments unless specifically desi gnated by atmel as military - grade. atmel products are not designed nor intended for use in automotive ap plications unless specifically designated by atmel as automotive - grade.

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