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1 of 125 GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 3g/hd/sd-sdi serializer with comp lete smpte audio & video support GS2972 www.semtech.com key features ? operation at 2.970gb/s, 2.970/1.001gb/s, 1.485gb/s, 1.485/1.001gb/s and 270mb/s ? supports smpte st 425 (level a and level b), smpte st 424, smpte st 292, smpte st 259-c and dvb-asi ? integrated cable driver ? integrated, low-noise vco ? integrated narrow-bandwidth pll ? integrated audio embedder for up to 8 channels of 48khz audio ? ancillary data insertion ? optional conversion from smpte st 425 level a to level b for 1080p 50/60 4:2:2 10-bit ? parallel data bus selectable as either 20-bit or 10-bit ? smpte video processing including trs calculation and insertion, line number calculation and insertion, line based crc calculation and insertion, illegal code re-mapping, smpte st 352 payload identifier generation and insertion ?gspi host interface ? +1.2v digital core power supply, +1.2v and +3.3v analog power supplies, and selectable +1.8v or +3.3v i/o power supply ? -20oc to +85oc operating temperature range ? low power operation (typic ally at 400mw, including cable driver) ? small 11mm x 11mm 100-ball bga package ? pb-free and rohs compliant applications application: 1080p 50/60 camera/camcorder adc audio processor video processor ccd 20 -bit GS2972 3g-sdi hv f/pclk ctrl/time code aes - in audio 1/2 audio 3/4 audio clocks storage : tape /disc /solid state mic optics application: dual link (hd-sdi) to single link (3g-sdi) converter hd-sdi deserializer (gs1559 or gs2970) link a fifo wr deserializer link b fifo wr GS2972 gs4910 10-bit 3g-sdi hvf xtal hv f/pclk hv f/pclk hv f/pclk (gs1559 or gs2970) 10-bit 10-bit 10-bit hd-sdi hd-sdi hd-sdi eq eq gs2974b gs2974b application: multi-format audio embedder module sd/hd/3g-sdi pclk 10 -bit gs2970 GS2972 adc switch logic & buffers sd/hd/3g-sdi analog audio inputs aes audio inputs audio 1/2 audio 3/4 audio 5/6 audio 7/8 src gs4911 xtal hvf audio clocks eq gs2974b
2 of 125 GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 www.semtech.com description the GS2972 is a complete sdi transmitter, generating a smpte st 424, smpte st 292, smpte st 259-c or dvb-asi compliant serial digital output signal. the integrated narrow bw pll allows the device to accept parallel clocks with high input jitter, and still provide a smpte compliant serial digital output. the device can operate in four basic user selectable modes: smpte mode, dvb-asi mode, data-through mode, or standby mode. in smpte mode, the GS2972 perf orms all smpte processing features. both smpte st 425 level a and level b formats are supported with optional conversion from level a to level b for 1080p 50/60 4:2:2 10-bit. in dvb-asi mode, the device will perform 8b/10b encoding prior to transmission. in data-through mode, all smpte and dvb-asi processing is disabled. the device can be used as a simple parallel to serial converter. the device can also operate in a lower power standby mode. in this mode, no signal is generated at the output. the GS2972 integrates a fully smpte-compliant cable driver for smpte st 259-c, smpte st 292 and smpte st 424 interfaces. it features automatic dual slew-rate selection, depending on 3gb/s or hd or sd operational requirements. in accordance with smpte st 272 and smpte st 299, up to eight channels (two audio groups) of serial digital audio may be embedded into the video data stream.the input audio signal formats supported by the device include aes/ebu, i 2 s and serial audio. 16, 20 and 24-bit audio formats are supported at 48khz synchronous for sd modes and 48khz synchronous or asynchronous in hd, 3gb/s modes. application: multi-format digital vtr/video server storage : tape / hdd/solid state audio processor video processor 20 -bit hvf/pclk audio inputs v ideo inputs gs4911 audio clocks GS2972 3g-sdi sync seperator analog sync audio 1/2 audio 3/4 audio 5/6 audio 7/8 xtal keyer keyer application: multi-format presentation switcher (output stage) dve mixers key & fill logo inserter image store key/fill inputs GS2972 10 -bit + clk 20 -bit + clk sd/hd/3g-sdi auxiliary preview program audio mixer ae s from input dem ux v oice-over p re s e t a e s in program aes in p rogram ae s out p re v ie w a e s out i2s audio + clocks 20 -bit + clk gs4911 analog sync xtal sync seperator clock & sync distribution GS2972 GS2972 sd/hd/3g-sdi sd/hd/3g-sdi application: 3gb/s sdi test signal generator gs4911 analog sync sync seperator video signal generator xtal audio generator memory hv f/pclk audio clocks 20 -bit GS2972 3g-sdi aes 1/2 aes 3/4 aes 5/6 aes 7/8 hv f/pclk
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 3 of 125 www.semtech.com functional block diagram figure a: GS2972 fun c tional blo c k diagram input mux/ demux din[19:0] anc data insertion trs , line number and crc insertion edh packet insertion dvb-asi 8b/10b encoder f/de v/vsync h/hsync tim_861 parallel to serial converter mux smpte cable driver sdo sdo rset sdo_en/dis pclk aclk1 aclk2 wclk1 wclk2 ain_1/2 ain_3/4 ain_5/6 ain_7/8 audio_int grp1_en/dis grp2_en/dis hanc/ vanc blanking pll with low noise vco narrow bw pll locked dvb_asi nrz/nrzi smpte scrambler lf vbg rate_sel[1:0] cd_vdd cd_gnd core_vdd core_gnd io_vdd io_gnd reset standby 20bit/10bit anc_blank pll_vdd pll_gnd avdd agnd vco_vdd vco_gnd ioproc_en/dis smpte_bypass smpte st 425 level a to level b 1080p 50/60 4:2:2 10-bit smpte st 352 generation and insertion 3g/hd/sd audio embedding gspi host interface cs_tms sclk_tck sdin_tdi sdout_tdo jtag controller tms tdi tdo jtag/host tck dedicated jtag pins shared jtag and gspi pins (for drop-in compatibility with gs1572/82)
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 4 of 125 www.semtech.com revision history version eco pcn date changes and/or modifi c ations 9 01480 6 ? s eptem b er 2013 up d ates throu g hout the d o c ument. 8 011355 ? fe b ruary 2013 up d ate d to the s emte c h template. 7 155820 5 6 554 fe b ruary 2011 a dd e d se c tion 4.7.22.2 blankin g values followin g au d io data pa c ket insertion . 6 155 6 08 ? j anuary 2011 c larifie d the fun c tion of the a cs _re g en b it in s e c tion 4.7.11 au d io c hannel s tatus . 5 155080 5 6 059 o c to b er 2010 revise d power ratin g in stan db y mo d e. do c umente d cs um b ehaviour in s e c tion 4.8 , s e c tion 4.9.4 an d vi d eo c ore c onfi g uration an d s tatus re g isters . 4 153717 ? mar c h 2010 up d ates throu g hout entire d o c ument. a dd e d fi g ure 4-2 , fi g ure 4-3 an d fi g ure 4-4 . c orre c tion to re g isters 040h to 13fh in ta b le 4-34: vi d eo c ore c onfi g uration an d s tatus re g isters . 3 152220 ? j uly 2009 up d ate d devi c e laten c y num b ers in 2.4 a c ele c tri c al c hara c teristi c s . up d ates to 4.8 an c data insertion . repla c e d 7.3 markin g dia g ram . 2 151320 ? j anuary 2009 c orre c tion to timin g values in ta b le 4-1: gs 2972 di g ital input a c ele c tri c al c hara c teristi c s . 1 150803 ? de c em b er 2008 c onverte d to data s heet. up d ates to all se c tions. 0 150717 ? o c to b er 2008 c onverte d to preliminary data s heet. d 149428 ? au g ust 2008 up d ate d typi c al appli c ation c ir c uit . applie d new format to the d o c ument. up d ates to all se c tions. c 148810 ? fe b ruary 2008 up d ates to all se c tions. b 148770 ? de c em b er 2007 up d ates an d revise d 5.1 typi c al appli c ation c ir c uit . a 147987 ? de c em b er 2007 new do c ument.
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 5 of 125 www.semtech.com contents key features ................................................................................................................... .....................................1 applications................................................................................................................... ......................................1 description.................................................................................................................... .......................................2 functional block diagram ..................................... .................................................................. .......................3 revision history ............................................................................................................... ..................................4 1. pin out..................................................................................................................... ....................................... 10 1.1 pin assignment ............................................................................................................ ................... 10 1.2 pin descriptions .......................................................................................................... ................... 11 2. electrical characteristics .................................................................................................. ....................... 20 2.1 absolute maximum ratings .................................................................................................. ..... 20 2.2 recommended operating conditions ..... ........... .......... ........... ........... ........... ........... ......... ..... 20 2.3 dc electrical characteristics ...... ....................................................................................... ........ 21 2.4 ac electrical characterist ics ............................................................................................. ........ 23 3. input/output circuits ....................................................................................................... ........................ 26 4. detailed description........................................................................................................ .......................... 30 4.1 functional overview ....................................................................................................... ............. 30 4.2 parallel data inputs ...................................................................................................... ................. 31 4.2.1 parallel input in smpte mode....................................................................................... 33 4.2.2 parallel input in dvb-asi mode................................................................................... 33 4.2.3 parallel input in data-through mode......................................................................... 34 4.2.4 parallel input clock (pclk) ............................................................................................ 34 4.3 smpte mode ................................................................................................................ ................... 35 4.3.1 h:v:f timing ............................................................................................................. .......... 35 4.3.2 cea 861 timing........................................................................................................... ....... 38 4.4 dvb-asi mode .............................................................................................................. ................. 44 4.5 data-through mode ......................................................................................................... ............ 44 4.6 standby mode .............................................................................................................. ................... 44 4.7 audio embedding ........................................................................................................... ............... 45 4.7.1 serial audio data inputs ................................................................................................. 45 4.7.2 serial audio data format support............................................................................... 47 4.7.3 3g mode.................................................................................................................. .............. 49 4.7.4 hd mode.................................................................................................................. ............. 49 4.7.5 sd mode.................................................................................................................. .............. 50 4.7.6 audio embedding operating modes .......................................................................... 50 4.7.7 audio packet detection................................................................................................... 51 4.7.8 audio packet deletion .................................................................................................... .51 4.7.9 audio packet detection and deletion ........................................................................ 51 4.7.10 audio mute (default off).............................................................................................. 52 4.7.11 audio channel status .................................................................................................... 53 4.7.12 audio crosspoint........................................................................................................ ..... 54 4.7.13 audio word clock ........................................................................................................ .. 55 4.7.14 channel & group activation ....................................................................................... 55 4.7.15 audio fifo - sd......................................................................................................... ...... 56 4.7.16 audio fifo - hd and 3g............................................................................................... 57
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 6 of 125 www.semtech.com 4.7.17 five-frame sequence detection - sd........................................................................ 57 4.7.18 frame sequence detection - hd/3g ........................................................................ 60 4.7.19 ecc error detection and correction ........................................................................ 61 4.7.20 audio control packet insertion - sd......................................................................... 61 4.7.21 audio control packet insertion - hd and 3g......................................................... 62 4.7.22 audio data packet insertion........................................................................................ 63 4.7.23 audio interrupt control ................................................................................................ 6 4 4.8 anc data insertion ........................................................................................................ ............... 65 4.8.1 anc insertion operating modes .................................................................................. 65 4.8.2 3g anc insertion......................................................................................................... ...... 67 4.8.3 hd anc insertion......................................................................................................... ..... 69 4.8.4 sd anc insertion......................................................................................................... ...... 70 4.9 additional processing functions ........................................................................................... ... 71 4.9.1 video format detection .................................................................................................. 7 1 4.9.2 3g format detection ...................................................................................................... .. 74 4.9.3 anc data blanking ........................................................................................................ ... 75 4.9.4 anc data checksum calculation and insertion..................................................... 75 4.9.5 trs generation and insertion ....................................................................................... 75 4.9.6 hd and 3g line number calculation and insertion.............................................. 76 4.9.7 illegal code re-mapping................................................................................................. 7 6 4.9.8 smpte st 352 payload identifier packet inse rtion ................................................ 77 4.9.9 line based crc generation and insertion (hd/3g) .............................................. 78 4.9.10 edh generation and insertion ................................................................................... 78 4.9.11 GS2972 3g/hd hanc space consid erations when embedding audio ...... 79 4.9.12 smpte st 372 conversion ........................................................................................... 79 4.9.13 processing feature disable .......................................................................................... 80 4.10 smpte st 352 data extraction ............................................................................................. .. 81 4.11 serial clock pll ......................................................................................................... .................. 82 4.11.1 pll bandwidth........................................................................................................... ...... 82 4.11.2 lock detect............................................................................................................. ........... 83 4.12 serial digital output .................................................................................................... .............. 84 4.12.1 output signal interface levels ................................................................................... 85 4.12.2 overshoot/undershoot .... ........... ........... ........... ........... ........... ........... ........... ........... ..... 85 4.12.3 slew rate selection..................................................................................................... .... 86 4.12.4 serial digital output mute ........................................................................................... 86 4.13 gspi host interface ...................................................................................................... ............... 87 4.13.1 command word descript ion ............... ........... ........... ........... ........... ........... ........... ..... 88 4.13.2 data read or write access........................................................................................... 88 4.13.3 gspi timing............................................................................................................. .......... 89 4.14 host interface register maps ............................................................................................. ..... 91 4.14.1 video core registers.................................................................................................... .. 91 4.14.2 sd audio core........................................................................................................... ..... 100 4.14.3 hd and 3g audio core registers............................................................................. 111 4.15 jtag id codeword ......................................................................................................... .......... 119 4.16 jtag test operation ...................................................................................................... .......... 119 4.17 device power-up .......................................................................................................... ............ 119 4.18 device reset ............................................................................................................. ................... 119
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 7 of 125 www.semtech.com 5. application reference design ................................................................................................ ............. 120 5.1 typical application circuit ............................................................................................... ....... 120 6. references & relevant standards ............................................................................................. .......... 121 7. package & ordering information .............................................................................................. .......... 122 7.1 package dimensions ........................................................................................................ ........... 122 7.2 packaging data ............................................................................................................ ................. 123 7.3 marking diagram ........................................................................................................... .............. 123 7.4 solder reflow profiles .................................................................................................... ............ 124 7.5 ordering information ...................................................................................................... ........... 124 list of figures figure 1-1: pin assignment .................................................................................................... ..................... 10 figure 3-1: differential output stage (sdo/sdo ) .............................................................................. 26 figure 3-2: digital input pin .................................................................................................. ...................... 26 figure 3-3: digital input pin with schmitt trigger (reset ) .............................................................. 26 figure 3-4: digital input pin with weak pull-do wn - maximum pull-down current ............... 27 figure 3-5: digital input pin with weak pull-up - maximum pull-up current ........................... 27 figure 3-6: bidirectional digital input/output pin with programmable drive strength......... 27 figure 3-7: bidirectional digital input/output pin with programmable drive strength......... 28 figure 3-8: vbg ............................................................................................................... ............................... 28 figure 3-9: loop filter ....................................................................................................... ........................... 29 figure 4-1: GS2972 video host interfa ce timing diagrams ............................................................ 31 figure 4-2: h:v:f output timing - 3g level a and hdtv 20-bit mode ...................................... 36 figure 4-3: h:v:f output timing - 3g level a and hdtv 10-bit mode 3g level b 20-bit mode, each 10-bit stream .................................................................................... ..... 36 figure 4-4: h:v:f output timing - 3g level b 10-bit mode ............................................................. 36 figure 4-5: h:v:f input timing - hd 20-bit input mode ................................................................... 36 figure 4-6: h:v:f input timing - hd 10-bit input mode ................................................................... 37 figure 4-7: h:v:f input timing - sd 20-bit mode ............................................................................... 37 figure 4-8: h:v:f input timing - sd 10-bit mode ............................................................................... 37 figure 4-9: h:v:de input timing 1280 x 720p @ 59.94/60 (format 4) ........................................ 39 figure 4-10: h:v:de input timing 1920 x 1080i @ 59.94/60 (format 5) ..................................... 39 figure 4-11: h:v:de input timing 720 (1440) x 480i @ 59.94/60 (format 6&7) ....................... 40 figure 4-12: h:v:de input timing 1280 x 720p @ 50 (format 19) ................................................ 40 figure 4-13: h:v:de input timing 1920 x 1080i @ 50 (format 20) ............................................... 41 figure 4-14: h:v:de input timing 720 (1440) x 576 @ 50 (format 21&22) ................................ 41 figure 4-15: h:v:de input timing 1920 x 1080p @ 59.94/60 (format 16) ................................. 42 figure 4-16: h:v:de input timing 1920 x 1080p @ 50 (format 31) .............................................. 42 figure 4-17: h:v:de input timing 1920 x 1080p @ 23.94/24 (format 32) ................................. 42 figure 4-18: h:v:de input timing 1920 x 1080p @ 25 (format 33) .............................................. 43 figure 4-19: h:v:de input timing 1920 x 1080p @ 29.97/30 (format 34) ................................. 43 figure 4-20: aclk to data and control signal input timing .......................................................... 46 figure 4-21: i 2 s audio input format ....................................................................................................... 47 figure 4-22: aes/ebu audio input format ....................................................................................... ... 48 figure 4-23: serial audio, left justified, msb first .......................................................................... ... 48 figure 4-24: serial audio, left justified, lsb first .......................................................................... .... 48 figure 4-25: serial audio, right justified, msb first ......................................................................... .48 figure 4-26: serial audio, right justified, lsb first ......................................................................... .. 48 figure 4-27: ancillary data packet placement example for sd mode ........................................ 52 figure 4-28: orl matching network, bnc and coaxia l cable connection ............................... 84
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 8 of 125 www.semtech.com figure 4-29: gspi application interface connection .......... .............................................................. 87 figure 4-30: command word format .............................................................................................. ....... 88 figure 4-31: data word format ................................................................................................. ............... 88 figure 4-32: write mode ....................................................................................................... ....................... 89 figure 4-33: read mode ........................................................................................................ ....................... 89 figure 4-34: gspi time delay .................................................................................................. .................. 89 figure 4-35: reset pulse ...................................................................................................... ....................... 119 figure 5-1: typical application circuit ..................... .................................................................. ......... 120 figure 7-1: package dimensions ................................................................................................ ............. 122 figure 7-2: marking diagram ................................................................................................... ................ 123 figure 7-3: pb-free solder reflow profile ..................................................................................... ....... 124 list of tables table 1-1: pin descriptions .................................................................................................... ..................... 11 table 2-1: absolute maximum ratings........................... ................................................................. ....... 20 table 2-2: recommended operating conditions................................................................................ 20 table 2-3: dc electrical characteristics ....................................................................................... .......... 21 table 2-4: ac electrical characteristics ....................................................................................... .......... 23 table 4-1: GS2972 digital input ac el ectrical characteristics ................ ....................................... 31 table 4-2: GS2972 input video data format selections................................................................... 31 table 4-3: GS2972 pclk input rates............................................................................................. .......... 34 table 4-4: cea861 timing formats ............................................................................................... .......... 38 table 4-5: serial audio input pin description................ .................................................................. .... 45 table 4-6: GS2972 serial audio data inputs - ac el ectrical characteristics............................. 46 table 4-7: audio input formats ................................................................................................. ............... 47 table 4-8: GS2972 audio operating mode selection ........................................................................ 50 table 4-9: GS2972 sd audio crosspoint channel selection . .......................................................... 54 table 4-10: audio source host interface fields ............... .................................................................. . 54 table 4-11: GS2972 sd audio buffer size selection .......................................................................... 56 table 4-12: GS2972 sd audio five frame sequence sample count............................................ 58 table 4-13: GS2972 sd audio group 1 audio sample distribution - 525 line.......................... 58 table 4-14: GS2972 sd audio group 2 audio sample distribution - 525 line.......................... 59 table 4-15: GS2972 sd audio group 3 audio sample distribution - 525 line.......................... 59 table 4-16: GS2972 sd audio group 4 audio sample distribution - 525 line.......................... 59 table 4-17: GS2972 sd audio group 1 audio sample distribution - 625 line.......................... 59 table 4-18: GS2972 sd audio group 2 audio sample distribution - 625 line.......................... 60 table 4-19: GS2972 sd audio group 3 audio sample distribution - 625 line.......................... 60 table 4-20: GS2972 sd audio group 4 audio sample distribution - 625 line.......................... 60 table 4-21: audio interrupt control ? host interface bit description ......................................... 64 table 4-22: supported video standards.......................................................................................... ....... 72 table 4-23: ioproc register bits ......... ...................................................................................... .............. 80 table 4-24: smpte st 352 packet data.... ....................................................................................... ........ 81 table 4-25: pclk and serial digital clock rates ................................................................................ . 82 table 4-26: GS2972 pll bandwidth............................................................................................... .......... 83 table 4-27: GS2972 lock detect indication ...................................................................................... .... 83 table 4-28: serial digital output - serial output data ra te ............................................................ 84 table 4-29: r set resistor value vs. output swing .............................................................................. 85 table 4-30: serial digital output - overshoot/undershoot ... ............ ........... ........... ........... ......... .... 85 table 4-31: serial digital output - rise/fall time............ ................................................................. .. 86 table 4-32: gspi time delay.................................................................................................... .................. 89 table 4-33: gspi ac characteristics............................................................................................ ............ 90 table 4-34: video core config uration and status registers............................................................ 91 table 4-35: sd audio core configurat ion and status registers................................................... 100
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 9 of 125 www.semtech.com table 4-36: hd and 3g audio core configuration and status registers .................................. 111 table 7-1: packaging data...................................................................................................... ................... 123 table 7-2: ordering information.............................. .................................................................. ............. 124
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 10 of 125 www.semtech.com 1. pin out 1.1 pin assignment fi g ure 1-1: pin assi g nment 1 3 2 45 6 7 8 9 10 a b c d e f g h j k vbg dvb_asi 20bit/ 10bit din18 sdo locked aclk1 jtag/ host reset wclk1 core _gnd sdo din17 sdo_ en/dis f/de h/hsync vco_ gnd pll_ vdd a_gnd detect _trs core _vdd core _gnd core _gnd core _gnd vco_ vdd core _vdd core _vdd standby rsv a_vdd lf tdi a_gnd rsv io_gnd io_vdd cd_vdd cd_gnd pll_ gnd pll_ gnd grp2_en /dis v/vsync sdout_ tdo cs_ tms sdin_ tdi sclk_ tck smpte_ bypass io_gnd io_vdd anc_ blank audio_ int pclk ain_1/2 ain_3/4 ain_5/6 ain_7/8 tim_861 tck ioproc_ en/dis din15 din16 din19 din13 din14 din12 din11 din10 pll_ gnd din9 din8 din7 din6 din5 din4 din3 din1 din0 din2 core _gnd core _gnd core _gnd core _vdd core _gnd cd_gnd cd_gnd cd_gnd rset wclk2 aclk2 tdo tms grp1_en /dis pll_ vdd rsv rsv rsv rsv rsv rate_ sel0 rate_ sel1
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 11 of 125 www.semtech.com 1.2 pin descriptions table 1-1: pin des c riptions pin number name timing ty p e des c ription b3, a2, a1, b2, b1, c 2, c 1, c 3, d1, d2 din[19:10] input parallel data bu s . please refer to the input lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. 20- b it mo d e 20bit/10bit = hi g h data s tream 1/luma d ata input in s mpte mo d e ( s mpte_bypa ss = hi g h) data input in d ata throu g h mo d e ( s mpte_bypa ss = low) 10- b it mo d e 20bit/10bit = low multiplexe d data s tream 1/luma an d data s tream 2/ c hroma d ata input in s mpte mo d e ( s mpte_bypa ss = hi g h) data input in d ata throu g h mo d e ( s mpte_bypa ss = low) dvb-a s i d ata input in dvb-a s i mo d e ( s mpte_bypa ss = low) (dvb_a s i = hi g h) a3 f/de s yn c h- ronous with p c lk input parallel data timin g . please refer to the input lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. tim_8 6 1 = low: use d to in d i c ate the odd / even fiel d of the vi d eo si g nal when dete c t_tr s is set low. the d evi c e will set the f b it in all out g oin g tr s si g nals for the entire perio d that the f input si g nal is hi g h (iopro c _en/di s must also b e hi g h). the f si g nal shoul d b e set hi g h for the entire perio d of fiel d 2 an d shoul d b e set low for all lines in fiel d 1 an d for all lines in pro g ressive s c an systems. the f si g nal is i g nore d when dete c t_tr s = hi g h. tim_8 6 1 = hi g h: the de si g nal is use d to in d i c ate the a c tive vi d eo perio d when dete c t_tr s is low. de is hi g h for a c tive d ata an d low for b lankin g . s ee s e c tion 4.3 an d s e c tion 4.3.2 for timin g d etails. the de si g nal is i g nore d when dete c t_tr s = hi g h.
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 12 of 125 www.semtech.com a4 h/h s yn c s yn c h- ronous with p c lk input parallel data timin g . please refer to the input lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. tim_8 6 1 is low: the h si g nal is use d to in d i c ate the portion of the vi d eo line c ontainin g a c tive vi d eo d ata, when dete c t_tr s is set low. a c tive line blankin g the h si g nal shoul d b e low for the a c tive portion of the vi d eo line. the si g nal g oes low at the first a c tive pixel of the line, an d then g oes hi g h after the last a c tive pixel of the line. the h si g nal shoul d b e set hi g h for the entire horizontal b lankin g perio d , in c lu d in g b oth eav an d s av tr s wor d s, an d low otherwise. tr s base d blankin g (h_ c onfi g = 1 h ) the h si g nal shoul d b e set hi g h for the entire horizontal b lankin g perio d as in d i c ate d b y the h b it in the re c eive d tr s id wor d s, an d low otherwise. tim_8 6 1 = hi g h: the h s yn c si g nal in d i c ates horizontal timin g . s ee s e c tion 4.3 . when dete c t_tr s is hi g h, this pin is i g nore d at all times. if dete c t_tr s is set hi g h an d tim_8 6 1 is set hi g h, the dete c t_tr s feature will take priority. a5, e1, g 10, k8 c ore_vdd input power power supply c onne c tion for d i g ital c ore lo g i c . c onne c t to +1.2v d c d i g ital. a 6 , b 6 pll_vdd input power power supply pin for pll. c onne c t to +1.2v d c analo g . a7 lf analo g output loop filter c omponent c onne c tion. a8 vb g output ban dg ap volta g e filter c onne c tion. a9, d 6 , d7, d8, f4 r s v ? these pins are reserve d an d shoul d b e left un c onne c te d . a10 a_vdd input power vdd for sensitive analo g c ir c uitry. c onne c t to +3.3vd c analo g . b4 p c lk input parallel data bu s c lo c k. please refer to the input lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. 3 g 20- b it mo d ep c lk @ 148.5mhz 3 g 10- b it mo d e ddr p c lk @ 148.5mhz hd 20- b it mo d ep c lk @ 74.25mhz hd 10- b it mo d ep c lk @ 148.5mhz s d 20- b it mo d ep c lk @ 13.5mhz s d 10- b it mo d ep c lk @ 27mhz dvb-a s i mo d ep c lk @ 27mhz b5, c 5, e2, e5, e 6 , f5, f 6 , g 9 c ore_ g nd input power g nd c onne c tion for d i g ital lo g i c . c onne c t to d i g ital g nd. table 1-1: pin des c riptions (continued) pin number name timing ty p e des c ription
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 13 of 125 www.semtech.com b7 v c o_vdd input powe r power pin for v c o. c onne c t to +1.2v d c analo g followe d b y an r c filter (see typi c al appli c ation c ir c uit on pa g e 120 ). v c o_vdd is nominally 0.7v. b8 v c o_ g nd input power g roun d c onne c tion for v c o. c onne c t to analo g g nd. b9, b10 a_ g nd input power g nd pins for sensitive analo g c ir c uitry. c onne c t to analo g g nd. c 4v/v s yn c s yn c h- ronous with p c lk input parallel data timin g . please refer to the input lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. tim_8 6 1 = low: the v si g nal is use d to in d i c ate the portion of the vi d eo fiel d /frame that is use d for verti c al b lankin g , when dete c t_tr s is set low. the v si g nal shoul d b e set hi g h for the entire verti c al b lankin g perio d an d shoul d b e set low for all lines outsi d e of the verti c al b lankin g interval. the v si g nal is i g nore d when dete c t_tr s = hi g h. tim_8 6 1 = hi g h: the v s yn c si g nal in d i c ates verti c al timin g . s ee s e c tion 4.3 for timin g d etails. the v s yn c si g nal is i g nore d when dete c t_tr s = hi g h. c6 , c 7, c 8pll_ g nd input power g roun d c onne c tion for pll. c onne c t to analo g g nd. c 9, d9, e9, f9 c d_ g nd input power g roun d c onne c tion for the serial d i g ital c a b le d river. c onne c t to analo g g nd. c 10, d10 s do, s do output s erial data output s i g nal. s erial d i g ital output si g nal operatin g at 2.97 gb /s, 2.97/1.001 gb s, 1.485 gb /s, 1.485 /1.001 gb /s or 270m b /s. the slew rate of the output is automati c ally c ontrolle d to meet s mpte s t 424, s mpte s t 292 an d s t 259- c spe c ifi c ations a cc or d in g to the settin g of the rate_ s el0 an d rate_ s el1 pins. d3 s tandby input power down input. hi g h to power d own d evi c e. d4 s do_en/di s input c ontrol s i g nal input. please refer to the input lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. use d to ena b le or d isa b le the serial d i g ital output sta g e. when s do_en/di s is low, the serial d i g ital output si g nals s do an d s do are d isa b le d an d b e c ome hi g h impe d an c e. when s do_en/di s is hi g h, the serial d i g ital output si g nals s do an d s do are ena b le d . d5, f7 r s v ? these pins are reserve d an d shoul d b e c onne c te d to c ore_ g nd. table 1-1: pin des c riptions (continued) pin number name timing ty p e des c ription
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 14 of 125 www.semtech.com e3, e4 rate_ s el0, rate_ s el1 input c ontrol s i g nal input. please refer to the input lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. use d to c onfi g ure the operatin g d ata rate. e7 tdi input c ommuni c ation s i g nal input. please refer to the input lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. de d i c ate d j ta g pin. test d ata in. this pin is use d to shift j ta g test d ata into the d evi c e when the j ta g /ho s t pin is low. e8 tm s input c ommuni c ation s i g nal input. please refer to the input lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. de d i c ate d j ta g pin. test mo d e start. this pin is j ta g test mo d e s tart, use d to c ontrol the operation of the j ta g test when the j ta g /ho s t pin is low. e10 c d_vdd input power power for the serial d i g ital c a b le d river. c onne c t to +3.3v d c analo g . f1, f2, h1, h2, j 1, j 2, k1, k2, j 3, k3 din[9:0] input parallel data bu s . please refer to the input lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. in 10- b it mo d e, these pins are not use d . 20- b it mo d e 20bit/10bit = hi g h data s tream 2/ c hroma d ata input in s mpte mo d e s mpte_bypa ss = hi g h dvb_a s i = low data input in d ata throu g h mo d e s mpte_bypa ss = low dvb_a s i = low not use d in dvb-a s i mo d e s mpte_bypa ss = low dvb_a s i = hi g h 10- b it mo d e 20bit/10bit = low hi g h impe d an c e. table 1-1: pin des c riptions (continued) pin number name timing ty p e des c ription rate_ s el0 data rate 0 0 1 0 1 x 1.485 or 1.485/1.001 gb /s 2.97 or 2.97/1.001 gb /s 270m b /s rate_ s el1
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 15 of 125 www.semtech.com f3 dete c t_tr s input c ontrol s i g nal input. please refer to the input lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. use d to sele c t external hvf timin g mo d e or tr s extra c tion timin g mo d e. when dete c t_tr s is low, the d evi c e extra c ts all internal timin g from the supplie d h:v:f or c ea-8 6 1 timin g si g nals, d epen d ent on the status of the tim8 6 1 pin. when dete c t_tr s is hi g h, the d evi c e extra c ts all internal timin g from tr s si g nals em b e dd e d in the supplie d vi d eo stream. f8 tdo output c ommuni c ation s i g nal output. please refer to the output lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. de d i c ate d j ta g pin. j ta g test data output. this pin is use d to shift results from the d evi c e when the j ta g /ho s t pin is low. f10 r s et input an external 1% resistor c onne c te d to this input is use d to set the s do/ s do output si g nal amplitu d e. g 1, h10 io_vdd input power power c onne c tion for d i g ital i/o. c onne c t to +3.3v or +1.8v d c d i g ital. g 2, h9 io_ g nd input power g roun d c onne c tion for d i g ital i/o. c onne c t to d i g ital g nd. g 3tim_8 6 1 input c ontrol s i g nal input. please refer to the input lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. use d to sele c t external c ea-8 6 1 timin g mo d e. when dete c t_tr s is low an d tim-8 6 1 is low, the d evi c e extra c ts all internal timin g from the supplie d h:v:f timin g si g nals. when dete c t_tr s is low an d tim-8 6 1 is hi g h, the d evi c e extra c ts all internal timin g from the supplie d h s yn c , v s yn c , de timin g si g nals. when dete c t_tr s is hi g h, the d evi c e extra c ts all internal timin g from tr s si g nals em b e dd e d in the supplie d vi d eo stream. g 4 20bit/10bit input c ontrol s i g nal input. please refer to the input lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. use d to sele c t the input b us wi d th. g 5dvb_a s i input c ontrol s i g nal input. please refer to the input lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. use d to ena b le/ d isa b le the dvb-a s i d ata transmission. when dvb_a s i is set hi g h an d s mpte_bypa ss is set low, then the d evi c e will c arry out dvb-a s i wor d ali g nment, i/o pro c essin g an d transmission. when s mpte_bypa ss an d dvb_a s i are b oth set low, the d evi c e operates in d ata-throu g h mo d e. table 1-1: pin des c riptions (continued) pin number name timing ty p e des c ription
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 16 of 125 www.semtech.com g6 s mpte_bypa ss input c ontrol s i g nal input. please refer to the input lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. use d to ena b le / d isa b le all forms of en c o d in g / d e c o d in g , s c ram b lin g an d edh insertion. when set low, the d evi c e operates in d ata throu g h mo d e (dvb_a s i= low), or in dvb-a s i mo d e (dvb_a s i = hi g h). no s mpte s c ram b lin g takes pla c e an d none of the i/o pro c essin g features of the d evi c e are availa b le when s mpte_bypa ss is set low. when set hi g h, the d evi c e c arries out s mpte s c ram b lin g an d i/o pro c essin g . g 7iopro c _en/di s input c ontrol s i g nal input. please refer to the input lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. use d to ena b le or d isa b le the i/o pro c essin g features. when iopro c _en/di s is hi g h, the i/o pro c essin g features of the d evi c e are ena b le d . when iopro c _en/di s is low, the i/o pro c essin g features of the d evi c e are d isa b le d . only appli c a b le in s mpte mo d e. g 8re s et input c ontrol s i g nal input. please refer to the input lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. use d to reset the internal operatin g c on d itions to d efault settin g s an d to reset the j ta g sequen c e. normal mo d e ( j ta g /ho s t = low). when low, all fun c tional b lo c ks will b e set to d efault c on d itions an d all input an d output si g nals b e c ome hi g h impe d an c e. when hi g h, normal operation of the d evi c e resumes. j ta g test mo d e ( j ta g /ho s t = hi g h). when low, all fun c tional b lo c ks will b e set to d efault an d the j ta g test sequen c e will b e reset. when hi g h, normal operation of the j ta g test sequen c e resumes. h3 an c _blank input c ontrol s i g nal input. please refer to the input lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. when an c _blank is low, the luma an d c hroma input d ata is set to the appropriate b lankin g levels d urin g the h an d v b lankin g intervals. when an c _blank is hi g h, the luma an d c hroma d ata pass throu g h the d evi c e unaltere d . only appli c a b le in s mpte mo d e. h4 lo c ked output s tatu s s i g nal output. please refer to the output lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. pll lo c k in d i c ation. hi g h in d i c ates pll is lo c ke d . low in d i c ates pll is not lo c ke d . table 1-1: pin des c riptions (continued) pin number name timing ty p e des c ription
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 17 of 125 www.semtech.com h5 g rp2_en/di s input ena b les au d io g roup 2 em b e dd in g . s et hi g h to ena b le. please refer to the input lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. h 6g rp1_en/di s input ena b les au d io g roup 1 em b e dd in g . s et hi g h to ena b le. please refer to the input lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. h7 audio_int output s tatu s s i g nal output. please refer to the output lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. s ummary interrupt from au d io pro c essin g . this si g nal is set hi g h b y the d evi c e to in d i c ate a pro b lem with the au d io pro c essin g whi c h requires the host pro c essor to interro g ate the interrupt status re g isters. io_vdd = +3.3v drive s tren g th = 8ma io_vdd = +1.8v drive s tren g th = 4ma note: by d efault, out of reset, the audio_int pin will output the hd_audio_ c lo c k, rather than the au d io interrupt si g nal. in or d er to output the interrupt fla g s from the au d io c ore as inten d e d , the user must write 0001h to re g ister 0232h. h8 j ta g /ho s t input c ontrol s i g nal input. please refer to the input lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. use d to sele c t j ta g test mo d e or host interfa c e mo d e. when j ta g /ho s t is hi g h, the host interfa c e port is c onfi g ure d for j ta g test. when j ta g /ho s t is low, normal operation of the host interfa c e port resumes an d the separate j ta g pins b e c ome the j ta g port. j 4ain_5/ 6 input s erial au d io input; c hannels 5 an d 6 . please refer to the input lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. j 5w c lk2 input 48khz wor d c lo c k asso c iate d with ain_5/ 6 an d ain_7/8 ( c hannels 5, 6 , 7 an d 8). please refer to the input lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. j6 ain_1/2 input s erial au d io input; c hannels 1 an d 2. please refer to the input lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. j 7w c lk1 input 48khz wor d c lo c k asso c iate d with ain_1/2 an d ain_3/4 ( c hannels 1, 2, 3 an d 4). please refer to the input lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. table 1-1: pin des c riptions (continued) pin number name timing ty p e des c ription
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 18 of 125 www.semtech.com j 8t c k input c ommuni c ation s i g nal input. please refer to the input lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. j ta g s erial data c lo c k s i g nal. this pin is the j ta g c lo c k when the j ta g /ho s t pin is low. j 9 s dout_tdo output c ommuni c ation s i g nal output. please refer to the output lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. s hare d j ta g /ho s t pin. provi d e d for c ompati b ility with the gs 1582. s erial data output/test data output. host mo d e ( j ta g /ho s t = low) this pin operates as the host interfa c e serial output, use d to rea d status an d c onfi g uration information from the internal re g isters of the d evi c e. j ta g test mo d e ( j ta g /ho s t = hi g h) this pin is use d to shift test results an d operates as the j ta g test d ata output, tdo (for new d esi g ns, use the d e d i c ate d j ta g port). note: if the host interfa c e is not b ein g use d leave this pin un c onne c te d . io_vdd = +3.3v drive s tren g th = 12ma io_vdd = +1.8v drive s tren g th = 4ma j 10 sc lk_t c k input c ommuni c ation s i g nal input. please refer to the input lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. s hare d j ta g /ho s t pin. provi d e d for pin c ompati b ility with gs 1582. s erial d ata c lo c k si g nal. host mo d e ( j ta g /ho s t = low) sc lk_t c k operates as the host interfa c e b urst c lo c k, sc lk. c omman d an d d ata rea d /write wor d s are c lo c ke d into the d evi c e syn c hronously with this c lo c k. j ta g test mo d e ( j ta g /ho s t = hi g h) this pin is the te s t mode s tart pin, use d to c ontrol the operation of the j ta g test c lo c k, t c k (for new d esi g ns, use the d e d i c ate d j ta g port). note: if the host interfa c e is not b ein g use d , tie this pin hi g h. k4 ain_7/8 input s erial au d io input; c hannels 7 an d 8. k5 a c lk2 input 6 4 x w c lk asso c iate d with ain_5/ 6 an d ain_7/8 ( c hannels 5, 6 , 7 an d 8). k 6 ain_3/4 input s erial au d io input; c hannels 3 an d 4. k7 a c lk1 input 6 4 x w c lk asso c iate d with ain_1/2 an d ain_3/4 ( c hannels 1, 2, 3an d 4). table 1-1: pin des c riptions (continued) pin number name timing ty p e des c ription
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 19 of 125 www.semtech.com k9 cs _tm s input c ommuni c ation s i g nal input. please refer to the input lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. c hip sele c t / test mo d e start. j ta g test mo d e ( j ta g /ho s t = hi g h) cs _tm s operates as the j ta g test mo d e start, tm s , use d to c ontrol the operation of the j ta g test, an d is a c tive hi g h (for new d esi g ns, use the d e d i c ate d j ta g port). host mo d e ( j ta g /ho s t = low), cs _tm s operates as the host interfa c e c hip s ele c t, cs , an d is a c tive low. k10 s din_tdi input c ommuni c ation s i g nal input. please refer to the input lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. s hare d j ta g /ho s t pin. provi d e d for pin c ompati b ility with gs 1582. s erial d ata in/test d ata in. in j ta g mo d e, this pin is use d to shift test d ata into the d evi c e (for new d esi g ns, use the d e d i c ate d j ta g port). in host interfa c e mo d e, this pin is use d to write a dd ress an d c onfi g uration d ata wor d s into the d evi c e. table 1-1: pin des c riptions (continued) pin number name timing ty p e des c ription
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 20 of 125 www.semtech.com 2. electrical characteristics 2.1 absolute maximum ratings 2.2 recommended operating conditions table 2-1: absolute maximum ratings parameter value/units s upply volta g e, di g ital c ore ( c ore_vdd) -0.3v to +1.5v s upply volta g e, di g ital i/o (io_vdd) -0.3v to +3. 6 v s upply volta g e, analo g +1.2v (pll_vdd, v c o_vdd) -0.3v to +1.5v s upply volta g e, analo g +3.3v ( c d_vdd, a_vdd) -0.3v to +3. 6 v input volta g e ran g e (r s et) -0.3v to ( c d_vdd + 0.3)v input volta g e ran g e (vb g ) -0.3v to (a_vdd + 0.3)v input volta g e ran g e (lf) -0.3v to (pll_vdd + 0.3)v input volta g e ran g e ( d i g ital inputs) -2.0v to +5.25v temperature ran g e -40 c to +85 c s tora g e temperature ran g e -40 c to +125 c peak reflow temperature ( j ede c j - s td-020 c )2 6 0 c e s d s ensitivity, hbm ( j e s d22-a114) 2kv note: absolute maximum ratings are those values beyond which dama ge may occur. functional operation outside of the ranges shown in table 2-1 is not implied. table 2-2: re c ommended operating conditions parameter symbol conditions min ty p max units note operatin g temperature ran g e, am b ient t a ?-20 ? 85 c ? s upply volta g e, di g ital c ore c ore_vdd ? 1.14 1.2 1.2 6 v? s upply volta g e, di g ital i/o io_vdd +1.8v mo d e 1.71 1.8 1.89 v ? +3.3v mo d e 3.13 3.3 3.47 v ? s upply volta g e, pll pll_vdd ? 1.14 1.2 1.2 6 v? s upply volta g e, v c ov c o_vdd ? ? 0.7 ? v 1 s upply volta g e, analo g a_vdd ? 3.13 3.3 3.47 v ? s upply volta g e, c d c d_vdd ? 3.13 3.3 3.47 v ?
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 21 of 125 www.semtech.com 2.3 dc electrical characteristics operatin g temperature ran g e? ? -20 ? 85 c 2 fun c tional temperature ran g e? ? -40 ? 85 c 2 notes: 1. this is 0.7v rather than 1.2v because there is a voltage drop across an external 105 resistor. see typical applic ation circuit . 2. operating temperature range guarantees the para meters given in the dc electrical characteristics and ac electrical characteristics . functional temperature range guarantees a de vice start-up. table 2-2: re c ommended operating conditions (continued) parameter symbol conditions min ty p max units note table 2-3: dc ele c tri c al chara c teristi c s v cc = +3.3v 5%, t a = -20 c to +85 c , unless otherwise shown parameter symbol conditions min ty p max units note system +1.2v s upply c urrent i 1v2 10 b it 3 g ? 135 200 ma ? 20 b it 3 g ? 135 200 ma ? 10/20 b it hd ? 100 1 6 0ma ? 10/20 b it s d ? 75 120 ma ? dvb_a s i ? 75 120 ma ? +1.8v s upply c urrent i 1v8 10 b it 3 g ? 15 30 ma ? 20 b it 3 g ? 15 32 ma ? 10/20 b it hd ? 15 32 ma ? 10/20 b it s d ? 310ma ? dvb_a s i ? 310ma ? +3.3v s upply c urrent i 3v3 10 b it 3 g ? 90 110 ma ? 20 b it 3 g ? 90 110 ma ? 10/20 b it hd ? 90 110 ma ? 10/20 b it s d ? 70 90 ma ? dvb_a s i ? 70 90 ma ? total devi c e power (io_vdd = +1.8v) p 1d8 10 b it 3 g ? 400 5 6 0mw ? 20 b it 3 g ? 400 5 6 0mw ? 10/20 b it hd ? 350 510 mw ? 10/20 b it s d ? 300 450 mw ? dvb_a s i ? 300 450 mw ? reset ? 200 ? mw ? s tan db y ? 110 180 mw 1
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 22 of 125 www.semtech.com total devi c e power (io_vdd = +3.3v) p 3d3 10 b it 3 g ? 430 6 00 mw ? 20 b it 3 g ? 450 6 10 mw ? 10/20 b it hd ? 420 550 mw ? 10/20 b it s d ? 320 450 mw ? dvb_a s i ? 320 450 mw ? reset ? 230 ? mw ? s tan db y ? 110 180 mw 1 digital i/o input lo g i c low v il +3.3v or +1.8v operation io_v ss -0.3 ? 0.3 x io_vdd v ? input lo g i c hi g h v ih +3.3v or +1.8v operation 0.7 x io_vdd ? io_vdd+0.3 v ? output lo g i c low v ol iol=5ma, +1.8v operation ?? 0.2 v ? iol=8ma, +3.3v operation ?? 0.4 v ? output lo g i c hi g h v oh ioh=-5ma, +1.8v operation 1.4 ? ?v ? ioh=-8ma, +3.3v operation 2.4 ? ?v ? serial output s erial output c ommon mo d e volta g e v c mout 75 loa d , r s et = 750 s d an d hd mo d e ? c d_vdd - v s dd/2 ? v ? note: 1. devices manufactured prior 1 to april 1, 2011 consume 150mw of power in standby mode. table 2-3: dc ele c tri c al chara c teristi c s (continued) v cc = +3.3v 5%, t a = -20 c to +85 c , unless otherwise shown parameter symbol conditions min ty p max units note
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 23 of 125 www.semtech.com 2.4 ac electrical characteristics table 2-4: ac ele c tri c al chara c teristi c s v cc = +3.3v 5%, t a = -20 c to +85 c , unless otherwise shown parameter symbol conditions min ty p max units note system devi c e laten c y ? 3 g b ypass (p c lk = 148.5 mhz) ?54?p c lk ? ? 3 g s mpte without au d io (p c lk = 148.5 mhz) ?95?p c lk ? ? 3 g s mpte with au d io (p c lk = 148.5 mhz) ? 110 6 ?p c lk ? ? 3 g iopro c d isa b le d 20- b it mo d e (p c lk = 148.5mhz) ?94?p c lk ? ? hd b ypass (p c lk = 74.25 mhz) ?54?p c lk ? ? hd s mpte without au d io (p c lk = 74.25 mhz) ?95?p c lk ? ? hd s mpte with au d io (p c lk = 74.25 mhz) ? 110 6 ?p c lk ? ? hd iopro c d isa b le d 10- b it mo d e (p c lk = 74.25mhz) 98 ? s d b ypass (p c lk = 27 mhz) ?54?p c lk ? ? s d s mpte without au d io ? 112 ? p c lk ? ? s d s mpte with au d io ? 6 38 ? p c lk ? ? s d iopro c d isa b le d 10- b it mo d e (p c lk = 27mhz) ?94?p c lk ? ?dvb-a s i?52?p c lk ? reset pulse wi d th t reset ?1??ms? parallel input parallel c lo c k frequen c y f p c lk ? 13.5 ? 148.5 mhz ? parallel c lo c k duty c y c le d c p c lk ?40? 6 0%? input data s etup time t su 50% levels; +3.3v or +1.8v operation 1.2 ? ? ns 1 input data hol d time t ih 0.8 ? ? ns 1 serial digital output
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 24 of 125 www.semtech.com s erial output data rate dr s do ? ? 2.97 ? gb /s ? ? ? 2.97/1.001 ? gb /s ? ? ? 1.485 ? gb /s ? ? ? 1.485/1.001 ? gb /s ? ? ? 270 ? m b /s ? s erial output s win g v s dd r s et = 750 75 loa d 750 800 850 mv pp 2 s erial output rise/fall time 20% ~ 80% trf s do 3 g /hd mo d e ? 120 135 ps ? trf s do s d mo d e 400 66 0 800 ps ? mismat c h in rise/fall time t r , t f ???35ps? duty c y c le distortion ? ? ? ? 5 % 2 overshoot ?3 g /hd mo d e? 510% 2 ? s d mo d e?38% 2 output return loss orl 1.485 g hz - 2.97 g hz ?-12? d b 3 5 mhz - 1.485 g hz ? -18 ? d b 3 s erial output intrinsi c j itter t o j pseu d oran d om an d s mpte c olour bars 3 g si g nal ?40 6 8ps 4 , 6 t o j pseu d oran d om an d s mpte c olour bars hd si g nal ?5095ps 4 , 6 s erial output intrinsi c j itter t o j pseu d oran d om an d s mpte c olour bars s d si g nal ? 200 400 ps 5 gspi gs pi input c lo c k frequen c y f sc lk 50% levels +3.3v or +1.8v operation ??80mhz? gs pi input c lo c k duty c y c le d c sc lk 40 50 6 0%? gs pi input data s etup time ? 1.5 ? ? ns ? gs pi input data hol d time ? 1.5 ? ? ns ? gs pi output data hol d time ? 15pf loa d 1.5 ? ? ns ? cs low b efore sc lk risin g e dg e t 0 50% levels +3.3v or +1.8v operation 1.5 ? ? ns ? time b etween en d of c omman d wor d (or d ata in auto-in c rement mo d e) an d the first sc lk of the followin g d ata wor d - write c y c le t 4 50% levels +3.3v or +1.8v operation p c lk (mhz) ns ??ns? unlo c ke d 445 13.5 74.2 27.0 37.1 74.25 13.5 148.5 6 .7 table 2-4: ac ele c tri c al chara c teristi c s (continued) v cc = +3.3v 5%, t a = -20 c to +85 c , unless otherwise shown parameter symbol conditions min ty p max units note
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 25 of 125 www.semtech.com time b etween en d of c omman d wor d (or d ata in auto-in c rement mo d e) an d the first sc lk of the followin g d ata wor d - rea d c y c le t 5 50% levels +3.3v or +1.8v operation p c lk (mhz) ns ??ns? unlo c ke d 1187 13.5 297 27.0 148.4 74.25 53.9 148.5 27 cs hi g h after sc lk fallin g e dg e t 7 50% levels +3.3v or +1.8v operation p c lk (mhz) ns ??ns? unlo c ke d 445 13.5 74.2 27.0 37.1 74.25 13.5 148.5 6 .7 notes: 1. input setup and hold time is de pendent on the rise and fall time on the parallel input . parallel clock and data with rise tim e or fall time greater than 500ps require larger setup and hold times. 2. single ended into 75 external load. 3. orl depends on board design. 4. alignment jitter = measured from 100khz to seri al data rate/10. 5. alignment jitter = measured from 1khz to 27mhz. 6. this is the maximum jitter for a ber of 10-12. the equivalent ji tter value as per rp184 is 40ps max. table 2-4: ac ele c tri c al chara c teristi c s (continued) v cc = +3.3v 5%, t a = -20 c to +85 c , unless otherwise shown parameter symbol conditions min ty p max units note
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 26 of 125 www.semtech.com 3. input/output circuits fi g ure 3-1: differential output s ta g e ( s do/ s do ) fi g ure 3-2: di g ital input pin (20 b it/ 10 b it , an c _blank , dete c t_tr s , dvb_a s i, rate_ s el0, s mpte_bypa ss , rate_ s el1, tim_8 6 1, f/de, h/h s yn c , p c lk, v/v s yn c ) fi g ure 3-3: di g ital input pin with sc hmitt tri gg er ( re s et ) i ref c d_vdd s do s do io_vdd 200 input pin io_vdd 200 input pin
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 27 of 125 www.semtech.com fi g ure 3-4: di g ital input pin with weak pull- d own - maximum pull- d own c urrent <110a ( j ta g / ho s t , s tandby, sc lk_t c k, s din_tdi, t c k, tdi) fi g ure 3-5: di g ital input pin with weak pull-up - maximum pull-up c urrent <110a (a c lk1, a c lk2, ain_7/8, ain_5/ 6 , ain_3/4, ain_1/2, cs _tm s , g rp1_en/ di s , g rp2_en/ di s , iopro c _en/ di s , s do_en/ di s , tm s , w c lk1, w c lk2) fi g ure 3- 6 : bi d ire c tional di g ital input/output pin with pro g ramma b le d rive stren g th. these pins are c onfi g ure d to input at all times ex c ept in test mo d e. (din0, din2, din3, din4, din5, din 6 , din7, din8, din9, di n10, din11, din12, din13, din14, din15, din1 6 , din17, din18, din19, din1) io_vdd 200 input pin 200 input pin io_vdd io_vdd io_vdd 200 output pin
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 28 of 125 www.semtech.com fi g ure 3-7: bi d ire c tional di g ital input/output pin with pro g ramma b le d rive stren g th. these pins are c onfi g ure d to output at all times ex c ept in reset mo d e. (lo c ked, audio_int, s dout_tdo, tdo) fi g ure 3-8: vb g io_vdd 200 output pin vb g 50 2k a_vdd
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 29 of 125 www.semtech.com fi g ure 3-9: loop filter 30 pll_vdd lf 30
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 30 of 125 www.semtech.com 4. detailed description 4.1 functional overview the GS2972 is a multi-rate tr ansmitter with integrated smpte digital video processing and an integrated cable driver and embe dded audio multiplexer. it provides a complete transmit solution at 2.970gb/s, 2.970/1.001gb/s, 1.485gb/s, 1.485/1.001gb/s or 270mb/s. the device has four basic modes of operation that must be set through external device pins: smpte mode, dvb-asi mode, data-through mode and standby mode. in smpte mode, the device will accept 10- bit multiplexed or 20-bit demultiplexed smpte compliant data. by default, the device's additional processing features, including audio embedding, will be enabled in this mode. in dvb-asi mode, the GS2972 wi ll accept an 8-bit parallel dvb-asi compliant transport stream on din[17:10]. the serial output data stream will be 8b/10b encoded with stuffing characters added as per the standard. data-through mode allows for the serializing of data not conforming to smpte or dvb-asi streams. no additional processing will be done in this mode. in addition, the device may be put into standby, to reduce power consumption. the serial digital output features a high-impedance mode and adjustable signal swing. the output slew rate is automatically set by the rate_sel0 and rate_sel1 pin setting. the GS2972 provides several data processing functions; including generic anc insertion, smpte st 352 and edh data packet generation and insertion, automatic video standards detection, and trs, crc, anc data checksum, and line number calculation and insertion. these features are all enabled/disabled collectively using the external i/o processing pin, but may be individually disabled via internal registers accessible through the gspi host interface. finally, the GS2972 contains a jtag interfac e for boundary scan test implementations.
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 31 of 125 www.semtech.com 4.2 parallel data inputs data signal inputs enter the device on the rising edge of pclk, as shown in figure 4-1 . fi g ure 4-1: gs 2972 vi d eo host interfa c e timin g dia g rams ds1_0 transition zone ds2_0 transition zone pclk 3.36ns ds1_n-1 ds1_n-1 transition zone ds2_0 t su t h t h ds1_0 ddr interface note: ds = data stream as per smpte st 425 ds2_* is launched on the negative edge of pclk by the source chip to the GS2972 ds1_* is launched on the positive edge of pclk by the source chip to the GS2972 t su data_1 transition zone data_1 data_0 transition zone pclk pclk period din[19:0], f_de, h_hsync, v_vsync data_0 t h sdr interface ds* is launched on the positive edge of pclk by the source chip to the GS2972 t su t h t su din[19:0], f_de, h_hsync, v_vsync t h t h table 4-1: GS2972 digital input ac ele c tri c al chara c teristi c s parameter symbol conditions min ty p max units input d ata set-up time t s u 50% levels; +1.8v operation 1.2 - - ns input d ata hol d time t ih 0.8 - - ns input d ata set-up time t s u 50% levels; +3.3v operation 1.3 - - ns input d ata hol d time t ih 0.8 - - ns table 4-2: GS2972 input video data format sele c tions input data format pin/register bit settings din[9:0] din[19:10] 20bit /10bit rate _sel0 rate _sel1 smpte _bypass dvb_asi 20- b it d emultiplexe d 3 g format hi g hlowhi g hhi g hlow data s tream two data s tream one 20- b it d ata input 3 g format hi g hlowhi g hlow low data data 20- b it d emultiplexe d hd format hi g hlowlow hi g hlow c hroma luma
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 32 of 125 www.semtech.com the GS2972 is a high performance 3gb/s capabl e transmitter. in or der to optimize the output jitter performance across all operating conditions, input levels and overshoot at the parallel video data inputs of the device need to be controlled. in order to do this, source series termination resistors should be used to match the impedance of the pcb data trace line. ibis models can be used to simulate the board effects and then optimize the output drive strength and the termination resistors to allow for the best transition (one that produces minimal overshoot). if this is not viable, semtech recommends matching the source series resistance to the trace impedance, and then adjusting the output drive strength to the minimum value that will give zero errors. the above also applies to the pclk input line . hvf and the audio inputs should also be well terminated, however due to the lower data rates and transition density it is not as critical. 20- b it d ata input hd format hi g h low low low low data data 20- b it d emultiplexe d s d format hi g hhi g hx hi g hlow c hroma luma 20- b it d ata input s d format hi g hhi g hx low low data data 10- b it multiplexe d 3 g ddr format low low hi g hhi g hlow hi g h impe d an c e data s tream one/data s tream two 10- b it multiplexe d hd format low low low hi g hlow hi g h impe d an c e luma/ c hroma 10- b it d ata input hd format low low low low low hi g h impe d an c e data 10- b it multiplexe d s d format low hi g hx hi g hlow hi g h impe d an c e luma/ c hroma 10- b it multiplexe d s d format low hi g hx low low hi g h impe d an c e data 10- b it a s i input s d format low hi g hx lowhi g h hi g h impe d an c e dvb-a s i d ata table 4-2: GS2972 input video data format sele c tions (continued) input data format pin/register bit settings din[9:0] din[19:10] 20bit /10bit rate _sel0 rate _sel1 smpte _bypass dvb_asi
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 33 of 125 www.semtech.com 4.2.1 parallel input in smpte mode when the device is operatin g in smpte mode (smpte_bypass = high), data must be presented to the input bus in either multiplexed or demultiplexed form, depending on the setting of the 20bit/10bit pin. when operating in 20-b it mode (20bit/10bit = high), the input data format must be word aligned, demultiplexed luma and chro ma data (sd or hd), or word aligned demultiplexed data stream one an d data stream two data (3g). in 3g level b mode, by default, the device takes data stream one input from data port din[19:10] and data stream two input from din[9:0]. when operating in 10-b it mode (20bit/10bit = low), the input data format must be multiplexed luma (y) and chro ma (c) data (sd, hd), or mul tiplexed data stream one and data stream two data (3g). c words pr ecede y words, and data stream 2 words precede data stream 1 words. in this mode, the data must be presented on the din[19:10] pins. the din[9:0] inputs are ignored. in 3g 10-bit mode, the device operates in ddr mode. that is , the input data is sampled on both the rising and falling edges of the pclk. in 3g mode, data stream two words precede data stream one words. the data stream two words are sampled on the rising edge of the input pclk, and the data stream one words are sampled on the following falling edge. h, v and f timing pulses, if us ed, are sampled on the rising edge of pclk. 4.2.1.1 input data format in sdti mode sdti and hd-sdti are a sub-set of sdi and hd -sdi formats. they ma y contain sdti data on any line in the frame. those lines which contain sdti or hd-sdti data are identified with an sdti or hd-sdti head er packet in the hanc space. the GS2972 does not differentiate between a si gnal carrying video and a signal carrying sdti or hd-sdti data in sd or hd formats. the user is responsible for ensuring that the headers and data are not corrupted. 4.2.2 parallel input in dvb-asi mode the GS2972 is in dvb-asi mode when the smpte_bypass pin is set low, the dvb_asi pin is set high, and the rate_sel0 pin is set high. in this mode, all smpte processing features are disabled. when operating in dvb-asi mode, the device must be set to 10-bit mode by setting the 20bit/10bit pin low. the device will accept 8-bit data words on din[17:10], where din17 = hin is the most significant bit of the encoded transport stream data and din10 = ain is the least significant bit. in addition, din19 and din18 will be configured as the dvb-asi control signals inssyncin and ki n respectively. din19 = inssyncin din18 = kin din17~10 = hin ~ ain where ain is the least significant bit of the transport stream data.
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 34 of 125 www.semtech.com 4.2.3 parallel input in data-through mode data-through mode is enabled when the smpte_bypass pin and the dvb_asi pin are low. in this mode, data at the input bus is serialized without any encoding, scrambling or word alignment taking place. the input data width is controlled by the setting of the 20bit/10bit pin as shown in table 4-2 above. note: when in hd 10-bit mode, asserting the smpte_bypass low to put the device in smpte-bypass mode will create video errors. if the user desires to use the device as a simple serializer in hd 10-bit mode, all vi deo processing features may be disabled by setting the ioproc_en/dis pin low. 4.2.4 parallel input clock (pclk) the frequency of the pclk input signal of the GS2972 is determined by the input data format and operating mode selection. table 4-3 below lists the input pclk rates and input signal formats according to the external selection pins for the GS2972. table 4-3: GS2972 pclk input rates input data format pin settings pclk rate 20bit/10bit rate_ sel0 rate_ sel1 smpte_ bypass dvb-asi 20- b it d emultiplexe d 3 g format hi g hlowhi g hhi g h x 148.5 or 148.5/1.001mhz 20- b it d emultiplexe d hd format hi g hlowlowhi g h x 74.25 or 74.25/1.001mhz 20- b it d ata input 3 g format hi g hlowhi g h low low 148.5 or 148.5/1.001mhz 20- b it d ata input hd format hi g h low low low low 74.25 or 74.25/1.001mhz 20- b it d emultiplexe d s d format hi g hhi g hx hi g h low 13.5mhz 20- b it d ata input s d format hi g hhi g h x low low 13.5mhz 10- b it multiplexe d 3 g ddr format low low hi g hhi g h low 148.5 or 148.5/1.001mhz 10- b it multiplexe d hd format low low low hi g h low 148.5 or 148.5/1.001mhz 10- b it d ata input hd format low low low low low 148.5 or 148.5/1.001mhz 10- b it multiplexe d s d format low hi g hx hi g h x 27mhz
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 35 of 125 www.semtech.com 4.3 smpte mode the function of this block is to carry out data scrambling according to smpte st 424/smpte st 292, and to carry out nrz to nrzi en coding pr ior to presentation to the parallel to serial converter. these functions are only enabled when the smpte_bypass pin is high. in addition, the GS2972 requires the dvb_asi pin to be set low to enable this feature. 4.3.1 h:v:f timing in smpte mode, the GS2972 can automatically detect the video stan dard and generate all internal timing signals. the total line length, active line length, total number of lines per field/frame and total active lines per field/frame are calculated for the received parallel video. when detect_trs is low, the video standa rd and timing signals are based on the externally supplied h_blanking, v_blanking, and f_digital signals. these signals are supplied by the h/hsync, v/vsync and f/de pins respectively. when detect_trs is high, the video standard timing signals wi ll be extracted from the embedded trs id words in the parallel input data. both 8-bit and 10-bit trs code words will be identified by the device. note: i/o processing must be enabled for the device to remap 8-bit trs words to the corresponding 10-bit value for transmission. the GS2972 determines the video standard by timing the horizontal and vertical reference information supplied at the h/hs ync, v/vsync, and f/de input pins, or contained in the trs id words of the received video data. therefore, full synchronization to the received video standard requires at least one complete video frame. once synchronization has been achieved, the GS2972 will continue to monitor the received trs timing or the supplied h, v, and f timing information to maintain synchronization. the GS2972 will lose all ti ming information immediately following loss of h, v and f. the h signal timing should also be configured via the h_config bit of the internal ioproc register as either active line based blanki ng or trs based blanking. active line based blanking is enabled when the h_config bit is set low. in this mode, the h input should be high for the entire horizontal blanking period, including the eav and sav trs words. this is the defa ult h timing used by the device. 10- b it d ata input s d format low hi g h x low low 27mhz 10- b it a s i input s d format low hi g hx lowhi g h 27mhz table 4-3: GS2972 pclk input rates (continued) input data format pin settings pclk rate 20bit/10bit rate_ sel0 rate_ sel1 smpte_ bypass dvb-asi
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 36 of 125 www.semtech.com the timing of these signals is shown in figure 4-5 , figure 4-6 , figure 4-7 , figure 4-8 , table 4-6 , table 4-7 and table 4-8 . fi g ure 4-2: h:v:f output timin g - 3 g level a an d hdtv 20- b it mo d e fi g ure 4-3: h:v:f output timin g - 3 g level a an d hdtv 10- b it mo d e 3 g level b 20- b it mo d e, ea c h 10- b it stream fi g ure 4-4: h:v:f output timin g - 3 g level b 10- b it mo d e fi g ure 4-5: h:v:f input timin g - hd 20- b it input mo d e pclk luma data chroma data h 000 000 3ff 000 000 3ff v f xyz (sav) 000 000 3ff 000 000 3ff xyz (sav) xyz (eav) xyz (eav) 000 000 3ff 3ff 000 000 pclk (hd) h v f multiplexed y?cbcr data (hd) multiplexed ds1/ds2 data (3g) pclk (3g ddr) 000 000 3ff 3ff 000 000 xyz (eav) multiplexed y?cbcr data (hd) multiplexed ds1/ds2 data (3g) h v f pclk (hd) pclk (3g ddr) h signal timing: h_config = low h_config = high hvf timingat sav hvf timingat eav xyz (eav) xyz (sav) xyz (sav) 3ff pclk (ddr) h v f multiplexed linka/linkb data 3ff 3ff 3ff 000 000 000 000 000 000 000 000 xyz (sav) xyz (sav ) xyz (sav) xyz (sav ) multiplexed linka/linkb data pclk (ddr) h v f 3ff 000 000 000 000 000 000 000 000 xyz (eav) xyz (eav) xyz (eav) xyz (eav) 3ff 3ff 3ff h signal timing: h_config = low h_config = high hvf timingat eav hvf timingat sav p c lk lu m a d a t a in p u t c hroma data input h x y z (eav) 000 000 3ff 000 000 3ff v f 000 000 3ff 000 000 3ff x y z (eav) x y z ( s av) x y z ( s av) h s i g nal timin g : h_ c onfi g = low h_ c onfi g = hi g h
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 37 of 125 www.semtech.com fi g ure 4- 6 : h:v:f input timin g - hd 10- b it input mo d e fi g ure 4-7: h:v:f input timin g - s d 20- b it mo d e fi g ure 4-8: h:v:f input timin g - s d 10- b it mo d e hvf timin g at s av 000 000 3ff 3ff 000 000 p c lk multiplexed y' cbc r d a t a in p u t h v f hvf timin g at eav p c lk 000 000 3ff 3ff x y z (eav) 000 000 multiplexed y' cbc r d a t a in p u t h v f x y z (eav) xyz ( s av) x y z ( s av) p c lk c hroma data input luma data input h 000 3ff x y z (eav) 000 v f 000 3ff 000 h s i g nal timin g : h_ c onfi g = low h_ c onfi g = hi g h x y z ( s av) multiplexed y' cbc r data input p c lk h v f x y z (eav) 000 000 3ff 000 000 3ff x y z ( s av) h s i g nal timin g : h_ c onfi g = low h_ c onfi g = hi g h
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 38 of 125 www.semtech.com 4.3.2 cea 861 timing the GS2972 extracts timing information from externally provided hsync, vsync, and de signals when cea 861 timing mode is selected by setting detect_trs = low and tim_861 = high. horizontal sync (h), vertical sync (v), and data enable (de) timing must be provided via the h/hsync, v/vsync and f/de input pins. the host interface register bit h_config is ignored in cea 861 input timing mode. the GS2972 determines the eia/cea-861 st andard and embeds eav and sav trs words in the output serial video stream. video standard detection is not dependent on the hsync pulse width or the vsync pulse width and therefore the GS2972 tolerates non-standard pulse wi dths. in addition, the device can compensate for up to 1 pclk cycle of jitter on vsync with respect to hsync and sample vsync correctly. note 1: the period between the leading edge of the hsync pulse and the leading edge of data enable (de) must follow the timing requirements described in the eia/cea-861 specification. the GS2972 embeds trs words according to this timing relationship to maintain compatibility with the corresponding smpte standard. note 2: when cea 861 standards 6 & 7 [720( 1440)x480i] are presented to the GS2972, the device embeds trs words corresponding to the timing defined in smpte st 125 to maintain smpte compatibility. cea 861 standards 6 & 7 [720(1440)x480i] define the active area on lines 22 to 261 and 285 to 524 inclusive (240 active lines per field). smpte st 125 defines the active area on lines 20 to 263 and 283 to 525 inclusive (244 lines on field 1, 243 lines on field 2). therefore, in the first field, the GS2972 adds two active lines above and two active lines below the original active image. in the second field, it adds two lines above and one line below the original active image. the cea861 timing formats are summarized in table 4-4 . and are shown in figure 4-9 to figure 4-19 . table 4-4: cea861 timing formats format parameters 4 h:v:de input timin g 1280 x 720p @ 59.94/ 6 0hz 5 h:v:de input timin g 1920 x 1080i @ 59.94/ 6 0hz 6 &7 h:v:de input timin g 720 (1440) x 480i @ 59.94/ 6 0hz 19 h:v:de input timin g 1280 x 720p @ 50hz 20 h:v:de input timin g 1920 x 1080i @ 50hz 21&22 h:v:de input timin g 720 (1440) x 57 6 @ 50hz 1 6 h:v:de input timin g 1920 x 1080p @ 59.94/ 6 0hz 31 h:v:de input timin g 1920 x 1080p @ 50hz 32 h:v:de input timin g 1920 x 1080p @ 23.94/24hz 33 h:v:de input timin g 1920 x 1080p @ 25hz 34 h:v:de input timin g 1920 x 1080p @ 29.97/30hz
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 39 of 125 www.semtech.com fi g ure 4-9: h:v:de input timin g 1280 x 720p @ 59.94/ 6 0 (format 4) fi g ure 4-10: h:v:de input timin g 1920 x 1080i @ 59.94/ 6 0 (format 5) 1 66 0 total horizontal c lo c ks per line 1280 c lo c ks for a c tive vi d eo data ena b le 220 c lo c ks 40 370 110 h s yn c pro g ressive frame: 30 verti c al blankin g lines 720 a c tive verti c al lines 1 6 50 c lo c ks data ena b le h s yn c 110 v s yn c 2 6 0 745 74 6 747 748 749 750 1 2 3 4 5 6 7 25 2 6 745 74 6 750 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 148 c lo c ks 1920 c lo c ks for a c tive vi d eo 280 data ena b le h s yn c v s yn c 1123 1124 1125 1 2 3 4 5 6 7 8 data ena b le h s yn c 2200 total horizontal c lo c ks per line 44 88 fiel d 1: 22 verti c al blankin g lines 2200 c lo c ks 88 19 20 21 5 6 0 5 6 1 5 6 2 192 540 a c tive verti c al lines per fiel d 540 a c tive verti c al lines per fiel d fiel d 2: 23 verti c al blankin g lines 192 88 2200 c lo c ks 1100 v s yn c data ena b le h s yn c 5 6 0 5 6 1 5 6 2 5 6 3 5 6 4 5 6 5 5 66 5 6 7 5 6 8 5 6 9 570 582 583 584 1123 1124 1125 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 40 of 125 www.semtech.com fi g ure 4-11: h:v:de input timin g 720 (1440) x 480i @ 59.94/ 6 0 (format 6 &7) fi g ure 4-12: h:v:de input timin g 1280 x 720p @ 50 (format 19) 1440 c lo c ks for a c tive vi d eo 27 6 data ena b le 171 6 total horizontal c lo c ks per line h s yn c data ena b le h s yn c v s yn c data ena b le h s yn c v s yn c 114 c lo c ks 124 38 fiel d 1: 22 verti c al blankin g lines 171 6 c lo c ks 238 240 a c tive verti c al lines per fiel d ~ ~ ~ ~ 38 240 a c tive verti c al lines per fiel d fiel d 2: 23 verti c al blankin g lines ~ ~ 524 525 1 2 3 4 5 6 7 8 9 21 22 ~ ~ ~ ~ 238 38 171 6 c lo c ks 858 2 6 1 2 6 2 2 6 3 2 6 4 2 6 5 2 66 2 6 7 2 6 8 2 6 9 270 271 524 525 1 284 285 2 6 1 2 6 2 2 6 3 220 c lo c ks 1280 c lo c ks for a c tive vi d eo 700 data ena b le h s yn c v s yn c 745 74 6 747 748 749 750 1 2 3 4 5 6 7 data ena b le h s yn c 1980 total horizontal c lo c ks per line 40 440 pro g ressive frame: 30 verti c al blankin g lines 1980 c lo c ks 440 745 74 6 2 6 0 720 a c tive verti c al lines ~ ~ ~ ~ ~ ~ ~ 25 2 6 ~ ~ ~ ~ 750
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 41 of 125 www.semtech.com fi g ure 4-13: h:v:de input timin g 1920 x 1080i @ 50 (format 20) fi g ure 4-14: h:v:de input timin g 720 (1440) x 57 6 @ 50 (format 21&22) 148 clocks 1920 clocks for active video 720 data enable hsync 2640 total horizontal clocks per line 44 528 vsync 1123 1124 1125 1 2 3 4 5 6 7 8 data enable hsync field 1: 22 vertical blanking lines 2640 clocks 528 19 20 21 560 561 562 192 540 active vertical lines per field 540 active vertical lines per field field 2: 23 vertical blanking lines 192 528 2640 clocks 1320 vsync data enable hsync 560 561 562 563 564 565 566 567 568 569 570 582 583 584 1123 1124 1125 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 1440 c lo c ks for a c tive vi d eo 288 data ena b le 1728 total horizontal c lo c ks per line h s yn c 138 c lo c ks 12 6 24 data ena b le h s yn c v s yn c data ena b le h s yn c v s yn c fiel d 1: 24 verti c al blankin g lines 1728 c lo c ks 2 6 4 288 a c tive verti c al lines per fiel d ~ ~ ~ ~ 24 288 a c tive verti c al lines per fiel d fiel d 2: 25 verti c al blankin g lines ~ ~ 6 23 6 24 6 25 1 2 3 4 5 6 7 22 23 ~ ~ ~ ~ 2 6 4 24 1728 c lo c ks 8 6 4 310 311 312 313 314 315 31 6 317 318 319 320 6 23 6 24 6 25 335 33 6 310 311 312 ~ ~
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 42 of 125 www.semtech.com fi g ure 4-15: h:v:de input timin g 1920 x 1080p @ 59.94/ 6 0 (format 1 6 ) fi g ure 4-1 6 : h:v:de input timin g 1920 x 1080p @ 50 (format 31) fi g ure 4-17: h:v:de input timin g 1920 x 1080p @ 23.94/24 (format 32) 148 c lo c ks 1920 c lo c ks for a c tive vi d eo 280 data ena b le h s yn c 2200 total horizontal c lo c ks per line 44 88 v s yn c 1121 1122 1123 1124 1125 1 2 3 4 5 6 7 data ena b le h s yn c pro g ressive frame: 45 verti c al blankin g lines 2200 c lo c ks 88 1121 1122 1123 1124 1125 192 1080 a c tive verti c al lines ~ ~ ~ ~ ~ ~ 41 42 ~ ~ ~ 148 c lo c ks 1920 c lo c ks for a c tive vi d eo 720 data ena b le h s yn c 2 6 40 total horizontal c lo c ks per line 44 528 v s yn c 1121 1122 1123 1124 1125 1 2 3 4 5 6 7 data ena b le h s yn c pro g ressive frame: 45 verti c al blankin g lines 2 6 40 c lo c ks 528 1121 1122 1123 1124 1125 192 1080 a c tive verti c al lines ~ ~ ~ ~ ~ ~ 41 42 ~ ~ ~ 148 c lo c ks 1920 c lo c ks for a c tive vi d eo 830 data ena b le h s yn c 2750 total horizontal c lo c ks per line 44 6 38 v s yn c 1121 1122 1123 1124 1125 1 2 3 4 5 6 7 data ena b le h s yn c pro g ressive frame: 45 verti c al blankin g lines 2750 c lo c ks 6 38 1121 1122 1123 1124 1125 192 1080 a c tive verti c al lines ~ ~ ~ ~ ~ ~ 41 42 ~ ~ ~
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 43 of 125 www.semtech.com fi g ure 4-18: h:v:de input timin g 1920 x 1080p @ 25 (format 33) fi g ure 4-19: h:v:de input timin g 1920 x 1080p @ 29.97/30 (format 34) 148 c lo c ks 1920 c lo c ks for a c tive vi d eo 720 data ena b le h s yn c 2 6 40 total horizontal c lo c ks per line 44 528 v s yn c 1121 1122 1123 1124 1125 1 2 3 4 5 6 7 data ena b le h s yn c pro g ressive frame: 45 verti c al blankin g lines 2 6 40 c lo c ks 528 1121 1122 1123 1124 1125 192 1080 a c tive verti c al lines ~ ~ ~ ~ ~ ~ 41 42 ~ ~ ~ 148 c lo c ks 1920 c lo c ks for a c tive vi d eo 280 data ena b le h s yn c 2200 total horizontal c lo c ks per line 44 88 v s yn c 1121 1122 1123 1124 1125 1 2 3 4 5 6 7 data ena b le h s yn c pro g ressive frame: 45 verti c al blankin g lines 2220 c lo c ks 88 1121 1122 1123 1124 1125 192 1080 a c tive verti c al lines ~ ~ ~ ~ ~ ~ 41 42 ~ ~ ~
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 44 of 125 www.semtech.com 4.4 dvb-asi mode when operating in dvb-asi mode, all smpte processing features are disabled, and the device accepts 8-bit transport stream data and control signal inputs on the din[19:10] port. this mode is only enabled when smpte_bypass pin is low, dvb_asi pin is high and the rate_sel0 pin is high. the interface consists of eight data bits and two control signals, inssyncin and kin. when inssyncin is set high, the GS2972 inse rts k28.5 sync characters into the data stream. this function is us ed to assist system implem entations where the GS2972 may be preceded by a data fifo. the fifo can be fed data at a rate somewh at less than 27mhz. the ?fifo empty? signal could be used to feed the inssyncin pin, ca using the GS2972 to pad the data up to the transmission rate of 27mhz. when kin is set high the data input is interpreted as a special character (such as a k28.5 sync character), as defined by the dvb-asi standard. when kin is set low the input is interpreted as data. after sync signal in sertion, the GS2972 8b/10b encode s the data, generating a 10-bit data stream for the parallel to serial conversion and transmission process. 4.5 data-through mode the GS2972 may be configured to operate as a si mple parallel-to-serial converter. in this mode, the device passes data to the serial output without performing any scrambling or encoding. data-through mode is enabled on ly when both the smpte_bypass and dvb_asi pins are set low. 4.6 standby mode the standby pin reduces power to a minimum by disabling all circuits except for the register configuration. upon removal of th e signal to the standby pin, the device returns to its previous operating condition within 1 second, without requiring input from the host interface. in addition, the serial digital output signals becomes high-impedance when the device is powered-down.
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 45 of 125 www.semtech.com 4.7 audio embedding the GS2972 includes an audio mu ltiplexer, which by defaul t will be active when the transmitter is configured for smpte mode. audio embedding is controlled by: ?grp1_en/dis and grp2_en/dis pins are set high to enable embedding of their respective groups ?the audio_ins bit in the io proc register is set low to enable audio embedding ?the ioproc_en/dis pin is set high to enable audio embedding in non-smpte modes, the audio multiplexer will be powered down to reduce power. note: when audio is embedded by the GS2972, if either of the grp1_en/dis or grp2_en/dis pins are toggled, the output video stream is lost. for example: with a 3gb/s sdi level a input signal as the source, and either aes or i 2 s mode audio embedded; if one of the audio groups is disabled, there is no a longer valid video signal present at the output. toggling the audio disable pins on the fly must be avoided. the user has to set the pins before resetting the chip, and not change the setting during normal operation. the audio may be enabled or disabled during the oper ation of the chip by writing to the host interface registers. sd audio group embeddin g may be enabled, or disabled, by writing to act1...act8 bits of register 40fh. hd/3g audio group embedding may be enabled, or disabled, by writing to act1...a ct8 bits of register 80eh. 4.7.1 serial audio data inputs the GS2972 supports the inse rtion of up to 8 channels of embedded audio, in two groups of 4 channels. each audio group has a dedicated audio group enable input pin; a word clock (wclk) input pin operating at 48khz; an audio cloc k input pin (aclk) operating at 3.072mhz (64 x wclk); and two serial digital audio input pins (ain_1/2, etc.), supporting one stereo audio signal pair per pin. the serial audio data inputs for each audio group are listed in table 4-5 . table 4-5: serial audio input pin des c ription pin name des c ription audio group 1 g rp1_en/di s ena b le input for au d io g roup 1 ain_1/2 s erial au d io input; c hannels 1 an d 2 ain_3/4 s erial au d io input; c hannels 3 an d 4 a c lk1 6 4 x w c lk asso c iate d with ain_1/2 an d ain_3/4 ( c hannels 1, 2, 3an d 4) w c lk1 48khz wor d c lo c k asso c iate d with ain_1/2 an d ain_3/4 ( c hannels 1, 2, 3 an d 4)
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 46 of 125 www.semtech.com the serial audio input signals and wclk input signals will enter the device on the rising edge of aclk as shown in figure 4-20 . fi g ure 4-20: a c lk to data an d c ontrol s i g nal input timin g when grp1_en/dis and grp2_en/dis are set high, the respective audio group is enabled, and the audio input signals associated with that group are processed and embedded into the video data stream. when grp1_en/dis and grp2_en/dis are set low, the respective audio group is disabled and the audio input signals associated with that group are ignored. in addition, all functional logic associated with audio inse rtion for the disabled audio group is placed in a static operating mode, such that sy stem power is reduced while the device configuration is retained. audio group 2 g rp2_en/di s ena b le input for au d io g roup 2 ain_5/ 6s erial au d io input; c hannels 5 an d 6 ain_7/8 s erial au d io input; c hannels 7 an d 8 a c lk2 6 4 x w c lk asso c iate d with ain_5/ 6 an d ain_7/8 ( c hannels 5, 6 , 7 an d 8) w c lk2 48khz wor d c lo c k asso c iate d with ain_5/ 6 an d ain_7/8 ( c hannels 5, 6 , 7 an d 8) table 4-6: GS2972 serial audio data inputs - ac ele c tri c al chara c teristi c s parameter symbol conditions min ty p max units input d ata set-up time t s u 50% levels ; +3.3v or +1.8v operation 1.3 ?? ns input d ata hol d time t ih 0.8 ?? ns table 4-5: serial audio input pin des c ription (continued) pin name des c ription aclk data data ain_1/2, ain_3/4, ain_5/6, ain_7/8 wclk t ih t su
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 47 of 125 www.semtech.com 4.7.2 serial audio data format support the GS2972 supports the following serial audio data formats: ?i 2 s audio (default) ?aes/ebu ? serial audio, left justified, msb first ? serial audio, left justified, lsb first ? serial audio, right justified, msb first ? serial audio, right justified, lsb first by default (at power up or after system reset), the i 2 s data format is enabled. the audio format can be di fferent for both audio grou ps. normally, ain_1/2 and ain_3/4 are embedded in audio group a, and ain_5/6 and ain_7/ 8 are embedded in audio group b. as well, the audio formats can be different within the same group. under normal conditions: ama sets the audio format for ain_1/2 amb sets the audio format for ain_3/4 amc sets the audio format for ain_5/6 amd sets the audio format for ain_7/8 note: these four formats can all be set to different modes if desired. table 4-7 shows the audio input formats for the gs 2972. note that the same values apply for amb + lsb_firstb, amc + lsb_ firstc and amd + lsb_firstd. fi g ure 4-21: i 2 s au d io input format table 4-7: audio input formats ama[1:0] (address 40bh for sd, address 80ah for hd/3g) lsb_firsta (address 40fh for sd, address 80eh for hd/3g) audio input formats 00 x ae s /ebu au d io input 01 0 s erial au d io input: left j ustifie d ; m s b first 01 1 s erial au d io input: left j ustifie d ; l s b first 10 0 s erial au d io input: ri g ht j ustifie d ; m s b first 10 1 s erial au d io input: ri g ht j ustifie d ; l s b first 11 x 1 2 s ( d efault) w c lk a c lk a in[8/7:2/1] m s b 0 3 21 2 3 4 5 6 22 l s b m s b 0 3 2 1 2 3 4 5 6 22 l s b c hannel a (left) c hannel b (ri g ht)
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 48 of 125 www.semtech.com fi g ure 4-22: ae s /ebu au d io input format fi g ure 4-23: s erial au d io, left j ustifie d , m s b first fi g ure 4-24: s erial au d io, left j ustifie d , l s b first fi g ure 4-25: s erial au d io, ri g ht j ustifie d , m s b first fi g ure 4-2 6 : s erial au d io, ri g ht j ustifie d , l s b first w c lk a c lk a in[8/7:2/1] 123 4 l s b m s b 0 c hannel a (left) c hannel b (ri g ht) 5 6 78 27 29 28 30 31 123 4 0 5 6 7 8 27 29 28 30 31 aux pream b le p c vu l s bm s b aux pream b le p c vu w c lk a c lk ain[8/7:2/1] 23 m s b 0 2 21 2 3 4 5 6 21 l s b 23 m s b 0 2 21 2 3 4 5 6 21 l s b c hannel a (left) c hannel b (ri g ht) w c lk a c lk ain[8/7:2/1] 0 l s b 3 2 122 21 20 19 18 17 2 m s b 0 l s b 3 2 122 21 20 19 18 17 2 m s b c hannel a (left) c hannel b (ri g ht) w c lk a c lk ain[8/7:2/1] 23 m s b 0 2 21 2 20 17 18 19 21 l s b 23 m s b 0 2 21 2 20 17 18 19 21 l s b c hannel a (left) c hannel b (ri g ht) w c lk a c lk ain[8/7:2/1] 0 l s b 3 2 122 21 3 6 5 4 2 m s b 0 l s b 3 2 122 21 3 6 5 4 2 m s b c hannel a (left) c hannel b (ri g ht)
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 49 of 125 www.semtech.com 4.7.3 3g mode when the GS2972 is operating in 3g mode, 8 channels of audio in 4 pairs can be embedded in the serial output signal, according to smpte st 299. the 8 channels are in 2 groups, which are sele ctable via the host interface from the four groups allowed by smpte st 299. the default is group one and group two. smpte st 425 describes different mappings for the video si gnal, each with its own locations for audio data and control packets: 4.7.3.1 level a signals: smpte st 425 level a describes a single vide o signal carried in a 3g bit stream. the bit stream is made of two multiplexed virtual streams, data stream one and data stream two. data stream one carries audio control packets in the same way that the y channel carries audio control packet s in smpte st 292 hd signals, but at twice the rate. data stream two carries audio data packets in the same way that the c channel carries audio data packets in smpte st 292 hd signals, but at twice the rate. for level a signals with mappings 2 (1080i/p, 720p 4:4:4 10-bit), 3 (1080i/p 4:4:4 12-bit) or 4 (1080i/p, 720p 4:2:2 12-bit), the audio data packets are em bedded at the full rate of 148.5mhz, but the clock phase bits are calculated assuming th e original pclk signal of 74.25mhz. this factor of two must be taken into consideration when calculating the clock bits. smpte st 425 requires smpte st 352 payload pa ckets to be embedd ed in both data stream one and da ta stream two. 4.7.3.2 level b signals: smpte st 425 level b describe s the carriage of two smpte st 292 signals in a single 3g bit stream. it also applies to a smpte st 372 dual link signal. the two signals are designated link a and link b. each can carry audio data in the same way that a smpte st 292 bit stream carries audio data. the GS2972 is capable of embedding audio data onto either link a or link b of the level b signal. the default will be link a. link a and link b are presen ted to the GS2972 as 10-bit sign als at a 148.5mhz pclk rate. 4.7.4 hd mode when the GS2972 is operating in hd mode, 8 channels of au dio in 4 pairs are embedded in the serial output signal , according to smpte st 299. the 8 channels will be in 2 groups, which are selectable via the host interface from the 4 groups allowed by smpte st 299. the de fault group is group one and group two.
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 50 of 125 www.semtech.com 4.7.5 sd mode when the GS2972 is operating in sd mode, eight channels of audio in four pairs are embedded in the serial outp ut signal, according to smpt e st 272. the eight channels will be in two groups, which are selectable via the host interface from the four groups allowed by smpte st 272. the defaul t group is group one and group two. 4.7.6 audio embedding operating modes audio embedding operates in one of three di stinct modes: 1. normal mode (default) all previously embedded audio packets are deleted from the video stream. arbitrary packets, sdti packets and smpte st 352 packets are not deleted. up to two audio groups can be added to the video output. sdti packets and smpte st 352 packets are placed before the audio packets. arbitrary packets are placed after the audio packets. 2. cas c ade mode no previously embedded packets are deleted from the video stream. up to two audio groups can be added to the video output. the added audio groups will not repl ace existing embedded audio groups. the added audio packets are appended to the last packet in the video input. 3. group repla c ement mode all packets associated with the groups being replaced are deleted. up to two audio groups can be added to the video output. the added audio groups replace any embedded audio groups with the same group number. this will not affect any of the other audio groups, and they will remain in the data stream. the embedded audio groups are sorted in ascending order by audio group number. sdti packets and smpte st 352 packets are placed before the audio packets. arbitrary packets are placed after the audio packets. the operating mode is selected using a combination of the en_cascade and the agr bits in the host interface, as stated in table 4-8 below. table 4-8: GS2972 audio operating mode sele c tion control signals operating mode en_ c a sc ade=0, a g r=0 normal mo d e en_ c a sc ade=1, a g r=0 c as c a d e mo d e en_ c a sc ade=0, a g r=1 g roup repla c ement mo d e en_ c a sc ade=1, a g r=1 g roup repla c ement mo d e
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 51 of 125 www.semtech.com 4.7.7 audio packet detection the input video stream to the GS2972 may already contain embedded audio packets. the GS2972 detects these embedded packets, and signals their presence to the host interface. register 404h is used for sd, register 803h is used for hd/3g. 4.7.8 audio packet deletion in normal mode (default), the GS2972 deletes all au dio packets from the input video data stream. in cas c ade mode , the GS2972 does not delete any au dio packets from the input video data stream. in group repla c ement mode , the GS2972 does not delete any audio packets from the input video data stream. in all operating modes, the GS2972 deletes all audi o packets from the input video stream if any embedded audi o packets do not fully comply with the sm pte st 291 standard. 4.7.9 audio packet detection and deletion in sd modes, the first ancillary data flag (adf) must always be contiguous after the eav words. for hd mode, the first adf must always be contiguous after the two line crc words. ancillary data packets with non-audio data id words, such as arbitrary, edh (sd only), sdti header and smpte st 352, are not deleted from the da ta stream. on lines where smpte st 352 or sdti header pa ckets exist, the audio data packets must be contiguous from the st 352 and sdti packets. if this is not the case, all existing audio data and control packets will be deleted. when cascade is set high, all pre-existing audio data and control packets remain in the video stream. when the agr bit in the host interface is set high, audio group replacement mode is selected. in this mode, existing audio data and control packets are not deleted from the data stream. in cases where the adf is not placed immediately after the crc or eav words, or there are gaps between the packets, the audio core deletes all existing audio data and control packets, regardless of the cascade or agr setting. figure 4-27 shows an example of correct and incorrect placement of ancillary data packets for sd mode.
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 52 of 125 www.semtech.com fi g ure 4-27: an c illary data pa c ket pla c ement example for s d mo d e 4.7.10 audio mute (default off) the GS2972 mutes all of the input channels wh en the mute_all host interface bit is set high. the GS2972 mutes any individual audio inputs as commanded by the following host interface fields: mute1 - mute input channel 1 mute2 - mute input channel 2 mute3 - mute input channel 3 mute4 - mute input channel 4 mute5 - mute input channel 5 mute6 - mute input channel 6 mute7 - mute input channel 7 mute8 - mute input channel 8 blank blank blank eav hanc with space between eav and ancillary data (audio packets will be deleted) sav audio group 1 audio group 2 correct placement of ancillary data within hanc space blank eav sav audio group 1 audio group 2 st 352 / sdti packet st 352 / sdti packet
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 53 of 125 www.semtech.com 4.7.11 audio channel status the GS2972 adds audio channel status to those audio input channels that do not use the aes/ebu format. the audio channel status block complies with the aes3-1992 (ansi s4.40-1992) standard. the GS2972 uses the acsr[183:0] host interface field as th e source of audio channel status for those input channels that do not use the aes/ebu format. the GS2972 replaces the audio channel stat us block in all ei ght channels as commanded by the acs_regen host interface bit. the status block information is supplied by the acsr[183: 0] host interface field. the acs_regen bit (sd core register 403h, hd/3g core register 802h) is set in two states: acs_regen = 0 -> incoming audio channel status is passed through the device to the output. for i 2 s audio formats, the transmitter will embed default audio channel status to the output stream. acs_regen = 1 -> channel stat us is based on user-defined data stored in the acsr. with acs_regen = 1, the GS2972 will serializ e user-defined inform ation to the output data. the user-defined data is applied to the output when the following steps are followed, and the time that the new status boundary occurs for the audio channel. audio channel status replacement follows the same procedure when replacing audio channel status for either aes or i 2 s audio formats. to replace audio channel status, the following procedure should be used: 1. write the desired acs data to the acsr [183:0] (sd core registers 420h-42ch, hd/3g core registers 820h-82ch). 2. set acs_regen bit = 1. 3. the audio channel status on the serial ized output will now contain the user defined acs data. to replace audio channel status on the fly, the following procedure should be used: 1. write the desired acs data to the acsr [183:0] (sd core registers 420h-42ch, hd/3g core registers 820h-82ch) 2. set acs_regen bit = 1, if acs_regen is already set, re-write acs_regen = 1 again. 3. the audio channel status on the serialized output will now contain the user-defined acs data. the GS2972 automatically calculates the crc required for the au dio channel status block.
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 54 of 125 www.semtech.com 4.7.12 audio crosspoint the GS2972 is capable of mapping any inpu t channel to any pr imary or secondary group channel. each group channel specifies the audio source using a 3-bit select or defined below in table 4-9 : each primary and secondary group channe l specifies the audio source using the following host interface fields: audio channels can be paired only when both channels are derived from the same word clock and are synchronous. the same audio channel cannot be used in both primary and secondary groups at the same time. the GS2972 asserts the xpoint_error host interface bit if any audio channel is programmed to be included in both the primary and secondary groups. table 4-9: GS2972 sd audio crosspoint channel sele c tion audio sour c e sd sele c tor hd/3g sele c tor input c hannel 1 000 000 input c hannel 2 001 001 input c hannel 3 010 010 input c hannel 4 011 011 input c hannel 5 100 100 input c hannel 6 101 101 input c hannel 7 110 110 input c hannel 8 111 111 table 4-10: audio sour c e host interfa c e fields host interfa c e field des c ription default g pa_ c h1_ s r c [2:0] primary g roup c hannel 1 s our c e s ele c tor 000 g pa_ c h2_ s r c [2:0] primary g roup c hannel 2 s our c e s ele c tor 001 g pa_ c h3_ s r c [2:0] primary g roup c hannel 3 s our c e s ele c tor 010 g pa_ c h4_ s r c [2:0] primary g roup c hannel 4 s our c e s ele c tor 011 g pb_ c h1_ s r c [2:0] s e c on d ary g roup c hannel 1 s our c e s ele c tor 100 g pb_ c h2_ s r c [2:0] s e c on d ary g roup c hannel 2 s our c e s ele c tor 101 g pb_ c h3_ s r c [2:0] s e c on d ary g roup c hannel 3 s our c e s ele c tor 110 g pb_ c h4_ s r c [2:0] s e c on d ary g roup c hannel 4 s our c e s ele c tor 111
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 55 of 125 www.semtech.com 4.7.13 audio word clock when the GS2972 combines two stereo pair in puts into one audio group, the format allows for only one word clock, or sampling clock. for the primary group, the GS2972 uses the word clock associated with the source selected by the gpa_wclk_src[2:0] host inte rface field. if in sd mode, address 40ch. if in hd/3g mode, address 80bh. for the secondary group, the GS2972 uses th e word clock associat ed with the source selected by the gpb_wclk_src[2:0] host inte rface field. if in sd mode, address 40dh. if in hd/3g mode, address 80ch. for proper operation, the combined stereo pair inputs must have identical word clocks. wclk is not required for aes/ebu audio. 4.7.14 channel & group activation the GS2972 embeds primary group packets when any of the following host interface bits are set and the associated audio group enable pin is high: act1 embed primary group audio channel 1 act2 embed primary group audio channel 2 act3 embed primary group audio channel 3 act4 embed primary group audio channel 4 if none of the bits are set, then no audio will be embedded. the GS2972 will embed secondar y group packets when any of the following host interface bits are set and the associated audio group enable pin is high: act5 embed secondary group audio channel 1 act6 embed secondary group audio channel 2 act7 embed secondary group audio channel 3 act8 embed secondary group audio channel 4 when an embedded packet contains one or more channels with the actx bit set to zero, the GS2972 replaces the data for those channels with null samples (a ll bits set to zero). in the default state, the GS2972 embeds all audio channels in ac cordance with the setting of the respective audio group enable pins of the device.
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 56 of 125 www.semtech.com 4.7.15 audio fifo - sd each input channel has a first in first out (fifo) buffer that can hold up to 52 samples. samples are added (written) to the fifo as they are received from the audio inputs. samples are removed (read) from the fifo as they are embedded in audio data packets and audio extended packets. after power up, reset or clear, the fifo is in the start-up state where it will output zeroes until it has accumulated the start-up count of 26 samples. when the start-up state ends, the buffer operates as a normal fifo, and expects to receive an equal number of read and write operations over the period of five frames. at the end of five frames, the fifo still has 26 samples in the buffer. when the fifo does not receive an equal number of read and write operations, the fifo checks for the overflow and underflow conditions. when a sample is required for embedding into a packet and the fifo is holding less than 6 samples, the GS2972 prevents the underflow condition by repeatin g the last sample without removing a sample from the fifo. therefore, a sample will be duplicated. when an input sample is received and the fi fo has room for less than six more samples, the GS2972 prevents the overfl ow condition by discarding the sample. therefore, a sample will be dropped. if 28 consecutive samples are duplicated or dropped, the audio fifo is cleared and placed into the start-up state. if the clear_audio host interface bit is set, the audio fifo is cleared and put into the start-up state. when the detected video standard changes, the audio fifo is cleared and put into the start-up state. the buffer size and start-up count can be re duced using the os_sel host interface field, as seen in table 4-11 below: table 4-11: GS2972 sd audio buffer size sele c tion address os_sel[1:0] buffer size start-up count 00 52 samples ( d efault) 2 6 samples 01 24 samples 12 samples 10 12 samples 6 samples 11 reserve d reserve d
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 57 of 125 www.semtech.com 4.7.16 audio fifo - hd and 3g for hd and 3g formats, the audio fifo block is a maximum of seven samples deep. according to smpt e st 299, audio samples are multip lexed immediately in the next hanc region after the audio sample occurs. a buffer size of seven samples takes into account that there are no samples after the switching line (for one line) and the worst-case vide o standard of 720p/24, plus a one-sample safety margin. due to the sample distribution used in hd video standards and the size of the buffer in hd mode, no checking is made for buffer un derflow/overflow conditions. the pointers should maintain a variable offset between 0 and 6. 4.7.17 five-frame sequence detection - sd the GS2972 detects the frame sequence that describes the sample distribution for synchronous audio. the frame sequence is used in the generation of audio control packets; where the audio frame number (afn) field describes the position of the current frame within the frame sequence. the frame sequence is also used in the ge neration of audio sample distribution for formats with 525 lines. each frame has 1602 samples or 1601 sample s, depending upon the frame sequence. the GS2972 sets the afn of the primary grou p control packets to zero, unless the afna_auto host interface bit (400h bit 7) is set to produce auto matic afn generation. the multiplexer sets the afn of the secondar y group control packets to zero unless the afnb_auto host interfac e bit (800h bit 10) is set to pr oduce automatic afn generation. when the frame rate is 25hz, every frame has 1920 samples and the afn is always set to one. when the frame rate is 29.97hz, an even nu mber of samples (8008) are distributed over five frames in the following sequence: 1602 1601 1602 1601 1602 the GS2972 sets the afn field to a number between one and five, depending on where the current frame lies within the sequence. the GS2972 adds the offset specified in the af n_ofs host interface field (400h bits 6-4) to the generated afn. the result of the addition wraps around such that the afn will always be in the range of one to five.
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 58 of 125 www.semtech.com 4.7.17.1 525-line audio sample distribution as per the smpte st 272 standard, the foll owing sample distri bution allows the embedding of 16 channels (4 audio groups) of 24-bit sampled audio into the hanc of 525-line based video formats. the sample distribution is established for group one and then offset by one line for each subsequent group. the sample distributi on is as follows (start line is 12): {[3] (10+g) ,([4],[3] 15 ) 15 ,[4],[3] (11-g) ,[0],[3] (3+g) ,([4],[3] 15 ) 15 ,[4/3],[3] 12 ,[4],[3] (4-g) ,[0]} 5 [#] = number of samples / line [4/3] = one line with either 3 or 4 samples depending on five-frame sequence (#) = number of times to repeat the sequence. when this # is 0, no samples are inserted g = audio group number from 1 to 4 {?} 5 = 5-frame sequence as shown in table 4-12 : the following tables show the audio sample distribution for each of the four audio groups. each distributi on has 525 lines. each distribution has 1602 samples or 1601 samp les, based on the frame number in the five-frame sequence. when 1602 samples are required in a frame, the [4/3] term re presents a line with four samples. when 1601 samples are required in a frame, the [4/3] term re presents a line with three samples. table 4-12: GS2972 sd audio five frame sequen c e sample count frame number of samples 11 6 02 21 6 01 31 6 02 41 6 01 51 6 02 table 4-13: GS2972 sd audio group 1 audio sample distribution - 525 line [3] (6) ,[4],[3] (3) [0],[3] (11) ([4],[3] 15 ) 15 [4],[3] (10) [0],[3] (4) ([4],[3] 15 ) 15 [4/3],[3] (6) s amples 31 33 735 34 12 735 22/21 lines 10 12 240 11 5 240 7
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 59 of 125 www.semtech.com 4.7.17.2 625-line audio sample distribution the GS2972 uses the following sa mple distribution to maximi ze the available space in the ancillary data region. note: the following formula starts from line 1: [3] 6 ,[0],[3](g-1),([4],[3]11)25,[4 ],[3](12-g),[0],[3](g-1),([4],[3]11)24,[4],[3](17-g) ? [#] represents one line with # samples ? (#) represents the number of times to repeat the line sequence ? [3](0) represents no lines and no samples ? g is the audio group number from one to four the following tables show the audio sample distribution for each of the four audio groups: each distributi on has 625 lines. each distribution has 1920 samples. table 4-14: GS2972 sd audio group 2 audio sample distribution - 525 line [3] (7) ,[4],[3] (2) [0],[3] (12) ([4],[3] 15 ) 15 [4],[3] (9) [0],[3] (5) ([4],[3] 15 ) 15 [4/3],[3] (5) s amples 31 3 6 735 31 15 735 19/18 lines 10 13 240 10 6 240 6 table 4-15: GS2972 sd audio group 3 audio sample distribution - 525 line [3] (8) ,[4],[3] (1) [0],[3] (13) ([4],[3] 15 ) 15 [4],[3] (8) [0],[3] (6) ([4],[3] 15 ) 15 [4/3],[3] (4) s amples 31 39 735 28 21 735 1 6 /15 lines 10 14 240 9 7 240 5 table 4-16: GS2972 sd audio group 4 audio sample distribution - 525 line [3] (9) ,[4],[3] (0) [0],[3] (14) ([4],[3] 15 ) 15 [4],[3] (7) [0],[3] (7) ([4],[3] 15 ) 15 [4/3],[3] (3) s amples 31 42 735 25 21 735 13/12 lines 10 15 240 8 8 240 4 table 4-17: GS2972 sd audio group 1 audio sample distribution - 625 line [3] 6 [0],[3] (0) ([4],[3] 11 ) 25 [4],[3] (11) [0],[3] (0) ([4],[3] 11 ) 24 [4],[3] (16) s amples 18 0 925 37 0 888 52 lines 6 1 300 12 1 288 17
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 60 of 125 www.semtech.com 4.7.18 frame sequence detection - hd/3g the GS2972 detects the frame sequence that describes the sample distribution for synchronous audio. the frame sequence is only used in the generation of audio control packets; where the audio frame number (afn) field describes the position of the current frame within the frame sequence. the GS2972 sets the afn of the primary group control packets to ze ro when the asxa host interface bit is set for asynchronous audio. the GS2972 sets the afn of the primary group control packets to zero, unless the afna _auto host interface bit is set to produce automatic afn generation. the GS2972 sets the afn of the secondary gr oup control packets to zero, when the asxb host interface bi t is set for asynchronous audio. the GS2972 sets the afn of the secondary group control packets to zero, unless the afnb_auto host interface bit is set to produce automatic afn generation. the GS2972 sets the afn to on e when every frame has the same number of samples: frame rate 23.976hz - each frame has exactly 2002 samples frame rate 24.000hz - each frame has exactly 2000 samples frame rate 25.000hz - each frame has exactly 1920 samples frame rate 30.000hz - each frame has exactly 1600 samples frame rate 50.000hz - each frame has exactly 960 samples frame rate 60.000hz - each frame has exactly 800 samples table 4-18: GS2972 sd audio group 2 audio sample distribution - 625 line [3] 6 [0],[3] (1) ([4],[3] 11 ) 25 [4],[3] (10) [0],[3] (1) ([4],[3] 11 ) 24 [4],[3] (15) s amples 18 3 925 34 3 888 49 lines 6 2 300 11 2 288 1 6 table 4-19: GS2972 sd audio group 3 audio sample distribution - 625 line [3] 6 [0],[3] (2) ([4],[3] 11 ) 25 [4],[3] (9) [0],[3] (2) ([4],[3] 11 ) 24 [4],[3] (14) s amples 18 6 925 31 6 888 4 6 lines 6 3 300 10 3 288 15 table 4-20: GS2972 sd audio group 4 audio sample distribution - 625 line [3] 6 [0],[3] (3) ([4],[3] 11 ) 25 [4],[3] (8) [0],[3] (3) ([4],[3] 11 ) 24 [4],[3] (13) s amples 18 9 925 28 9 888 43 lines 6 4 300 9 4 288 14
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 61 of 125 www.semtech.com when the frame rate is 29.97hz, an even nu mber of samples (8008) are distributed over five frames in the following sequence: 1602 1601 1602 1601 1602 when the frame rate is 59.94hz, an even nu mber of samples (4004) are distributed over five frames in the following sequence: 801 800 801 801 801 the GS2972 sets the afn field to a number between one and five, depending on where the current frame lies within the sequence. the GS2972 adds the offset specified in th e afn_ofs host interface field to the generated afn. the result of the addition wraps around such that the afn will always be in the range of one to five. 4.7.19 ecc error detection and correction the GS2972 generates the error detection and corr ection fields in the audio data packets. the error detection an d correction complies with smpte st 299. 4.7.20 audio control packet insertion - sd the GS2972 embeds audio contro l packets associated with the primary gr oup audio and the secondary group audio. the primary group audio to be embedded is specified using the ida[1:0] host interface field (address 400h). the secondary group audio to be embedded is specified using the idb[1:0] host interface field. the primary group audio control packets is embedded as commanded by the ctra_on host interface bit. (default is on) the secondary group audio control packets is embedded as commanded by the ctrb_on host interface bit. (default is on) the primary group audio control packets is replaced as commanded by the ctr_agr host interface bit. (default is off) the secondary group audio control packets is replaced as commanded by the ctr_agr and one_agr host interface bits. (default is off) the contents of the primary group audio control packet is specified using the following host interface fields: afna_auto primary group audio frame number generation. ebit1a primary group delay valid flag for channel 1. del1a[25:0] primary grou p delay for channel 1. ebit2a primary group delay valid flag for channel 2. del2a[25:0] primary grou p delay for channel 2. ebit3a primary group delay valid flag for channel 3. del3a[25:0] primary grou p delay for channel 3. ebit4a primary group delay valid flag for channel 4. del4a[25:0] primary grou p delay for channel 4.
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 62 of 125 www.semtech.com the contents of the secondary group audio control packet is specified using the following host interface fields: afnb_auto secondary group audi o frame number generation. ebit1b secondary group delay valid flag for channel 1. del1b[25:0] seco ndary group delay for channel 1. ebit2b secondary group delay valid flag for channel 2. del2b[25:0] seco ndary group delay for channel 2. ebit3b secondary group delay valid flag for channel 3. del3b[25:0] seco ndary group delay for channel 3. ebit4b secondary group delay valid flag for channel 4. del4b[25:0] seco ndary group delay for channel 4. 4.7.21 audio control packe t insertion - hd and 3g the GS2972 embeds audio contro l packets associated with the primary gr oup audio and the secondary group audio. the primary group audio to be embedded is specified using the ida[1:0] host interface field. (default is 00 in normal mode). the secondary group audio to be embedded is specified using the idb[1:0] host interface field. (default is 01 in normal mode). the primary group audio control packet s are embedded as commanded by the ctra_on host interface bit. (default is 1). the secondary group audio control packet s are embedded as commanded by the ctrb_on host interface bit. (default is 1). the primary group audio control packets are replaced as commanded by the ctr_agr host interface bit. (default is 0). the secondary group audio control packets are replaced as commanded by the ctr_agr and one_agr host interface bits. (default is 0). the primary group audio control packets are not embedded or replaced unless one or more of the act1, act2, act3 or act4 host interface bits are set. the secondary group audio control packets are not embedded or replaced unless one or more of the act5, act6, act7 or act8 host interface bits are set. the contents of the primary group audio control packet is specified using the following host interface fields: afna_auto - primary group audio frame number auto-generation. asxa - primary group asynchronous mode. del1_2a[25:0] - primary group au dio delay for channels 1 and 2. del3_4a[25:0] - primary group au dio delay for channels 3 and 4. the contents of the secondary group audio control packet is specified using the following host interface fields: afnb_auto - secondary group audio frame number auto-generation. asxb - secondary group asynchronous mode. del1_2b[25:0] - secondary group audio delay for channels 1 and 2. del3_4b[25:0] - secondary group audio delay for channels 3 and 4.
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 63 of 125 www.semtech.com 4.7.22 audio data packet insertion in normal mode, the GS2972 embeds audio data packets into a space where all pre-existing embedded audio data packets have been removed. in cascade mode, the GS2972 embeds audio data packets contiguously after all of the pre-existing audio da ta packets. the GS2972 does not replace any pre-existing audio data packets with new audio packets, even if the new audio packets have the same group number. in this situation, the new audio data packets are appended to the last packet, and there is an illegal mix of different groups using the same group number. this condition will be indicated by the following host interface bits: ? mux_erra: set in cascade mode when primary group audio data packets are added to video that already contains audio data packets with the same group number ? mux_errb: set in cascade mode when secondary group audio data packets are added to video that alre ady contains audio data packets with the same group number in group replacement mode the GS2972 embeds audio data packets and sorts all of the embedded audio data packets in order of gr oup number. if there are any pre-existing audio data packets with the same group number as the new audio packets, then the pre-existing packets will be replaced. in group replacement mode the GS2972 replac es only the primary group audio if the one_agr host interface bit is set. the GS2972 deletes arbitrary data packets if there is not enou gh room in the horizontal ancillary data space to embed the selected audio data packets. the GS2972 does not embed audio data packets when there is insufficient room in the horizontal ancillary data space afte r deleting arbitrary data packets. 4.7.22.1 audio data packet insertion - sd only the GS2972 embeds the audio channels specifie d by the act[8:1] host interface fields. the GS2972 detects and preser ves embedded edh packets. the GS2972 generates ex tended packets for 24-bit audi o when the audio_24bit host interface bit is set. 4.7.22.2 blanking values following audio data packet insertion for 3g level a, level b dual-str eam, and level b dual-link y?c? b c? r 4:2:2 10-bit formats, the audio insertion block will in sert blanking data in accord ance with the original video format. for all other video formats (for exampl e: rgb 4:4:4 10-bit or 12-bit, y?c? b c? r 12-bit), the audio block will insert blanking values of 200h and 040h, which may not match the blanking data of the original format.
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 64 of 125 www.semtech.com 4.7.23 audio interrupt control the GS2972 will assert the inte rrupt signal when an inte rnal interrup t condition becomes true and the type of interrupt is enabled. the following host interface bits enable the various interrupt sources: i by default, the interrupts are all disabled. table 4-21: audio interrupt control C host interfa c e bit des c ription bit name des c ription bit address (sd) bit address (hd&3g) en_no_video asserts interrupt when vi d eo format is unknown 40eh-14 80dh-14 en_a c p g 1_det asserts interrupt when a c p g 1_det fla g is set 40eh-4 80dh-4 en_a c p g 2_det asserts interrupt when a c p g 2_det fla g is set 40eh-5 80dh-5 en_a c p g 3_det asserts interrupt when a c p g 3_det fla g is set 40eh- 6 80dh- 6 en_a c p g 4_det asserts interrupt when a c p g 4_det fla g is set 40eh-7 80dh-7 en_adp g 1_det asserts interrupt when adp g 1_det fla g is set 40eh-0 80dh-0 en_adp g 2_det asserts interrupt when adp g 2_det fla g is set 40eh-1 80dh-1 en_adp g 3_det asserts interrupt when adp g 3_det fla g is set 40eh-2 80dh-2 en_adp g 4_det asserts interrupt when adp g 4_det fla g is set 40eh-3 80dh-3 en_ae s _erra asserts interrupt when ae s _erra fla g is set 40eh-8 80dh-8 en_ae s _errb asserts interrupt when ae s _errb fla g is set 40eh-9 80dh-9 en_ae s _err c asserts interrupt when ae s _err c fla g is set 40eh-10 80dh-10 en_ae s _errd asserts interrupt when ae s _errd fla g is set 40eh-11 80dh-11 en_mux_erra asserts interrupt when mux_erra fla g is set 40eh-12 80dh-12 en_mux_errb asserts interrupt when mux_errb fla g is set 40eh-13 80dh-13
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 65 of 125 www.semtech.com 4.8 anc data insertion horizontal or vertical ancillary data words may be inserted on up to four different lines per video frame. up to 512 data words may be in serted per frame wi th all data words - including the anc packet adf, dbn, dcnt, did, sdid and csum words - being provided by the user via host interface configuration. the csum word is re-calculated and inserted by the anc data checks um calculation and insertion function. note that any value may be used for the cs um word, provided that it is outside the protected ranges from 000h to 00 3h and from 3fch to 3ffh. if a csum value in either of these ranges is used, it will not be corrected by the device. the GS2972 does not provide error checking or correction to the an c data provided by user via the host interface. it is the responsibility of the user to ensure that all data provided for insertion is fully standard compliant. in 3g level a mode, ancillary data packets ar e inserted into data stream one or data stream two as selected by the host interface. the default insertion will be in data stream one. see address 02dh, stream_type1_line_x. in 3g level b mode, ancillary data packets are inserted into the y or c video stream of link a or link b as selected by the user in the host interface. the default insertion will be in the y video stream of link a. for link a or link b, see register 02dh. for y or c, see registers 026h, 028h, 02ah and 02ch. in hd mode, anc data packets are inserted into the y or c video stream, as selected via the host interface. the default insertion will be in the y stream. for y or c, see registers 026h, 028h, 02ah and 02ch. in sd mode, the anc data packets are inserted into the multiplexed cbycr data stream. anc data insertion only takes place if the ioproc_en/dis pin is high and smpte_bypass is high. in addition to this, the GS2972 requires th e anc_ins bit to be set low in the ioproc register. the anc_packet_bank register (040h - 13fh) is used to program the anc data words for anc data insertion. 4.8.1 anc insertion operating modes user selection of one of the two operating modes is provided through host interface configuration, using the anc_ins_mode register bit (see table 4-34: video core configuration and status registers ). the supported operating modes are concatenated mode and separate line operating mode. by default (at power up or after system reset), the separate line operating mode is enabled. ancillary data packets are programmed into the anc_packet_bank host register at addresses 040h to 13fh.
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 66 of 125 www.semtech.com 4.8.1.1 separate line operating mode in separate line mode, it is po ssible to insert horizontal or vertical ancillary data on up to four lines per video frame. in separate line mode, the anc_packet_bank bits are separated in four sections. each section consists of 64 x 16-bit registers. anc_packet_bank_1 uses registers 040h to 07fh. anc_packet_bank_2 uses registers 080h to 0bfh. anc_packet_ban k_3 uses registers 0c0h to 0ffh. anc_packet_bank_4 uses regi sters 100h to 13fh. hanc or vanc can be specified, independently of each other, on a per-li ne basis. 025h firs t_line_number, 027h second_line_number, 029h th ird_line_number and 02bh fourth_line_number. for each of the four video lines, up to 128 x 8-bit hanc or vanc data words can be inserted. separate line mode is selected by setting the anc_ins_mode bit in the host interface low. by default, at power up, separate line mode is selected. the lines on which ancillary data is to be inserted is programmed in the host register addresses 025h to 02ch. for hd formats, the stream into which the an cillary data is to be inserted (luma or chroma) is also programmed in these register addresses. the non-zero video line numbers on which to insert the ancillary data, the ancillary data type (hanc or vanc), and the total number of words to insert per line must be provided via the host interface (see section 4.14 ). at power up, or after system reset, all ancillary data insertion line numbers and total number of words default to zero. if the total number of data words specified per li ne exceeds 128 only the first 128 data words will be inserted, th e rest will be ignored. the data words are programmed as two 8-bi t values per address, starting at host interface address 040h in the anc_packet_bank register (see table 4-34 ). the device automatically converts the provided 8-bit data words into the 10-bit data, formatted according to smpte st 291 prior to insertion. 4.8.1.2 concatenated operating mode in concatenated mode, it is po ssible to insert up to 512 8-bit horizontal or vertical ancillary data words on one line per video frame. concatenated line mode can be selected by setting the anc_ins_mode bit in the host interface high. by default, at power up, separate line mode is selected. in concatenated mode, only the first_line registers of the host interface need to be programmed (addresses 025h and 026h). see table 4-34 . the non-zero video line number on which to insert the ancillary data, the ancillary data type (hanc or vanc), and the total number of words to insert must be provided via the host interface. at power up, or after system reset, the ancillary data insertion line number and total number of words default to zero. if the total number of data words specifie d exceeds 512 only th e first 512 data words will be inserted, the rest will be ignored. the data words are programmed as two 8-bi t values per address, starting at host interface address 040h in the anc_packet_bank register. see table 4-34 . the device automatically converts the provided 8-bit data words into the 10-bit data formatted according to smpte st 291 prior to insertion.
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 67 of 125 www.semtech.com 4.8.2 3g anc insertion 4.8.2.1 level a mode when operating in 3g (rate _sel0 = low, rate_sel1 = high) level a mode, the GS2972 inserts vanc or hanc da ta packets into data stre am one (default) or data stream two. the data stream for insertion is selectable fo r each of the anc insert ion lines selected via the host interface. data stream one is selected when the stream_type_1 bit in the register associated with the insertion line is set low (default). data stream two is selected when the stream_type_1 bit associat ed with the insertion line is set high. anc data should be placed in ds1 first in level a mode, and only in ds2 as an overflow if ds1 is full. data insertion starts at the first available location in the hanc space following any audio and pre-existing arbitrary data packets. all data words identified by the user are inse rted in a contiguous fashion starting at the first available data space. hanc data insertion terminates when all data words identified by the user have been inserted; or by the start of the four word trs sav code, regardless of the number of data words actually inserted. the rest of the packet will be ignored. vertical ancillary data (vanc), is inserted into the data stream on the video line(s) defined by the user. data insertion starts at the first active pixel immediately following the last word of the trs sav code. all data words identified by the user are insert ed in a contiguous fashion, starting at the first active pixel. vanc data insertion terminates when all data words identified by the user have been inserted; or by the start of the four word trs eav code, regardless of the number of data words actually inserted. the total number of data words to be inserted and the line number on which the anc data insertion takes place is provided by the user via the host interface as part of the configuration of the anc data insertion function. the user data for insertion is provided vi a the host interface register stream_type_1 (02dh).
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 68 of 125 www.semtech.com 4.8.2.2 level b mode when operating in 3g (rate_sel0 = low, rate_sel1 = high) level b mode, the GS2972 inserts vanc or hanc data packets into either the y or c data stream of data stream one (default) or data stream two, as selected by the stream_type_1 bit in the host interface on a per line basis. by default (at power up or after system reset), all anc data insertion takes place in the y data stream of data stream one. the user can select between the y or c data stream for insertion on a per line basis in separate line mode. the y data stream is selected when the stream_type_0 bit is low (default). the c data stream is select ed when the stream_type_0 bit is high. the user can select between the y or c data stream for insertion on a single line basis in concatenated mode. the y data stream is selected when the stream_type_0 bit is low (default). the c data stream is selected when the stream_type_0 bit is high. horizontal ancillary data (hanc), is inserted into the y or c data stream on the video line(s) defined by the user. data insertion starts at the first available location in the hanc space following any audio and pre-existing arbitrary data packets. all data words identified by the user are inserted in a contiguous fashion, starting at the first available data space. hanc data insertion terminates when all data words identified by the user have been inserted; or by the start of the four word trs sav code, regardless of the number of data words actually inserted. vertical ancillary data (vanc), is inserted into the y or c data stream on the video line(s) defined by the user. data insertion starts at the first active pixel immediately following the last word of the trs sav code. all data words identified by the user are inserted in a contiguous fashion starting at the first active pixel. vanc data insertion terminates when all data words identified by the user have been inserted; or by the start of the four word trs eav code, regardless of the number of data words actually inserted. the total number of data words to be inserted and line number on which anc data insertion takes place is provided by the user via the host interface as part of the configuration of the anc data insertion function. the user data for insertion is provided via the host interface. stream_type_1 = address 02dh, stream_type_0 for the four lines of in sertion is at addresses 026h (bit 14), 028h (bit 14), 02ah (bit 14) and 02ch (bit 14).
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 69 of 125 www.semtech.com 4.8.3 hd anc insertion when operating in hd mode (rate_sel0 = low, rate_sel1 = low), the GS2972 inserts vanc or hanc data packets into either the y data stream or c data stream. by default (at power up or after system reset), all anc data insertion takes place in the y data stream. the user can select between y or c data stream for insertion on a per line basis in separate line mode. the y data stream is selected when the stream_type_0 bit is low (default). the c data stream is select ed when the stream_type_0 bit is high. the user can select between y or c data stream for insertion on a single line basis in concatenated mode. the y data stream is selected when the stream_type_0 bit is low (default). the c data stream is selected when the stream_type_0 bit is high. horizontal ancillary data (hanc), is inserted into the y or c data stream on the video line(s) defined by the user. data insertion starts at the first available location in the hanc space, following any audio and pre-existing arbitrary data packets. all data words identified by the user are inserted in a contiguous fashion starting at the first available data space. hanc data insertion terminates when all data words identified by the user have been inserted; or by the start of the four word tr s sav code, regardless of the number of data words actually inserted. vertical ancillary data (vanc), is inserted into the y or c data stream on the video line(s) defined by the user. data insertion starts at the first active pixel immediately following the last word of the trs sav code. all data words identified by the user are inserted in a contiguous fashion, starting at the first active pixel. vanc data insertion terminates when all data words identified by the user have been inserted; or by the start of the four word trs eav code, regardless of the number of data words actually inserted. the total number of data words to be insert ed and the line number on which anc data insertion takes place is provided by the user via the host interface as part of the configuration of the anc data insertion function. the user data for insertion is provided via host interface configuration. stream_type_1 = address 02dh, stream_type_0 for the four lines of insertion is at addresses 026h (bit 14), 028h (bit 14), 02ah (bit 14) and 02ch (bit 14).
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 70 of 125 www.semtech.com 4.8.4 sd anc insertion when operating in sd mode (rate_sel0 = high), the GS2972 inserts vanc or hanc data packets into the multiplexed cbycr data stream. horizontal ancillary data (hanc), is inserted on the video line(s) defined by the user. data insertion starts at the first available location in the hanc space following any audio and pre-existing arbitrary data packets. all data words identified by the user are inserted in a contiguous fashion, starting at the first available data space. hanc data insertion terminates when all data words identified by the user have been inserted; or by the start of the four word tr s sav code, regardless of the number of data words actually inserted. for the case where hanc data insertion is required on the same line as the edh packet, data insertion is terminated by the start of the edh packet, regardless of the number of data words actually inserted. vertical ancillary data (vanc), is inserted into the data stream on the video line(s) defined by the user. data insertion starts at the first active cb pixel immediately following the last word of the trs sav code. all data words identified by the user are inserted in a contiguous fashion, starting at the first active pixel. vanc data insertion terminates when all data words identified by the user have been inserted; or by the start of the four word trs eav code, regardless of the number of data words actually inserted. the total number of data words to be inserted and the line number on which anc data insertion takes place is provided by the user via the host interface as part of the configuration of the anc data insertion function. the user data for insertion is provided via host interface configuration. stream_type_1 = address 02dh, stream_type_0 for the four lines of insertion is at addresses 026h (bit 14), 028h (bit 14), 02ah (bit 14) and 02ch (bit 14).
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 71 of 125 www.semtech.com 4.9 additional processing functions the GS2972 contains a number of signal proc essing features. thes e features are only enabled in smpte mode of operation (smpte_bypass = high), and when i/o processing is enabled (ioproc_en/dis = high). signal processing features include: ? trs generation and insertion ? line number calculation and insertion ? line based crc calculation and insertion ? illegal code re-mapping ? smpte st 352 payload identi fier packet insertion ? anc checksum calculation and correction ? edh generation and insertion ?audio embedding ? smpte st 372 conversion to enable these fe atures in the gs2 972, the smpte_bypass pin must be high, the ioproc_en/dis pin must be high and the individual feature must be enabled via bits set in the ioproc register of the host interface. by default, all of the processing features are enabled, except for smpte st 372 conversion. 4.9.1 video format detection by using the timing parameters extracted from the received trs signals, or the supplied external timing signals, the gs 2972 calculates the video format. the total samples per line, active samples per line, total lines per field/frame, and active lines per field/frame are measured and reported to the user via the four raster_struc_x registers in the host interface. these line and sample count registers are updated once per frame at the end of line 12. the raster_struc_x registers also contain two status bits: std_lock and int/prog . the std_lock bit is set high whenever the automatic video format detection circuit has achieved full synchronization. the int/prog bit is set low if the detected video standard is progressive, and is set high if the detected vide o standard is interlaced. the gennum video standard code (vd_st d), as used in the GS2972, gs1582 and gs1572, is included in table 4-22 for reference purposes.
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 72 of 125 www.semtech.com table 4-22: supported video standards smpte standard active video area length of hanc length of active video total samples smpte st 352 lines gennum vd_std [4:0] rate_ sel1 s t 428.1 2048x1080/24 (1:1) 6 90 2048 2750 10 1 c h1 s t 428.1 2048x1080/25 (1:1) 580 2048 2 6 40 10 1 c h1 s t 425 (3 g ) 4:2:2 1920x1080/ 6 0 (1:1) 2 6 8 1920 2200 10 (18) 1 0bh 1 1920x1080/50 (1:1) 708 1920 2 6 40 10 (18) 1 0dh 1 s t 425 (3 g ) 4:4:4 1920x1080/ 6 0 (2:1) or 1920x1080/30 (psf) 2 6 8 2 1920 2 2200 10, 572 0ah 1 1920x1080/50 (2:1) or 1920x1080/25 (psf) 708 2 1920 2 2 6 40 10, 572 0 c h1 1280x720/ 6 0 (1:1) 358 2 1280 2 1 6 50 10 (13) 1 00h 1 1280x720/50 (1:1) 6 88 2 1280 2 1980 10 (13) 1 04h 1 1920x1080/30 (1:1) 2 6 8 2 1920 2 2200 10 (18) 1 0bh 1 1920x1080/25 (1:1) 708 2 1920 2 2 6 40 10 (18) 1 0dh 1 1280x720/25 (1:1) 2 66 8 2 1280 2 39 6 0 10 (13) 1 0 6 h1 1920x1080/24 (1:1) 818 2 1920 2 2750 10 (18) 1 10h 1 1280x720/24 (1:1) 2833 2 1280 2 4125 10 (13) 1 08h 1 s t 2 6 0 (hd) 1920x1035/ 6 0 (2:1) 2 6 8 1920 2200 10, 572 15h 0 s t 295 (hd) 1920x1080/50 (2:1) 444 1920 237 6 10, 572 14h 0 s t 274 (hd) 1920x1080/ 6 0 (2:1) or 1920x1080/30 (psf) 2 6 8 1920 2200 10, 572 0ah 0 1920x1080/50 (2:1) or 1920x1080/25 (psf) 708 1920 2 6 40 10, 572 0 c h0 1920x1080/30 (1:1) 2 6 8 1920 2200 10 (18) 1 0bh 0 1920x1080/25 (1:1) 708 1920 2 6 40 10 (18) 1 0dh 0 1920x1080/24 (1:1) 818 1920 2750 10 (18) 1 10h 0 1920x1080/24 (psf) 818 1920 2750 10, 572 11h 0 1920x1080/25 (1:1) ? em 324 2304 2 6 40 10 (18) 1 0eh 0 1920x1080/25 (psf) ? em 324 2304 2 6 40 10, 572 0fh 0 1920x1080/24 (1:1) ? em 338 2400 2750 10 (18) 1 12h 0 1920x1080/24 (psf) ? em 338 2400 2750 10, 572 13h 0
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 73 of 125 www.semtech.com by default (at power up or after system reset), the four raster_struc_x, std_lock and int/prog registers are set to zero. these re gisters are also cleared when the smpte_bypass pin is low, or the locked pin is low. note 1: the line numbers in brackets refe r to version zero smpte st 352 packet locations, if they are different from the version one locations. note 2: 3g formats cannot be fully determined from these measurements. their detailed information will be derived from smpte st 352 packets, which must be in the video stream as a mandator y requirement of the smpte st 424 specification, as described below. s t 29 6 (hd) 1280x720/30 (1:1) 2008 1280 3300 10 (13) 1 02h 0 1280x720/30 (1:1) ? em 408 2880 3300 10 (13) 1 03h 0 1280x720/50 (1:1) 6 88 1280 1980 10 (13) 1 04h 0 1280x720/50 (1:1) ? em 240 1728 1980 10 (13) 1 05h 0 1280x720/25 (1:1) 2 66 8 1280 39 6 0 10 (13) 1 0 6 h0 1280x720/25 (1:1) ? em 492 345 6 39 6 0 10 (13) 1 07h 0 1280x720/24 (1:1) 2833 1280 4125 10 (13) 1 08h 0 1280x720/24 (1:1) ? em 513 3 6 00 4125 10 (13) 1 09h 0 1280x720/ 6 0 (1:1) 358 1280 1 6 50 10 (13) 1 00h 0 1280x720/ 6 0 (1:1) ? em 198 1440 1 6 50 10 (13) 1 01h 0 s t 125 ( s d) 1440x487/ 6 0 (2:1) (or d ual link pro g ressive) 2 6 8 1440 171 6 13, 27 6 1 6 hx 1440x507/ 6 0 (2:1) 2 6 8 1440 171 6 13, 27 6 17h x 525-line 487 g eneri c ?? 171 6 13, 27 6 19h x 525-line 507 g eneri c ?? 171 6 13, 27 6 1bh x itu-r bt. 6 5 6 ( s d) 1440x57 6 /50 (2:1) (or d ual link pro g ressive) 280 1440 1728 9, 322 18h x 6 25-line g eneri c (em) ?? 1728 9, 322 1ah x unknown hd rate_ s el0 = 0 ?? ?? 1dh unknown s d rate_ s el0 = 1 ?? ?? 1eh x unknown 3 g rate_ s el0 = 0 ?? ?? 1fh 1 notes: 1. the line numbers in brackets refer to version zero smpte st 352 packet locations, if they are different from version 1. 2. the part may provide full or limited functionality with standa rds that are not included in this table. please consult a semte ch technical representative. table 4-22: supported video standards (continued) smpte standard active video area length of hanc length of active video total samples smpte st 352 lines gennum vd_std [4:0] rate_ sel1
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 74 of 125 www.semtech.com 4.9.2 3g format detection format detection is more difficu lt for 3g signals, as there are two levels of signal (level a and level b) and multiple mappings within each level. timing information is not sufficient to fully deco de the video format. for this reason smpte st 352 video payload identifi er packets are mandatory for all smpte st 424 serial signals. note: the only exception is when the smpte st 425 mapping is level b twin smpte st 292 streams, and one or both of the smpte st 292 streams carries hd-sdti data. in this case the hd-sdti header packets are used for payload identification. 4.9.2.1 level a and level b signals: the GS2972 uses smpte st 352 packets to determine the video format. the smpte st 352 packets used for form at detection will either be: ? when the 352_ins (address 000h bit 6) bit is low, then if either bit 6 or 7 of address 20ah are high, the format is 3g level b. if both are low, then it will look at the information programmed at address 00ah video_format_out_ds1_x. see smpte st 425 standard for details. ? when the bit is high, the format is 3g level a. extraction of smpte st 352 packets cannot be done in 3g level b. the GS2972 uses the programmed smpte st 352 packets if the 352_ins register bit in the ioproc register is high. if there are no smpte st 352 packets embedded in the input signal, and the user does not embed smpte st 352 packets from the ho st interface, the GS2972 assumes an input signal of 1080p/50 or 1080p/59.94. th e GS2972 uses information from the raster_struc_x registers to select between these two frame rates. for level b inputs, the GS2972 does not extract the smpte st 352 packets from the parallel input. the only source of smpte st 352 packets in level b mode, to be used for format detection and for embedding in the output data streams, is from the user programmed registers in the host interface. note: if proper smpte video is applied and th en removed from the input, the device does not flag that the h_lock, v_lock, vd_sdt etc. has changed (been lost). this is the case for either trs detect or hvf modes. this problem occurs only when the video data is removed, but not the pclk. usually, when a video signal is removed, it includes the clock, the video data, as well as the h, v, f as a whole. so the scenario is not likely to occur.
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 75 of 125 www.semtech.com 4.9.3 anc data blanking the GS2972 can blank the video input data duri ng the h and v blanking periods. this function will be enabled by setting the anc_blank pin low. this function is only available when the device is operating in smpte mode (smpte_bypass = high). in this mode, input video data in the horizontal and vertical blanking periods will be replaced by smpte comp liant blanking values. the blanking function will operate only on the video input signal and will remove all ancillary data already embedded in the input video stream. in sd mode, sav and eav code words already embedded in the input video stream will be protected and will not be blanked. in hd and 3g modes, sav and eav code wo rds, line numbers and line based crc's already embedded in the input video stream will be protected and will not be blanked. the above two statements are really impleme ntation specific, and are provided only to ensure that the ?detect trs? function for timing generation is supported by the device, even when the blanking function is enabled. from a system perspective, use of the input blanking function is not recommended unless trs, line number and crc generation and insertion functions are enabled. the active image area will not be blanked. the input blanking function will not blank any of the ancillary data, trs words, line numbers, crc's, edh, smpte st 352 payloa d identifiers or audi o control and data packets inserted by the device itself. 4.9.4 anc data checksum calculation and insertion the GS2972 calculates ch ecksums for all detect ed ancillary data pa ckets and audio data presented to the device. anc data checksum insertion only takes place if the ioproc_en/dis pin is high, the smpte_bypass is high and the anc_csum_ins bit is set low in the ioproc register. note: the device will correct any csum value outside the protected ranges from 000h to 003h and from 3fch to 3ffh. if a csum valu e in either of these ranges is presented to the device, it will not be corrected. 4.9.5 trs generation and insertion the GS2972 is capable of genera ting and inserting trs codes. trs word generation and insertion are performed in accordance with the timing parameters generated by the timing circuits, which is locked to the externally provided h:v:f or cea-861 signals, or the trs signal s embedded in the input data stream. the GS2972 will overwrite the trs signals if they 're already embedded. when a 3g level a signal is applied to the gs2 972, and when the conv_372 (bit 9 address 000h) is set low (level a to level b conversion), trs will be inserted according to 3g level b format. 10-bit trs code words are inserted at all times.
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 76 of 125 www.semtech.com the insertion of trs id words only take place if the ioproc_en/dis pin is high and the smpte_bypass pin is high. in addition to this, the GS2972 requires th e trs_ins bit to be set low in the ioproc register. if the tim_861 pin is high, then the timing circuits are locked to cea-861 timing. 4.9.6 hd and 3g line number calculation and insertion the GS2972 is capable of line number generation and insertion, in accordance with the relevant hd video standard, as determined by the automatic video standard detector. line numbers are inserted into both the y and c channels. note: line number generation and insertion only occurs in hd and 3g modes (rate_sel0 = low). the insertion of line numbers only take place if the ioproc_en/dis pin is high and smpte_bypass pin is high. in addition to this, the GS2972 requires the lnum_ins bit to be set low in the ioproc register. 4.9.7 illegal code re-mapping the GS2972 detects and co rrects illegal code words within the ac tive picture area. all codes within the active picture (outside th e horizontal and vertical blanking periods), between the values of 3fch and 3ffh are re-mapped to 3fbh. all codes within the active picture area between the values of 000h and 003h are remapped to 004h. 8-bit trs code words are re-mapped to 10-bit values. the illegal code re-mapping will only take place if the ioproc_en/dis pin is high and smpte_bypass is high. in addition to this , the GS2972 requires the illegal_ word_remap bit to be set low in the ioproc register. note: due to the architecture of the GS2972 seri alizer, illegal code words appearing in the middle of a line that look like trs sequ ences will be treated as such by the device. for example, any sequ ence in the middle of a line that produces 3ffh 000h 000h followed by another 10-bit word will be treated as a trs, even if that following word does not match the xyzh code words allowed by smpte. to avoid this issue, any groupings of words th at look like trs sequ ence must be kept out of the active picture portion of the video line or it will not be remapped.
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 77 of 125 www.semtech.com 4.9.8 smpte st 352 payload id entifier packet insertion when enabled by the smpte_352m_ins bit in the ioproc register, new smpte st 352 payload identifier packets are inserted into the data stream. these packets are supplied by the user via the host interface. sett ing the smpte_352m_ins bit low enables this insertion. the device will automatically calculate the checksum and generate version one compliant st 352 ancilla ry data preambles: did, sdid, dbn, dc. the smpte st 352 packet is inserted into the data stream ac cording to the line number and sample po sition rules defined in the 2002 standard. for hdtv video systems the smpte st 352 packet is plac ed in the y channel only. by default (at power up or after system reset), the four video_format_in_ds1 registers and the four video_format_o ut_ds1 registers are set to zero. 4.9.8.1 3g smpte st 352 payload identifier packet insertion when enabled by the smpte_352m_ins bit in the ioproc register (000h), new smpte st 352 payload identifier packets are inserted into the data streams. setting this bit low enables insertion. insertion of smpte st 352 pack ets into each data stream is controlled by the status format describing bit, sdti_tdm_ds1 an d sdti_tdm_ds2 for data stream one and data stream two. if sdti_tdm_ds1 (default low) is set high by the user, the GS2972 does not insert smpte st 352 pa ckets into data stream on e. similarly, smpte st 352 packets are inserted in data stream two only if sdti_tdm_ds2 is set low. this allows the user to individually disable smpte st 352 packets where the data stream is carrying an hd-sdti or tdm signal, which must no t have smpte st 352 packets embedded. note: the user must ensure that there is sufficient space in the horizontal blanking interval for the insertion of the smpte st 352 packets. if the first_avail_position bit in the host interface registers is set high (by default), the smpte st 352 packets are inserted in the first available position following any existing ancillary data. if the first_avail_position csr bit is set low, then the packets are inserted immediately after the eav/crc1. if the first available position is high and there is insufficient space, st 352 packets will no t be inserted. if there are pre-existing st 352 packets, they will be over written, indepe ndent of the setting of the first_avail_position csr bit.
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 78 of 125 www.semtech.com 4.9.9 line based crc genera tion and insertion (hd/3g) when operating in hd mode (rate_sel0 pin = low, rate_sel1 pin = low), the GS2972 generates an d inserts line based cr c words into both the y and c channels of the data stream. when operating in 3g (rate_sel0 pin = low, rate_sel1 pin = high) level a mode, the GS2972 generates and inserts line based crc words in to both data stream one and data stream two. when operating in 3g (rate_sel0 pin = low, rate_sel1 pin = high) level b mode, the GS2972 generates and inserts line based crc words in to both y and c channels of both link a and link b. the line based crc insertion only takes place if the ioproc_en/dis pin is high and smpte_bypass is high. in addition to this, the gs 2972 requires the edh_crc_ins bit to be set low in the ioproc register. 4.9.10 edh generati on and insertion when operating in sd mode , the GS2972 generates and inse rts edh packets into the data stream. the edh packet generation and insertion only takes place if the ioproc_en/dis pin is high, smpte_bypass pin is high, the rate_sel0 pin is high and the edh_crc_ins bit is set low in the ioproc register. calculation of both full field (ff) and active picture (ap) crcs is carried out by the device. edh error flags edh, eda, idh, ida and ues for ancillary data, full field and active picture are also inserted. ? when the edh_crc_update bit of the host interface is set low, these flags are sourced from the anc_edh_flag, ff_edh_flag and ap_edh_flag registers of the device, where they are programmed by the application layer ? when the edh_crc_update bit of the host interface is set high, incoming edh flags are preserved and inserted in the outgoing edh packets. in this mode the anc_edh_flag, ff_edh_flag and ap_edh_flag registers contain the incoming edh flags, and will be read only the GS2972 generates all of the required edh packet data including all ancillary data preambles: did, dbn, dc, rese rved code words and checksum. the prepared edh packet is inserted at the appropriate line of the video stream (in accordance with rp165). the start pixel position of the in serted packet is based on the sav position of that line, such that the last byte of the edh packet (the checksum) is placed in the sample immediately preceding the start of the sav trs word. note 1: when the edh_crc_update bit of the ho st interface is set low, it is the responsibility of the application interface to ensure that the edh flag registers are updated regularly (once per field). note 2: it is also the responsibility of the application interface to ensure that there is sufficient space in the horizontal blanking interval for the edh packet to be inserted.
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 79 of 125 www.semtech.com 4.9.11 GS2972 3g/hd hanc space considerations when embedding audio standards having mo re than 1024 hanc words in th e blanking can potentially re-transmit pre-embedded packets twice in cascade or agr modes. here is the list of standards at risk: (1920x1080/24/1:1, 444) = 1648 words in hanc (2048x1080/25/1:1, 444) = 1172 words in hanc (2048x1080/24/1:1, 444) = 1392 words in hanc (1280x720/24/1:1, 444) = 5678 words in hanc (1280x720/23.98/1:1, 444) = 5678 words in hanc (1280x720/25/1:1, 444) = 5348 words in hanc (1280x720/50/1:1, 444) = 1388 words in hanc (1920x1080/23.98/1:1, 444) = 1648 words in hanc (1920x1080/50/2:1, 444) = 1428 words in hanc (1920x1080/25/1:1, 444) = 1428 words in hanc (1920x1080/25/psf, 444) = 1428 words in hanc (1280x720/30/1:1, 422) = 2008 words in hanc (1280x720/29.97/1:1, 422) = 2008 words in hanc (1280x720/25/1:1, 422) = 2668 words in hanc (1280x720/24/1:1, 422) = 2833 words in hanc (1280x720/23.98/1:1, 422) = 2833 words in hanc note: for all of the standards listed above, semtech recommends using the GS2972 as the source of any ancillary data packets. if packets already exist in the video coming in to the GS2972, semtech recommends deleting al l anc packets if this problem is to be avoided. 4.9.12 smpte st 372 conversion when the ioproc_en/dis pin is high and the conv_372 bi t in the ioproc register is low, the GS2972 converts smpte st 425 leve l a mapping 1 (1080p 4:2:2) to level b smpte st 372 dual link pr ior to serialization.
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 80 of 125 www.semtech.com 4.9.13 processing feature disable the GS2972 contains an ioproc register. th is register contain s one bit for each processing feature, allowing the user to enable/disable each process individually. by default (at power up or after system reset), all of the ioproc register bits are low, except for the smpte st 372 conversion. to disable an individual processing feature, the application interface must set the corresponding bit high in the ioproc re gister. to enable these features, the ioproc_en/dis pin must be high, and the indivi dual feature must be enabled by setting bits low in the ioproc register of the host interface. the i/o processing functions supp orted by the GS2972 are shown in table 4-25 below. table 4-23: ioproc register bits i/o pro c essing feature ioproc register bit tr s insertion tr s _in s (000h bit 0) y an d c line num b er insertion lnum_in s (000h bit 1) y an d c line b ase d c r c insertion c r c _in s (000h bit 2) an c illary d ata c he c ksum c orre c tion an c _ cs um_in s (000h bit 3) edh c r c error c al c ulation an d insertion edh_ c r c _in s (000h bit 4) ille g al wor d re-mappin g ille g al_word_remap (000h bit 5) s mpte s t 352 pa c ket insertion s mpte_352m_in s (000h bit 6 ) s mpte s t 372 c onversion c onv_372 (000h bit 9) au d io em b e dd in g audio_embed (000h bit 10)
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 81 of 125 www.semtech.com 4.10 smpte st 352 data extraction if there are no smpte st 352 packets embedded in the input signal, the GS2972 will raise an error flag in the ?no_352_err? bit. if there are st 352 packets present in the stream, the GS2972 reports th e extracted smpte st 352 packets in the video_format_352_ in registers in th e host interface. the user can use this information, along with the raster_struc_x registers, to determine the video format. if there is a conflict between the numbers in the raster_struc_x registers and the format defined in the smpte st 352 packets, the GS2972 will raise a timing_err flag via the host interface. note: smpte st 352 packets will no t be present in an hd-s dti input stream, and will not be embedded in an output hd-sdti serial stream. this is controlled by the user as described in section 4.9.8.1 . by default (at power up or after system re set), the video_format_352_in registers are set to zero (undefined video format). these registers are also cleared when the smpte_bypass pin is set low, or the locked pi n is low. the smpte st 352 packet should be received once per field for in terlaced systems and once per frame for progressive video systems. if the packet is not received for two complete video frames, the video_format_352_in registers are cleared to zero. table 4-24: smpte st 352 pa c ket data register name bit bit name des c ription r/w default video_format_352_in_word_2 15-8 video_format_in_ d s 1_4 (byte 4) data will b e availa b le in this re g ister when vi d eo payloa d i d entifi c ation pa c kets are d ete c te d in the d ata stream. r0 7-0 video_format_in_ d s 1_3 (byte 3) data will b e availa b le in this re g ister when vi d eo payloa d i d entifi c ation pa c kets are d ete c te d in the d ata stream. r0 video_format_352_in_word_1 15-8 video_format_in_ d s 1_2 (byte 2) data will b e availa b le in this re g ister when vi d eo payloa d i d entifi c ation pa c kets are d ete c te d in the d ata stream. r0 7-0 video_format_in_ d s 1_1 (byte 1) data will b e availa b le in this re g ister when vi d eo payloa d i d entifi c ation pa c kets are d ete c te d in the d ata stream. r0 video_format_352_in_word_4 15-8 video_format_in_ d s 2_4 (byte 4) data will b e availa b le in this re g ister when vi d eo payloa d i d entifi c ation pa c kets are d ete c te d in the d ata stream. r0 7-0 video_format_in_ d s 2_3 (byte 3) data will b e availa b le in this re g ister when vi d eo payloa d i d entifi c ation pa c kets are d ete c te d in the d ata stream. r0 video_format_352_in_word_3 15-8 video_format_in_ d s 2_2 (byte 2) data will b e availa b le in this re g ister when vi d eo payloa d i d entifi c ation pa c kets are d ete c te d in the d ata stream. r0 7-0 video_format_in_ d s 2_1 (byte 1) data will b e availa b le in this re g ister when vi d eo payloa d i d entifi c ation pa c kets are d ete c te d in the d ata stream. r0
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 82 of 125 www.semtech.com 4.11 serial clock pll an internal vco provides the transmission clock rates for the GS2972. the power supply to the vco is provided to the vco_vdd/vco_gnd pins of the device. this vco is locked to the input pclk via an on-chip pll and charge pump. internal division ratios for the pclk are dete rmined by the setting of the rate_sel0 pin, the rate_sel1 pin and the 20bit/10bit pin as shown in table 4-25 : as well as generating the serial digital output clock signals, the pll is also responsible for generating all internal clock signals required by the device. 4.11.1 pll bandwidth table 4-26 shows the GS2972 pll loop bandwidt h variations. pll bandwidth is a function of the external loop filter resistor and the charge pump current. we recommend using a 200 loop filter resistor, however, this value can be varied from 100 to 380 , depending on application. values other than 200 are not guaranteed. as the resistor is changed, the bandwidth will scale proportionately (for example, a change from a 200 to 300 resistor will cause a 50% in crease in bandwidth). the charge pump current is preset to 100 a and should not be changed. the external loop filter capacitor does not affect the pll loop bandwidth. the external loop filter capacitor affects pll loop settling time, phase marg in and noise. it is selectable from 1 f to 33 f. however, it should be kept at 10 f for optimal performance. a smaller capacitor results in shorter lock time but less stability. a larg er capacitor results in longer lock time but more stability. narrower loop bandwidths require a larger capacitor to be stable. in other words, a small loop filter resistor requires a larger loop capacitor. table 4-25: pclk and serial digital clo c k rates external pin setting supplied pclk rate serial digital output rate rate_sel0 rate_sel1 20bit/10bit low hi g hhi g h 148.5 or 148.5/1.001mhz 2.97 or 2.97/1.001 gb /s low hi g hlow 148.5 or 148.5/1.001mhz (ddr) 2.97 or 2.97/1.001 gb /s low low hi g h 74.25 or 74.25/1.001mhz 1.485 or 1.485/1.001 gb /s low low low 148.5 or 148.5/1.001mhz 1.485 or 1.485/1.001 gb /s hi g hxhi g h 13.5mhz 270m b /s hi g h low low 27mhz 270m b /s
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 83 of 125 www.semtech.com 4.11.2 lock detect the lock detect block controls the serial digital output signal and indicates to the application layer the lock status of the device. the locked output pin is provided to indicate the device operating status. the locked output signal is set high by the lock detect block under the following conditions (see table 4-27 ): any other combination of signal states not included in the above table results in the locked pin being low. note: when the locked pin is low, the serial digital output is in the muted state. table 4-26: GS2972 pll bandwidth mode pclk frequen c y (mhz) filter resistor ( ) charge pump current ( a) bandwidth (khz) s d 13.50 200 100 4.78 s d 27.00 200 100 9.57 hd 74.25 200 100 2 6 .32 hd 148.50 200 100 52. 6 3 3 g 148.50 200 100 52. 6 3 table 4-27: GS2972 lo c k dete c t indi c ation reset pll lo c k smpte_bypass dvb_asi rate_sel0 hi g hhi g hhi g hlowx hi g hhi g hlow hi g hhi g h hi g hhi g hlow low x
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 84 of 125 www.semtech.com 4.12 serial digital output the GS2972 has a single, low-impedance curr ent mode differential output driver, capable of driving at least 800mv into a 75 single-ended load. the output signal amplitude, or swing, wi ll be user-confi gurable using an external resistor on the rset pin. the serial digital output data rate supports smpte st 424, smpte st 292, smpte st 259-c and dvb-asi operat ion. this is summarized in table 4-28 : the sdo and sdo pins of the device provide the serial digital output. compliance with all requirements defined in section 4.12.1 through section 4.12.4 is guaranteed when measured across a 75 terminated load at the output of 1m of belden 1694a cable, including the effects of the semtech recommended orl matching network, bnc and coaxial cable connection, except where otherwise stated. figure 4-28 illustrates this requirement, which is in accordance with the measurement methodology defined in smpte st 4 24, smpte st 292 and smpte st 259-c. fi g ure 4-28: orl mat c hin g network, bn c an d c oaxial c a b le c onne c tion table 4-28: serial digital output - serial output data rate parameter symbol conditions min ty p max units s erial output data rate br s do s mpte s t 424 si g nal ? 2.97, 2.97/1.001 ? gb /s s mpte s t 292 si g nal ? 1.485, 1.485/1.001 ? gb /s s mpte s t 259- c si g nal ? 270 ? m b /s dvb-a s i si g nal ? 270 ? m b /s dut GS2972 orl matching network bnc 1m belden 1694a 75 coaxial cable bnc 75 resistive load measuring device
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 85 of 125 www.semtech.com 4.12.1 output sign al interface levels the serial digital output signals (sdo and sdo pins), of the device meet the amplitude requirements as defined in smpte st 424 fo r an unbalanced gene rator (single-ended). the signal amplitude is controlled to better than +/-7% of the nominal level defined in smpte st 424, when an external 750 1% resistor is connected between the rset pin of the device and vcc. the output signal amplitude can be reduced to less than 1/10th of the nominal amplitude, defined above, by increasing the value of the resistor connected between the rset pin of the device and vcc. these requirements are met across all ambient temperature and power supply operating conditions described in section 2. the output amplitude of the GS2972 can be adjusted by changing the value of the r set resistor as shown in table 4-29 . for a 800mv pp output a value of 750 is required. a 1% smt resistor should be used. the r set resistor is part of the high speed ou tput circuit of the GS2972. the resistor should be placed as close as possible to the rset pin. in addition, an anti-pad should be used underneath the resistor. 4.12.2 overshoot/undershoot the serial digital output signal overshoot and undershoot is controlled to be less that 7% of the output signal amplitude, when operating as an unbalanced generator (single-ended). this requirement is met for nominal signal amplitudes as defined by smpte st 292. this requirement is met regardless of the output slew rate setting of the device. this requirement is met across all ambient temperature and power supply operating conditions described in section 2. this requirement is summarized in table 4-30 : table 4-29: r set resistor value vs. output swing r set resistor values ( ) output swing (mv pp ) 995 6 08 824 734 750 800 6 80 884 table 4-30: serial digital output - overshoot/undershoot parameter symbol conditions min ty p max units s erial output overshoot /un d ershoot ??? 07%
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 86 of 125 www.semtech.com 4.12.3 slew rate selection the GS2972 supports two user-sel ectable output slew rates. control of the slew rate is determined by the setting of the rate_sel0 input pin. when this pin is set high, the output slew rate matches the requirements as defined by the smpte st 259-c standard. when this pin is set low, the output slew rate is better than the requirements as defined by the smpte st 424 standard. these requirements is met across all ambient temperature and power supply operating conditions described in section 2. this requirement is summarized in table 4-31 : 4.12.4 serial dig ital output mute when the sdo_en/dis pin is low, the serial digital output signals of the device become high-impedance, reducing system power. the serial digital output is also placed in the high-impedance state when the locked pin is low, or when the standby pin is high. table 4-31: serial digital output - rise/fall time parameter symbol conditions min ty p max units s erial output rise/fall time 20% ~ 80% s do tr s mpte s t 292/ s t 424 si g nal ?? 135 ps s mpte s t 259- c si g nal 400 ? 800 ps
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 87 of 125 www.semtech.com 4.13 gspi host interface note: when using more than one semtech serializer or deserializer (serdes) in the same design, carefully read this section to see how the gspi ports of multiple ics should be connected to each other. unlike some previous devices, the sdout pin of these serdes ics is a non-clocked, loop-through of sd in (allowing for mult iple devices to be connected to the gspi chain). the sdout pins of multiple serdes ics should not be bussed together, as was the case with some older generations of serdes ics. the gspi, or gennum serial peripheral interfac e, is a 4-wire interface provided to allow the application layer to access additional status information through configuration registers in the GS2972. the gspi comprises a serial da ta input signal (sdin), serial data output signal (sdout), an active-low chip select (cs ) and a burst clock (sclk). because these pins can be shared with the jt ag interface port for compatibility with the gs1582, an addition al control signal pin jtag/host is provided. when jtag/host is low, the gspi interface is enabled. when jtag/host is high, the jtag interface is enabled. when operating in gspi mode, the sclk, sdin, and cs signals are provided by the application interface. the sdout pin is a non-clocked loop-through of sdin, and may be connected to the sdin of another device, allowing multiple devi ces to be connected to the gspi chain. the interface is illustrated in figure 4-29 below. fi g ure 4-29: gs pi appli c ation interfa c e c onne c tion all read or write access to the GS2972 is initiated and terminated by the application host processor. each access always begins wi th a command/address word followed by a data read to or written from the GS2972. application host sclk sclk sclk sdout sdin sdout sdout sdin sdin GS2972 GS2972 cs1 cs cs cs2
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 88 of 125 www.semtech.com 4.13.1 command word description the command word consists of a 16-bit word transmitted msb first and contains a read/write bit, an auto-increment bit and a 12-bit address. figure 4-30 shows the command word format and bit configurations. command words are clocked into the GS2972 on the rising edge of the serial clock sclk, which operates in a burst fashion. when the auto-increment bit is set low, each command word must be followed by only one data word to ensure proper operation. if the auto-increment bit is set high, the following data word will be written into the address specified in the command word, and subsequent data wo rds will be written into incremental addresses from the previous data word. this facilitates multiple address writes without sending a command word for each data word. fi g ure 4-30: c omman d wor d format 4.13.2 data read or write access serial data is transmitted or received msb first synchronous with the rising edge of the serial clock, sclk. the chip select (cs ) signal must be active low a minimum of 1.5ns (t0 in figure 4-32 ) before the first clock edge to ensure proper operation. during a read sequence (command word r/w bit set high), a wait state of 148ns (4 x 1/fpclk, t5 in figure 4-32 ) is required between writing the command word and reading the following data word. the read bits are clocked out on the negative edges of sclk. note 1: where several devices are connected to the gspi chain, only one cs _tms may be asserted during a read sequence. during a write sequence (command word r/w bit set low), a wait state of 37ns (1 x 1/fpclk, t4 in figure 4-32 ) is required between the command word and the following data word. this wait state must also be maintained between successive command word/data word write sequences. when auto-increment mode is selected (autoinc = 1), the wait state must be main tained between successi ve data words after the initial command word/data word sequence. during the write sequence, all command and following data words input at the sdin pin are output at the sdout pin as is. when several devices are connected to the gspi chain, data can be written simultaneously to all the devices which have cs set low. note 2: if the application interface performs a read or write access after power-up, prior to the application of a valid serial video input signal, the sclk frequency must not exceed 10mhz. fi g ure 4-31: data wor d format a0 a1 a2 a3 a4 a5 a 6 a7 a8 a9 a11 m s b l s b a10 r/w r s vr s v autoin c d15 d14 d13 d12 d0 d1 d2 d3 d4 d5 d 6 d7 d8 d9 d11 d10 m s b l s b
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 89 of 125 www.semtech.com 4.13.3 gspi timing write and read mode timing for the gspi interface is as shown in the following diagrams: fi g ure 4-32: write mo d e fi g ure 4-33: rea d mo d e fi g ure 4-34: gs pi time delay sc lk_t c k cs _tm s s din_tdi s dout_tdo t 0 t 3 t 1 t 2 r/w t 8 t 4 t 7 r/w auto _in c auto _in c a11 a11 a10 a10 a9 a9 a8 a8 a7 a7 a 6 a 6 a5 a5 a4 a4 a3 a3 a2 a2 a1 a1 a0 a0 d15 d15 d14 d14 d13 d13 d12 d12 d11 d11 d10 d10 d9 d9 d8 d8 d7 d7 d 6 d 6 d5 d5 d4 d4 d3 d3 d2 d2 d1 d1 d0 d0 r s v r s v r s v r s v sc lk_t c k cs _tm s s din_tdi s dout_tdo r/w r/w auto _in c auto _in c a11 a11 a10 a10 a9 a9 a8 a8 a7 a7 a 6 a 6 a5 a5 a4 a4 a3 a3 a2 a2 a1 a1 a0 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d 6 d5 d4 d3 d2 d1 d0 r s v r s v r s v r s v t 6 t 5 sdin_tdi data_0 sdin_tdi to sdout_tdo combinational path for daisy chain connection of multiple GS2972 devices. sdout_tdo data_0 t delay table 4-32: gspi time delay parameter symbol conditions min ty p max units delay time t delay 50% levels; +1.8v operation ?? 10.5 ns delay time t delay 50% levels; +3.3v operation ?? 8.7 ns
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 90 of 125 www.semtech.com table 4-33: gspi ac chara c teristi c s parameter symbol conditions min ty p max units cs low b efore sc lk risin g e dg e t 0 50% levels; +3.3v or +1.8v operation 1.5 ?? ns sc lk perio d t 1 12.5 ?? ns sc lk d uty c y c le t 2 40 50 6 0% input d ata setup time t 3 1.5 ?? ns time b etween en d of c omman d wor d (or d ata in auto-in c rement mo d e) an d the first sc lk of the followin g data wor d ? write c y c le. t 4 p c lk (mhz) ns ?? ns unlo c ke d 445 13.5 74.2 27.0 37.1 74.25 13.5 148.5 6 .7 time b etween en d of c omman d wor d (or d ata in auto-in c rement mo d e) an d the first sc lk of the followin g data wor d ? rea d c y c le. t 5 p c lk (mhz) ns ?? ns unlo c ke d 1187 13.5 297 27.0 148.5 74.25 53.9 148.5 27 output hol d time (15pf loa d ) t 6 1.5 ?? ns cs hi g h after last sc lk risin g e dg e t 7 p c lk (mhz) ns ?? ns unlo c ke d 445 74.2 74.2 37.10 37.1 74.25 13.5 148.5 6 .7 input d ata hol d time t 8 1.5 ?? ns note: if the appli c ation interfa c e performs a rea d or write a cc ess after power-up, prior to the appli c ation of a vali d serial vi d eo input si g nal, the sc lk frequen c y must not ex c ee d 10mhz.
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 91 of 125 www.semtech.com 4.14 host interf ace register maps 4.14.1 video core registers table 4-34: video core configuration and status registers address register name bit name bit des c ription r/w default 000h iopro c r s vd 15 reserve d . r 0 delay_line_enable 14 hi g h - ena b les the d elay line. low - d isa b les the d elay line. r/w 0 audio_levelb_ s tream_2_1b 13 hi g h - em b e d s au d io on the d s 2 of a 3 g level b si g nal. low - em b e d s au d io on the d s 1 of a 3 g level b si g nal. r/w 0 edh_ c r c _update 12 hi g h - preserve in c omin g edh fla g s an d insert into out g oin g edh pa c kets. low - em b e d fla g s from 003 in edh pa c ket. r/w 0 an c _in s 11 hi g h - d isa b le an c illary d ata insertion. low - em b e d s an c pa c ket store d at 040h to 13fh a cc or d in g to parameters at 005h to 02dh. r/w 0 audio_embed 10 hi g h - d isa b le au d io em b e dd in g . low - ena b les au d io em b e dd in g . r/w 0 c onv_372 9 hi g h - d isa b le level a-b c onversion. low - ena b le level a-b c onversion. r/w 1 h_ c onfi g 8 c hooses h c onfi g uration; low - a c tive-line b ase d b lankin g is ena b le d . hi g h - s mpte h timin g . r/w 0 r s vd 7 reserve d . r/w 0 s mpte_352m_in s6 hi g h - d isa b les insertion of s mpte s t 352 pa c kets. low - ena b les insertion of s mpte s t 352 pa c kets r/w 0 ille g al_word_remap 5 hi g h - d isa b les ille g al wor d remappin g . r/w 0 edh_ c r c _in s 4 hi g h - d isa b les edh c r c error c orre c tion an d insertion. r/w 0 an c _ cs um_in s 3 hi g h - d isa b les insertion of an c illary d ata c he c ksums. r/w 0 c r c _in s 2 hi g h - d isa b les insertion of hd/3 g c r c wor d s. r/w 0
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 92 of 125 www.semtech.com 000h iopro c lnum_in s 1 hi g h = d isa b les insertion of hd/3 g line num b ers. r/w 0 tr s _in s 0 hi g h = d isa b les insertion of tr s wor d s. r/w 0 001h error_ s tat r s vd 15-7 reserve d . r 0 tr s _perr 6 tr s prote c tion error. low - no errors in tr s . hi g h - errors in tr s . r0 y1_edh_ cs _err 5 s ame as cs _err b ut only up d ates its state when pa c ket b ein g inspe c te d is an edh pa c ket. r0 y1_ cs _err 4 hi g h in d i c ates that a c he c ksum error is d ete c te d . it is up d ate d every time a cs wor d is present on the output. note: this b it will not b e set for cs um values in the prote c te d ran g es (from 000h to 003h an d from 3f c h to 3ffh). r0 format_err 3 hi g h in d i c ates stan d ar d is not re c o g nize d for 8 6 1d c onversion. r0 timin g _err 2 hi g h in d i c ates that the ra s ter measurements d o not line up with the extra c te d s t 352 pa c ket information. r0 no_352m_err 1 hi g h in d i c ates no s t 352 pa c ket em b e dd e d in in c omin g vi d eo. r0 lo c k_err 0 hi g h in d i c ates pll lo c k error in d i c ation. r0 table 4-34: video core configuration and status registers (continued) address register name bit name bit des c ription r/w default
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 93 of 125 www.semtech.com 002h edh_fla g _ext r s vd 15 reserve d . r 0 an c _ue s _ext 14 an c illary d ata - unknown error status fla g . r0 an c _ida_ext 13 an c illary d ata - internal error d ete c te d alrea d y fla g . r0 an c _idh_ext 12 an c illary d ata - internal error d ete c te d here fla g . r0 an c _eda_ext 11 an c illary d ata - error d ete c te d alrea d y fla g . r0 an c _edh_ext 10 an c illary d ata - error d ete c te d here fla g . r0 ff_ue s _ext 9 edh full fiel d - unknown error status fla g . r0 ff_ida_ext 8 edh full fiel d - internal error d ete c te d alrea d y fla g . r0 ff_idh_ext 7 edh full fiel d - internal error d ete c te d here fla g . r0 ff_eda_ext 6 edh full fiel d - error d ete c te d alrea d y fla g . r0 ff_edh_ext 5 edh full fiel d - error d ete c te d here fla g . r0 ap_ue s _ext 4 edh a c tive pi c ture - unknown error status fla g . r0 ap_ida_ext 3 edh a c tive pi c ture - internal error d ete c te d alrea d y fla g . r0 ap_idh_ext 2 edh a c tive pi c ture - internal error d ete c te d here fla g . r0 ap_eda_ext 1 edh a c tive pi c ture - error d ete c te d alrea d y fla g . r0 ap_edh_ext 0 edh a c tive pi c ture - error d ete c te d here fla g . r0 table 4-34: video core configuration and status registers (continued) address register name bit name bit des c ription r/w default
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 94 of 125 www.semtech.com 003h edh_fla g _p g m r s vd 15 reserve d . r 0 an c _ue s _p g m14 an c illary d ata - unknown error status fla g . r0 an c _ida_p g m13 an c illary d ata - internal error d ete c te d alrea d y fla g . r/w 0 an c _idh_p g m12 an c illary d ata - internal error d ete c te d here fla g . r/w 0 an c _eda_p g m11 an c illary d ata - error d ete c te d alrea d y fla g . r/w 0 an c _edh_p g m10 an c illary d ata - error d ete c te d here fla g . r/w 0 ff_ue s _p g m9 edh full fiel d - unknown error status fla g . r/w 0 ff_ida_p g m8 edh full fiel d - internal error d ete c te d alrea d y fla g . r/w 0 ff_idh_p g m7 edh full fiel d - internal error d ete c te d here fla g . r/w 0 ff_eda_p g m 6 edh full fiel d - error d ete c te d alrea d y fla g . r/w 0 ff_edh_p g m5 edh full fiel d - error d ete c te d here fla g . r/w 0 ap_ue s _p g m4 edh a c tive pi c ture - unknown error status fla g . r/w 0 ap_ida_p g m3 edh a c tive pi c ture - internal error d ete c te d alrea d y fla g . r/w 0 ap_idh_p g m2 edh a c tive pi c ture - internal error d ete c te d here fla g . r/w 0 ap_eda_p g m1 edh a c tive pi c ture - error d ete c te d alrea d y fla g . r/w 0 ap_edh_p g m0 edh a c tive pi c ture - error d ete c te d here fla g . r/w 0 004h data_format r s vd 15-10 reserve d . r 0 vd_ s td 9-5 dete c te d vi d eo stan d ar d .r0 int/pro g b 4 hi g h = interla c e d si g nal low = pro g ressive si g nal r0 c onv_372_lo c ked 3 c onvert 372 lo c k in d i c ation. a c tive hi g h. r0 s td_lo c k2 s tan d ar d lo c k in d i c ation. a c tive hi g h. r0 v_lo c k1 verti c al lo c k in d i c ation. a c tive hi g h. r0 h_lo c k0 horizontal lo c k in d i c ation. a c tive hi g h. r0 table 4-34: video core configuration and status registers (continued) address register name bit name bit des c ription r/w default
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 95 of 125 www.semtech.com 005h r s vd r s vd 15-0 reserve d . r 0 00 6 hv s d_for c e r s vd 15- 6 reserve d . r 0 v s d_for c e5 use the cs r re g ister s td value rather than the flywheels s td value. a c tive hi g h. r/w 0 vid_ s td_for c e4-0for c e vid s td cs r. r/w 0 007h edh_ s tatu s r s vd 15-2 reserve d . r 0 ff_ c r c _v 1 full fiel d extra c te d v b it. r 0 ap_ c r c _v 0 a c tive pi c ture extra c te d v b it. r 0 008h fir s t_avail_ po s ition r s vd 15-1 reserve d . r 0 fir s t_avail_po s ition 0 hi g h - s t 352 insertion o cc urs on first availa b le an c spa c e. low - insert s t 352 pa c kets ri g ht after eav/ c r c 1. r/w 1 009h re s erved re s erved_7 15-0 reserve d . r 0 00ah video_format_3 52_out_word_1 video_format_out_d s 1_2 15-8 s mpte s t 352 d s 1 em b e dd e d pa c ket - b yte 2. r/w 0 video_format_out_d s 1_1 7-0 s mpte s t 352 d s 1 em b e dd e d pa c ket - b yte 1. r/w 0 00bh video_format_3 52_out_word_2 video_format_out_d s 1_4 15-8 s mpte s t 352 d s 1 em b e dd e d pa c ket - b yte 4. r/w 0 video_format_out_d s 1_3 7-0 s mpte s t 352 d s 1 em b e dd e d pa c ket - b yte 3. r/w 0 00 c h video_format_3 52_out_word_3 video_format_out_d s 2_2 15-8 s mpte s t 352 d s 2 em b e dd e d pa c ket - b yte 2. r/w 0 video_format_out_d s 2_1 7-0 s mpte s t 352 d s 2 em b e dd e d pa c ket - b yte 1. r/w 0 00dh video_format_3 52_out_word_4 video_format_out_d s 2_4 15-8 s mpte s t 352 d s 2 em b e dd e d pa c ket - b yte 4. r/w 0 video_format_out_d s 2_3 7-0 s mpte s t 352 d s 2 em b e dd e d pa c ket - b yte 3. r/w 0 00eh video_format_3 52_in_word_1 video_format_in_d s 1_2 15-8 s mpte s t 352 d s 1 extra c te d pa c ket - b yte 2. r0 video_format_in_d s 1_1 7-0 s mpte s t 352 d s 1 extra c te d pa c ket - b yte 1. r0 00fh video_format_3 52_in_word_2 video_format_in_d s 1_4 15-8 s mpte s t 352 d s 1 extra c te d pa c ket - b yte 4. r0 video_format_in_d s 1_3 7-0 s mpte s t 352 d s 1 extra c te d pa c ket - b yte 3. r0 table 4-34: video core configuration and status registers (continued) address register name bit name bit des c ription r/w default
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 96 of 125 www.semtech.com 010h video_format_3 52_in_word_3 video_format_in_d s 2_2 15-8 s mpte s t 352 d s 2 extra c te d pa c ket - b yte 2. r0 video_format_in_d s 2_1 7-0 s mpte s t 352 d s 2 extra c te d pa c ket - b yte 1. r0 011h video_format_3 52_in_word_4 video_format_in_d s 2_4 15-8 s mpte s t 352 d s 2 extra c te d pa c ket - b yte 4. r0 video_format_in_d s 2_3 7-0 s mpte s t 352 d s 2 extra c te d pa c ket - b yte 3. r0 012h ra s ter_ s tru c _1 r s vd 15-11 reserve d . r 0 line s _per_frame 10-0 total lines per frame. r 0 013h ra s ter_ s tru c _2 r s vd 15-14 reserve d . r 0 word s _per_line 13-0 total wor d s per line. r 0 014h ra s ter_ s tru c _3 r s vd 15-13 reserve d . r 0 a c tive_word s _per_line 12-0 wor d s per a c tive line. r 0 015h ra s ter_ s tru c _4 r s vd 15-11 reserve d . r 0 a c tive_line s _per_field 10-0 a c tive lines per frame. r 0 01 6 h to 023h r s vd r s vd 15-0 reserve d . r 0 024h fir s t_line _number_ s tatu s r s vd 15-2 reserve d . r 0 pa c ket_mi ss ed 1 an c d ata pa c ket c oul d not b e inserte d in its entirety. hi g h - an c pa c ket c annot b e inserte d in it ? s entirety. r0 rw_ c onfli c t0 s ame ram a dd ress was rea d an d written to at the same time. hi g h - one of the a dd resses from 040h to 13fh was rea d an d written to at the same time. r0 025h fir s t_line_ number r s vd 15-12 reserve d . r 0 an c _in s _mode 11 an c d ata insertion mo d e. hi g h - c on c atenate low - s eparate r/w 0 fir s t_line_number 10-0 first line num b er to insert an c pa c ket on. r/w 0 table 4-34: video core configuration and status registers (continued) address register name bit name bit des c ription r/w default
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 97 of 125 www.semtech.com 02 6 h fir s t_line_ number_of_ word s fir s t_line_number_an c _ type 15 an c re g ion to insert pa c ket in hi g h - van c , low - han c . r/w 0 fir s t_line_number_ s tream_type 14 s tream to insert pa c ket in hi g h - c stream, low - y stream. r/w 0 r s vd 13-10 reserve d . r 0 fir s t_line_number_of_ word s 9-0 total num b er of wor d s in an c pa c ket to b e inserte d in first line. r/w 0 027h s e c ond_line_ number r s vd 15-11 reserve d . r 0 s e c ond_line_number 10-0 s e c on d line num b er to insert an c pa c ket on in s eparate line mo d e. r/w 0 028h s e c ond_line_ number_of_ word s s e c ond_line_number_ an c _type 15 an c re g ion to insert pa c ket in. hi g h - van c , low - han c . r/w 0 s e c ond_line_number_ s tream_type 14 s tream to insert pa c ket in. hi g h - c stream, low - y stream. r/w 0 r s vd 13-10 reserve d . r 0 s e c ond_line_number_ of_word s 9-0 total num b er of wor d s in an c pa c ket to b e inserte d in se c on d line. r/w 0 029h third_line_ number r s vd 15-11 reserve d . r 0 third_line_number 10-0 thir d line num b er to insert an c pa c ket on in s eparate line mo d e. r/w 0 02ah third_line_ number_of_ word s third_line_number_an c _ type 15 an c re g ion to insert pa c ket in. hi g h - van c , low - han c . r/w 0 third_line_number_ s tream_type 14 s tream to insert pa c ket in. hi g h - c stream, low - y stream. r/w 0 r s vd 13-10 reserve d . r 0 third_line_number_of_ word s 9-0 total num b er of wor d s in an c pa c ket to b e inserte d in thir d line. r/w 0 02bh fourth_line_ number r s vd 15-11 reserve d . r 0 fourth_line_number 10-0 fourth line num b er to insert an c pa c ket on in s eperate line mo d e. r/w 0 table 4-34: video core configuration and status registers (continued) address register name bit name bit des c ription r/w default
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 98 of 125 www.semtech.com 02 c h fourth_line_ number_of_ word s fourth_line_number_ an c _type 15 an c re g ion to insert pa c ket in hi g h - van c , low - han c . r/w 0 fourth_line_number_ s tream_type 14 s tream to insert pa c ket in. hi g h - c stream, low - y stream. r/w 0 r s vd 13-10 reserve d . r 0 fourth_line_ number_of_ word s 9-0 total num b er of wor d s in an c pa c ket to b e inserte d in fourth line. r/w 0 02dh s tream_type_1 r s vd 15-5 reserve d . r 0 edh_line_ c he c k_en 4 hi g h - an c b lo c k will not insert d ata into the edh re g ion of the han c spa c e. low - an c b lo c k will insert d ata into the edh re g ion. r/w 1 s tream_type1_line_4 3 hi g h - d ata for the fourth line in separate mo d e is inserte d into data s tream two. low - data s tream one. parameter only appli c a b le for 3 g . r/w 0 s tream_type1_line_3 2 hi g h - d ata for the thir d line in separate mo d e is inserte d into data s tream two. low - data s tream one. parameter only appli c a b le for 3 g . r/w 0 s tream_type1_line_2 1 hi g h - d ata for the se c on d line in separate mo d e is inserte d into data s tream two. low - data s tream one. parameter only appli c a b le for 3 g . r/w 0 s tream_type1_line_1 0 hi g h - d ata for the first line in separate mo d e is inserte d into data s tream two. low - data s tream one. parameter only appli c a b le for 3 g . r/w 0 02eh to 03fh r s vd r s vd 15-0 reserve d . r 0 040h to 07fh an c _pa c ket_ bank_1 an c _pa c ket_bank 15-0 first b ank of user- d efine d 8- b it an c illary d ata. bit 15 - 8: 2n d b yte (m s b to l s b) bit 7 - 0: 1st b yte (m s b to l s b) s ee 4.8 an c data insertion . ?? 080h to 0bfh an c _pa c ket_ bank_2 an c _pa c ket_bank 15-0 s e c on d b ank of user- d efine d 8- b it an c illary d ata. bit 15 - 8: 2n d b yte (m s b to l s b) bit 7 - 0: 1st b yte (m s b to l s b) s ee 4.8 an c data insertion . ?? table 4-34: video core configuration and status registers (continued) address register name bit name bit des c ription r/w default
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 99 of 125 www.semtech.com 0 c 0h to 0ffh an c _pa c ket_ bank_3 an c _pa c ket_bank 15-0 thir d b ank of user- d efine d 8- b it an c illary d ata. bit 15 - 8: 2n d b yte (m s b to l s b) bit 7 - 0: 1st b yte (m s b to l s b) s ee 4.8 an c data insertion . ?? 100h to 13fh an c _pa c ket_ bank_4 an c _pa c ket_bank 15-0 fourth b ank of user- d efine d 8- b it an c illary d ata. bit 15 - 8: 2n d b yte (m s b to l s b) bit 7 - 0: 1st b yte (m s b to l s b) s ee 4.8 an c data insertion . ?? 140h to 209h r s vd r s vd ? reserve d . r 0 20ah s dti_tdm r s vd 15-8 reserve d . r 0 s dti_tdm_d s 27 hi g h in d i c ates an s dti type si g nal on input for data s tream two. r/w 0 s dti_tdm_d s 1 6 hi g h in d i c ates an s dti type si g nal on input for data s tream one. r/w 0 r s vd 5-0 reserve d . r 0 20bh to 20 c h r s vd r s vd ? reserve d . r 0 20dh levelb_indi c ation r s vd 15-9 reserve d . r 0 level_b 8 hi g h in d i c ates level b d ete c te d . only relevant for 3 g input streams. r0 r s vd 7-0 reserve d . r 0 20eh drive_ s tren g th r s vd 15- 6 reserve d . r/w 0 audio_int_d s 5-4 drive stren g th value for audio_int pin. 00: 4ma; 01: 6 ma; 10: 8ma(+1.8v), 10ma(+3.3v); 11: 10ma(+1.8v), 12ma(+3.3v) r/w 0 lo c ked_d s 3-2 drive stren g th value for lo c ked pin. 00: 4ma; 01: 6 ma; 10: 8ma(+1.8v), 10ma(+3.3v); 11: 10ma(+1.8v), 12ma(+3.3v) r/w 0 s dout_tdo_d s 1-0 drive stren g th value for s dout_tdo pin. 00: 4ma; 01: 6 ma; 10: 8ma(+1.8v), 10ma(+3.3v); 11: 10ma(+1.8v), 12ma(+3.3v) r/w 2 20fh r s vd r s vd 15-0 reserve d . r/w 0 table 4-34: video core configuration and status registers (continued) address register name bit name bit des c ription r/w default
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 100 of 125 www.semtech.com 4.14.2 sd audio core 210h drive_ s tren g th2 tdo_d s 15-14 drive stren g th value for tdo pin. 00: 4ma; 01: 6 ma; 10: 8ma(+1.8v), 10ma(+3.3v); 11: 10ma(+1.8v), 12ma(+3.3v) r/w 0 r s vd 13-0 reserve d . r/w 0 211h to 232h r s vd r s vd 15-0 reserve d . r 0 table 4-34: video core configuration and status registers (continued) address register name bit name bit des c ription r/w default table 4-35: sd audio core configuration and status registers address register name bit name bit des c ription r/w default 400h c f g _aud c tr_a g r15 s ele c ts repla c ement of au d io c ontrol pa c kets. low - do not repla c e au d io c ontrol pa c kets hi g h - repla c e all au d io c ontrol pa c kets r/w 0 a g r14 s ele c ts au d io g roup repla c ement operatin g mo d e. a c tive hi g h. r/w 0 one_a g r13 s pe c ifies the repla c ement of just the primary g roup. low - repla c e b oth the primary an d se c on d ary g roups hi g h - repla c e only the primary g roup r/w 0 c trb_on 12 s pe c ifies the em b e dd in g of the se c on d ary g roup au d io c ontrol pa c kets. a c tive hi g h. r/w 1 c lear_audio 11 c lears all au d io fifo b uffers an d puts them in the start-up state. a c tive hi g h. r/w 0 afnb_auto 10 ena b les s e c on d ary g roup au d io frame num b er g eneration. a c tive hi g h. r/w 1 c tra_on 9 s pe c ifies the em b e dd in g of primary g roup au d io c ontrol pa c kets. a c tive hi g h. r/w 1 audio_24bit 8 s pe c ifies the sample size for em b e dd e d au d io. hi g h - 24- b it low - 20- b it/1 6 - b it r/w 0
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 101 of 125 www.semtech.com 400h c f g _aud afna_auto 7 ena b les primary g roup au d io frame num b er g eneration. a c tive hi g h. r/w 1 afn_of s6 -4 offset to a dd to g enerate d au d io frame num b er. must b e in the ran g e of 0 to 4. r/w 0 idb 3-2 s pe c ifies the se c on d ary au d io g roup to em b e d . note: s houl d ida an d idb b e set to the same value, they automati c ally revert to their d efault values. r/w 1 ida 1-0 s pe c ifies the primary au d io g roup to em b e d . note: s houl d ida an d idb b e set to the same value, they automati c ally revert to their d efault values. r/w 0 401h fifo_buf_ s ide r s vd 15-3 reserve d .r0 off s et_di s able 2 s et to d isa b le sta gg erin g of se c on d ary g roup au d io sample d istri b ution b y one line. a c tive hi g h. r/w 0 o s _ s el 1-0 s pe c ifies the au d io fifo b uffer size. 00-52 samples d eep, 2 6 sample start-up c ount 01-24 samples d eep, 12 sample start-up c ount 10-12 samples d eep, 6 sample start-up c ount 11-reserve d r/w 0 402h ae s _ebu_err_ s tatu s r s vd 15-4 reserve d . r 0 ae s _errd 3 s tereo pair d (7&8) au d io input parity error when usin g ae s format. automati c ally c leare d when rea d . r0 ae s _err c 2 s tereo pair c (5& 6 ) au d io input parity error when usin g ae s format. automati c ally c leare d when rea d . r0 ae s _errb 1 s tereo pair b (3&4) au d io input parity error when usin g ae s format. automati c ally c leare d when rea d . r0 ae s _erra 0 s tereo pair a (1&2) au d io input parity error when usin g ae s format. automati c ally c leare d when rea d . r0 table 4-35: sd audio core configuration and status registers (continued) address register name bit name bit des c ription r/w default
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 102 of 125 www.semtech.com 403h c hannel_ s tat_ re g en r s vd 15-1 reserve d . r 0 a cs _re g en 0 s pe c ifies that au d io c hannel s tatus of all c hannels shoul d b e repla c e d with a cs r[183:0] fiel d . low: do not repla c e c hannel s tatus hi g h: repla c e c hannel s tatus of all c hannels r/w 0 404h pa c ket_det_ s tatu s r s vd 15-14 reserve d . r 0 axp g 4_det 13 s et while g roup 4 au d io exten d e d pa c kets are d ete c te d . r0 axp g 3_det 12 s et while g roup 3 au d io exten d e d pa c kets are d ete c te d . r0 axp g 2_det 11 s et while g roup 2 au d io exten d e d pa c kets are d ete c te d . r0 axp g 1_det 10 s et while g roup 1 au d io exten d e d pa c kets are d ete c te d . r0 a c p g 4_det 9 s et while g roup 4 au d io c ontrol pa c kets are d ete c te d . r0 a c p g 3_det 8 s et while g roup 3 au d io c ontrol pa c kets are d ete c te d . r0 a c p g 2_det 7 s et while g roup 2 au d io c ontrol pa c kets are d ete c te d . r0 a c p g 1_det 6 s et while g roup 1 au d io c ontrol pa c kets are d ete c te d . r0 adp g 4_det 5 s et while g roup 4 au d io d ata pa c kets are d ete c te d . r0 adp g 3_det 4 s et while g roup 3 au d io d ata pa c kets are d ete c te d . r0 adp g 2_det 3 s et while g roup 2 au d io d ata pa c kets are d ete c te d . r0 adp g 1_det 2 s et while g roup 1 au d io d ata pa c kets are d ete c te d . r0 a cs _apply_waitb 1 s et while the gs 2972 is waitin g for a status b oun d ary in the s e c on d ary g roup b efore applyin g the a cs r[183:0] d ata to that g roup. r0 a cs _apply_waita 0 a cs _apply_waita: s et while the gs 2972 is waitin g for a status b oun d ary in primary g roup b efore applyin g the a cs r[183:0] d ata. r0 table 4-35: sd audio core configuration and status registers (continued) address register name bit name bit des c ription r/w default
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 103 of 125 www.semtech.com 405h ae s _ebu_err_ s tatu s 1 r s vd 15- 6 reserve d . r 0 final_held_a s d_err 5 final au d io sample d istri b ution error. r0 held_a s d_err 4 au d io sample d istri b ution error. r 0 held_ae s _err 3-0 ae s re c eive d errors for the 4 au d io lines. r0 40 6 h c a sc ade r s vd 15-1 reserve d . r 0 en_ c a sc ade 0 if hi g h, puts the gs 2972 into c as c a d e mo d e. this b it is only effe c tive if the a g r b it = low. r/w 0 407h to 40ah r s vd r s vd 15-0 reserve d . r 0 40bh s erial_audio_ format amd 15-14 au d io input format sele c tor for s tereo pair d input c hannels 7 an d 8. 00: ae s /ebu 01: s erial left j ustifie d 10: s erial ri g ht j ustifie d 11: i 2 s r/w 3 am c 13-12 au d io input format sele c tor for s tereo pair c input c hannels 5 an d 6 . ( s ee a b ove for d e c o d in g ). r/w 3 amb 11-10 au d io input format sele c tor for s tereo pair b input c hannels 3 an d 4. ( s ee a b ove for d e c o d in g ). r/w 3 ama 9-8 au d io input format sele c tor for s tereo pair a input c hannels 1 an d 2. ( s ee a b ove for d e c o d in g ). r/w 3 mute8 7 au d io input c hannel 8 mute ena b le. a c tive hi g h. r/w 0 mute7 6 au d io input c hannel 7 mute ena b le. a c tive hi g h. r/w 0 mute 6 5 au d io input c hannel 6 mute ena b le. a c tive hi g h. r/w 0 mute5 4 au d io input c hannel 5 mute ena b le. a c tive hi g h. r/w 0 mute4 3 au d io input c hannel 4 mute ena b le. a c tive hi g h. r/w 0 mute3 2 au d io input c hannel 3 mute ena b le. a c tive hi g h. r/w 0 mute2 1 au d io input c hannel 2 mute ena b le. a c tive hi g h. r/w 0 mute1 0 au d io input c hannel 1 mute ena b le. a c tive hi g h. r/w 0 table 4-35: sd audio core configuration and status registers (continued) address register name bit name bit des c ription r/w default
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 104 of 125 www.semtech.com 40 c h c hannel_xp_ g rpa r s vd 15 reserve d . r 0 g pa_w c lk_ s r c 14-12 primary au d io g roup wor d c lo c k sour c e sele c tor. input c hannel 1 000 input c hannel 2 001 input c hannel 3 010 input c hannel 4 011 input c hannel 5 100 input c hannel 6 101 input c hannel 7 110 input c hannel 8 111 r/w 0 g pa_ c h4_ s r c 11-9 primary au d io g roup c hannel 4 sour c e sele c tor. 011. r/w 3 g pa_ c h3_ s r c 8- 6 primary au d io g roup c hannel 3 sour c e sele c tor. 010. r/w 2 g pa_ c h2_ s r c 5-3 primary au d io g roup c hannel 2 sour c e sele c tor. 001. r/w 1 g pa_ c h1_ s r c 2-0 primary au d io g roup c hannel 1 sour c e sele c tor. 000 - input c hannel r/w 0 40dh c hannel_xp_ g rpb r s vd 15 reserve d . r 0 g pb_w c lk_ s r c 14-12 s e c on d ary au d io g roup wor d c lo c k sour c e sele c tor. r/w 4 g pb_ c h4_ s r c 11-9 s e c on d ary au d io g roup c hannel 4 sour c e sele c tor. r/w 7 g pb_ c h3_ s r c 8- 6 s e c on d ary au d io g roup c hannel 3 sour c e sele c tor. r/w 6 g pb_ c h2_ s r c 5-3 s e c on d ary au d io g roup c hannel 2 sour c e sele c tor. r/w 5 g pb_ c h1_ s r c 2-0 s e c on d ary au d io g roup c hannel 1 sour c e sele c tor. r/w 4 table 4-35: sd audio core configuration and status registers (continued) address register name bit name bit des c ription r/w default
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 105 of 125 www.semtech.com 40eh interrupt_ma s k en_a s d_err 15 asserts a s d error fla g .r/w0 en_no_video 14 mask b it when the vi d eo format is unknown. r/w 0 en_mux_errb 13 asserts audio_int when the mux_errb fla g is set. r/w 0 en_mux_erra 12 asserts audio_int when the mux_erra fla g is set. r/w 0 en_ae s _errd 11 asserts audio_int when the ae s _errd fla g is set. r/w 0 en_ae s _err c 10 asserts audio_int when the ae s _err c fla g is set. r/w 0 en_ae s _errb 9 asserts audio_int when the ae s _errb fla g is set. r/w 0 en_ae s _erra 8 asserts audio_int when the ae s _erra fla g is set. r/w 0 en_a c p g 4_det 7 asserts audio_int when the a c p g 4_det fla g is set. r/w 0 en_a c p g 3_det 6 asserts audio_int when the a c p g 3_det fla g is set. r/w 0 en_a c p g 2_det 5 asserts audio_int when the a c p g 2_det fla g is set. r/w 0 en_a c p g 1_det 4 asserts audio_int when the a c p g 1_det fla g is set. r/w 0 en_adp g 4_det 3 asserts audio_int when the adp g 4_det fla g is set. r/w 0 en_adp g 3_det 2 asserts audio_int when the adp g 3_det fla g is set. r/w 0 en_adp g 2_det 1 asserts audio_int when the adp g 2_det fla g is set. r/w 0 en_adp g 1_det 0 asserts audio_int when the adp g 1_det fla g is set. r/w 0 table 4-35: sd audio core configuration and status registers (continued) address register name bit name bit des c ription r/w default
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 106 of 125 www.semtech.com 40fh a c tive_ c hannel r s vd 15-13 reserve d . r 0 mute_all 12 mutes all input au d io c hannels. r/w 0 l s b_fir s td 11 c auses the fourth stereo pair serial input formats to use l s b first. use d in c onjun c tion with amd, an d only relevant when amd is 01 or 10 fi g ure 4-1 6 to 4-19. r/w 0 l s b_fir s t c 10 c auses the thir d stereo pair serial input formats to use l s b first. use d in c onjun c tion with am c an d only relevant when am c is 01 or 10 fi g ure 4-1 6 to 4-19. r/w 0 l s b_fir s tb 9 c auses the se c on d stereo pair serial input formats to use l s b first. use d in c onjun c tion with amb an d only relevant when amd is 01 or 10 fi g ure 4-1 6 to 4-19. r/w 0 l s b_fir s ta 8 c auses the first stereo pair serial input formats to use l s b first. use d in c onjun c tion with ama an d only relevant when ama is 01 or 10 fi g ure 4-1 6 to 4-19. r/w 0 a c t8 7 s pe c ifies em b e dd in g of se c on d ary au d io g roup c hannel 8. a c tive hi g h. r/w 1 a c t7 6 s pe c ifies em b e dd in g of se c on d ary au d io g roup c hannel 7. a c tive hi g h. r/w 1 a c t 6 5 s pe c ifies em b e dd in g of se c on d ary au d io g roup c hannel 6 . a c tive hi g h. r/w 1 a c t5 4 s pe c ifies em b e dd in g of se c on d ary au d io g roup c hannel 5. a c tive hi g h. r/w 1 a c t4 3 s pe c ifies em b e dd in g of primary au d io g roup c hannel 4. a c tive hi g h. r/w 1 a c t3 2 s pe c ifies em b e dd in g of primary au d io g roup c hannel 3. a c tive hi g h. r/w 1 a c t2 1 s pe c ifies em b e dd in g of primary au d io g roup c hannel 2. a c tive hi g h. r/w 1 a c t1 0 s pe c ifies em b e dd in g of primary au d io g roup c hannel 1. a c tive hi g h. r/w 1 table 4-35: sd audio core configuration and status registers (continued) address register name bit name bit des c ription r/w default
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 107 of 125 www.semtech.com 410h xpoint_error r s vd 15-3 reserve d . r 0 mux_errb 2 s et in c as c a d e mo d e when the in c omin g vi d eo c ontains pa c kets with the same g roup num b er as the s e c on d ary g roup. r0 mux_erra 1 s et in c as c a d e mo d e when the in c omin g vi d eo c ontains pa c kets with the same g roup num b er as the primary g roup. r0 xpoint_error 0 s et when the c rosspoint swit c h is c onfi g ure d to put the same au d io c hannel in b oth primary an d s e c on d ary g roups. r0 411h to 41fh r s vd r s vd ? reserve d . r 0 420h c hannel_ s tatu s _ re g _1 r s vd 15-8 reserve d . r 0 a cs r_byte_1 7-0 au d io c hannel status b lo c k b yte 1. r/w 133 421h c hannel_ s tatu s _ re g _2 r s vd 15-8 reserve d . r 0 a cs r_byte_2 7-0 au d io c hannel status b lo c k b yte 2. r/w 8 422h c hannel_ s tatu s _ re g _3 a cs r_byte_4 15-8 au d io c hannel status b lo c k b yte 4. r/w 0 a cs r_byte_3 7-0 au d io c hannel status b lo c k b yte 3. r/w 44 423h c hannel_ s tatu s _ re g _4 a cs r_byte_ 6 15-8 au d io c hannel status b lo c k b yte 6 .r/w 0 a cs r_byte_5 7-0 au d io c hannel status b lo c k b yte 5. r/w 0 424h c hannel_ s tatu s _ re g _5 a cs r_byte_8 15-8 au d io c hannel status b lo c k b yte 8. r/w 0 a cs r_byte_7 7-0 au d io c hannel status b lo c k b yte 7. r/w 0 425h c hannel_ s tatu s _ re g _ 6 a cs r_byte_10 15-8 au d io c hannel status b lo c k b yte 10. r/w 0 a cs r_byte_9 7-0 au d io c hannel status b lo c k b yte 9. r/w 0 42 6 h c hannel_ s tatu s _ re g _7 a cs r_byte_12 15-8 au d io c hannel status b lo c k b yte 12. r/w 0 a cs r_byte_11 7-0 au d io c hannel status b lo c k b yte 11. r/w 0 427h c hannel_ s tatu s _ re g _8 a cs r_byte_14 15-8 au d io c hannel status b lo c k b yte 14. r/w 0 a cs r_byte_13 7-0 au d io c hannel status b lo c k b yte 13. r/w 0 428h c hannel_ s tatu s _ re g _9 a cs r_byte_1 6 15-8 au d io c hannel status b lo c k b yte 1 6 . r/w 0 a cs r_byte_15 7-0 au d io c hannel status b lo c k b yte 15. r/w 0 table 4-35: sd audio core configuration and status registers (continued) address register name bit name bit des c ription r/w default
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 108 of 125 www.semtech.com 429h c hannel_ s tatu s _ re g _10 a cs r_byte_18 15-8 au d io c hannel status b lo c k b yte 18. r/w 0 a cs r_byte_17 7-0 au d io c hannel status b lo c k b yte 17. r/w 0 42ah c hannel_ s tatu s _ re g _11 a cs r_byte_20 15-8 au d io c hannel status b lo c k b yte 20. r/w 0 a cs r_byte_19 7-0 au d io c hannel status b lo c k b yte 19. r/w 0 42bh c hannel_ s tatu s _ re g _12 a cs r_byte_22 15-8 au d io c hannel status b lo c k b yte 22. r/w 0 a cs r_byte_21 7-0 au d io c hannel status b lo c k b yte 21. r/w 0 42 c h c hannel_ s tatu s _ re g _13 r s vd 15-8 reserve d . r/w 0 a cs r_byte_23 7-0 au d io c hannel status b lo c k b yte 23. r/w 0 42dh to 43fh r s vd r s vd ? reserve d . r 0 440h audio_ c trl_ g rpa_re g _1 r s vd 15-9 reserve d . r 0 del1a_byte_1 8-1 primary au d io g roup d elay d ata for c hannel 1 b yte 1. r/w 0 ebit1a 0 primary au d io g roup d elay d ata for c hannel 1. hi g h - in d i c ates d elay spe c ifie d at del1a_byte_1 is vali d . s ee s mpte s t 272 for a dd itional information. r/w 0 441h audio_ c trl_ g rpa_re g _2 r s vd 15-9 reserve d . r 0 del1a_byte_2 8-0 primary au d io g roup d elay d ata for c hannel 1 b yte 2. r/w 0 442h audio_ c trl_ g rpa_re g _3 r s vd 15-9 reserve d . r 0 del1a_byte_3 8-0 primary au d io g roup d elay d ata for c hannel 1 b yte 3. r/w 0 443h audio_ c trl_ g rpa_re g _4 r s vd 15-9 reserve d . r 0 del2a_byte_1 8-1 primary au d io g roup d elay d ata for c hannel 2 b yte 1. r/w 0 ebit2a 0 primary au d io g roup d elay d ata vali d fla g for c hannel 2. r/w 0 444h audio_ c trl_ g rpa_re g _5 r s vd 15-9 reserve d . r 0 del2a_byte_2 8-0 primary au d io g roup d elay d ata for c hannel 2 b yte 2. r/w 0 445h audio_ c trl_ g rpa_re g _ 6 r s vd 15-9 reserve d . r 0 del2a_byte_3 8-0 primary au d io g roup d elay d ata for c hannel 2 b yte 3. r/w 0 table 4-35: sd audio core configuration and status registers (continued) address register name bit name bit des c ription r/w default
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 109 of 125 www.semtech.com 44 6 h audio_ c trl_ g rpa_re g _7 r s vd 15-9 reserve d . r 0 del3a_byte_1 8-1 primary au d io g roup d elay d ata for c hannel 3 b yte 1. r/w 0 ebit3a 0 primary au d io g roup d elay d ata vali d fla g for c hannel 3. r/w 0 447h audio_ c trl_ g rpa_re g _8 r s vd 15-9 reserve d . r 0 del3a_byte_2 8-0 primary au d io g roup d elay d ata for c hannel 3 b yte 2. r/w 0 448h audio_ c trl_ g rpa_re g _9 r s vd 15-9 reserve d . r 0 del3a_byte_3 8-0 primary au d io g roup d elay d ata for c hannel 3 b yte 3. r/w 0 449h audio_ c trl_ g rpa_re g _10 r s vd 15-9 reserve d . r 0 del4a_byte_1 8-1 primary au d io g roup d elay d ata for c hannel 4 b yte 1. r/w 0 ebit4a 0 primary au d io g roup d elay d ata vali d fla g for c hannel 4. r/w 0 44ah audio_ c trl_ g rpa_re g _11 r s vd 15-9 reserve d . r 0 del4a_byte_2 8-0 primary au d io g roup d elay d ata for c hannel 4 b yte 2. r/w 0 44bh audio_ c trl_ g rpa_re g _12 r s vd 15-9 reserve d . r 0 del4a_byte_3 8-0 primary au d io g roup d elay d ata for c hannel 4 b yte 3. r/w 0 44 c h audio_ c trl_ g rpb_re g _1 r s vd 15-9 reserve d . r 0 del1b_byte_1 8-1 s e c on d ary au d io g roup d elay d ata for c hannel 1 b yte 1. r/w 0 ebit1b 0 s e c on d ary au d io g roup d elay d ata vali d fla g for c hannel 1. r/w 0 44dh audio_ c trl_ g rpb_re g _2 r s vd 15-9 reserve d . r 0 del1b_byte_2 8-0 s e c on d ary au d io g roup d elay d ata for c hannel 1 b yte 2. r/w 0 44eh audio_ c trl_ g rpb_re g _3 r s vd 15-9 reserve d . r 0 del1b_byte_3 8-0 s e c on d ary au d io g roup d elay d ata for c hannel 1 b yte 3. r/w 0 44fh audio_ c trl_ g rpb_re g _4 r s vd 15-9 reserve d . r 0 del2b_byte_1 8-1 s e c on d ary au d io g roup d elay d ata for c hannel 2 b yte 1. r/w 0 ebit2b 0 s e c on d ary au d io g roup d elay d ata vali d fla g for c hannel 2. r/w 0 table 4-35: sd audio core configuration and status registers (continued) address register name bit name bit des c ription r/w default
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 110 of 125 www.semtech.com 450h audio_ c trl_ g rpb_re g _5 r s vd 15-9 reserve d . r 0 del2b_byte_2 8-0 s e c on d ary au d io g roup d elay d ata for c hannel 2 b yte 2. r/w 0 451h audio_ c trl_ g rpb_re g _ 6 r s vd 15-9 reserve d . r 0 del2b_byte_3 8-0 s e c on d ary au d io g roup d elay d ata for c hannel 2 b yte 3. r/w 0 452h audio_ c trl_ g r pb_re g _7 r s vd 15-9 reserve d . r 0 del3b_byte_1 8-1 s e c on d ary au d io g roup d elay d ata for c hannel 3 b yte 1. r/w 0 ebit3b 0 s e c on d ary au d io g roup d elay d ata vali d fla g for c hannel 3. r/w 0 453h audio_ c trl_ g r pb_re g _8 r s vd 15-9 reserve d . r 0 del3b_byte_2 8-0 s e c on d ary au d io g roup d elay d ata for c hannel 3 b yte 2. r/w 0 454h audio_ c trl_ g r pb_re g _9 r s vd 15-9 reserve d . r 0 del3b_byte_3 8-0 s e c on d ary au d io g roup d elay d ata for c hannel 3 b yte 3. r/w 0 455h audio_ c trl_ g r pb_re g _10 r s vd 15-9 reserve d . r 0 del4b_byte_1 8-1 s e c on d ary au d io g roup d elay d ata for c hannel 4 b yte 1. r/w 0 ebit4b 0 s e c on d ary au d io g roup d elay d ata vali d fla g for c hannel 4. r/w 0 45 6 h audio_ c trl_ g r pb_re g _11 r s vd 15-9 reserve d . r 0 del4b_byte_2 8-0 s e c on d ary au d io g roup d elay d ata for c hannel 4 b yte 2. r/w 0 457h audio_ c trl_ g r pb_re g _12 r s vd 15-9 reserve d . r 0 del4b_byte_3 8-0 s e c on d ary au d io g roup d elay d ata for c hannel 4 b yte 3. r/w 0 table 4-35: sd audio core configuration and status registers (continued) address register name bit name bit des c ription r/w default
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 111 of 125 www.semtech.com 4.14.3 hd and 3g au dio core registers table 4-36: hd and 3g audio core configuration and status registers address register name bit name bit des c ription r/w default 800h c f g _aud c tr_a g r15 s ele c ts repla c ement of au d io c ontrol pa c kets. low - do not repla c e au d io c ontrol pa c kets hi g h - repla c e all au d io c ontrol pa c kets r/w 0 a g r14 s ele c ts au d io g roup repla c ement operatin g mo d e. a c tive hi g h. r/w 0 one_a g r13 s pe c ifies the repla c ement of just the primary g roup. low - repla c e b oth the primary an d se c on d ary g roups. hi g h - repla c e only the primary g roup. r/w 0 c trb_on 12 s pe c ifies the em b e dd in g of the se c on d ary g roup au d io c ontrol pa c kets. a c tive hi g h. r/w 1 a s xb 11 s e c on d ary g roup asyn c hronous mo d e. a c tive hi g h. r/w 0 afnb_auto 10 ena b les s e c on d ary g roup au d io frame num b er g eneration. a c tive hi g h. r/w 1 c tra_on 9 s pe c ifies the em b e dd in g of primary g roup au d io c ontrol pa c kets. a c tive hi g h. r/w 1 a s xa 8 primary g roup asyn c hronous mo d e. r/w 0 afna_auto 7 ena b les primary g roup au d io frame num b er g eneration. r/w 1 anf_of s6 -4 offset to a dd to g enerate d au d io frame num b er. must b e in the ran g e of 0 to 4. r/w 0 idb 3-2 s pe c ifies the s e c on d ary au d io g roup to em b e d . 00: au d io g roup #1 01: au d io g roup #2 10: au d io g roup #3 11: au d io g roup #4 r/w 1 ida 1-0 s pe c ifies the primary au d io g roup to em b e d . 00: au d io g roup #1 01: au d io g roup #2 10: au d io g roup #3 11: au d io g roup #4 r/w 0 801h r s vd r s vd 15-0 reserve d . r 0
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 112 of 125 www.semtech.com 802h c hannel_ s tat_ re g ren r s vd 15-1 reserve d . r 0 a cs _re g en 0 s pe c ifies that au d io c hannel s tatus of all c hannels shoul d b e repla c e d with a cs r[183:0] fiel d . low: do not repla c e c hannel s tatus hi g h: repla c e c hannel s tatus of all c hannels r/w 0 803h pa c ket_det_ s tatu s r s vd 15-14 reserve d . r 0 ae s _errd 13 s tereo pair d au d io input parity error when usin g ae s format. automati c ally c leare d when rea d . r0 ae s _err c 12 s tereo pair c au d io input parity error when usin g ae s format. automati c ally c leare d when rea d . r0 ae s _errb 11 s tereo pair b au d io input parity error when usin g ae s format. automati c ally c leare d when rea d . r0 ae s _erra 10 s tereo pair a au d io input parity error when usin g ae s format. automati c ally c leare d when rea d . r0 a c p g 4_det 9 s et while g roup 4 au d io c ontrol pa c kets are d ete c te d . r0 a c p g 3_det 8 s et while g roup 3 au d io c ontrol pa c kets are d ete c te d . r0 a c p g 2_det 7 s et while g roup 2 au d io c ontrol pa c kets are d ete c te d . r0 a c p g 1_det 6 s et while g roup 1 au d io c ontrol pa c kets are d ete c te d . r0 adp g 4_det 5 s et while g roup 4 au d io d ata pa c kets are d ete c te d . r0 adp g 3_det 4 s et while g roup 3 au d io d ata pa c kets are d ete c te d . r0 adp g 2_det 3 s et while g roup 2 au d io d ata pa c kets are d ete c te d . r0 adp g 1_det 2 s et while g roup 1 au d io d ata pa c kets are d ete c te d . r0 a cs _apply_waitb 1 s et while the gs 2972 is waitin g for a status b oun d ary in the s e c on d ary g roup b efore applyin g the a cs r[183:0] d ata to that g roup. r0 803h pa c ket_det_ s tatu s a cs _apply_waita 0 a cs _apply_waita: s et while the multiplexer is waitin g for a status b oun d ary in primary g roup b efore applyin g the a cs r[183:0] d ata. r0 table 4-36: hd and 3g audio core configuration and status registers (continued) address register name bit name bit des c ription r/w default
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 113 of 125 www.semtech.com 804h ae s _ebu_err_ s tatu s r s vd 15-4 reserve d . r 0 held_ae s _err 3-0 ae s re c eive d errors for the 4 au d io lines. r0 805h c a sc ade r s vd 15-1 reserve d . r 0 en_ c a sc ade 0 if hi g h, puts the gs 2972 into c as c a d e mo d e. this b it is only effe c tive if the a g r b it is low. r/w 0 80 6 h to 809h r s vd r s vd 15-0 reserve d . r 0 80ah s erial_audio_ format amd 15-14 au d io input format sele c tor for s tereo pair d input c hannels 7 an d 8. 00: ae s /ebu 01: s erial left j ustifie d 10: s erial ri g ht j ustifie d 11: i 2 s r/w 3 am c 13-12 au d io input format sele c tor for s tereo pair c input c hannels 5 an d 6 . ( s ee a b ove for d e c o d in g ). r/w 3 amb 11-10 au d io input format sele c tor for s tereo pair b input c hannels 3 an d 4. ( s ee a b ove for d e c o d in g ). r/w 3 ama 9-8 au d io input format sele c tor for s tereo pair a input c hannels 1 an d 2. ( s ee a b ove for d e c o d in g ). r/w 3 mute8 7 au d io input c hannel 8 mute ena b le. r/w 0 mute7 6 au d io input c hannel 7 mute ena b le. r/w 0 mute 6 5 au d io input c hannel 6 mute ena b le. r/w 0 mute5 4 au d io input c hannel 5 mute ena b le. r/w 0 mute4 3 au d io input c hannel 4 mute ena b le. r/w 0 mute3 2 au d io input c hannel 3 mute ena b le. r/w 0 mute2 1 au d io input c hannel 2 mute ena b le. r/w 0 80ah mute1 0 au d io input c hannel 1 mute ena b le. r/w 0 table 4-36: hd and 3g audio core configuration and status registers (continued) address register name bit name bit des c ription r/w default
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 114 of 125 www.semtech.com 80bh c hannel_xp_ g rpa r s vd 15 reserve d . r 0 g pa_w c lk_ s r c 14-12 primary au d io g roup wor d c lo c k sour c e sele c tor. r/w 0 g pa_ c h4_ s r c 11-9 primary au d io g roup c hannel 4 sour c e sele c tor. r/w 3 g pa_ c h3_ s r c 8- 6 primary au d io g roup c hannel 3 sour c e sele c tor. r/w 2 g pa_ c h2_ s r c 5-3 primary au d io g roup c hannel 2 sour c e sele c tor. r/w 1 g pa_ c h1_ s r c 2-0 primary au d io g roup c hannel 1 sour c e sele c tor. r/w 0 80 c h c hannel_xp_ g rpb r s vd 15 reserve d . r 0 g pb_w c lk_ s r c 14-12 s e c on d ary au d io g roup wor d c lo c k sour c e sele c tor. r/w 4 g pb_ c h4_ s r c 11-9 s e c on d ary au d io g roup c hannel 4 sour c e sele c tor. r/w 7 g pb_ c h3_ s r c 8- 6 s e c on d ary au d io g roup c hannel 3 sour c e sele c tor. r/w 6 g pb_ c h2_ s r c 5-3 s e c on d ary au d io g roup c hannel 2 sour c e sele c tor. r/w 5 g pb_ c h1_ s r c 2-0 s e c on d ary au d io g roup c hannel 1 sour c e sele c tor. r/w 4 table 4-36: hd and 3g audio core configuration and status registers (continued) address register name bit name bit des c ription r/w default
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 115 of 125 www.semtech.com 80dh interrupt_ ma s k r s vd 15 reserve d . r 0 en_no_video 14 asserts audio_int mask b it when the vi d eo format is unknown i.e. when no_video re g ister b it is set. r/w 0 en_mux_errb 13 asserts audio_int when the mux_errb fla g is set. r/w 0 en_mux_erra 12 asserts audio_int when the mux_erra fla g is set. r/w 0 en_ae s _errd 11 asserts audio_int when the ae s _errd fla g is set. r/w 0 en_ae s _err c 10 asserts audio_int when the ae s _err c fla g is set. r/w 0 en_ae s _errb 9 asserts audio_int when the ae s _errb fla g is set. r/w 0 en_ae s _erra 8 asserts audio_int when the ae s _erra fla g is set. r/w 0 en_a c p g 4_det 7 asserts audio_int when the a c p g 4_det fla g is set. r/w 0 en_a c p g 3_det 6 asserts audio_int when the a c p g 3_det fla g is set. r/w 0 en_a c p g 2_det 5 asserts audio_int when the a c p g 2_det fla g is set. r/w 0 en_a c p g 2_det 5 asserts audio_int when the a c p g 2_det fla g is set. r/w 0 en_a c p g 1_det 4 asserts audio_int when the a c p g 1_det fla g is set. r/w 0 en_adp g 4_det 3 asserts audio_int when the adp g 4_det fla g is set. r/w 0 en_adp g 3_det 2 asserts audio_int when the adp g 3_det fla g is set. r/w 0 en_adp g 2_det 1 asserts audio_int when the adp g 2_det fla g is set. r/w 0 en_adp g 1_det 0 asserts audio_int when the adp g 1_det fla g is set. r/w 0 table 4-36: hd and 3g audio core configuration and status registers (continued) address register name bit name bit des c ription r/w default
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 116 of 125 www.semtech.com 80eh a c tive_ c hannel r s vd 15-13 reserve d . r 0 mute_all 12 mutes all input au d io c hannels. r/w 0 l s b_fir s td 11 c auses the fourth stereo pair serial input formats to use l s b first. r/w 0 l s b_fir s t c 10 c auses the thir d stereo pair serial input formats to use l s b first. r/w 0 l s b_fir s tb 9 c auses the se c on d stereo pair serial input formats to use l s b first. r/w 0 l s b_fir s ta 8 c auses the first stereo pair serial input formats to use l s b first. r/w 0 a c t8 7 s pe c ifies em b e dd in g of se c on d ary au d io g roup c hannel 8. a c tive hi g h. r/w 1 a c t7 6 s pe c ifies em b e dd in g of se c on d ary au d io g roup c hannel 7. a c tive hi g h. r/w 1 a c t 6 5 s pe c ifies em b e dd in g of se c on d ary au d io g roup c hannel 6 . a c tive hi g h. r/w 1 a c t5 4 s pe c ifies em b e dd in g of se c on d ary au d io g roup c hannel 5. a c tive hi g h. r/w 1 a c t4 3 s pe c ifies em b e dd in g of se c on d ary au d io g roup c hannel 4. a c tive hi g h. r/w 1 a c t3 2 s pe c ifies em b e dd in g of se c on d ary au d io g roup c hannel 3. a c tive hi g h. r/w 1 a c t2 1 s pe c ifies em b e dd in g of se c on d ary au d io g roup c hannel 2. a c tive hi g h. r/w 1 a c t1 0 s pe c ifies em b e dd in g of se c on d ary au d io g roup c hannel 1. a c tive hi g h. r/w 1 80fh xpoint_error r s vd 15-3 reserve d . r 0 mux_errb 2 s et in c as c a d e mo d e when the in c omin g vi d eo c ontains pa c kets with the same g roup num b er as the s e c on d ary g roup. r0 mux_erra 1 s et in c as c a d e mo d e when the in c omin g vi d eo c ontains pa c kets with the same g roup num b er as the primary g roup. r0 xpoint_error 0 s et when the c rosspoint swit c h is c onfi g ure d to put the same au d io c hannel in b oth primary an d s e c on d ary g roups. r0 table 4-36: hd and 3g audio core configuration and status registers (continued) address register name bit name bit des c ription r/w default
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 117 of 125 www.semtech.com 810h to 81fh r s vd r s vd ? reserve d . r 0 820h c hannel_ s tatu s _re g _1 r s vd 15-8 reserve d . r 0 a cs r_byte_1 7-0 au d io c hannel status b lo c k b yte 1. r/w 133 821h c hannel_ s tatu s _re g _2 r s vd 15-8 reserve d . r 0 a cs r_byte_2 7-0 au d io c hannel status b lo c k b yte 2. r/w 8 822h c hannel_ s tatu s _re g _3 a cs r_byte_4 15-8 au d io c hannel status b lo c k b yte 4. r/w 0 a cs r_byte_3 7-0 au d io c hannel status b lo c k b yte 3. r/w 44 823h c hannel_ s tatu s _re g _4 a cs r_byte_ 6 15-8 au d io c hannel status b lo c k b yte 6 .r/w 0 a cs r_byte_5 7-0 au d io c hannel status b lo c k b yte 5. r/w 0 824h c hannel_ s tatu s _re g _5 a cs r_byte_8 15-8 au d io c hannel status b lo c k b yte 8. r/w 0 a cs r_byte_7 7-0 au d io c hannel status b lo c k b yte 7. r/w 0 825h c hannel_ s tatu s _re g _ 6 a cs r_byte_10 15-8 au d io c hannel status b lo c k b yte 10. r/w 0 a cs r_byte_9 7-0 au d io c hannel status b lo c k b yte 9. r/w 0 82 6 h c hannel_ s tatu s _re g _7 a cs r_byte_12 15-8 au d io c hannel status b lo c k b yte 12. r/w 0 a cs r_byte_11 7-0 au d io c hannel status b lo c k b yte 11. r/w 0 827h c hannel_ s tatu s _re g _8 a cs r_byte_14 15-8 au d io c hannel status b lo c k b yte 14. r/w 0 a cs r_byte_13 7-0 au d io c hannel status b lo c k b yte 13. r/w 0 828h c hannel_ s tatu s _re g _9 a cs r_byte_1 6 15-8 au d io c hannel status b lo c k b yte 1 6 .r/w 0 a cs r_byte_15 7-0 au d io c hannel status b lo c k b yte 15. r/w 0 829h c hannel_ s tatu s _re g _10 a cs r_byte_18 15-8 au d io c hannel status b lo c k b yte 18. r/w 0 a cs r_byte_17 7-0 au d io c hannel status b lo c k b yte 17. r/w 0 82ah c hannel_ s tatu s _re g _11 a cs r_byte_20 15-8 au d io c hannel status b lo c k b yte 20. r/w 0 a cs r_byte_19 7-0 au d io c hannel status b lo c k b yte 19. r/w 0 82bh c hannel_ s tatu s _re g _12 a cs r_byte_22 15-8 au d io c hannel status b lo c k b yte 22. r/w 0 a cs r_byte_21 7-0 au d io c hannel status b lo c k b yte 21. r/w 0 82 c h c hannel_ s tatu s _re g _13 r s vd 15-8 reserve d . r 0 a cs r_byte_23 7-0 au d io c hannel status b lo c k b yte 23. r/w 0 82dh to 83fh r s vd r s vd ? reserve d . r 0 840h audio_ c trl_ g rpa_re g _1 r s vd 15-9 reserve d . r 0 del1_2a_byte_1 8-1 primary au d io g roup d elay d ata for c hannel 1 & 2. r/w 0 ebit1_2a 0 primary au d io g roup d elay d ata vali d fla g for c hannel 1 & 2. r/w 0 table 4-36: hd and 3g audio core configuration and status registers (continued) address register name bit name bit des c ription r/w default
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 118 of 125 www.semtech.com 841h audio_ c trl_ g rpa_re g _2 r s vd 15-9 reserve d . r 0 del1_2a_byte_2 8-0 primary au d io g roup d elay d ata for c hannel 1 & 2. r/w 0 842h audio_ c trl_ g rpa_re g _3 r s vd 15-9 reserve d . r 0 del1_2a_byte_3 8-0 primary au d io g roup d elay d ata for c hannel 1 & 2. r/w 0 843h audio_ c trl_ g rpa_re g _4 r s vd 15-9 reserve d . r 0 del3_4a_byte_1 8-1 primary au d io g roup d elay d ata for c hannel 3 & 4. r/w 0 ebit3_4a 0 primary au d io g roup d elay d ata vali d fla g for c hannel 3 & 4. r/w 0 844h audio_ c trl_ g rpa_re g _5 r s vd 15-9 reserve d . r 0 del3_4a_byte_2 8-0 primary au d io g roup d elay d ata for c hannel 3 & 4. r/w 0 845h audio_ c trl_ g rpa_re g _ 6 r s vd 15-9 reserve d . r 0 del3_4a_byte_3 8-0 primary au d io g roup d elay d ata for c hannel 3 & 4. r/w 0 84 6 h audio_ c trl_ g rpb_re g _1 r s vd 15-9 reserve d . r 0 del1_2b_byte_1 8-1 s e c on d ary au d io g roup d elay d ata for c hannel 1 & 2. r/w 0 ebit1_2b 0 s e c on d ary au d io g roup d elay d ata vali d fla g for c hannel 1 & 2. r/w 0 847h audio_ c trl_ g rpb_re g _2 r s vd 15-9 reserve d . r 0 del1_2b_byte_2 8-0 s e c on d ary au d io g roup d elay d ata for c hannel 1 & 2. r/w 0 848h audio_ c trl_ g rpb_re g _3 r s vd 15-9 reserve d . r 0 del1_2b_byte_3 8-0 s e c on d ary au d io g roup d elay d ata for c hannel 1 & 2. r/w 0 849h audio_ c trl_ g rpb_re g _4 r s vd 15-9 reserve d . r 0 del3_4b_byte_1 8-1 s e c on d ary au d io g roup d elay d ata for c hannel 3 & 4. r/w 0 ebit3_4b 0 s e c on d ary au d io g roup d elay d ata for c hannel 3 & 4. r/w 0 84ah audio_ c trl_ g rpb_re g _5 r s vd 15-9 reserve d . r 0 del3_4b_byte_2 8-0 s e c on d ary au d io g roup d elay d ata for c hannel 3 & 4. r/w 0 84bh audio_ c trl_ g rpb_re g _ 6 r s vd 15-9 reserve d . r 0 del3_4b_byte_3 8-0 s e c on d ary au d io g roup d elay d ata for c hannel 3 & 4. r/w 0 table 4-36: hd and 3g audio core configuration and status registers (continued) address register name bit name bit des c ription r/w default
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 119 of 125 www.semtech.com 4.15 jtag id codeword the platform id for the 297x family is 0fh. the part number field of the jtag id codeword for the GS2972 is set to 0f01h. 4.16 jtag test operation when the jtag/host pin is high, the gspi host interf ace port is configured for jtag test operation. in this mode the sclk, sdin, sdout and cs become tck, tdi, tdo and tms. in addition, the trst pin becomes active. boundary scan testing using the jtag interface is enabled in this mode. when the jtag/host pin is low, the dedicated jtag interface is used. in this mode the tck, tdi, tdo and tms pins are active. this is the recommended mode for new designs. 4.17 device power-up because the GS2972 is designed to operat e in a multi-voltage environment, any power-up sequence is allowed. the charge pump, phase detector, core logic, serial digital output and i/o buffers can all be powered up in any order. 4.18 device reset note: at power-up, the device must be reset to operate correctly. in order to initialize all internal operating conditions to their default states, hold the reset signal low for a minimum of t reset = 1ms after all power supplies are stable. there are no requirements for power supply sequencing. when held in reset, all device outputs will be driven to a high-impedance state. fi g ure 4-35: reset pulse s upply volta g e re s et t reset 95% of nominal level nominal level reset reset t reset
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 120 of 125 www.semtech.com 5. application reference design 5.1 typical application circuit fi g ure 5-1: typi c al appli c ation c ir c uit aclk1 wclk1 ain_1/2 ain_3/4 aclk2 wclk2 sdo ain_5/6 ain_7/8 sdo audio_int tdo tck tms tdi pclk cd_vdd gnd_a gnd_a +1.2v_a gnd_a +1.2v io_vdd gnd_a +1.2v_a gnd_a cd_vdd gnd_a gnd_a +3.3v_a return loss compensation network sdi output video data, clock & timing input audio data and clock input (subject to change) notes: 1. dnp (do not populate). 2. the value of the series resistors on video data, clock, and timing connections should be determined by board signal integrity test (see section 4.1.1). 3. for analog power and ground isolation refer to pcb lay out guide. 4. for critital 3g signal layout refer to pcb layout guide. 5. for impedance controlled signals refer to pcb layout guide. close to GS2972. close to GS2972. sdo sdo pclk vco_vdd b7 vbg a8 vco_gnd b8 tdi e7 rsv a9 tim_861 g3 pclk b4 io_vdd g1 din 18 a2 din 19 b3 lf a7 a_vdd a10 b10 din 17 a1 core_vdd k8 grp1_en/dis h6 detect_trs f3 core_gnd e6 a_gnd b9 din 16 b2 core_vdd g10 pll_vdd a6 pll_vdd b6 rsv d5 standby d3 aclk1 k7 wclk1 j7 ain_1/2 j6 din 14 c2 din 15 b1 core_gnd c5 core_gnd b5 rsv d6 rsv d7 dvb_asi g5 locked h4 grp2_en/dis h5 ain_3/4 k6 din 12 c3 din 13 c1 rsv d8 tms e8 tdo f8 rate_sel0 e3 core_gnd e5 core_vdd e1 aclk2 k5 io_vdd h10 din 10 d2 din 11 d1 rsv f4 tck j8 core_gnd g9 20bit/10bit g4 core_gnd f5 core_vdd a5 wclk2 j5 io_gnd g2 din 8 f2 din 9 f1 rsv f7 cd_gnd f9 cd_gnd e9 ioproc_en/dis g7 smpte_bypass g6 reset g8 ain_5/6 j4 anc_blank h3 din 6 h2 din 7 h1 cd_gnd d9 core_gnd e2 audio_int h7 cs_tms k9 sclk_tck j10 sdout_tdo j9 ain_7/8 k4 h/hsync a4 din 4 j2 din 5 j1 core_gnd f6 pll_gnd c8 pll_gnd c7 pll_gnd c6 sdo_en/dis d4 sdin_tdi k10 v/vsync c4 io_gnd h9 din 2 k2 din 3 k1 rset f10 cd_vdd e10 sdo c10 sdo d10 cd_gnd c9 jtag/host h8 f/de a3 rate_sel1 e4 din 0 k3 din 1 j3 gs 2972-ibe3 10f 200 75 1f 1 3 2 5.6nh 75 1 3 2 5.6nh 10nf 4.7f dnp 105 4.7f 10nf dnp 75 10nf 10f 100pf 75 750 10nf grp1_en/dis grp2_en/dis din[19:0] +1.2v_a 0 10nf +1.2v 10nf 10nf 10nf 10nf io_vdd +1.2v 10nf power filtering 10nf 10nf gnd_a +3.3v_a 0 10nf 10nf gnd_a 1f 1f 1f 1f power decoupling place close to GS2972 1f 1f io_vdd 1f +3.3v cd_vdd 0 10nf 10nf gnd_a tim_861 detect_trs standby dvb_asi rate_sel0 rate_sel1 locked reset cs_tms sclk_tck sdout_tdo sdin_tdi jtag/host h/hsync v/vsync f/de cd_vdd ioproc_en/dis 20bit/10bit sdo_en/dis smpte_bypass 0 gnd_a gnd_a a_gnd anc_blank
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 121 of 125 www.semtech.com 6. references & relevant standards s mpte s t 125 c omponent vi d eo si g nal 4:2:2 ? b it parallel interfa c e s mpte s t 259- c 10- b it 4:2:2 c omponent an d 4fs c c omposite di g ital s i g nals - s erial di g ital interfa c e s mpte s t 2 6 0 1125 / 6 0 hi g h d efinition pro d u c tion system ? d i g ital representation an d b it parallel interfa c e s mpte s t 2 6 7 bit parallel d i g ital interfa c e ? c omponent vi d eo si g nal 4:2:2 1 6 x 9 aspe c t ratio s mpte s t 272 formattin g ae s /ebu au d io an d auxiliary data into di g ital vi d eo an c illary data s pa c e s mpte s t 274 1920 x 1080 s c annin g analo g an d parallel d i g ital interfa c es for multiple pi c ture rates s mpte s t 291 an c illary data pa c ket an d s pa c e formattin g s mpte s t 292 bit- s erial di g ital interfa c e for hi g h-definition television s ystems s mpte s t 293 720 x 483 a c tive line at 59.94hz pro g ressive s c an pro d u c tion ? d i g ital representation s mpte s t 29 6 1280 x 720 s c annin g , analo g an d d i g ital representation an d analo g interfa c e s mpte s t 299 24-bit di g ital au d io format for hdtv bit- s erial interfa c e s mpte s t 305 s erial data transport interfa c e s mpte s t 348 hi g h data-rate s erial data transport interfa c e (hd- s dti) s mpte s t 352 vi d eo payloa d i d entifi c ation for di g ital television interfa c es s mpte s t 372 dual link s t 292 interfa c e for 1920 x 1080 pi c ture raster s mpte s t 424 3 gb /s s i g nal/data s erial interfa c e s mpte s t 425 3 gb /s s i g nal/data s erial interfa c e - s our c e ima g e format mappin g s mpte rp1 6 5 error dete c tion c he c kwor d s an d s tatus fla g s for use in bit- s erial di g ital interfa c es for television s mpte rp1 6 8 definition of verti c al interval s wit c hin g point for s yn c hronous vi d eo s wit c hin g c ea 8 6 1vi d eo timin g requirements
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 122 of 125 www.semtech.com 7. package & ordering information 7.1 package dimensions fi g ure 7-1: pa c ka g e dimensions
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 123 of 125 www.semtech.com 7.2 packaging data 7.3 marking diagram fi g ure 7-2: markin g dia g ram table 7-1: pa c kaging data parameter value pa c ka g e type 11mm x 11mm 100- b all lb g a pa c ka g e drawin g referen c e j ede c m0192 (with ex c eptions note d in pa c ka g e dimensions on pa g e 122 ). moisture s ensitivity level 3 j un c tion to c ase thermal resistan c e, j- c 10.4 c /w j un c tion to air thermal resistan c e, j-a (at zero airflow) 37.1 c /w j un c tion to boar d thermal resistan c e, j- b 2 6 .4 c /w psi, 0.4 c /w p b -free an d roh s c ompliant yes gs 2972 xxxxxxe3 yyww pin 1 id xxxxxx - last 6 digits (excluding decimal) of sap batch assembly (fin) as listed on packing slip. e3 - pb-free & green indicator yyww - date code
GS2972 3g/hd/sd-sdi serializer with complete smpte audio & video support final data sheet rev. 9 gendoc-047479 september 2013 124 of 125 www.semtech.com 7.4 solder reflow profiles the GS2972 is available in a pb-free packag e. it is recommende d that the pb-free package be soldered with pb-free paste using the reflow profile shown in figure 7-3 . fi g ure 7-3: p b -free s ol d er reflow profile 7.5 ordering information 25c 150c 200c 217c 260c 250c time temperature 8 min. max 60-180 sec. max 60-150 sec. 20-40 sec. 3c/sec max 6c/sec max table 7-2: ordering information part number pa c kage pb-free temperature range gs 2972-ibe3 100- b all b g a yes -20 c to 85 c
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