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data sheet i 2 c programmable ethernet clock generator 8T49N4811 8T49N4811 revision a 3/30/15 1 ?2015 integrated device technology, inc. general description the 8T49N4811i is a highly flexible femtoclock ? ng pin-programmable clock generator suitable for networking and communications applications. it is able to generate five different output frequencies with multiple co pies of each. a fundamental mode crystal, single-ended, or differential input reference may be used as the source for the output frequency. the use of pin-programming to sele ct the input source / frequency, desired output frequencies and output styles allow a single device to be used in a wide variety of applications without the need for register programming. selection pins use 3-level options to maximize flexibility while minimizing package size. selection is performed by tying a selection pin high or low or by leaving it floating, eliminating the need for passive components to drive a desired logic level. features ? fourth generation femtoclock ? ng technology ? generates multiple copies of 25mhz, 50mhz, 100mhz, 125mhz, 156.25mhz or 312.5mhz ? typical input frequency is 25mhz, with optional 125mhz and 156.25mhz input support ? differential outputs are pin programmable for lvds or lvpecl ? rms phase jitter at 156.25mhz: <300fs typical ? power supply rejection ratio better than -50dbc from 10k-1.5mhz at 3.3v power supply ? full 3.3v and 2.5v supply voltages ? -40c to +85c ambient operating temperature ? 56-pin vfqfpn, lead-free (rohs 6) packaging block diagram /d1 lvpecl/lvd s lvpecl/lvd s lvpecl/lvd s lvpecl/lvd s 125mhz/156.25mhz/ 3 12.5mhz 50mhz/125mhz/156.25mhz 100mhz/125mhz/156.25mhz 25mhz/125mhz/156.25mhz xtal_out o s c xtal_in din ndin 25mhz/125mhz lvcmo s 100 f in b a nk a b a nk d1 b a nk c b a nk b 2.5v 5% or 3 . 3 v 10% apll /d0 /c /b /a f in pll byp ass b a nk d0 s data, s clk iic_adrx_ s el qx_ctrl qb_ctrl [1:0] div s el_x input_div s el lvcmo s _ctrl s lew_lvcmo s in_ s el fre qu ency, o u tp u t type, s lew r a te, & o u tp u t en ab le control inp u t divider fre qu ency s elect o u tp u t en ab le,type, & s lew r a te control 1 6 2 1 0 1 1 0 1 0 1 0 1 4 3
i 2 c programmable ethernet clock generator 2 revision a 3/30/15 8T49N4811 data sheet pin assignment 12 3 4567 89 10 11 12 1 3 14 4 3 44 45 46 47 4 8 4 9 50 51 52 5 3 54 55 56 22 2 3 24 25 26 27 2 8 21 20 1 9 1 8 17 16 15 3 4 3 5 3 6 3 7 38 39 40 41 42 33 3 2 3 1 3 02 9 div s el_c v dd in_ s el din v dd_xtal xtal_in xtal_out pll_bypa ss iic_adrx_ s el v dda input_div s el div s el_d0 lvcmo s _ctrl s clk s data re s erved div s el_b nc qd0_ s v dd_od s qd_ctrl nqd0 qd0 v dd_od qb_ctrl1 v dd s lew_lvcmo s nqb2 qb2 v dd_ob nqb1 qb1 nqb0 qb0 qb 3 nqb 3 v dd_ob qb4 nqb4 qb5 nqb5 qa0 qc_ctrl v dd_oc nqc1 qc1 nqc0 qc0 v dd_oc div s el_a nqa0 v dd_oa qa_ctrl v dd qb_ctrl0 ndin idt8T49N4811i 56-lead vfqfn 8mm x 8mm x 0.90mm package body 5.9mm x 5.9mm epad size nlg suffix to p v i e w
revision a 3/30/15 3 i 2 c programmable ethernet clock generator 8T49N4811 data sheet pin description and pin characteristic tables table 1. pin description number name type description 1 divsel_c input pullup/pulldown output divider selection for bank c. lvcmos interface levels. 2v dd power core supply. 3 in_sel input pullup/pulldown input select between xtal or different ial input. lvcmos interface levels. 4 din input differential reference input. accepts dc-coupled lvds and is internally biased to accept ac-coupled lvpecl, cml, hcsl or lvpecl signals. the differential inputs have an internal 100 ? resistor biased to v dd ?1.3v approximately. 5 ndin input 6v dd_xtal power crystal oscillator power supply. 7 xtal_in input crystal input. 8 xtal_out output crystal output. 9 pll_bypass input pulldown pll bypass. provides copy of f in to output banks a, b, c. lvcmos interface levels. 10 iic_adrx_sel input pulldown selects between i 2 c addresses. lvcmos interface levels. 11 v dda power analog supply. 12 input_divsel input pullup/pulldown selects proper divide ratios for differential reference input. lvcmos interface levels. 13 divsel_d0 input pullup/pulldown output divider selection for bank d0 differential output. lvcmos interface levels. 14 lvcmos_ctrl input pullup/pulldown divider and output enable control fo r bank d1 lvcmos output. lvcmos interface levels. 15 sclk input pullup i 2 c clock input. lvcmos/lvttl interface levels. 16 sdata i/o pullup i 2 c data input/output. input: lvcmos/lvttl interface levels. output: open drain. 17 reserved pulldown reserved. internally connected to 50k ? pulldown. 18 divsel_b input pullup/pulldown output divider selection for bank b. lvcmos interface levels. 19 nc this pin is not internally connected. connect to ground to maintain second source compatibility. 20 qd0_s output bank d1 lvcmos output. 21 v dd_ods power power supply for bank d1 lvcmos output. 22 qd_ctrl input pullup/pulldown control input for bank d0 output type an d oe status. lvcmos interface levels. 23 nqd0 output bank d0 differential output. lvds or lvpecl output levels. 24 qd0 output bank d0 differential out put. lvds or lvpecl output levels. 25 v dd_od power power supply for bank d0 differential output. 26 qb_ctrl1 input pullup/pulldown control input for bank b outputs qb3 to qb5 output type and oe status. lvcmos interface levels. 27 v dd power power supply. 28 slew_lvcmos input pulldown slew rate control pin for lvcmos output. lvcmos interface levels. 29 nqb5 output bank b differential output. lvds or lvpecl output levels. 30 qb5 output bank b differential output. lvds or lvpecl output levels. 31 nqb4 output bank b differential output. lvds or lvpecl output levels. 32 qb4 output bank b differential output. lvds or lvpecl output levels. 33 v dd_ob power power supply for bank b. 34 nqb3 output bank b differential output. lvds or lvpecl output levels.
i 2 c programmable ethernet clock generator 4 revision a 3/30/15 8T49N4811 data sheet table 2. pin characteristics 35 qb3 output bank b differential output. lvds or lvpecl output levels. 36 nqb2 output bank b differential output. lvds or lvpecl output levels. 37 qb2 output bank b differential output. lvds or lvpecl output levels. 38 v dd_ob power power supply for bank b. 39 nqb1 output bank b differential output. lvds or lvpecl output levels. 40 qb1 output bank b differential output. lvds or lvpecl output levels. 41 nqb0 output bank b differential output. lvds or lvpecl output levels. 42 qb0 output bank b differential output. lvds or lvpecl output levels. 43 qb_ctrl0 input pullup/pulldown control input for bank b outputs qb 0 to qb2 output type and oe status . lvcmos interface levels. 44 v dd power power supply. 45 qa_ctrl input pullup/pulldown control input for bank a output type and oe status . lvcmos interface levels. 46 v dd_oa power power supply for bank a. 47 nqa0 output bank a differential output. lvds or lvpecl output levels. 48 qa0 output bank a differential output. lvds or lvpecl output levels. 49 divsel_a input pullup/pulldown output divider selection for bank a . lvcmos interface levels. 50 qc_ctrl input pullup/pulldown control input for bank c output type and oe status . lvcmos interface levels. 51 v dd_oc power power supply for bank c. 52 nqc1 output bank c differential outp ut. lvds or lvpecl output levels. 53 qc1 output bank c differential outp ut. lvds or lvpecl output levels. 54 nqc0 output bank c differential outp ut. lvds or lvpecl output levels. 55 qc0 output bank c differential outp ut. lvds or lvpecl output levels. 56 v dd_oc power power supply for bank c. e-pad gnd power connect to ground; use thermal vias. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 3.5 pf r pullup input pullup resistor sclk, sdata 50 k ? divsel_x, in_sel, in_sel, input_divsel, lvcmos_ctrl, qx_ctrl, qb_ctrl[1:0] 58 k ? r pulldown input pulldown resistor 42 k ? pll_bypass, iic_adrx_sel, reserved, slew_lvcmos 50 k ? c pd power dissipation capacitance qdo_s v dd = v ddo_ods = 3.63v 18 pf qdo_s v dd = v ddo_ods = 2.625v 16 pf r out output impedance qdo_s v ddo_ods = 3.3v 24 ? qdo_s v ddo_ods = 2.5v 30 ? table 1. pin description (continued)
revision a 3/30/15 5 i 2 c programmable ethernet clock generator 8T49N4811 data sheet function tables table 3a. input frequency select table table 3b. slew rate control table table 3c. pll bypass table table 3d. i 2 c address selection table table 3e. bank a frequency select table table 3f. bank b frequency select table table 3g. bank c frequency select table table 3h. bank d1 lvcmos control table table 3i. bank d0 qd0 frequency select table table 3j. clock select function table table 3k. qx_ctrl and qb_ctrl[1:0] pin table note 1: qd_ctrl affects differential outputs only. note 2: qb_ctrl0 affects output s qb[0:2]. qb_ctrl1 affects outputs qb[3:5]. note 3: high impedance mode: 100k pulldown on true output, 100k pullup on compliment output. input_divsel 0 25mhz 1 125mhz float 156.25mhz slew_lvcmos 0 (default) normal 1 slow pll_bypass 0 (default) normal operation 1 pll bypassed iic_adrx_sel address 0 (default) dc (h) 1 de (h) divsel_a frequency 0 156.25mhz 1 125mhz float 312.5mhz divsel_b frequency 0 156.25mhz 1 125mhz float 50mhz divsel_c frequency 0 156.25mhz 1 125mhz float 100mhz lv c m o s _ c t r l state 0 high impedance 1 125mhz float f in divsel_d0 frequency 0 156.25mhz 1 125mhz float f in control input clock in_sel crystal din, ndin 0 selected de-selected 1 de-selected selected float selected (doubler = on) de-selected bank mode pin bank mode lvpecl lvds 0 selected; note 1, 2 de-selected 1 de-selected selected; note 1, 2 float high impedance; note 3 high impedance; note 3
i 2 c programmable ethernet clock generator 6 revision a 3/30/15 8T49N4811 data sheet serial interface configuration description the idt8T49N4811i has an i 2 c-compatible configuration interface to access any of the internal registers for frequency and pll parameter programming. the idt8T49N4811i acts as a slave device on the i 2 c bus and has the address 0b1101110. the interface accepts byte-oriented block write and block read operations. data bytes (registers) are accessed in sequentia l order from the lowest to the highest byte (most significant bit first, see block write/read operation tables). read and write block transfers can be stopped after any complete byte transfer. for full electrical i 2 c compliance, it is recommended to use external pull-up resistors for sdata and sclk. the internal pull-up resistors have a size of 50k ? typical. table 4a. block write operation table 4b. block read operation table 4c. divsel_a programming table 4d. divsel_b programming table 4e. divsel_c programming table 4f. divsel_d0 programming table 4g. lvcmos_ctrl programming table 4h. input_divsel programming bit 1 2:08 9 10 11:18 19 20:27 28 ... ... ... description start slave address w(0) ack data byte (p) ack data byte (p+1) ack data byte ? ack stop length (bits) 1 7 1 1 8 1 8 1 8 1 1 bit 1 2:08 9 10 11:18 19 20-27 28 ... ... ... description start slave address r(1) ack data byte (p) ack data byte (p+1) ack data byte ? ack stop length (bits) 1 7118181811 00 156.25mhz 01 312.5mhz 10 125mhz 11 100mhz 00 156.25mhz 01 50mhz 10 125mhz 11 100mhz 00 156.25mhz 01 100mhz 10 125mhz 11 50mhz 00 156.25mhz 01 f in 10 125mhz 11 100mhz 00 output disabled 01 f in 10 125mhz 11 100mhz 00 25mhz 01 156.25mhz 10 125mhz 11 100mhz
revision a 3/30/15 7 i 2 c programmable ethernet clock generator 8T49N4811 data sheet table 4i. frequency selection register, output table 4j. frequency selection register, misc. table 4k. output enable bank a and b register note: unlike the external control pins, in iic each output is individually controlled table 4l. output enable bank c and d. output type select register byte 0 pin # control function description 0 1 default bit 0 vendor id 0 bit 1 vendor id 0 bit 2 divsel_a(0) bank a output divider see divsel_a table 0 bit 3 divsel_a(1) 0 bit 4 divsel_b(0) bank b output divider see divsel_b table 0 bit 5 divsel_b(1) 0 bit 6 divsel_c(0) bank c output divider see divsel_c table 0 bit 7 divsel_c(1) 0 byte1 pin # control function description 0 1 default bit 0 divsel_d0(0) bank d0 output divid er see divsel_d0 table 1 bit 1 divsel_d0(1) 1 bit 2 lvcmos_ctrl(0) bank d1 lvcmos output divider and oe see lvcmos_ctrl table 1 bit 3 lvcmos_ctrl(1) 1 bit 4 input_divsel(0) input mux selection frequency see input_divsel table 0 bit 5 input_divsel(1) 0 bit 6 iic_adrx_sel selects iic write address dc (h) de (h) 0 bit 7 iic_pin control selects external pins or iic control external pin iic 0 byte2 pin # control function description 0 1 default bit 0 noe qa0 output enable enable disable 0 bit 1 noe qb0 output enable enable disable 0 bit 2 noe qb1 output enable enable disable 0 bit 3 noe qb2 output enable enable disable 0 bit 4 noe qb3 output enable enable disable 0 bit 5 noe qb4 output enable enable disable 0 bit 6 noe qb5 output enable enable disable 0 bit 7 n/a byte3 pin # control function description 0 1 default bit 0 noe qc0 output enable enable disable 0 bit 1 noe qc1 output enable enable disable 0 bit 2 noe qd0 output enable enable disable 0 bit 3 noe qdo_s output enable enable disable 0 bit 4 output type select qc0 lvpecl/lvds select lvpecl lvds 0 bit 5 output type select qc1 lvpecl/lvds select lvpecl lvds 0 bit 6 output type select qd0 lvpecl/lvds select lvpecl lvds 0 bit 7 n/a
i 2 c programmable ethernet clock generator 8 revision a 3/30/15 8T49N4811 data sheet table 4m. output type select bank a and b table 4n. misc. control byte4 pin # control function description 0 1 default bit 0 output type select qa0 lvpecl/lvds select lvpecl lvds 0 bit 1 output type select qb0 lvpecl/lvds select lvpecl lvds 0 bit 2 output type select qb1 lvpecl/lvds select lvpecl lvds 0 bit 3 output type select qb2 lvpecl/lvds select lvpecl lvds 0 bit 4 output type select qb3 lvpecl/lvds select lvpecl lvds 0 bit 5 output type select qb4 lvpecl/lvds select lvpecl lvds 0 bit 6 output type select qb5 lvpecl/lvds select lvpecl lvds 0 bit 7 n/a byte5 pin # control function description 0 1 default bit 0 in_sel select xtal or mux input crystal clock 0 bit 1 reserved 0 bit 2 slew_lvcmos slew rate control for lvcmos output normal slow 0 bit 3 pll_bypass pll bypass active bypass 0 bit 4 n_doubler_en turns 25mhz crystal input doubler circuit on/off on off 0 bit 5 reserved 0 bit 6 reserved 0 bit 7 n/a
revision a 3/30/15 9 i 2 c programmable ethernet clock generator 8T49N4811 data sheet absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the idt8T49N4811i. thes e ratings, which are standard values for idt commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operationa l sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. item rating supply voltage, v dd 3.63v inputs, v i xtal_in other inputs 0v to 2v -0.5v to v ddo_x + 0.5v outputs, v o (lvcmos) -0.5v to v ddo_a + 0.5v outputs, v o (lvds) continuous current 10ma 15ma outputs, v o (lvpecl) -0.5v to v ddo_c + 0.5v junction temperature, t j 125c storage temperature, t stg -65c to 150c
i 2 c programmable ethernet clock generator 10 revision a 3/30/15 8T49N4811 data sheet dc characteristics table 5a. power supply dc characteristics, v dd = v dda = v dd_xtal = v dd_ods = v dd_oa = v dd_ob = v dd_oc = v dd_od = 3.3v10 % , t a = -40c to 85c note: v dd_x denotes v dd , v dd_xtal , v dd_ods , v dd_oa , v dd_ob , v dd_oc , v dd_od. note: i dd_x denotes i dd , i dd_xtal , i dd_ods , i dd_oa , i dd_ob , i dd_oc , i dd_od. note: core supply voltage cannot be lo wer than the output supply voltage. note 1: total power supply current with all differential outputs ar e set to lvds output format and lvcmos clock is running at 1 25mhz. note 2: core power supply current with a ll differential outputs are set to lvpecl out put format and lvcmos clock is running at 125mhz. table 5b. power supply dc characteristics, v dd = v dda = v dd_xtal = v dd_ods = v dd_oa = v dd_ob = v dd_oc = v dd_od = 2.5v5 % , t a = -40c to 85c note: v dd_x denotes v dd , v dd_xtal , v dd_ods , v dd_oa , v dd_ob , v dd_oc , v dd_od. note: i dd_x denotes i dd , i dd_xtal , i dd_ods , i dd_oa , i dd_ob , i dd_oc , i dd_od. note: core supply voltage cannot be lo wer than the output supply voltage. note 1: total power supply current with all differential outputs ar e set to lvds output format and lvcmos clock is running at 1 25mhz. note 2: core power supply current with a ll differential outputs are set to lvpecl out put format and lvcmos clock is running at 125mhz. symbol parameter test conditions minimum typical maximum units v dd_x power supply voltage 2.97 3.3 3.63 v v dda analog supply voltage 2.97 3.3 3.63 v i dd_x power supply current; note 1 320 373 ma i dda analog supply current 43 50 ma i ee core supply current; note 2 275 326 ma symbol parameter test conditio ns minimum typical maximum units v dd_x power supply voltage 2.375 2.5 2.625 v v dda analog supply voltage 2.375 2.5 2.625 v i dd_x power supply current; note 1 310 362 ma i dda analog supply current 34 41 ma i ee core supply current; note 2 251 293 ma
revision a 3/30/15 11 i 2 c programmable ethernet clock generator 8T49N4811 data sheet table 5c. lvcmos input dc characteristics, v dd = v dd_ods = 3.3v10 % or 2.5v5 % , t a = -40c to 85c note: core supply voltage cannot be lo wer than the output supply voltage. table 5d. differential i nput dc characteristics, v dd = 3.3v10 % or 2.5v5 % , t a = -40c to 85c note: core supply voltage cannot be lo wer than the output supply voltage. note 1: v il should not be less than -0.3v. note 2: common mode input voltage is defined as the cross point. note 3: the differential inputs have internal 100 ? and biased to v dd ?1.3v approximately. symbol parameter test conditio ns minimum typical maximum units v ih input high voltage except sclk, sdata v dd = 3.3 v 10 % 2v dd + 0.3 v v dd = 2.5 v 5 % 1.7 v dd + 0.3 v v ih input high voltage sclk, sdata v dd = 3.3 v 10 % 2.4 v dd + 0.3 v v dd = 2.5 v 5 % 1.8 v dd + 0.3 v v il input low voltage v dd = 3.3 v 10 % -0.3 0.8 v v dd = 2.5 v 5 % -0.3 0.5 v i ih input high current pullup inputs v dd = v in = v dd max 5a pulldown inputs 150 a i il input low current pullup inputs v dd = v dd max , v in = 0 v -150 a pulldown inputs -5 a v oh output high voltage lv c m o s outputs v dd_ods = 3.3v 10 % ; i oh = ?12 ma 2.45 v v dd_ods = 2.5v 5 % ; i oh = ?8 ma 1.8 v v ol output low voltage lv c m o s outputs v dd_ods = 3.3v 10 % ; i ol = 12 ma 0.5 v v dd_ods = 2.5v 5 % ; i ol = 8 ma 0.5 v symbol parameter test conditio ns minimum typical maximum units v pp peak to peak input voltage; note 1 0.15 1.3 v v cmr common mode input voltage; note 1, 2 0.5 v dd - 0.85 v i ih input high current; note 3 din, ndin ndin = open, v dd = v in = v dd max 175 a din = open, v dd = v in = v dd max 175 a i il input low current; note 3 din, ndin ndin = open, v dd = v dd max , v in = 0 v -225 a din = open, v dd = v dd max , v in = 0 v -225 a
i 2 c programmable ethernet clock generator 12 revision a 3/30/15 8T49N4811 data sheet table 5e. lvpecl output dc characteristics, v dd_oa = v dd_ob = v dd_oc = v dd_od = 3.3v10 % or 2.5v5 % , t a = -40c to 85c note: v dd_ox denotes v dd_oa , v dd_ob , v dd_oc , v dd_od . note: core supply voltage cannot be lo wer than the output supply voltage. note 1: outputs terminated with 50 ? to v dd_ox - 2v. table 5f. lvds output dc characteristics, v dd_oa = v dd_ob = v dd_oc = v dd_od = 3.3v10 % or 2.5v5 % , t a = -40c to 85c note: core supply voltage cannot be lo wer than the output supply voltage. table 6. crystal characteristics symbol parameter test conditio ns minimum typical maximum units v oh output high voltage; note 1 v dd_ox ?1.1 v dd_ox ? 0.7 v v ol output low voltage; note 1 v dd_ox ?1.9 v dd_ox ? 1.6 v v swing peak to peak output voltage swing 0.6 1.0 v symbol parameter test conditio ns minimum typical maximum units v od differential output voltage 0.25 0.325 0.454 v ? v od v od magnitude change 50 mv v os offset voltage 1.125 1.375 v ? v os v os magnitude change 50 mv parameter test conditions mi nimum typical maximum units mode of oscillation fundamental frequency 25 mhz load capacitance (c l ) 12 18 pf equivalent series resistance (esr) 50 ? shunt capacitance 7pf
revision a 3/30/15 13 i 2 c programmable ethernet clock generator 8T49N4811 data sheet ac characteristics table 7. ac output characteristic. v dd = v dda = v dd_xtal = v dd_ods = v dd_oa = v dd_ob = v dd_oc = v dd_od = 3.3v10 % or 2.5v 5 % ,t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions note: v dd_ox denotes v dd_oa , v dd_ob , v dd_oc , v dd_od , v dd_ods . note: core supply voltage cannot be lo wer than the output supply voltage. note 1: qdo_s lvcmos output is set to 125mhz. note 2: in pll mode. symbol parameter test conditio ns minimum typical maximum units f out output frequency lvpecl, lvds 312.5 mhz lvcmos 125 mhz t r /t f output rise/fall time, normal mode lvpecl, lvds; 20 % - 80 % 250 400 ps lv c m o s ; 2 0 % - 80 % 150 850 ps t r /t f output rise/fall time , slow mode lv c m o s ; 2 0 % - 80 % 2ns tjit(?) phase jitter, rms; note 1 f out = 50, 100, 125, 156.25, 312.5mhz, xtal = 25mhz integration range: 10khz - 20mhz 277 fs f out = 25mhz (f in ) crystal input = 25mhz integration range: 10khz - 5mhz 413 fs f n single-side band phase noise 156.25mhz, offset 1khz -120 dbc/hz 156.25mhz, offset 10khz -130 dbc/hz 156.25mhz, offset 100khz -133 dbc/hz 156.25mhz, offset 1mhz -145 dbc/hz 156.25mhz, offset 10mhz -154 dbc/hz psnr power supply noise rejection v dd 50mvpp, 10k-1.5mhz -61 dbc v dda 50mvpp, 10k-1.5mhz -60 dbc v dd_ox 50mvpp, 10k-1.5mhz -50 dbc odc output duty cycle; note 2 lvpecl, lvds 48 52 % lvcmos 45 55 % t lock pll lock time startup (default config., power-on reset) 15 ms
i 2 c programmable ethernet clock generator 14 revision a 3/30/15 8T49N4811 data sheet typical phase noise at 15 6.25mhz (12khz - 20mhz) noise power (dbc/hz) offset frequency (hz)
revision a 3/30/15 15 i 2 c programmable ethernet clock generator 8T49N4811 data sheet parameter measureme nt information 3.3v core/3.3v lvpecl out put load test circuit 3.3v core/3.3v lvds output load test circuit pll lock time 2.5v core/2.5v lvpecl ou tput load test circuit 2.5v core/2.5v lvds output load test circuit rms phase jitter scope qx nqx gnd 2v -1.3v0.165v v dd, v dda, v dd_xtal, v dd_oa, v dd_oc, v dd_od scope qx nqx 3.3v10 % power supply +? float gnd v dd, v dda, v dd_xtal, v dd_oa, v dd_oc, v dd_od scope qx nqx gnd 2v -0.5v0.125v v dd, v dda, v dd_xtal, v dd_oa, v dd_oc, v dd_od v dd, v dda, v dd_xtal, v dd_oa, v dd_oc, v dd_od
i 2 c programmable ethernet clock generator 16 revision a 3/30/15 8T49N4811 data sheet parameter measurement in formation, continued lvcmos output rise/fall time lvds output rise/fall time lvcmos output duty cycle/output pulse width/period offset voltage setup lvpecl output rise/fall time differential input levels differential output duty cycle/output pulse width/period differential output voltage setup 20 % 80 % 80 % 20 % t r t f qd0_s 20 % 80 % 80 % 20 % t r t f v od nqxx qxx t period t pw t period odc = v ddo 2 x 100 % t pw qd0_s nqxx qxx v dd gnd din ndin nqxx qxx
revision a 3/30/15 17 i 2 c programmable ethernet clock generator 8T49N4811 data sheet applications information recommendations for unused input and output pins inputs: din/ndin input if the input buffer is not used, then connect din input to vdd and ndin input to gnd via 1k ? resistors xtal inputs for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from xtal_in to ground. lvcmos control pins some control pins have internal pullup or pulldown resistors; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvpecl outputs all unused lvpecl output pairs c an be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. lvds outputs all unused lvds output pairs can be either left floating or terminated with 100 ? across. if they are left floating there should be no trace attached. lvcmos outputs if the lvcmos output is not used, then disable the output using control pin
i 2 c programmable ethernet clock generator 18 revision a 3/30/15 8T49N4811 data sheet overdriving the xtal interface the xtal_in input can be overdriven by an lvcmos driver or by one side of a differential driver through an ac coupling capacitor. the xtal_out pin can be left floating. the amplitude of the input signal should be between 500mv and 1.8v and the slew rate should not be less than 0.2v/ns. for 3.3v lvcmos inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. figure 1a shows an example of the interface diagram for a high speed 3.3v lvcmos driver. this c onfiguration requires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and changing r2 to 50 ? . the values of the resistors can be increased to reduce the loading for a slower and weaker lvcmos driver. figure 1b shows an example of the interface diagram for an lvpecl driver. this is a standard lvpecl termination with one side of the driver feeding the xtal_in input. it is recommended that all components in the schematics be placed in the layout. though some components might not be used, they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. figure 1a. general diagram for lvcmos driver to xtal input interface figure 1b. general diagram for lvpec l driver to xtal input interface vcc xtal_out xtal_in r1 100 r2 100 zo = 50 ohms rs ro zo = ro + rs c1 .1uf lvcmos driver xta l _ o u t xta l _ i n zo = 50 ohms c2 .1uf lvpecl driver zo = 50 ohms r1 50 r2 50 r3 50
revision a 3/30/15 19 i 2 c programmable ethernet clock generator 8T49N4811 data sheet lvds driver termination for a general lvds interface, the recommended value for the termination impedance (z t ) is between 90 ? and 132 ? . the actual value should be selected to match the differential impedance (z 0 ) of your transmission line. a typical point-to-point lvds design uses a 100 ? parallel resistor at the receiver and a 100 ? differential transmission-line environment. in order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. idt offers a full line of lvds compliant devices with two types of output struct ures: current source and voltage source. the standard termination schematic as shown in figure 2a can be used with either type of output structure. figure 2b , which can also be used with both output types, is an optional termination with center tap capacitance to help filter comm on mode noise. the capacitor value should be approximately 50pf. if using a non-standard termination, it is recommended to contact idt and confirm if the out put structure is current source or voltage source type. in addition, since these outputs are lvds compatible, the input receiver?s amplitude and common-mode input range should be verified for compatibility with the output. lvds termination lvds driver lvds driver lv d s receiver lv d s receiver z t c z o ? z t z o ? z t z t 2 z t 2 figure 2a. standard termination figure 2b. optional termination
i 2 c programmable ethernet clock generator 20 revision a 3/30/15 8T49N4811 data sheet termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. the differential outputs generate ecl/lvpecl compatible outputs. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. t hese outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figure 3a and figure 3b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 3a. 3.3v lvpecl out put termination figure 3b. 3.3v lvpecl output termination r1 84 ? r2 84 ? 3.3v r3 125 ? r4 125 ? z o = 50 ? z o = 50 ? input 3.3v 3.3v + _
revision a 3/30/15 21 i 2 c programmable ethernet clock generator 8T49N4811 data sheet termination for 2.5v lvpecl outputs figure 4a and figure 4b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 ? to v ddo ? 2v. for v ddo = 2.5v, the v ddo ? 2v is very close to ground level. the r3 in figure 4b can be eliminated and the termination is shown in figure 4b. figure 4a. 2.5v lvpecl driver termination example figure 4b. 2.5v lvpecl driver termination example figure 4c. 2.5v lvpecl driver termination example 2.5v lvpecl driver v ddo = 2.5v 2.5v 2.5v 50 50 r1 250 r3 250 r2 62.5 r4 62.5 + ? 2.5v lvpecl driver v ddo = 2.5v 2.5v 50 50 r1 50 r2 50 r3 18 + ? 2.5v lvpecl driver v ddo = 2.5v 2.5v 50 50 r1 50 r2 50 + ?
i 2 c programmable ethernet clock generator 22 revision a 3/30/15 8T49N4811 data sheet schematic example figure 5 (next page) shows an example idt8T49N4811i application schematic in which the device is operated at v dd = 3.3v. this example focuses on functional connections and is not configuration specific. to illustrate t he three level input control pins to configure the output banks, qa_ctrl and qb_ctrl0 are pulled to a logic 1 to enable lvds outputs for bank a and the first half of bankb, qb_ctrl1 is a no connect to place the second half of bank b into tristate and qc_ctrl and qd_ctrl are pulled to a logic 0 for enabled lvpelc outputs. re fer to the pin description and functional tables in the datasheet to ensure that the logic control inputs are properly set for the application. the 12pf parallel resonant fox fx325bs 25mhz crystal is used with tuning capacitors c1 = c2 = 10pf recommended for frequency accuracy. crystals with other load ca pacitance specifications can be used, for example, a cl=18pf crystal can be used with two 22pf tuning capacitors. depending on the parasitics of the printed circuit board layout, the values of c1 and c2 might require a slight adjustment to optimize the frequency accuracy. for this device, the crystal tuning capacitors are required for proper operation. crystal layout is very important to minimize capacitive coupling between the crystal pads and leads and other metal in the circuit board. capacitive coupling to other conductors has two adverse effects; it reduces the oscillator frequency leaving less tuning margin and noise coupling from power planes and logic transitions on signal traces can pull the phase of the crystal resonance, inducing jitter. routing i 2 c under the crystal is a very common layout error, based on the assumption that it is a low frequency signal and will not affect the crystal oscillation. in fact, i 2 c transition times are short enough to capacitively couple into the crystal if they are routed close enough to the crystal traces. in layout, all capacitive coupling to the crystal from any signal trace is to be minimized, that is to the xtal_in and xtal_out pins, traces to the crystal pads, the crystal pads and the tuning capacitors. using a crystal on the top layer as an example, void all signal and power layers under the crystal connections between the top layer and the ground plane used by the idt8T49N4811i. then calculate the parasitic capacity to the ground and determine if it is large enough to preclude tuning the oscillator. if the coupling is excessive, particularly if the first layer under the crystal is a ground plane, a layout option is to void the ground plane and all deeper layers until the next ground plane is reached. the ground conne ction of the tuning capacitors should first be made between the capacitors on the top layer, then a single ground via is dropped to connect the tuning cap ground to the ground plane as close to the idt8T49N4811i as possible as shown in the schematic. as with any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter performance, power supply isolation is requ ired. the idt8T49N4811i provides separate power supplies to isolate any high switching noise from coupling into the internal pll. in order to achieve the best possible filtering, it is recommended that the placement of the f ilter components be on the device side of the pcb as close to the power pins as possible. if space is limited, the 0.1f capacitor in each power pin filt er should be placed on the device side. the other components can be on the opposite side of the pcb. power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. the filter performance is designed for a wide range of noise frequencies. this low-pass filter starts to atte nuate noise at approximately 10 khz. if a specific frequency noise compone nt is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. additionally, good general design practices for power plane voltage stability suggests adding bulk capacitance in the local area of all devices.
revision a 3/30/15 23 i 2 c programmable ethernet clock generator 8T49N4811 data sheet figure 5. idt8T49N4811i schematic example lvpecl termi nat ion u1 div_selc 1 in _ se l 3 din 4 ndin 5 xta l_ i n 7 xta l_ o u t 8 pl l _b y pass 9 iic_adrx_sel 10 in p ut_ d i vsel 12 div sel_d0 13 lvcmos _ctrl 14 sc l k 15 sd ata 16 reserved 17 div sel_b 18 nc 19 qd_ctrl 22 qb_ctrl1 26 sl ew _ l vc mo s 28 qb_ctrl0 43 qa_ctrl 45 div sel_a 49 qc_ctrl 50 qdo_s 20 nqd0 23 qd0 24 nqb 5 29 qb 5 30 nqb 4 31 qb 4 32 nqb 3 34 qb 3 35 nqb 2 36 qb 2 37 nqb 1 39 qb 1 40 nqb 0 41 qb 0 42 nqa 0 47 qa 0 48 nqc1 52 qc1 53 nqc0 54 qc0 55 vdd 2 vd d _ xtal 6 vd d a 11 vd d _o d s 21 vd d _ o d 25 vd d 27 vd d _o b 33 vd d _o b 38 vd d 44 vd d _o a 46 vd d _ o c 51 vd d _ o c 56 e pad 57 qb0 nqb0 nqb1 qb1 qc1 nqc1 c7 0.1uf +3.3v c8 10uf fb1 bl m1 8b b2 2 1s n 1 1 2 c10 0.1uf c1 1 0.1uf qa_ctrl +3 . 3 v c20 0.1uf c21 10uf qb_ctrl0 qd_ctrl qc_ctrl place 0.1uf bypass caps directly adjacent to the corresponding vddo_xy pin. c16 0.1uf c17 0.1uf c26 0.1uf c27 0.1uf c28 0.1uf r16 2.2 c6 10uf c13 0.1uf r17 2.2 c9 10uf c12 0.1uf vdda v d d_ xtal fb2 b lm18bb221sn1 1 2 sc l k sd ata +3 . 3v r1 4.7k r2 4.7k pll_bypass div sel_b div sel_a div sel_d0 div sel_c slew_lvcmos lvcmos_ctrl i n pu t_ di vs el i i c _a dr x_ se l to l ogic inp ut pin s vd d vdd ru2 not install ru1 1k rd2 1k to lo gic inp ut pin s rd1 not install logic cont rol input examples set logic input to '1' set logic in p u t t o '0 ' lv ds driver zo = 50 ohm zo = 50 ohm place 0.1uf bypass caps directly adjacent to the corresponding vdd, vdda or vdd_xtal pin. in_sel c2 10pf c1 10pf fox 325bs crystal xtal _ in xtal _ o u t x2 1 3 2 4 25 mhz (12pf) vd d +3.3v c29 0.1uf c30 10uf c31 0.1uf fb3 bl m1 8b b2 21 s n1 1 2 c3 2 0.1uf lvds receiv er + - zo = 50 ohm zo = 50 ohm r3 100 nqb2 lvds term inati on lvds receiver + - zo = 50 ohm nqa0 zo = 50 ohm r18 100 qb2 qa0 qc0 +3. 3 v l vpe cl r e ce iv e r + - zo = 50 ohm zo = 50 ohm nqc0 zo = 50 r22 33 lv cm o s r e c ei v e r qd o _ s r23 50 r24 50 r25 50 zo = 50 ohm zo = 50 ohm r26 100 r27 150 r28 150 +3.3v lvp ecl receiver + -
i 2 c programmable ethernet clock generator 24 revision a 3/30/15 8T49N4811 data sheet vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) wit hin the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 6. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are nece ssary to effectively conduct from the surface of the pcb to the gro und plane(s). the land pattern must be connected to ground through thes e vias. the vias act as ?heat pipes?. the number of vias (i.e. ?h eat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirement s. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended t hat the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal la nd. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance lead frame base package, amkor technology. figure 6. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
revision a 3/30/15 25 i 2 c programmable ethernet clock generator 8T49N4811 data sheet lvpecl power considerations this section provides information on power dissipati on and junction temperature for the idt8T49N4811i. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the idt8T49N4811i is the sum of the core power plus the power dissipated due to loading. the following is the power dissipation for v dd = 3.63v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated due to loading. ? power (core) max = v dd_max * i ee_max = 3.63v * 326ma = 1183.38mw note: the current includes lvcmos output r unning at 125mhz, ac-coupled and terminated. ? power (outputs) max = 31mw/loaded output pair if all outputs are loaded, t he total power is 10 * 31mw = 310mw ? dynamic power dissipation at 125mhz power (125mhz) = c pd * frequency * (v ddo ) 2 = 18.1pf * 125mhz * (3.63v) 2 = 29.81mw per output ? total power_ max (3.63v, with all outputs switching) = 1183.38w + 310mw + 29.81mw = 1523.19mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate va lue is 25.6c/w per table 8 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 1.523w * 25.6c/w = 124c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 8. thermal resistance ? ja for 56-lead vfqfn, forced convection ? ja by velocity meters per second 012 multi-layer pcb, jedec standard test boards 25.6c 19.8c 18c
i 2 c programmable ethernet clock generator 26 revision a 3/30/15 8T49N4811 data sheet 3. calculations and equations. the purpose of this section is to calculate the power dissipation fo r the lvpecl output pair. lvpecl output driver circuit and termination are shown in figure 7. figure 7. lvpecl driver circuit and termination to calculate power dissipation per output pair due to l oading, use the following equations which assume a 50 ? load, and a termination voltage of v dd ? 2v. ? for logic high, v out = v oh_max = v dd_max ? 0.7v (v dd_max ? v oh_max ) = 0.7v ? for logic low, v out = v ol_max = v dd_max ? 1.6v (v dd_max ? v ol_max ) = 1.6v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v dd_max ? 2v))/r l ] * (v dd_max ? v oh_max ) = [(2v ? (v dd_max ? v oh_max ))/r l ] * (v dd_max ? v oh_max ) = [(2v ? 0.7v)/50 ? ] * 0.7v = 18.2mw pd_l = [(v ol_max ? (v dd_max ? 2v))/r l ] * (v dd_max ? v ol_max ) = [(2v ? (v dd_max ? v ol_max ))/r l ] * (v dd_max ? v ol_max ) = [(2v ? 1.6v)/50 ? ] * 1.6v = 12.8mw total power dissipation per output pair = pd_h + pd_l = 31mw v out v dd o v dd o - 2v q1 rl
revision a 3/30/15 27 i 2 c programmable ethernet clock generator 8T49N4811 data sheet lvds power considerations this section provides information on power dissipation and juncti on temperature for the idt8t49n 4811i for all outputs that are configured to lvds. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the idt8T49N4811iis the sum of th e core power plus the power dissipated due to loading. the fol lowing is the power dissipation for v dd = 3.3v + 10 % = 3.63v, which gives worst case results. ? the maximum current at 85c is as follows: i dd_max = 373ma, i dda_max = 43ma ? dynamic power dissipation at 125mhz, (d1 lvcmos output) dynamic_power(d1) = cpd * frequency * v dd_ods 2 = 18.1pf * 125mhz * 3.63v 2 = 29.81mw ? total power_ max = (3.63v * (373ma + 43ma)) + dynamic _power(d1) = 1510.08mw + 29.81mw = 1539.89mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate va lue is 25.6c/w per table 9 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 1.540w * 25.6c/w = 124.4c. th is is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 9. thermal resistance ? ja for 56-lead vfqfn, forced convection ? ja by velocity meters per second 012 multi-layer pcb, jedec standard te st boards 25.6c/ w 19.8c/w 18c/w
i 2 c programmable ethernet clock generator 28 revision a 3/30/15 8T49N4811 data sheet reliability information table 10. ? ja vs. air flow table for a 56-lead vfqfn note: theta ja ( ? ja ) values calculated using a 4-layer jede c pcb (114.3mm x 101.6mm), with 2oz. (70 ? m) copper plating on all four layers. transistor count the transistor count for idt8T49N4811i is: 177,252 ? ja vs. air flow meters per second 012 multi-layer pcb, jedec standard te st boards 25.6c/ w 19.8c/w 18c/w
revision a 3/30/15 29 i 2 c programmable ethernet clock generator 8T49N4811 data sheet 56-lead vfqfn nl package outline
i 2 c programmable ethernet clock generator 30 revision a 3/30/15 8T49N4811 data sheet 56-lead vfqfn nl package outline, continued idt8T49N4811i uses epad option p4
revision a 3/30/15 31 i 2 c programmable ethernet clock generator 8T49N4811 data sheet 56-lead vfqfn nl package outline, continued
i 2 c programmable ethernet clock generator 32 revision a 3/30/15 8T49N4811 data sheet ordering information table 11. ordering information part/order number marking package shipping packaging temperature 8T49N4811nlgi idt8T49N4811nlgi ?lead-free? 56-lead vfqfn tray -40 ? c to +85 ? c 8T49N4811nlgi8 idt8T49N4811nlgi ?lead-fr ee? 56-lead vfqfn tape & reel -40 ? c to +85 ? c
revision a 3/30/15 33 i 2 c programmable ethernet clock generator 8T49N4811 data sheet revision history sheet rev table page description of change date a t5a & t5b 10 datasheet error updated for idda specificat ion. iee is accurate and is inclusive of idda. no changes to manufacturing test specification. updated data sheet format. 3/30/15
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