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70412 sy 20120626-s00007 no.a2083-1/13 http://onsemi.com semiconductor components industries, llc, 2013 may, 2013 LV8824QA overview the LV8824QA is a pwm pre-driver ic suitable for use in 3-phase brushless motors. this ic was designed based on the assumption that nch fets are used as the upper and lower output transistors. the rotational speed is controllable by inputting pwm pulse or dc voltage externally and changing duty. LV8824QA incorporates latch-type constraint protection circuit. features ? i o max = 50ma ? speed control and synchronous rectification by pw m direct input (3.3v input-ready) and dc voltage. ? 3-hall fg output ? latch type constraint protection circuit (latch is released by s/b and f/r.) ? forward/reverse switch circuit, hall bias pin ? power saving circuit ? current limiter circuit, low-voltage prot ection circuit, thermal shut-down circuit ? charge pump circuit (external nch/nch), 5v regulator output. ? start/brake circuit specifications absolute maximum ratings at ta = 25 c parameter symbol conditions ratings unit v cc max v cc pin 34 v supply voltage v g max v g pin 42 v output current i o max 50 ma allowable power dissipation pd max mounted on a circuit board.*1 1.45 w junction temperature tj max 150 c operating temperature topr -40 to +105 c storage temperature tstg -55 to +150 c *1 : specified circuit board : 100mm 100mm 1.6mm, glass epoxy (double-layer board) caution 1) absolute maximum ratings represent the va lue which cannot be exceeded for any length of time. caution 2) even when the device is used within the range of abso lute maximum ratings, as a result of continuous usage under hig h temperature, high current, high voltage, or drastic temperature change, the reliability of th e ic may be degraded. please contact us for the further detai ls. bi-cmos ic for brushless motor drive pwm driver ic orderin g numbe r : ena2083 stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty.
LV8824QA no.a2083-2/13 allowable operating range at ta = 25 c parameter symbol conditions ratings unit supply voltage range v cc 7.0 to 33 v 5v constant voltage output current i reg 0 to -10 ma hb pin output current i hb 0 to -200 a 3fg pin applied voltage v 3fg 0 to 6 v 3fg pin output current i 3fg 0 to 10 ma electrical characteristics at ta = 25 c, v cc = 24v ratings parameter symbol conditions min typ max unit supply current 1 i cc 1 5.0 6.0 ma supply current 2 i cc 2 power saving 0.8 0.98 ma output block (uh, vh, wh, ul, vl, wl) low-side output on resistance 1 r on (l1) low level i o = 10ma 20 30 low-side output on resistance 2 r on (l2) high level i o = -10ma 20 30 high-side output on resistance 1 r on (h1) low level i o = 10ma 25 40 high-side output on resistance 2 r on (h2) high level i o = -10ma 65 90 5v constant-voltage output output voltage vreg i o = -5ma 4.8 5.1 5.4 v line regulation v (reg1) v cc = 7.0 to 33v, i o = -5ma 50 mv load regulation v (reg2) i o = -5m to -10ma 100 mv hall amplifier input bias current ib (ha) -2 a common-mode input voltage range 1 vicm1 when using hall elements 0.3 vreg-1.7 v common-mode input voltage range 2 vicm2 at one-si de input bias (hall ic application) 0 vreg v hall input sensitivity vhin sin wave 80 mvp-p hysteresis width v in (ha) 9 20 35 mv input voltage low high vslh 3 7.5 15 mv input voltage high low vshl -19 -11 -5 mv csd oscillator circuit high level output voltage v oh (csd) 2.7 3.0 3.3 v low level output voltage v ol (csd) 0.9 1.1 1.3 v amplitude v (csd) 1.6 1.9 2.2 vp-p external capacitor charge current ichg1 (csd) vchg1 = 2.0v -14 -11.5 -9 a external capacitor discharge current ichg2 (csd) vchg2 = 2.0v 9.5 12 14.5 a oscillation frequency f (csd) c = 0.022 f (design target*) 130 hz charge pump output (vg pin) output voltage vgout v cc +6.5 v cc +7.0 v cp1 pin output on resistance (high level) v oh (cp1) icp1 = -2ma 350 500 output on resistance (low level) v ol (cp1) icp1 = 2ma 200 280 charge pump frequency f (cp) 82 103 124 khz internal pwm frequency oscillation frequency f (pwm) 41 51.5 62 khz current limiter operation limiter voltage vrf 0.18 0.20 0.22 v * : design target value and no measurement is made. continued on next page.
LV8824QA no.a2083-3/13 continued from preceding page. ratings parameter symbol conditions min typ max unit pwm oscillator output high level voltage v o h(pwm) 2.8 3.05 3.3 v output low level voltage v o l(pwm) 0.85 1.0 1.15 v amplitude v(pwm) 1.7 2.0 2.3 vp-p external c charge current i chg 1(pwm) v chg 1 = 2.0v -135 -110 -85 a external c discharge current i chg 2(pwm) v chg 2 = 2.0v 1.4 1.8 2.2 ma oscillation frequency f(pwm) c = 2200pf (design target*) 25 khz ctl input voltage input voltage 1 v ctl 1 output duty 100% 2.79 3.1 3.4 v input voltage 2 v ctl 2 output duty 0% 0.84 1.05 1.3 v thermal shutdown operation operation temperature tsd design target* (junction temperature) 150 170 c hysteresis width tsd design target* (junction temperature) 30 c hb pin output voltage vhb ihb = -100 a 3.6 3.8 4.0 v low-voltage protection (5v constant voltage output detection) operation voltage vsd 3.95 4.15 4.35 v hysteresis width vsd 0.2 0.3 0.4 v 3fg pin output on resistance v o l (3fg) i3fg = 5ma 30 45 output leakage current il (3fg) v o = 6v 10 a stime pin input threshold voltage 1 v i 1(time) 0 1.0 v input threshold voltage 2 v i 2(time) 1.5 2.25 v input threshold voltage 3 v i 3(time) 2.8 3.5 v input threshold voltage 4 v i 4(time) 4.2 vreg v mode pin input threshold voltage 1 v i 1(mode) 0 1.0 v input threshold voltage 2 v i 2(mode) 1.5 2.25 v input threshold voltage 3 v i 3(mode) 2.8 3.5 v input threshold voltage 4 v i 4(mode) 4.2 vreg v s/b pin high level input voltage v ih (sb) 2.0 vreg v low level input voltage v il (sb) 0 1.0 v input open voltage v io (sb) vreg-2.2 vreg-2.0 vreg-1.8 v hysteresis width v is (sb) 0.25 0.33 0.4 v high level input current i ih (sb) v sb = vreg 45 65 85 a low level input current i il (sb) v sb = 0v -125 -95 -65 a pwmin pin recommended input frequency f (pwin) 0.5 60 khz high level input voltage v ih (pwin) 2.0 vreg v low level input voltage v il (pwin) 0 1.0 v input open voltage v io (pwin) vreg-2.2 vreg-2.0 vreg-1.8 v hysteresis width v is (pwin) 0.25 0.33 0.4 v high level input current i ih (pwin) vpwin = vreg 45 65 85 a low level input current i il (pwin) vpwin = 0v -125 -95 -65 a f/r pin high level input voltage v ih (fr) *design target value 2.0 vreg v low level input voltage v il (fr) *design target value 0 1.0 v input open voltage v io (fr) vreg-2.2 vreg-2.0 vreg-1.8 v hysteresis width v is (fr) *design target value 0.25 0.33 0.4 v high level input current i ih (fr) vf/r = vreg 45 65 85 a low level input current i il (fr) vf/r = 0v -125 -95 -65 a
LV8824QA no.a2083-4/13 package dimensions unit : mm (typ) 3436 pin assignment sanyo : vqfn32u(5.0x5.0) 5.0 5.0 side view top view side view bottom view (3.5) (3.5) 0.4 32 0.8 max 0.035 0.25 1 2 (0.75) 0.5 12 1 in3 - 2 in3 + 3 in2 - 4 in2 + 5 in1 - 6 in1 + 22 stime 21 rf 20 ctl 19 pwmin 18 wout 17 vg 31 hb 30 pwm 29 csd 28 f/r 27 3fg 25 s/b 7 sgnd 8 vreg 9 cp2 10 cp1 11 v cc 12 wh 13 14 15 16 23 24 26 32 vout wl vh vl uh uout ul mode pd max ? ta 0 0.52 1.45 1 1.5 0.5 2 --40 --20 80 60 20 40 0120 100 ambient temperature, ta -- c allowable power dissipation, pd max -- w specified board : 100 100 1.6mm 3 glass epoxy(two-layer board)
LV8824QA no.a2083-5/13 three-phase hall logi c truth table (in = ?high? means the following state: in+ > in-.) ("upper gate = vh" and "lower gate = ul" mean the following state: the upper fet connected to vh pin is on and the lower fet connected to ul pin operates by pwm signal.) f/r = high f/r = low driving output in1 in2 in3 in1 in 2 in3 upper gate lower gate (pwm) h l h l h l vh ul h l l l h h wh ul h h l l l h wh vl l h l h l h uh vl l h h h l l uh wl l l h h h l vh wl 3fg output in1 in2 in3 3fg h l h l h l l h h h l l l h l h l h h l l l h h s/b pin, pwmin pin input state s/b pin pwmin pin high or open stop (short brake) output off low start output on internal equivalent circuit and sa mple external component circuit csd osc csd control logic mosc lda 3fg fg hall hys amp 3fg ctl ctl pwmin pwmin start/ brake s/b + hb pre driver hb in3 - in3 + in2 - in2 + in1 - in1 + v cc mode v cc rf curr lim lvsd 5vreg mode select a/d(2bit) vreg vreg gnd sync time a/d (2bit) f/r pwm f/r vreg charge pump vg cp2 cp1 uh uout ul vh vout vl wh wout wl gnd vm pwm stime 3fg output f/r input ctl input pwmin input s/b input
LV8824QA no.a2083-6/13 pin functions pin no. pin name pin function equivalent circuit 1 hb hall bias pin (3.8vtyp output). connect npn transistor. (see p.11?9.hall input signal?.) during power saving mode, output is turned off (0v). hb pin enable to reduce power consumption of hall element to 0v during power saving mode. vreg 1 2 3 4 5 6 7 in3 - in3 + in2 - in2 + in1 - in1 + hall input pin. where in + > in - , voltage level becomes high. where in + < in - , voltage level becomes low. desirably, the amplitude of hall signal is 100mvp-p (differential) or higher. if the noise of hall signal is an issue, connect a capacitor between in + and in - . vreg 5 7 3 6 4 2 8 sgnd ground pin for control circuitry. 9 pwm triangular wave oscillation pin for pwm signal generation. connect a capacitor between this pin and gnd. (see p.9 ?4. pwm oscillation frequency.?) vreg 9 10 csd timing setting pin for constraint protection detection as well as setting pin for initial reset pulse. connect a capacitor between this pin and gnd. when protection circuitry is not used, connect a resistor of 220k ? and capacitor of 4700pf in parallel against gnd. (see p.10 ?5. constraint protection circuit?) vreg 10 11 vreg 5v regulator output pin (power supply for control circuitry). desirably, connect a capacitor of 0.1f between this pin and gnd for stabilization. (see p.10 ?8. vreg stabilization? and p.12 ?15. low voltage protection circuit?) v cc 11 continued on next page.
LV8824QA no.a2083-7/13 continued from preceding page. pin no. pin name pin function equivalent circuit 12 13 cp2 cp1 capacitor connect pin for charge pump. connect a capacitor between cp1 and cp2. 14 v cc supply pin for control. connect a capacitor between this pin and gnd to reject noise. (see p.12 ?14. supply stabilization?) 15 vg charge pump output pin. (power supply for upper fet gate.) connect a capacitor between this pin and v cc . (see p.10 ?7. charge pump circuit?) v cc 13 14 cp cg 15 12 16 19 22 wh vh uh high side output pin. (output pin for gate driver of upper side nch power fet.) (see p.9 ?1. output driving circuit.?) 17 20 23 wout vout uout voltage detection pin. (source voltage detection pin of upper side nch power fet.?) (see p.9 ?1. output driving circuit.?) v g 22 19 16 23 20 17 18 21 24 wl vl ul low side output pin. (output pin for gate driver of lower side nch power fet.) vreg 24 21 18 25 rf output current detection pin. connect a detection resistor (r f ) between this pin and gnd. current limit value is obtained as follow: i = vrf / r f (vref = 0.2vtyp). (see p.9 ?2. current limiter circuit?) vreg 25 26 s/b start/brake selector pin. ?high or open?: short brake. ?low?: start (see p.12 ?13. power saving circuit?) 28 f/r selects forward/reverse rotation. voltage level becomes high when this pin is open. 29 pwmin pwm direct input pin. output is controllable by the duty of the input pulse. when using pwmin pin, make sure that ctl pin is set to high level voltage. (see p.9 ?3. speed control method?) vreg 26 28 29 27 3fg 3 hall fg signal output pin. open drain output. vreg 27 continued on next page.
LV8824QA no.a2083-8/13 continued from preceding page. pin no. pin name pin function equivalent circuit 30 ctl control input pin. output on-duty is controllable using the comparison result of ctl pin voltage and pwm oscillation waveform. to use ctl pin, set pwmin pin to low level voltage. (see p.9 ?3. speed control method?) vreg 30 31 stime dead-time setting pin for synchronous rectification. depends on input voltage to stime pin, 4 types of mode are selectable. (see p.10 ?6. how to set stime?) 32 mode operation mode setting pin. depends on input voltage to mode pin, 4 types of mode are selectable. (see p.11 ?10. mode pin?) vreg 31 32
LV8824QA no.a2083-9/13 overview of LV8824QA 1. output driving circuit LV8824QA is designed to use nch fets for upper and lower output. it adopts direct pwm driving method to reduce the power loss during output. you can adjust motor torque by changing the duty cycle of the output of lower fet. make sure to connect capacitor at the proximity of eac h 3-phase output fet to prevent high frequency oscillation caused by leading pattern layout around the board (approx. 0.1 f between supply and rf). if the on speed of fet is too fast, penetration current may flow. in this case, insert serial resistors to a gate to control speed. on the other hand, if excessively high resistor is inserted to the gate, the waveform of the gate can be distorted and when the duty cycle of pwm is low, gate voltage becomes insufficient and lower side fet may be damaged or destroyed by heat generation. or even without resistance, the same phenomenon as what happens with high gate capacitor for fet could occur. in this case, make sure to take aso of the switching elemen t into consideration and limit the usage lowest duty. depends on types of fet, penetration current may flow when the duty cycle of pwm is low. as a countermeasure, you can insert capacitor between the gate and the source of the upper fet. however, caution is required since excessively high capacitor value slows down the speed of switching which may cause heat generation in the upper fet. 2. current limiter circuit the peak current of current limiter circuit is limite d by the current determined as follows. i = vrf/r f (v rf = 0.2v (typical), r f : current detection resistance). current is limited as th e duty cycle of output of ul, vl and wl lowers. the operation of current limiter circuit is delayed approximately for 1.5 s to avoid operation error of current limiter when it mistakenly detects reverse current of diode driven by pwm. however, if the coil re sistance or inductance of motor is too small, such delay may opera te current limiter at higher current th an the setting value because the current charge when starting up motor rotation is too fast (without back emf of the motor). hence, make sure to set current limiter value taking such increase of curr ent caused by delay into consideration. if noise leads to error operation, make sure to insert a filter. *pwm frequency of current limiter circuit. the pwm frequency of current limiter circuit is determined by the internal reference oscillator which is approx 50khz . 3. speed control method the speed control input of lv8824 supports digital and analog input. (1) digital input you can control output by the duty obtained as a result of inputting pulse to pwmin pin. pwmin pin: low level input voltage pwm side (lower side) output on high level input voltage pwm side (lower side) output off if you need to perform input with logic inversion, add external tr (npn). if the input of pwmin pin is at high level for a certain period (approx. 2.5ms), it is judged to be duty = 0%. when power saving mode is selected, hb pin output is set to low level. *to use pwmin pin, make sure to set ctl input to high level voltage. (2) analog input based on the comparison between ctl pin voltage and pwm oscillation waveform, you can control the duty cycle of output. by adjusting the ctl pin voltage approximately between 1v and 3v, on time of duty cycle is controllable from 0% to 100%. when ctl pin voltage < 1.05v (typ) is observed for approximately 2.5ms, the duty is judged to be 0%. if power saving mode is selected, hb pin output turns low level. *to use ctl pin, make sure to set pwmin input to low level voltage. 4. pwm oscillation frequency pwm oscillation frequency is configurable by the capacitance (c pwm ) connected to pwm pin. pwm oscillation frequency (khz) 48 -10.2*c pwm (nf) when the capacitor of 2.2nf is connected, pwd oscillation frequency is approximately 25khz.
LV8824QA no.a2083-10/13 5. constraint protection circuit lv8824 includes a constraint protection circuit to protect the ic and the motor that are under motor constraint mode. this circuit operates when the motor is under operation and the hall signal does not switch over a certain period of time. note that while this constraint protection circuit is under op eration, lower side output transistor is off. also during power saving mode, hb pin output is off. (see p.15 ?10. mode pin? and p.16 ?12. hb pin? for further details.) time is set by the value of capacitor connected the csd pin. set time (s) 90 c ( f) when the capacitor of 0.022 f is connected, the protectio n time becomes approximately 2.0 seconds. the set time should allow margin taking motor startup time into consideration. conditions for releasing constraint protection st ate conditions for restarting motor rotation s/b pin: h input (during power saving mode*1) s/b pin: l input *2 s/b pin: h input (during fg out put mode *1) s/b pin: l input f/r pin: input h/l switch (immediately after releasing constraint protection) after duty = 0% is detected from pwm input and duty up is detected. (immediately after rel easing constraint protection) low voltage protection circuit is in operation. after the recovery from low voltage state *2 *1 see p.15?10. mode pin? *2 since this is an initial reset state, after satisfying the conditions for restarting motor operation where csd pin voltage reaches to the defined voltage level, the motor starts up once again. the time for restart is approximately 1.0ms if the capacitor of 0.022f is connected to csd pin. if thermal shutdown is running under the constraint protect ion, even after the temperat ure decreases, the constraint protection state continues. csd pin also functions as initial reset generation pin. if it is connected to gnd, the logic circuit will go into a reset state and speed control cannot be performed. therefore, when you do not use constraint protection, connect a resistor of approximately 220k and a capacitor of approximately 4700pf in parallel to gnd. 6. how to set stime stime pin sets dead-time for synchronous rectification. this ic has the time for preventing ?shoot-through current? when it makes synchronous rectification. 4 types of dead-time are configurable accord ing to the input voltage to stime pin. stime pin input voltage dead-time z 0v to 1.0v approx. 2.0s z 1.5v to 2.25v approx. 1.5s z 2.8v to 3.5v approx. 1.0s z 4.2v to (vreg)v approx. 0.5s 7. charge pump circuit charge pump circuit boosts the voltage to generate gate voltage in the upper-side output fet. the capacitor cp connected between cp1 pin and cp2 boos ts the voltage which is stored in the capacitor cg between vg pin and v cc pin. the relation of cp and cg capacitance should be as follows: cg 4 cp the charge and discharge to cp capacitor is performed in the cycle of 100khz. the greater the cp capacitor is, the higher the current capability of vg supply become. however, if the capacitance is too large, the charge and discharge operation becomes insufficient. likewise, the larger the cg capacitor is, the more stable vg voltage becomes. however, if the capacitance is too large, generation time of vg voltage becomes longer at power supply. hence, caution is required for setting capacitance. the desirable capacitances of cp and cg are follows. cp = 0.1 f cg = 0.47 f 8. vreg stabilization make sure to connect capacitor of 0.1 f higher to stabilize vreg voltage which is used as supply voltage to control circuit. in the layout, gnd of the capacitor should be as close as possible to the gnd pin of the ic.
LV8824QA no.a2083-11/13 9. hall input signal the amplitude of hall input should be higher than the hysteresis width (35mv max). the amplitude should be 100mvp-p or higher to take the influence of noise and phase gap into consideration. if output wave form is distorted by noise when switching from one phase to another, make sure to insert capacitor between hall inputs. in constraint protection circuit, hall input is used as judgment signal. although the circuit ignores noise to a certain level, caution is still required. if all 3 phases of hall input signal turn to the same input state (hhh or lll), all of the outputs are turned off. if you use hall ic, by fixing one input side (either + or -) to the voltage within the range of common-mode input (0.3v to vreg-1.7v), the othe r input side accepts input from 0v to vreg. connection of hall elements connection (1) (where three hall elements in serial connection) merit ? compared to parallel connection, current consumption is less because serial connection enables sharing current among 3 hall elements. ? current limiter resistance is reducible. ? amplitude variation caused by temperature is less. demerit ? amplitude may not be sufficient because each hall element is powered with 1v only. ? current may fluctuate de pends on temperature. ? hall amplitude tends to be affected by the fluctuation of hall elements (especially for input resistor). connection (2) (three hall elements in parallel connection) merit ? the current for hall elements is adjustable with current limiter resistance. ? amplitude is sufficient because supply voltage to hall elements is adjustable. demerit ? current consumption is large because each hall element requires current independently. ? requires resistor for current limiter. ? amplitude may fluctuate depends on temperature. 10. mode pin mode pin allows selecting functions of the ic. mode pin sets 4 functions based on input voltage. mode pin input voltage mode z 0v to 1.0v mode b & power saving mode z 1.5v to 2.25v mode b & fg output mode z 2.8v to 3.5v mode a & fg output mode z 4.2v to (vreg)v mode a & power saving mode mode a (suitable for fan) mode b (suitable for office equipments) when duty cycle = 0% is detected synchronous rectifier off (free operation) short brake when frequency of pwm input is low (approx. 7.5khz or lower) synchronous rectifier off synchronous rectifier on when the duty cycle of pwm input is low (ex. frequency: 20khz, duty cycle: 3% or lower) synchronous rectifier off synchronous rectifier on reverse current detection function yes (during detection, synchronous rectifier is off) no power saving mode: when s/b pin = brake, power saving mode is set. when duty = 0% is detected as well as when constraint protection circuit is in operation, hb pin output is turned off. (see ?12. hb pin? and ?13. power saving circuit? for further details.) dg output is always feasible since fg output mode: power saving mode and hb pin output off are not set. v cc hb 3v constant-voltage output v cc hb 3v constant-voltage output (1) (2)
LV8824QA no.a2083-12/13 11. how to see stime pin and mode pin the input voltage of stime pin and mode pin are configurable by the following methods. z 0v to 1.0v short-circuit the pins to gnd z 1.5v to 2.25v connect the resistors of 33k ? and 22k ? between vreg and gnd in series. z 2.8v to 3.5v connect the resistors of 33k ? and 22k ? between vreg and gnd in series. z 4.2v to (vreg)v leave the pins open or short-circuit vreg. 12. hb pin *when power saving mode is selected. hb pin is used to reduce current to hall elements during standby mode (for power saving). after the motor operation is stopped, hb pin output is turned off in the following states: ? when s/b is in brake mode. ? when duties of the input of pwmin and ctl pin voltage are 0%. ? when constraint protection circuit is under operation. 13. power saving circuit (start/brake circuit) *when power saving mode is selected. in brake state, after the motor is stopped, majority of the circuits are stopped to reduce current consumption. by using hb pin, current consumption during power saving is less than 1ma. also, the output is fixed to short-brake state (lower-side is shorted). even in the power saving state, 5v regulator voltage is output. 14. supply stabilization the supply line of lv8824 is unstable because it adopts switching driving method. hence, you need to connect sufficient capacitor between v cc and gnd to stabilize power supply (el ectrolysis capacitor). if such capacitor (electrolytic capacitor) cannot be connect ed at the proximity of the pin, make sure to insert a ceramic capacitor of approx. 0.1f by the pin. if you insert diode to supply line to prevent reverse connection, make sure to select a larger capacitor. 15. low voltage protection circuit this ic incorporates comparator which uses band gap voltage as reference. where s/b pin is at low voltage level, vreg pin voltage (5v) is monitored and when this voltage decreases to 4.15v or lower (typ), protection circuit operates. in this case, output transistor of each phase is fixed to the following stat es according to the input voltage of mode pin and s/b pin. mode pin input voltage s/b pin input voltage source side sink side 0v to 2.25v l/h all off all on h all off all on 2.8v to (vreg)v l all off all off 16. thermal shutdown circuit when the junction temperature of the ic exceeds 170c (des ign target), thermal shutdown circuit operates and all the output transistors are turned off. when the temperature decreases by 30c (design target), each output transistor returns to operation state. however, the thermal shutdown operates when a junctio n temperature exceeds the ratings and th is does not protect an application against breakdown. 17. exposed die pad the exposed die pad should be gnd or open. 18. cautions for usage this ic operates at synchronous rectification for high efficiency. the synchronous rectification is effective for reducing heat generation and improving effi ciency because it reduces the loss of output transistor. however, synchronous rectification may increase supply voltage depends on usage conditions. ? if output duty decreases drastically. ? if pwm input frequency is low, etc. to prevent the voltage to exceed the maximum ratings as a result of increased supply voltage, following measures are highly recommended. ? select an optimum capacitor be tween power supply and gnd. ? insert a zener diode between power supply and gnd.
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