revision history 1gb auto-as4c128m8d3 - 78 ball fbga package date revision details rev 1.0 preliminary datasheet d? 201 ? alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 alliance memory inc. reserves the right to change products or specification without notice confidential -1- rev.1.0 may 2015 1gb auto-as4c128m8d3
features jedec standard compliant power supplies: v dd & v ddq = +1.5 v 0.075 v op erating temperature : -40c~1 05c (tc) aec - q100 compliant supports jedec clock jitter specification f ully synchronous operation fast clock rate: 667/800 mhz differential clock, ck & ck # bidirectional di f ferential data str obe - dq s & dqs # 8 internal ba n ks for concurrent operation 8n- bit prefetch architecture pipelined internal architecture precharge & active power down programmable mode & extended mode registers a dditive l atency (al) : 0, cl - 1, cl -2 programmable b urst lengths: 4 , 8 burst type: sequential / interleave output driver impedance co ntrol 8192 refresh cycles / 64ms - average refresh period 7.8? @ -40 c Qc Q+85c 3.9? @ +85c tc Q +105c write leveling zq calibration dynamic odt (rtt_nom & rtt_wr) rohs compliant auto refresh and self refresh 78- ball 8 x 1 0. 5 x 1.2mm fbga p ackage - pb and halogen free confidential -2- rev.1.0 may 2015 1gb auto-as4c128m8d3
overview the 1 gb double - data - rate -3 drams is double data rate architecture to achieve high - speed operation. it is internally configured as an eight bank dram. the 1 gb chip is organized as 16 mbit x 8 i/os x 8 bank devices. these synchronous devices ach ieve high speed double - data - rate transfer rates of up to 1 600 mb/sec/pin for general applications. the chip is designed to comply with all key ddr3 dram key features and all of the control and address inputs are synchronized with a pair of externally suppl ied differential clocks. inputs are latched at the cross point of differential clocks (ck rising and ck# falling). all i/os are synchronized with differential dqs pair in a source synchronous fashion. these devices operate with a single 1.5v 0.075v power supply and are available in bga packages. table . speed grade information 6 s h h g * u d g h clock frequency cas latency t rcd (ns) t rp (ns) ' ' 53 16 8 0 + ] 13.75 13.75 table . ordering information part number 2 u j 7 h p s h u d w x u h package $ 6 & |