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? semiconductor components industries, llc, 2017 february, 2017 ? rev. 1 1 publication order number: ncv7344/d ncv7344 high speed low power can, can fd transceiver description the ncv7344 can transceiver is the interface between a controller area network (can) protocol controller and the physical bus. the transceiver provides differential transmit capability to the bus and differential receive capability to the can controller. the ncv7344 is an addition to the can high ? speed transceiver family complementing ncv734x can stand ? alone transceivers and previous generations such as amis42665, amis3066x, etc. the ncv7344 guarantees additional timing parameters to ensure robust communication at data rates beyond 1 mbps to cope with can flexible data rate requirements (can fd). these features make the ncv7344 an excellent choice for all types of hs ? can networks, in nodes that require a low ? power mode with wake ? up capability via the can bus. features ? compatible with iso 11898 ? 2:2016 ? specification for loop delay symmetry up to 5 mbps ? v io pin on ncv7344 ? 3 version allowing direct interfacing with 3 v to 5 v microcontrollers ? very low current standby mode with wake ? up via the bus ? low electromagnetic emission (eme) and high electromagnetic immunity ? very low eme without common ? mode (cm) choke ? no disturbance of the bus lines with an un ? powered node ? transmit data (txd) dominant timeout function ? under all supply conditions the chip behaves predictably ? very high esd robustness of bus pins, >8 kv system esd pulses ? thermal protection ? bus pins short circuit proof to supply voltage and ground ? bus pins protected against transients in an automotive environment ? these are pb ? free devices quality ? wettable flank package for enhanced optical inspection ? ncv prefix for automotive and other applications requiring unique site and control change requirements; aec ? q100 qualified and ppap capable typical applications ? automotive ? industrial networks www. onsemi.com see detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. ordering information pin assignment marking diagram soic ? 8 d suffix case 751az nv7344 ? x = specific device code x = 0 or 3 a = assembly location l = wafer lot y = year w = work week = pb ? free package nv7344 ? x alyw 1 ncv7344mwx (top view) (note: microdot may be in either location) 1 dfn8 mw suffix case 506bw 1 nv7344 ? x alyw 1 ncv7344d1x (top view) stb canh canl txd gnd rxd nc ( ? 0) v io ( ? 3) v cc txd gnd rxd v cc stb canh canl nc ( ? 0) v io ( ? 3) ep flag
ncv7344 www. onsemi.com 2 block diagram mode & wake ? up control wake ? up filter ncv7344 ? 0 stb gnd rxd v cc 2 3 7 6 comp comp timer txd 1 driver control thermal shutdown v cc 8 4 v cc canh canl 5 nc figure 1. ncv7344 ? 0 block diagram mode & wake ? up control wake ? up filter ncv7344 ? 3 stb gnd rxd v cc 2 3 7 6 comp comp timer txd 1 driver control thermal shutdown v io 8 4 v io canh canl 5 v io figure 2. ncv7344 ? 3 block diagram
ncv7344 www. onsemi.com 3 typical application v cc micro ? controller nc vbat gnd 2 5 canh canl 3 6 7 can bus 5v ? reg r lt =60 r lt =60 gnd stb rxd txd 1 4 8 in out v cc ncv7344 figure 3. application diagram ncv7344 ? 0 5v ? reg v cc micro ? controller v io vbat gnd 2 5 canh canl 3 6 7 can bus 3v ? reg r lt =60 r lt =60 gnd stb rxd txd 1 4 8 ncv7344 ? 3 in out in out figure 4. application diagram ncv7344 ? 3 table 1. pin function description pin name description 1 txd transmit data input; low input dominant driver; internal pull ? up current 2 gnd ground 3 v cc supply voltage 4 rxd receive data output; dominant transmitter low output 5 5 nc v io not connected. on ncv7344 ? 0 only digital input / output pins and other functions supply voltage. on ncv7344 ? 3 only 6 canl low ? level can bus line (low in dominant mode) 7 canh high ? level can bus line (high in dominant mode) 8 stb standby mode control input; internal pull ? up current
ncv7344 www. onsemi.com 4 functional description operating modes ncv7344 provides two modes of operation as illustrated in table 2. these modes are selectable through pin stb. table 2. operating modes pin stb mode pin rxd low normal low when bus dominant high when bus recessive high standby follows the bus when wake ? up detected high when no wake ? up re- quest detected normal mode in the normal mode, the transceiver is able to communicate via the bus lines. the signals are transmitted and received to the can controller via the pins txd and rxd. the slopes on the bus lines outputs are optimized to give low eme. standby mode in standby mode both the transmitter and receiver are disabled and a very low ? power differential receiver monitors the bus lines for can bus activity. the bus lines are biased to ground and supply current is reduced to a minimum, typically 10 a. when a wake ? up request is detected by the low ? power differential receiver, the signal is first filtered and then verified as a valid wake signal after a time period of t wake_filt , the rxd pin is driven low by the transceiver (following the bus) to inform the controller of the wake ? up request. wake ? up when a valid wake ? up pattern (phase in order dominant ? recessive ? dominant) is detected during the standby mode the rxd pin follows the bus. minimum length of each phase is t wake_filt ? see figure 5. pattern must be received within t wake_to to be recognized as valid wake ? up otherwise internal logic is reset. canh canl rxdc t wake_filt t wake_filt ncv7344 www. onsemi.com 5 electrical characteristics definitions all voltages are referenced to gnd (pin 2). positive currents flow into the ic. sinking current means the current is flowing into the pin; sourcing current means the current is flowing out of the pin. absolute maximum ratings table 3. absolute maximum ratings symbol parameter conditions min max unit v sup supply voltage v cc , v io ? 0.3 +6 v v canh dc voltage at pin canh 0 < v cc < 5.25 v; no time limit ? 42 +42 v v canl dc voltage at pin canl 0 < v cc < 5.25 v; no time limit ? 42 +42 v v canh ? canl dc voltage between canh and canl ? 42 +42 v v i/o dc voltage at pin txd, rxd, stb ? 0.3 +6 v v esdhbm electrostatic discharge voltage at all pins, component hbm (note 1) ? 8 +8 kv v esdcdm electrostatic discharge voltage at all pins, component cdm (note 2) ? 750 +750 v v esdiec electrostatic discharge voltage at pins canh and canl, system hbm (note 4) (note 3) ? 8 +8 kv v schaff voltage transients, pins canh, canl. according to iso7637 ? 3, class c (note 4) test pulses 1 ? 100 v test pulses 2a +75 v test pulses 3a ? 150 v test pulses 3b +100 v latch ? up static latch ? up at all pins (note 5) 150 ma t stg storage temperature ? 55 +150 c t j maximum junction temperature ? 40 +170 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. standardized human body model electrostatic discharge (esd) pulses in accordance to eia ? jesd22. equivalent to discharging a 100 pf capacitor through a 1.5 k resistor. 2. standardized charged device model esd pulses when tested according to aec ? q100 ? 011 3. system human body model electrostatic discharge (esd) pulses in accordance to iec 61000 ? 4 ? 2. equivalent to discharging a 150 pf capacitor through a 330 resistor referenced to gnd. 4. results were verified by external test house. 5. static latch ? up immunity: static latch ? up protection level when tested according to eia/jesd78. table 4. thermal characteristics parameter symbol value unit thermal characteristics, soic ? 8 (note 6) thermal resistance junction ? to ? air, free air, 1s0p pcb (note 7) thermal resistance junction ? to ? air, free air, 2s2p pcb (note 8) r ja r ja 131 81 c/w c/w thermal characteristics, dfn8 (note 6) thermal resistance junction ? to ? air, free air, 1s0p pcb (note 7) thermal resistance junction ? to ? air, free air, 2s2p pcb (note 8) r ja r ja 125 58 c/w c/w 6. refer to electrical characteristics, recommended operating ranges and/or application information for safe operating parameters. 7. values based on test board according to eia/jedec standard jesd51 ? 3, signal layer with 10% trace coverage. 8. values based on test board according to eia/jedec standard jesd51 ? 7, signal layers with 10% trace coverage.
ncv7344 www. onsemi.com 6 electrical characteristics table 5. electrical characteristics v cc = 4.75 v to 5.25 v; v io = 2.8 to 5.25 v; t j = ? 40 to +150 c; r lt = 60 , c lt = 100 pf, c 1 not used unless specified otherwise. symbol parameter conditions min typ max unit supply (pin v cc ) v cc power supply voltage (note 9) 4.75 5 5.25 v i cc supply current dominant; v txd = low 20 45 70 ma recessive; v txd = high 2 5 10 ma i ccs supply current in standby mode t j 100 c, (note 10) ? 10 15 a v uvd(vcc)(stby) standby undervoltage detection v cc pin 3.5 4 4.3 v v uvd(vcc)(swoff) switch ? off undervoltage detection v cc pin 2.0 2.3 2.6 v v io supply voltage (pin v io ) only for ncv7344 ? 3 version v io supply voltage on pin v io 2.8 ? 5.5 v i ios supply current on pin v io in standby mode t j 100 c, (note 10) ? ? 11 a i ccs supply current on pin v cc in standby mode t j 100 c, (note 10) ? 0 4.0 a i ionm supply current on pin v io during normal mode dominant; v txd = low 0.45 0.65 0.9 ma recessive; v txd = low 0.32 0.43 0.58 v uvdvio undervoltage detection voltage on v io pin 2.0 2.3 2.6 v transmitter data input (pin txd) v ih high ? level input voltage output recessive 2.0 ? ? v v il low ? level input voltage output dominant ? ? 0.8 v i ih high ? level input current v txd = v cc /v io ? 5 0 +5 a i il low ? level input current v txd = 0 v ? 300 ? 150 ? 75 a c i input capacitance (note 10) ? 5 10 pf transmitter mode select (pin stb) v ih high ? level input voltage standby mode 2.0 ? ? v v il low ? level input voltage normal mode ? ? 0.8 v i ih high ? level input current v stb = v cc /v io ? 1 0 +1 a i il low ? level input current v stb = 0 v ? 15 ? ? 1 a c i input capacitance (note 10) ? 5 10 pf receiver data output (pin rxd) i oh high ? level output current normal mode v rxd = v cc /v io ? 0.4 v ? 8 ? 3 ? 1 ma i ol low ? level output current v rxd = 0.4 v 1 6 12 ma bus lines (pins canh and canl) i o(rec) recessive output current at pins canh and canl ? 27 v < v canh , v canl < +32 v; normal mode ? 5 ? +5 ma i li input leakage current 0 < r(v cc to gnd) < 1 m v canl = v canh = 5 v ? 5 0 +5 a v o(rec) (canh) recessive output voltage at pin canh normal mode, v txd = high 2.0 2.5 3.0 v v o(rec) (canl) recessive output voltage at pin canl normal mode, v txd = high 2.0 2.5 3.0 v v o(off) (canh) recessive output voltage at pin canh standby mode ? 0.1 0 0.1 v v o(off) (canl) recessive output voltage at pin canl standby mode ? 0.1 0 0.1 v v o(off (diff) differential bus output voltage (v canh ? v canl ) standby mode ? 0.2 0 0.2 v v o(dom) (canh) dominant output voltage at pin canh v txd = 0 v; t < t dom(txd); 50 < r lt < 65 2.75 3.5 4.5 v v o(dom) (canl) dominant output voltage at pin canl v txd = 0 v; t < t dom(txd); 50 < r lt < 65 0.5 1.5 2.25 v v o(dom) (diff) differential bus output voltage (v canh ? v canl ) v txd = 0 v; dominant; 45 < r lt < 65 1.5 2.25 3.0 v 9. in the range of 4.5 v to 4.75v and from 5.25 v to 5.5 v the chip is fully functional; some parameters may be outside of the s pecification. 10. values based on design and characterization, not tested in production
ncv7344 www. onsemi.com 7 table 5. electrical characteristics v cc = 4.75 v to 5.25 v; v io = 2.8 to 5.25 v; t j = ? 40 to +150 c; r lt = 60 , c lt = 100 pf, c 1 not used unless specified otherwise. symbol unit max typ min conditions parameter bus lines (pins canh and canl) v o(dom) (diff)_arb differential bus output voltage during arbitration (v canh + v canl ) r lt = 2.24 k (note 10) 1.5 ? 5.0 v v o(rec) (diff) differential bus output voltage (v canh ? v canl ) v txd = high; recessive; no load ? 50 0 +50 mv v o(dom) (sym) dominant output voltage driver symmetry (v canh + v canl ) r lt = 60 ; c 1 = 4.7 nf; txd = square wave up to 1 mhz 0.9 1.0 1.1 v cc i o(sc) (canh) short circuit output current at pin canh v canh = ? 3 v; v txd = low ? 3 v < v canh < +18 v ? 100 ? 115 ? 70 ? 40 115 ma i o(sc) (canl) short circuit output current at pin canl v canl = 36 v; v txd = low ? 3 v < v canl < +18 v 40 ? 115 70 100 115 ma v i(diff) (th)_norm differential receiver threshold voltage in normal mode ? 12 v < v canl < +12 v; ? 12 v < v canh < +12 v 0.5 ? 0.9 v v i(diff) (th)_stdby differential receiver threshold voltage in standby mode ? 12 v < v canl < +12 v; ? 12 v < v canh < +12 v 0.4 ? 1.05 v r i(cm) (canh) common ? mode input resistance at pin canh ? 2 v < v canh < +7 v; ? 2 v < v canl < +7 v 15 26 37 k r i(cm) (canl) common ? mode input resistance at pin canl ? 2 v < v canh < +7 v; ? 2 v < v canl < +7 v 15 26 37 k r i(cm) (m) matching between pin canh and pin canl common mode input resistance v canh = v canl = +5 v ? 1 0 +1 % r i(diff) differential input resistance 25 50 75 k c i(canh) input capacitance at pin canh v txd = high; (note 10) ? 7.5 20 pf c i(canl) input capacitance at pin canl v txd = high; (note 10) ? 7.5 20 pf c i(diff) differential input capacitance v txd = high; (note 10) ? 3.75 10 pf timing characteristics (see figures 6 and 8) t d(txd ? buson) delay txd to bus active ? 75 ? ns t d(txd ? busoff) delay txd to bus inactive ? 85 ? ns t d(buson ? rxd) delay bus active to rxd ? 24 ? ns t d(busoff ? rxd) delay bus inactive to rxd ? 32 ? ns t pd_dr propagation delay txd to rxd dominant to recessive transition 50 100 210 ns t pd_rd propagation delay txd to rxd recessive to dominant transition 50 120 210 ns t d(stb ? nm) delay standby mode to normal mode 5 11 20 s t wake_filt filter time for wake ? up via bus 0.5 ? 5 s t dwakerd delay to flag wake event (recessive to dominant transitions) valid bus wake ? up event 0.5 2.6 6 s t dwakedr delay to flag wake event (dominant to recessive transitions) valid bus wake ? up event 0.5 2.6 6 s t wake_to bus time for wake ? up timeout standby mode 1 ? 10 ms t dom(txd) txd dominant time for timeout v txd = low; normal mode 1 ? 10 ms t bit(rxd) bit time on rxd pin t bit(txd) = 500 ns 400 ? 550 ns t bit(txd) = 200 ns 120 ? 220 ns t bit(vi(diff)) bit time on bus (canh ? canl pin) t bit(txd) = 500 ns 435 ? 530 ns t bit(txd) = 200 ns 155 ? 210 ns t rec receiver timing symmetry t rec = t bit(rxd) ? t bit(vi(diff)) t bit(txd) = 500 ns ? 65 ? +40 ns t bit(txd) = 200 ns ? 45 ? +15 ns thermal shutdown t j(sd) shutdown junction temperature junction temperature rising 160 180 200 c 9. in the range of 4.5 v to 4.75v and from 5.25 v to 5.5 v the chip is fully functional; some parameters may be outside of the s pecification. 10. values based on design and characterization, not tested in production
ncv7344 www. onsemi.com 8 measurement setups and definitions txd 0.3v cc * 0.3v cc * 0.7v cc * 5t bit(txd) t bit(txd) 0.3v cc * t bit(rxd) rxd 500 mv t bit(vi(diff)) t pd_dr t pd_rd 900 mv v i(diff) =v canh ? v canl t d(txd ? buson) t d(txd ? busoff) 0.7v cc * t d(buson ? rxd) figure 6. transceiver timing diagram *on ncv7344 ? 3 v cc is replaced by v io edge length below 10 ns ncv7344 v cc gnd 2 3 canh canl 6 7 stb 8 rxd 4 txd 1 100nf +5 v 15pf 1nf 1nf transient generator v io 5 figure 7. test circuit for automotive transients figure 8. test circuit for timing characteristics v cc gnd 2 3 canh canl 5 6 7 r lt /2 c lt stb 8 rxd 4 txd 1 2x 30 100 pf 100 nf +5 v 15 pf ncv7344 v io r lt /2 c 1
ncv7344 www. onsemi.com 9 table 6. iso 11898 ? 2:2016 parameter cross ? reference table iso 11898 ? 2:2016 specification ncv7344 datasheet parameter notation symbol dominant output characteristics single ended voltage on can_h v can_h v o(dom)(canh) single ended voltage on can_l v can_l v o(dom)(canl) differential voltage on normal bus load v diff v o(dom)(diff) differential voltage on effective resistance during arbitration v diff v o(dom)(diff)_arb differential voltage on extended bus load range (optional) v diff v o(dom)(diff) driver symmetry driver symmetry v sym v o(dom)(sym) driver output current absolute current on can_h i can_h i o(sc)(canh) absolute current on can_l i can_l i o(sc)(canl) receiver output characteristics, bus biasing active single ended output voltage on can_h v can_h v o(rec)(canh) single ended output voltage on can_l v can_l v o(rec)(canl) differential output voltage v diff v o(rec)(diff) receiver output characteristics, bus biasing inactive single ended output voltage on can_h v can_h v o(off)(canh) single ended output voltage on can_l v can_l v o(off)(canl) differential output voltage v diff v o(off)(dif) optional transmit dominant timeout transmit dominant timeout, long t dom t dom(txd) transmit dominant timeout, short t dom na static receiver input characteristics, bus biasing active recessive state differential input voltage range v diff v i(diff)(th)_norm dominant state differential input voltage range v diff v i(diff)(th)_norm static receiver input characteristics, bus biasing inactive recessive state differential input voltage range v diff v i(diff)(th)_stdby dominant state differential input voltage range v diff v i(diff)(th)_stdby receiver input resistance differential internal resistance r diff r i(diff) single ended internal resistance r can_h r can_l r i(cm)(canh) r i(cm)(canl) receiver input resistance matching matching a of internal resistance m r r i(cm)(m) implementation loop delay requirement loop delay t loop t pd_rd t pd_dr optional implementation data signal timing requirements for use with bit rates above 1 mbit/s and up to 2 mbit/s transmitted recessive bit width @ 2 mbit/s t bit(bus) t bit(vi(diff)) received recessive bit width @ 2 mbit/s t bit(rxd) t bit(rxd)
ncv7344 www. onsemi.com 10 table 6. iso 11898 ? 2:2016 parameter cross ? reference table parameter symbol notation receiver timing symmetry @ 2 mbit/s t rec trec optional implementation data signal timing requirements for use with bit rates above 2 mbit/s and up to 5 mbit/s transmitted recessive bit width @ 5 mbit/s t bit(bus) t bit(vi(diff)) transmitted recessive bit width @ 5 mbit/s t bit(rxd) t bit(rxd) received recessive bit width @ 5 mbit/s t rec t rec maximum ratings of v can_h , v can_l and v diff maximum rating v diff v diff v canh ? canl general maximum rating v can_h and v can_l v can_h v can_l v canh v canl optional: extended maximum rating v can_h and v can_l v can_h v can_l na maximum leakage currents on can_h and can_l, unpowered leakage current on can_h, can_l i can_h i can_l i li bus biasing control timings can activity filter time, long t filter t wake_filt can activity filter time, short t filter na wake ? up timeout, short t wake t wake_to wake ? up timeout, long t wake t wake_to timeout for bus inactivity (required for selective wake ? up implementation only) t silence na bus bias reaction time (required for selective wake ? up implementation only) t bias na device ordering information part number description temperature range package shipping ? ncv7344d10r2g high speed low power can, canfd transceiver ? 40 c to +125 c soic 150 8 green (matte sn, jedec ms ? 012) (pb ? free) 3000 / tape & reel NCV7344D13R2G high speed low power can, canfd transceiver with v io pin ncv7344mw0r2g high speed low power can, canfd transceiver ? 40 c to +150 c dfn 8 wettable flank (pb ? free) 3000 / tape & reel ncv7344mw3r2g high speed low power can, canfd transceiver with v io pin ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncv7344 www. onsemi.com 11 package dimensions soic ? 8 case 751az issue b 7.00 8x 0.76 8x 1.52 1.27 dimensions: millimeters 1 pitch *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* recommended notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b does not include dambar protrusion. allowable protrusion shall be 0.004 mm in excess of maximum material condition. 4. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.006 mm per side. dimension e1 does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.010 mm per side. 5. the package top may be smaller than the package bot- tom. dimensions d and e1 are determined at the outer- most extremes of the plastic body at datum h. 6. dimensions a and b are to be determined at datum h. 7. dimensions b and c apply to the flat section of the lead between 0.10 to 0.25 from the lead tip. 8. a1 is defined as the vertical distance from the seating plane to the lowest point on the package body. 14 85 seating plane detail a 0.10 c a1 dim min max millimeters h 0.25 0.41 a --- 1.75 b 0.31 0.51 l 0.40 1.27 e 1.27 bsc c 0.10 0.25 a1 0.10 0.25 l2 m 0.25 a-b b 8x c d a b c top view side view 0.25 bsc e1 3.90 bsc e 6.00 bsc d e d 0.20 c 0.10 c 2x note 6 notes 4&5 notes 4&5 side view end view e e1 d 0.10 c d d notes 3&7 note 6 note 8 a a2 a2 1.25 --- d 4.90 bsc h seating plane detail a l c l2 h 45 chamfer c note 7
ncv7344 www. onsemi.com 12 package dimensions dfn8, 3x3, 0.65p case 506bw issue o notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from the terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. a b e d d2 e2 bottom view b e 8x 0.10 b 0.05 a c c k 8x note 3 2x 0.10 c pin one reference top view 2x 0.10 c a a1 (a3) 0.05 c 0.05 c c seating plane side view l 8x 14 5 8 dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.25 0.35 d 3.00 bsc d2 2.30 2.50 e 3.00 bsc e2 1.55 1.75 e 0.65 bsc k 0.20 ??? l 0.35 0.45 ?? ?? ?? ?? ? ? ? ? ?? ?? ?? ?? ? ? ? ? 1 0.65 pitch 3.30 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. recommended 8x dimensions: millimeters l1 detail a l optional constructions l 0.00 0.15 note 4 e/2 soldering footprint* on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent ? marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ncv7344/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative ?

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