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NAU8223 datasheet rev 1.3 page 1 of 23 july, 2012 NAU8223 3.1w stereo filter-free class-d audio amplifier 1 description the NAU8223 is a stereo high efficiency filter-free class-d audio amplifier, which is capable of drivi ng a 4 load with up to 3.1w output power. this device provides chip enable pin with extremely low standby current and f ast start-up time of 3.4ms. it has five selectable gain settings (i.e . 0db, 6db, 12db, 18db and 24db), which can be cont rolled by a single gain pin. the NAU8223 is ideal for the portable applications of battery drive, as it has advanced features like 87db psrr, 91% efficiency, ultra low quiescent current (i.e. 2.1ma at 3.7v for 2 channels) and superior emi performan ce. it has the ability to configure the inputs in either single-en ded or differential mode. NAU8223 is available in miniature qfn-20 package an d tssop-20 package. key features low quiescent current: ? 2.1ma at 3.7v for 2 channels ? 3.2ma at 5v for 2 channels 5 selectable gain settings: ? 0db / 6db / 12db / 18db / 24db powerful stereo class-d amplifier: ? 2ch x 3.1w (4 @ 5v, 10% thd+n) ? 2ch x 1.26w (4 @ 3.7v, 1% thd+n) ? 2ch x 1.76w (8 @ 5v, 10% thd+n) ? 2ch x 0.76w (8 @ 3.7v, 1% thd+n) low output noise: 20 v rms @0db gain 87db psrr @217hz low current shutdown mode click-and pop suppression applications notebooks / tablet pcs personal media players / portable tvs mp3 players portable game players digital camcorders figure 1: NAU8223block diagram
NAU8223datasheet rev 1.4 page 2 of 23 august, 2013 2 pinout 2.1 NAU8223 qfn 20 (top view)
NAU8223datasheet rev 1.4 page 3 of 23 august, 2013 2.2 tssop 20 (top view) part number dimension package package material NAU8223yg 4mm x 4mm qfn-20 pb-free NAU8223wg 4.4mm x 6.5mm tssop-20 pb-free
NAU8223datasheet rev 1.4 page 4 of 23 august, 2013 3 pin descriptions qfn tssop name type functionality 1 9 outrp analog output right channel positive btl output 2 10 vdd supply power supply 3 11 nc nc no connect 4 12 en digital input chip enable (high = enable; l ow = pd) 5 13 inr analog input right channel negative input 6 14 ipr analog input right channel positive input 7 15 gs analog input 5 selectable gain setting (0db / 6db / 12db / 18db / 24db) 8 16 vdd supply power supply 9 17 vss supply ground 10 18 ipl analog input left channel positive input 11 19 inl analog input left channel negative input 12 20 nc nc no connect 13 1 nc nc no connect 14 2 vdd supply power supply 15 3 outlp analog output left channel positive btl output 16 4 vss supply ground 17 5 outln analog output left channel negative btl output 18 6 vdd supply power supply 19 7 outrn analog output right channel negative btl output 20 8 vss supply ground 21 - ex-pad analog input thermal tab (must be conne cted to vss, qfn-20 package, only) notes 1. pins designated as nc (not internally connected) sh ould be left as no-connection table 1: NAU8223 pin description
NAU8223datasheet rev 1.4 page 5 of 23 august, 2013 4 electrical characteristics conditions: en = vdd = 5v, vss = 0v, av = 12db z l = , bandwidth = 20hz to 22khz, t a = 25 o c parameter symbol comments/conditions min typ max units power delivered output power (per channel) p out z l = 4 + 33h thd + n = 10% vdd = 5.0v 3.1 w vdd = 3.7v 1.57 z l = 4 + 33h thd + n = 1% vdd = 5.0v 2.46 vdd = 3.7v 1.26 z l = 8 + 68h thd + n = 10% vdd = 5.0v 1.76 vdd = 3.7v 0.95 z l = 8 + 68h thd + n = 1% vdd = 5.0v 1.41 vdd = 3.7v 0.76 parameter symbol comments/conditions min typ max units chip enable (en) voltage enable high v en_h vdd = 2.5v to 5.5v 1.4 v voltage enable low v en_l vdd = 2.5v to 5.5v 0.4 v input leakage current -1 +1 a thermal and current protection thermal shutdown temperature 130 o c thermal shutdown hysteresis 15 o c short circuit threshold i limit 2.1 a gain setting voltage gain a v tie gs to vss 24 db gs connect vss through 100k 5% 18 tie gs pin to vdd 12 gs connect vdd through 100k 5% 6 floating node 0 differential input resistance r in a v = 24db 35 k a v = 18db 70 a v = 12db 140 a v = 6db 280 a v = 0db 558
NAU8223datasheet rev 1.4 page 6 of 23 august, 2013 electrical characteristics (continued) conditions: en = vdd = 5v, vss = 0v, av = 12db, z l = , bandwidth = 20hz to 22khz, t a = 25 o c parameter symbol comments/conditions min typ max units normal operation quiescent current consumption i qui vdd = 3.7v 2.1 ma vdd = 5v 3.17 ma shut down current i off en = 0 0.1 a oscillator frequency f osc 300 khz efficiency 91 % start up time t start 3.4 msec output offset voltage v os 1 4 mv common mode rejection ratio cmrr f in = 1khz 80 db click-and-pop suppression into shutdown (z l =8 ) a weighted -72 dbv power supply rejection ratio dc psrr vdd = 2.5v to 5.5v 98 db ac psrr* v ripple = 0.2vpp@217hz** v ripple = 0.2vpp@1khz v ripple = 0.2vpp@10khz 87 74 54 db channel crosstalk f in = 1khz, z l = 8 + 68h -101 db * measured with 0.1uf capacitor on v dd and battery supply ** meas ured with 2.2uf input capacitor. parameter symbol comments/conditions min typ max units noise performance av = 0db (a-weighted) 20 v rms av = 6db (a-weighted) 21 av = 12db (a-weighted) 27 av = 18db (a-weighted) 36 av = 24db (a-weighted) 52 the following setup is used to measure the above pa rameters
NAU8223datasheet rev 1.4 page 7 of 23 august, 2013 absolute maximum ratings condition min max units analog supply -0.50 +5.50 v industrial operating temperature -40 +85 c storage temperature range -65 +150 c caution: do not operate at or near the maximum rati ngs listed for extended periods of time. exposure to such conditions may adversely influence product reliability and result in failures not covered by warranty. operating conditions condition symbol min typical max units analog supply range vdd 2.50 3.7 5.50 v ground vss 0 v
NAU8223datasheet rev 1.4 page 8 of 23 august, 2013 6 special feature description the NAU8223 offers excellent quantity performance a s high efficiency, high output power and low quiesc ent current. it also provides the following special features. 6.1 gain setting the NAU8223 has a gs pin, which can control five se lectable gain settings (i.e. 0db / 6db / 12db / 18d b / 24db). gs pin configuration internal gain (db) gs tie to vss 24 gs connect to vss through 100k 5% resistor 18 gs tie to vdd 12 gs connect to vdd through 100k 5% resistor 6 floating (open node) 0 6.2 device protection the NAU8223 includes device protection for three op erating scenarios. they are 1. thermal overload 2. short circuit 3. supply under voltage 6.2.1 thermal overload protection when the device internal junction temperature reach es 130c, the NAU8223 will disable the output drive rs. when the device cools down and a safe operating temperature of 115c has been reached for at least about 47msec , the output drivers will be enabled again. 6.2.2 short circuit protection if a short circuit is detected on any of the pull-u p or pull-down devices on the output drivers for at least 14usec, the output drivers will be disabled for 47msec. the out put drivers will then be enabled again and check fo r the short circuit. if the short circuit is still present, the output d rivers are disabled after 14usec. this cycle will c ontinue until the short circuit is removed. the short circuit threshold is set at 2.1a. 6.2.3 supply under voltage protection if the supply voltage drops under 2.1v, the output drivers will be disabled while the NAU8223 control circuitry still operates. this will avoid the battery supply to dra g down too low before the host processor can safely shut down the devices on the system. if the supply drops further below 1.0v the internal power on reset activated an d puts the entire device in power down state.
NAU8223datasheet rev 1.4 page 9 of 23 august, 2013 6.3 power up and power down control when the supply voltage ramps up, the internal powe r on reset circuit gets triggered. at this time all internal circuits will be set to power down state. the device can be enabl ed by setting the en pin high. upon setting the en pin high, the device will go through an internal power up sequenc e in order to minimize ?pops? on the speaker output . the complete power up sequence will take about 3.4msec. the devi ce will power down in about 30usec, when the en pin is set low. it is important to keep the input signal at zero am plitude or enable the mute condition in order to mi nimize the ?pops? when the en pin is toggled. .
NAU8223datasheet rev 1.4 page 10 of 23 august, 2013 7 typical operating characteristics conditions: en = v dd = 5v, vss = 0v, av = 12db, z l = , bandwidth = 20hz to 22khz, t a = 25 o c, unless otherwise noted 0 10 20 30 40 50 60 70 80 90 100 0 1 2 3 4 efficiency(%) output power(w) efficiency vs output power (v dd = 5.0v) zl=4?+33uh zl=8?+68uh 0 10 20 30 40 50 60 70 80 90 100 0 0.5 1 1.5 2 efficiency(%) output power(w) efficiency vs output power (v dd = 3.7v) zl=4?+ 33uh zl=8? +68uh 0.001 0.01 0.1 1 20 200 2000 20000 thd+n(%) frequency(hz) thd+n vs frequency (v dd = 3.7v, zl= 8? + 68uh) pout 0.2w pout 0.4w 0.001 0.01 0.1 1 20 200 2000 20000 thd+n(%) frequency(hz) thd+n vs frequency (v dd = 4.2v, zl= 8? + 68uh) pout 0.2w pout 0.6w
NAU8223datasheet rev 1.4 page 11 of 23 august, 2013 0.001 0.01 0.1 1 20 200 2000 20000 thd+n(%) frequency(hz) thd+n vs frequency (v dd = 5v, zl= 8? + 68uh) pout 0.2w pout 1.2w 0.001 0.01 0.1 1 10 100 0 0.5 1 1.5 thd+n (%) pout (w) thd+n vs pout (v dd = 3.7v, zl = 8? + 68uh) f 100hz f 1khz f 6khz 0.001 0.01 0.1 1 10 100 0 0.5 1 1.5 2 thd+n (%) pout (w) thd+n vs pout (v dd = 4.2v, zl= 8? + 68uh) f 100hz f 1khz f 6khz 0.001 0.01 0.1 1 10 100 0 1 2 3 thd+n (%) pout (w) thd+n vs pout (v dd = 5v, zl=8? + 68uh) f 100hz f 1khz f 6khz
NAU8223datasheet rev 1.4 page 12 of 23 august, 2013 0.001 0.01 0.1 1 20 200 2000 20000 thd+n(%) frequency(hz) thd+n vs frequency (v dd = 3.7v, zl= 4? + 33uh) pout 0.2w pout 0.8w 0.001 0.01 0.1 1 20 200 2000 20000 thd+n(%) frequency(hz) thd+n vs frequency (v dd = 4.2v, zl= 4? + 33uh) pout 0.2w pout 1w 0.001 0.01 0.1 1 20 200 2000 20000 thd+n(%) frequency (hz) thd+n vs frequency (v dd = 5v, zl= 4? + 33uh ) pout 1.5w pout 2w 0.001 0.01 0.1 1 10 100 0 1 2 3 thd+n (%) pout (w) thd+n vs pout (v dd = 3.7v, zl= 4? + 33uh) f = 100hz f = 1khz f = 6khz
NAU8223datasheet rev 1.4 page 13 of 23 august, 2013 0.001 0.01 0.1 1 10 100 0 1 2 3 thd+n (%) pout (w) thd+n vs pout (v dd = 4.2v, zl= 4? + 33uh) f = 100hz f = 1khz f = 6khz 0.001 0.01 0.1 1 10 100 0 1 2 3 4 thd+n (%) pout (w) thd+n vs pout (v dd = 5v, zl= 4? + 33uh) f = 100hz f = 1khz f = 6khz -10 -5 0 5 10 15 20 25 30 20 200 2000 20000 gain (db) frequency (hz) gain vs frequency gain 0db gain 6db gain 12db gain 18db gain 24db -120 -100 -80 -60 -40 -20 0 20 200 2000 20000 level (db) frequency (hz) crosstalk vs frequency left to right right to left
NAU8223datasheet rev 1.4 page 14 of 23 august, 2013 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 2.5 3.5 4.5 5.5 6.5 psrr (db) supply voltage (v) ac psrr vs supply voltage psrr @gain 0db, 1khz -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 20 200 2000 20000 psrr (db) frequency (hz) ac psrr vs frequency psrr @ gain 0db
NAU8223datasheet rev 1.4 page 15 of 23 august, 2013 0 0.5 1 1.5 2 2.5 3 3.5 2.5 3.5 4.5 5.5 supply current(ma) supply voltage (v) supplyvoltage vs supplycurrent
NAU8223datasheet rev 1.4 page 16 of 23 august, 2013 8 application information 8.1 application diagram vss outlp vdd ipl vdd en vss vdd nc gs vdd vss nc inr ipr outln nc outrn outrp 2 3 4 5 6 7 8 1 10 15 14 13 12 11 16 9 20 19 18 17 inl NAU8223 stereo class d qfn 20-pin p.s. gs pin ? the 100k resistors are optional. gs can be floating for int ernal gain setting = 0db. please refer section 2.1 (gain setting) for the detailed explanation.
NAU8223datasheet rev 1.4 page 17 of 23 august, 2013 8.2 component selection coupling capacitors an ac coupling capacitor (cin) is used to block the dc content from the input source. the input resist ance of the amplifier (rin) together with the cin will act as a high pass filter. so depending on the required cut off frequ ency the cin can be calculated by using the following formula where is the desired cut off frequency of the hi gh pass filter. input output cin rin(input resistance) amplifier bypass capacitors bypass capacitors are required to remove the ac rip ple on the vdd pins. the value of these capacitors depends on the length of the vdd trace. in most cases, 10uf and 0. 1uf are enough to get the good performance. 8.3 layout considerations the NAU8223 qfn package uses an exposed pad on the bottom side of the package to dissipate excess powe r from the output drivers. this pad must be soldered carefully to the pcb for proper operation of the NAU8223. th is pad is internally connected to vss. a typical layout is sh own below.
NAU8223datasheet rev 1.4 page 18 of 23 august, 2013 the pcb has to be designed in such a manner that it should have nine vias in 3x3 grid under NAU8223. t he vias should have hole size of 12mil and a spacing of 30mils. th e pad size of the vias is 24mils. the vias on the t op side of the board should be connected with a copper pour that has an area of 2mm x 2mm, centered underneath the NAU8223. the nine vias should connect to copper pour area on the bott om of the pcb. it is preferred to pour the complete bottom side of the board with vss. also good pcb layout and grounding techniques are e ssential to get the good audio performance. it is better to use low resistance traces as these devices are driving low impedance loads. the resistance of the traces has a significant effect on the output power delivered to the load. in order t o dissipate more heat, use wide traces for the powe r and ground lines. 8.4 class d without filter the NAU8223 is designed for use without any filter on the output line. that means the outputs can be d irectly connected to the speaker in the simplest configuration. this type of filter less design is suitable for portable applications where the speaker is very close to the amplifier. in other wo rds, this is preferable in applications where the l ength of the traces between the speaker and amplifier is short. the fo llowing diagram shows this simple configuration. NAU8223 outputs connected to speaker without filter circuit 8.5 class d with filter in some applications, the shorter trace lengths are not possible because of speaker size limitations a nd other layout reasons. in these applications, the long traces wil l cause emi issues. there are two types of filter c ircuits available to reduce the emi effects. these are ferrite bead and lc filters. ferrite bead filter the ferrite bead filters are used to reduce the hig h frequency emissions. the typical circuit diagram is shown in the figure. NAU8223 outputs connected to speaker with ferrite b ead filter
NAU8223datasheet rev 1.4 page 19 of 23 august, 2013 the characteristic of ferrite bead is such that it offers higher impedance at high frequencies. for be tter emi performance select ferrite bead which offers highest impedance at high frequencies, so that it will attenuate the signals at higher frequencies. usually the ferrite beads have low imp edance in the audio range, so it will act as a pass through filter in the audio frequency range. lc filter the lc filter is used to suppress the low frequency emissions. the following diagram shows the NAU8223 outputs connected to the speaker with lc filter circuit. r l is the resistance of the speaker coil. NAU8223 outputs connected to speaker with lc filter standard low pass lcr filter the following are the equations for the critically damped ( = 0.707) standard low pass lcr filter
is the cutoff frequency the l and c values for differential configuration c an be calculated by duplicating the single ended co nfiguration values and substituting r l = 2r.
NAU8223datasheet rev 1.4 page 20 of 23 august, 2013 8.6 NAU8223 emi performance the NAU8223 includes a spread spectrum oscillator f or reduced emi. the pwm oscillator frequency typica lly sweeps in a range of 300 khz +/- 15 khz in order to spread the energy of the pwm pulses over a larger frequen cy band. in addition, slew rate control on the output drivers a llows the application of ?filter less? loads, while suppressing emi at high frequencies. the below graph shows the emi per formance of NAU8223 with ferrite beads and speaker cable length of 30cm.
NAU8223datasheet rev 1.4 page 21 of 23 august, 2013 9 package dimensions 9.1 qfn20l 4x4 mm^2, pitch:0.50 mm top vi ew bottom vi ew 11 6 20 1 5 10 15 16 16 15 11 10 6 5 1 20
NAU8223datasheet rev 1.4 page 22 of 23 august, 2013 9.2 tssop20l 4.4x6.5 mm^2, pitch:0.65 mm
NAU8223datasheet rev 1.4 page 23 of 23 august, 2013 10 ordering information nuvoton part number description version history version date page description rev1.0 march, 2012 p.8, p.9 preliminary revision updated typical characteristics rev1.1 march, 2012 p.2, p.10 updated pin no. added application diagrams rev1.2 may, 2012 na updated electrical characteristics rev1.3 july, 2012 p.4, p.5, p.10-p.18 added application information section added/modified typical operating characteristics updated electrical characteristics rev1.4 august, 2013 p.4, p.5, p.22,p.23 added tssop20 package information section table 1: version history important notice nuvoton products are not designed, intended, author ized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy c ontrol instruments, airplane or spaceship instrumen ts, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications int ended to support or sustain life. furthermore, nuvoton products are no t intended for applications wherein failure of nuvo ton products could result or lead to a situation wherein personal inju ry, death or severe property or environmental damag e could occur. nuvoton customers using or selling these products f or use in such applications do so at their own risk and agree to fully indemnify nuvoton for any damages resulting from su ch improper use or sales. package type: y = 20-pin qfn package n au8223 _g package material: g = pb-free package w = 20-pin tssop package

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