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rev. b a ad8381 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2003 analog devices, inc. all rights reserved. fast, high voltage drive, 6-channel output decdriver decimating lcd panel driver functional block diagram db (0:9) vid0 vid1 vid2 vid3 vid4 2-stage latch xfr vid5 dac 10 10 10 10 10 10 10 10 10 10 10 10 dac 2-stage latch 2-stage latch 2-stage latch 2-stage latch 2-stage latch dac 10 sequence control dac dac dac bias scaling control vrefhi vreflo inv vmid stby byp clk stsq e/o r/l ad8381 features high voltage drive: rated settling time to within 1.3 v of supply rails output overload protection high update rates: fast, 100 ms/s 10-bit input word rate low power dissipation: 570 mw includes stby function voltage controlled video reference (brightness) and full-scale (contrast) output levels 3.3 v or 5 v logic and 9 v to 18 v analog supplies high accuracy: laser trimming eliminates external calibration flexible logic: inv reverses polarity of video signal stsq/xfr for parallel ad8381 operation in 12-channel systems drives capacitive loads: 27 ns settling time to 1% into 150 pf load slew rate 265 v/ s with 150 pf load available in 48-lead lqfp applications lcd analog column driver product description the ad8381 provides a fast, 10-bit latched decimating digital in put, which drives six high voltage outputs. ten-bit input words are sequentially loaded into six separate high speed, bipolar dacs. flexible digital input format allows several ad8381s to be used in parallel for higher resolution displays. stsq synchronizes sequential input loading, xfr controls synchronous output updating and r/l controls the direction of loading as either left-to-right or right-to-left. six channels of high voltage output drivers drive to within 1.3 v of the rail in rated settling time. the output signal can be adjusted for brightness, signal inversion, and contrast for maximum flexibility. t he ad8381 is fabricated on adi? proprietary, fast bipolar 24 v process, providing fast input logic, bipolar dacs with trimmed accuracy and fast settling, high voltage precision drive amplifiers on the same chip. the ad8381 dissipates 570 mw nominal static power. the stby pin reduces power to a minimum, with fast recovery. the ad8381 is offered in a 48-lead 7 mm 7 mm 1.4 mm lqfp package and operates over the commercial temperature range of 0 c to 85 c.
rev. b e2e ad8381especifications (@ 25 c, avcc = 15.5 v, dvcc = 3.3 v, vreflo = vmid = 7 v, vrefhi = 9.5 v, t min = 0 c, t max = 85 c, unless otherwise noted.) model conditions min typ max unit video dc performance 1 t min to t max vde dac code 450 to 800 e7.5 +1.0 +7.5 mv vcme dac code 450 to 800 e3.5 +0.5 +3.5 mv reference inputs (vrefhi e vreflo) = 2.5 v vmid range 2 6.25 9.25 v vmid bias current 35 77 m a vrefhi vreflo avcc v vreflo vmid e 0.5 vrefhi v vrefhi input resistance to vreflo 20 k w vreflo bias current 0.01 0.07 m a vrefhi input current 125 165 m a vfs range 3 0 5.75 v resolution coding binary 10 bits digital input characteristics clk rise and fall time = 5 ns input data update rate nrz 100 ms/s clk to data setup time: t 1 0ns clk to stsq setup time: t 3 0ns clk to xfr setup time: t 5 0ns clk to data hold time: t 2 5ns clk to stsq hold time: t 4 5ns clk to xfr hold time: t 6 5ns t clk high e/o = high 4.5 ns t clk low 3.5 ns c in 3pf i ih 0.6 0.7 m a i il 0.05 0.16 m a v ih 2.0 v v il 0.8 v v th threshold voltage 1.4 v video output characteristics output voltage swing avcc e voh, vol e agnd 1 1.3 v clk to vid delay 4 : t 7 50% of vidx 13.5 15.5 17.5 ns inv to vid delay 50% of vidx 12 14 16 ns output current 30 75 ma output resistance 29 w video output dynamic performance t min to t max , v o = 5 v step, c l = 150 pf data switching slew rate 265 v/ m s invert switching slew rate 410 v/ m s data switching settling time to 1% 27 32 ns data switching settling time to 0.25% 50 75 ns invert switching settling time to 1% 33 40 ns invert switching settling time to 0.25% 55 100 ns clk and data feedthrough 5 5 mv p-p all-hostile crosstalk 6 amplitude 50 mv p-p glitch duration 45 ns power supply supply rejection (vde) avccx = +15.5 v 1 v 0.6 mv/v dvcc, operating range 3 5.5 v dvcc, quiescent current 18 25 ma avcc, operating range 918v total avcc quiescent current 33 40 ma stby avcc current stby = h 1.8 3 ma stby dvcc current stby = h 0.03 0.1 ma operating temperature range 0 85 r c notes 1 vde = differential error voltage. vcme = common-mode error voltage. see the theory of operation section. 2 see figure 6 in theory of operation section. 3 vfs = 2 (vrefhi e vreflo). see the theory of operation section. 4 measured from 50% of falling clk edge to 50% of output change. measurement is made for both states of inv. 5 measured on one output as clk is driven and stsq and xfr are held low. 6 measured on one output as the other five are changing from 0x000 to 0x3ff for both states of inv. specifications subject to change without notice.
rev. b e3e ad8381 timing characteristics parameter conditions min typ max unit t 1 clk to data setup time clk rise and fall time = 5 ns 0 ns t 2 clk to data hold time clk rise and fall time = 5 ns 5 ns t 3 clk to stsq setup time clk rise and fall time = 5 ns 0 ns t 4 clk to stsq hold time clk rise and fall time = 5 ns 5 ns t 5 clk to xfr setup time clk rise and fall time = 5 ns 0 ns t 6 clk to xfr hold time clk rise and fall time = 5 ns 5 ns t 7 clk to vid delay 13.5 15.5 17.5 ns db (0:9) clk stsq, xfr e1 0 t 3, t 5 t 4, t 6 t 1 t 2 figure 1. timing requirement e/o = high db (0:9) clk stsq e1 0 xfr t 1 t 2 t 3 t 4 t 5 t 6 figure 2. timing requirements e/o = low clk xfr vidx t 7 figure 3. output timing
rev. b ad8381 e4e absolute maximum ratings 1 supply voltages avccx e agnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 v dvcc e dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 v input voltages maximum digital input voltages . . . . . . . . dvcc + 0.5 v minimum digital input voltages . . . . . . . . dgnd e 0.5 v maximum analog input voltages . . . . . . . . . avcc + 0.5 v minimum analog input voltages . . . . . . . . agnd e 0.5 v internal power dissipation 2 lqfp package @ 25 r c ambient . . . . . . . . . . . . . . . . 2.7 w output short circuit duration . . . . . . . . . . . . . . . . . . infinite operating temperature range . . . . . . . . . . . . . . 0 r c to 85 r c storage temperature range . . . . . . . . . . . . e65 r c to +125 r c lead temperature range (soldering 10 sec) . . . . . . . . 300 r c notes 1 stresses above those listed under the absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to the absolute maximum ratings for extended periods may reduce device reliability. 2 48-lead lqfp package: q ja = 45 r c/w (still air, 4-layer pcb) q jc = 19 r c/w overload protection the ad8381 employs a two-stage overload protection circuit t hat consists of an output current limiter and a thermal shutdown. th e maximum current at any one output of the ad8381 is internally limited to 100 ma average. in the event of a momen- tary short circuit between a video output and a power supply rail (vcc or agnd), the output current limit is sufficiently low to provide temporary protection. the thermal shutdown debiases the output amplifier when the junction temperature reaches the internally set trip point. in the event of an extended short circuit between a video output and a power supply rail, the output amplifier current continues to switch between 0 ma and 100 ma typ with a period determined by the thermal time constant and the hysteresis of the thermal trip point. the thermal shutdown provides long term protection by limiting the average junction temperature to a safe level. recovery from a momentary short circuit is fast, approximately 1 00 ns. recovery from a thermal shutdown is slow and is de pendent on the ambient temperature. maximum power dissipation the maximum power that can be safely dissipated by the ad8381 is limited by its junction temperature. the maximum safe junc- tion temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150 r c. exceeding this limit temporarily may cause a shift in the parametric performance due to a change in the stresses exerted on the die by the package. exceeding a junction temperature of 175 r c for an extended period can result in device failure. to ensure proper operation within the specified operating tem- perature range, it is necessary to limit the maximum power dissipation as follows: p dmax = ( t j max e t a )/ q ja where: t j max = 150 r c. ambient temperature e c 3.5 0 maximum power dissipation e w 3.0 2.5 2.0 1.5 1.0 0.5 10 20 30 40 50 60 70 80 90 figure 4. maximum power dissipation vs. temperature ordering guide temperature package package model range description option ad8381jst 0 r c to 85 r c 48-lead lqfp st-48 ad8381-eb evaluation board caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad8381 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
rev. b ad8381 e5e pin function descriptions pin no. mnemonic function description 1, 12, 19, 23, nc no connect 24, 43e45 2e11 db (0:9) data input 10-bit data input msb = db (9). 13 e/o even/odd select the active clk edge is the rising edge when this input is held high, and it is the falling edge when this input is held low. data is loaded sequentially on the rising edges of clk when this input is high and loaded on the falling edges when this input is low. 14 r/l right/left select a new data loading sequence begins on the left, with channel 0, when this input is low, and on the right, with channel 5, when this input is high. 15 inv invert when this pin is high, the analog output voltages are above vmid. when low, the analog output voltages are below vmid. 16 dgnd digital supply return this pin is normally connected to the analog ground plane. 17 dvcc digital power supply digital power supply. 18, 27, 31 avccx analog power supplies analog power supplies. 35, 42 20 stby standby when high, the internal circuits are debiased and the power dissipation drops to a minimum. 21 byp bypass a 0.1 m f capacitor connected between this pin and agnd ensures optimum settling time. 22, 25, 29 agndx analog supply returns these pins are normally connected to the analog ground plane. 33, 37, 41 26, 28, 30, vid5, vid4, vid3, analog outputs these pins are dir ectly connected to the analog inputs of the lcd panel. 32, 34, 36 vid2, vid1, vid0 38 vmid midpoint reference the voltage applied between this pin and agnd sets the midpoint reference of the analog outputs. this pin is normally connected to vcom. 39 vreflo full-scale reference the volt age applied between pins 39 and 40 sets the full- scale output voltage. 40 vrefhi full-scale reference the volt age applied between pins 39 and 40 sets the full- scale output voltage. 46 stsq start sequence a new data loading sequence begins on the rising edge of clk when this input was high on the preceding rising edge of clk and the e/o input is held high. a new data loading sequence begins on the falling edge of clk when this input was high on the preceding falling edge of clk and the e/o input is held low. 47 xfr data transfer data is transferred to the outputs on the immediately following falling edge of clk when this input is high on the rising edge of clk. 48 clk clock clock input. pin configuration 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) vid0 av cc0, 1 vid1 a gnd1, 2 vid2 av cc2, 3 vid3 nc db0 db1 db2 db3 db4 db5 nc = no connect db6 db7 db8 db9 a gnd3, 4 vid4 av cc4, 5 vid5 ad8381 nc a gnd5 e/o r/l inv dgnd dvcc av ccbias nc stby byp a gndbias nc nc a gnd0 vmid vreflo vrefhi a gnddac av c c dac nc nc nc stsq xfr clk
rev. b ad8381 e6e 12v 2v 20ns/div vidx c l 150pf vmid = 7v vfs = 5v tpc 1. invert switching 10 v step response (rise) at c l 7v 2v vidx c l 150pf vmid = 7v vfs = 5v 10ns/div tpc 2. data switching 5 v step response (rise) at c l , inv = l 12v 7v 20ns/div vidx c l 150pf vmid = 7v vfs = 5v tpc 3. data switching 5 v step response (rise) at c l , inv = h 12v 2v 20ns/div vidx c l 150pf vmid = 7v vfs = 5v tpc 4. invert switching 10 v step response (fall) at c l 7v 2v 10ns/div vidx c l 150pf vmid = 7v vfs = 5v tpc 5. data switching 5 v step response (fall) at c l , inv = l 12v 7v 20ns/div vidx c l 150pf vmid = 7v vfs = 5v tpc 6. data switching 5 v step response (fall) at c l , inv = h etypical performance characteristics
rev. b ad8381 e7e e0.25% 10ns/div vidx c l 150pf vmid = 7v vfs = 5v 0.25% 0.00% e0.50% e0.75% e1.00% 7v t = 0 tpc 7. output settling time (rising edge) at c l , 5 v step, inv = low e0.25% 10ns/div vidx c l 150pf vmid = 7v vfs = 5v 0.00% e0.50% e0.75% e1.00% 12v t = 0 tpc 8. output settling time (rising edge) at c l , 5 v step, inv = high 20ns/div 5v + 30mv + 20mv + 10mv vmid = 7v e10mv e20mv vid5 vid0 e vid4 tpc 9. all-hostile crosstalk at c l 0.75% 10ns/div vidx c l 150pf vmid = 7v vfs = 5v 1.00% 0.50% 0.25% 0.00% 2v e0.25% e0.50% e0.75% e1.00% t = 0 tpc 10. output settling time (falling edge) at c l , 5 v step, inv = low 0.75% 10ns/div vidx c l 150pf vmid = 7v vfs = 5v 1.00% 0.50% 0.25% 0.00% 7v t = 0 e0.25% e0.50% e0.75% tpc 11. output settling time (falling edge) at c l , 5 v step, inv = high 20ns/div + 10mv vmid = 7v e10mv db (0:9) tpc 12. data switching transient (feedthrough) at c l
rev. b ad8381 e8e input code 0.5 0 dnl e lsb 0.4 0.3 0.2 0.1 0.0 e0.1 e0.2 e0.3 e0.4 e0.5 256 512 768 1023 tpc 13. differential nonlinearity (dnl) vs. code, inv = h input code 0.5 0 inl e lsb 0.4 0.3 0.2 0.1 0.0 e0.1 e0.2 e0.3 e0.4 e0.5 256 512 768 1023 tpc 14. integral nonlinearity (inl) vs. code, inv = h vmid e v 5 5 normalized vde at code 0 e mv 0 e5 e10 e15 e20 e25 67 11 10 vfs = 4v 89 vfs = 4v vfs = 5v vfs = 5.75v vfs = 5.75v vfs = 5v tpc 15. normalized vde at code 0 vs. vmid, avcc = 15.5 v input code 0.5 0 dnl e lsb 0.4 0.3 0.2 0.1 0.0 e0.1 e0.2 e0.3 e0.4 e0.5 256 512 768 1023 tpc 16. differential nonlinearity (dnl) vs. code, inv = l input code 0.5 0 inl e lsb 0.4 0.3 0.2 0.1 0.0 e0.1 e0.2 e0.3 e0.4 e0.5 256 512 768 1023 tpc 17. integral nonlinearity (inl) vs. code, inv = l frequency e hz 0 10k psrr e db e20 e40 e60 e80 100k 1m 5m code 512, inv = low code 512, inv = high tpc 18. avcc power supply rejection vs. frequency
rev. b ad8381 e9e input code 7.5 0 vde e mv 2.5 0.0 e2.5 e5.0 512 768 1023 256 5.0 e7.5 tpc 19. differential error voltage (vde) vs. code temperature e c 7.5 0 vde e mv 2.5 0.0 e2.5 e5.0 40 60 100 20 5.0 e7.5 80 code 512 tpc 20. differential error voltage (vde) vs. temperature input code 3.50 0 vcme e mv 1.75 0.00 e1.75 512 768 1023 256 e3.50 tpc 21. common-mode error voltage (vcme) vs. code temperature e c 3.50 0 vcme e mv 1.75 0.00 e1.75 40 60 100 20 e3.50 80 code 512 tpc 22. common-mode error (vcme) vs. temperature
rev. b ad8381 e10e functional description the ad8381 is a system building block designed to directly drive the columns of lcd panels of the type popularized for use in data projectors. it comprises six channels of precision 10-bit d igital-to-analog converters loaded from a single, high speed, 10-bit-wide input. precision current feedback amplifiers, provid- ing well-damped pulse response and rapid voltage settling into large capacitive loads, buffer the six outputs. laser trimming at t he wafer level ensure low absolute output errors and tight channel- to- channel matching. in addition, tight part-to-part m atching in high channel count systems is guaranteed by the use of an external voltage reference. input data loading (start sequence control?stsq) a valid stsq control input initiates a new six-clock pulse loading cycle, during which six input data words are loaded sequentially into six internal channels. a new loading sequence begins on the current active clk edge only when stsq was held high at the preceding active clk edge. data loading?expanded systems (even/odd control) to facilitate expanded, even/odd systems, the active clk edge, at which input data is loaded, is set with the e/o control input. input data is loaded on rising clk edges while the e/o input is held high and loaded on falling clk edges while the e/o input is held low. data loading?inverted images (right/left control) to facilitate image mirroring, the order in which input data is loaded is set with the r/l input. a new loading sequence begins at channel 0 and proceeds to channel 5 when the r/l input is held high and begins at channel 5 and proceeding to channel 0 when the r/l input is held low. data transfer to outputs (xfr control) data transfer to all outputs is initiated by the xfr control input. when xfr is held high during a rising clk edge, data is simultaneously transferred to all outputs on the immediately following falling clk edge. vcom reference (vmid reference input) an external analog reference voltage connected to this input sets the reference level at the outputs. this input is normally connected to vcom. full-scale output (vrefhi, vreflo reference inputs) the difference between two external analog reference voltages, connected to these inputs, sets the full-scale output voltage at the outputs. vreflo is normally tied to vmid. analog voltage inversion (invert control) to facilitate systems that use column, row or pixel inversion, the analog output voltage inversion is controlled by the inv control input. while inv is high, the analog voltage equivalent of the input code is subtracted from (vmid + vfs) at each output. while inv is low, the analog voltage equivalent of the input code is added to (vmid e vfs) at each output. standby mode (stby control) a high applied to the stby input debiases the internal circuitry, dropping the quiescent power dissipation to a few milliwatts. since both digital and analog circuits are debiased, all stored data will be lost. upon returning stby to low, nor- mal operation is restored.
rev. b ad8381 e11e transfer function the ad8381 has two regions of operation, selected by the inv input, where the video output voltages are either above or below a reference voltage, applied externally at the vmid input. the transfer function defines the analog output voltage as the function of the digital input code as follows: vout vmid vfs n = ? ? ? 1 1023 e where: n = input code vfs = 2 (vrefhi e vreflo) 1023 input code av c c vmid v out (v) 0 ( vmid + vfs) ( vmid e vfs) inv = high inv = low v outp(n) v outn(n) a gnd figure 5. transfer function the region over which the output voltage varies with input code is selected by the inv input. when inv is low, the output volt- age increases from (vmid e vfs), (where vfs = the full-scale output voltage), to vmid as the input code increases from 0 to 1023. when inv is high, the output voltage decreases from (vmid + vfs) to vmid with increasing input code. for each value of input code there are then two possible values of output voltage. when inv is low, the output is defined as voutp(n) where n is the input code and p indicates the oper- ating region where the slope of the transfer function is positive. when inv is high, the output is defined as voutn(n) where n indicates the operating region where the slope of the transfer function is negative. accuracy to best correlate transfer function errors to image artifacts, the overall accuracy of the ad8381 is defined by two parameters, vde and vcme. vde, the differential error voltage, measures the deviation of the rms value of the output from the rms value of the ideal. it is depen- dent on the difference between the output amplitudes voutn(n) and voutp(n) at a particular code. the defining expression is vde voutn n voutp n vfs n = () ? ? ? ? ? ? 1 2 1 1023 ()e ()e e where: 1 2 () voutn n voutp n ()e () is the rms value of the output. ( vfs (1 e n /1023)) is the rms value of the ideal. vcme, the common-mode error voltage, measures the devia- tion of the average value of the output from the average value of the ideal. it is dependent on the average between the output amplitudes voutn(n) and voutp(n) at a particular code. the defining expression is: vcme voutn n voutp n vmid = + () ? ? ? 1 2 1 2 () ()e where: 1 2 + () voutn n voutp n () () is the average value of the output. vmid is the average value of the ideal. maximum full-scale output voltage the following conditions limit the range of usable output voltages: y the internal dacs limit the minimum allowed voltage at the vmid input to 5.3 v. y the scale factor control loop limits the maximum full-scale output voltage to 5.75 v. y the output amplifiers settle cleanly at voltages within 1.3 v from the supply rails. y the common-mode range of the output amplifiers limit the maximum value of vmid to avcc e 3. at any given valid value of vmid, the voltage required to reach any one of the above limits defines the maximum usable full- scale output voltage vfsmax. vfsmax is the envelope in figure 6. the valid range of vmid is the shaded area. av c c av cc/2 4.3 vfs (v) 5.75 av cc/2e1.3 2 va l id vmid 0 5.3 7 avcce7 avcce3 av c c /2 vmid (v) figure 6. vfsmax vs. vmid
rev. b ad8381 e12e operating modes?6-channel systems the simplest full color lcd based system is characterized by an image processor with a single 10-bit-wide data bus and a 6-channel lcd per color. such systems usually have vga or svga resolution and require a single ad8381 per color. t he inv input facilitates column and row inversion for these systems. e6 0 6 vid0 e5 1 7 vid1 e4 2 8 vid2 e3 3 9 vid3 e2 4 10 vid4 e1 5 11 vid5 outputs clk stsq xfr 012345678910 e1 11 12 db(0:9) inputs ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 0 6 12 1 7 2 8 3 9 4 10 e1 5 11 internal latches figure 7. 6-channel system timing diagram, e/o = h, r/l = low operating modes?12-channel systems sin gle and dual data bus type 12-channel systems are com- monly in use. the single data bus 12-channel system is characterized by an image processor with a single, 10-bit data bus and a 12-channel l cd per color. the maximum resolution of such a system is usually up to 85 hz xga or 75 hz sxga and requires two ad8381s per color. one ad8381 is set to run in even mode while the other is in odd mode. both ad8381s share the same data bus and clk. the timing diagram of such system is shown in figure 8. t he dual data bus 12-channel system is characterized by an i mage processor with two 10-bit parallel data buses and a 12-channel lcd. the maximum resolution of such system is usually up to 75 hz uxga and requires two ad8381s per color. both ad8381s may be set to run in even mode and may share the same clk. the timing diagram of each ad8381 in such system is identical to that of the 6-channel system. the inv input facilitates column, row, and pixel inversion for both types of 12-channel systems. 0 2 4 6 8 10 12 14 16 18 20 22 e2 0 2 4 6 8 10 12 14 18 20 22 internal latche s ch0 ch1 ch2 ch3 ch4 ch5 vid0 vid1 vid2 vid3 vid4 vid5 output ad8381 even 16 1 3 5 7 9 11 13 15 17 19 21 23 1 3 5 7 9 11 internal latche s ch0 ch1 ch2 ch3 ch4 ch5 vid0 vid1 vid2 vid3 vid4 vid5 output ad8381 odd 13 15 17 19 21 23 e3 stsq even stsq odd xfr r/l e/o even e/o odd inputs pixel clk e3 e2 12345678910 121314 15 16 17 18 19 20 21 22 23 24 db (0:9) clk 0 e1 e12 e10 e8 e6 e4 e2 e1 e11 e9 e7 e5 e3 e1 11 figure 8. twelve-channel even/odd system timing diagram operating modes?large channel count systems to facilitate 18, 24, or higher channel systems, any number of required ad8381s may be cascaded.
rev. b ad8381 e13e ad8381 ad8381 db(0:9) clk xfr stsq inv ch 0 ch 2 ch 4 ch 6 ch 8 ch 10 ch 1 ch 3 ch 5 ch 7 ch 9 ch 11 12-channel lcd vid0 vid1 vid2 vid3 vid4 vid5 vrefhi vmid vreflo db(0:9) clk xfr stsq inv vrefhi vmid vreflo vid0 vid2 vid3 vid4 vid5 e/o e/o r/l r/l vid1 references vrefhi vcom image processor db(0:9) clk xfr stsq1 stsq2 inv1 inv2 e/o1 e/o2 r/l h. reverse clk clk clk clk c lclk c c c c c c c c c c c c c c c c cl lc clk l clk l l l c c c clk l clk c c c lclk c
rev. b ad8381 e14e layout considerations t he ad8381 is a mixed-signal, high speed, very accurate de vice. in order to realize its specifications, it is essential to use a properly designed printed circuit board. layout and grounding the analog outputs and the digital inputs of the ad8381 are pinned out on opposite sides of the package. when laying out the circuit board, keep these sections separate from each other to minimize crosstalk and noise and the coupling of the digital input signals into the analog outputs. all signal trace lengths should be made as short and direct as possible to prevent signal degradation due to parasitic effects. note that digital signals should not cross or be routed near analog signals. it is imperative to provide a solid analog ground plane under and around the ad8381. all of the ground pins of the part should be connected directly to the ground plane with no extra signal path length. for conventional operation this includes the pins dgnd, agnddac, agndbias, agnd0, agnd1,2, agnd3,4, and agnd5. the return traces for any of the signals should be routed close to the ground pin for that section to prevent stray signals from coupling into other ground pins. power supply bypassing all power supply and reference pins of the ad8381 must be properly bypassed to the analog ground plane for optimum performance. all analog supply pins may be connected directly to an analog supply plane located as close to the part as possible. a 0.1 m f chip capacitor should be placed as close to each analog supply pin as possible and connected directly between each analog supply pin and the analog ground plane. a minimum of 47 m f tantalum capacitor should be placed near the analog supply plane and connected directly between the supply and analog ground planes. a minimum of 10 m f tantalum capacitor should be placed near the digital supply pin and connected directly to the analog ground plane. a 0.1 m f chip capacitor should be connected between the digital supply pin and the analog ground. vrefhi, vmid, vreflo reference distribution to ensure well-matched video outputs, all ad8381s must oper- ate from equal reference voltages. each reference voltage should be distributed to each ad8381 directly from the source of the reference voltage with approxi- mately equal trace lengths. a 0.1 m f chip capacitor should be placed as close to each refer- ence input pin as possible and directly connected between the reference input pin and the analog ground plane. db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 a gnddac vrefhi clk x fr stsq vmid av c c dac vreflo dgnd dvcc inv byp e/o r/l av ccbias a gndbias stby 13 14 15 16 17 19 20 21 23 24 vid0 vid1 av cc0 ,1 vid2 a gnd1,2 vid3 av cc2 ,3 vid4 a gnd3,4 vid5 av cc4 ,5 a gnd5 12 11 10 9 8 7 6 5 4 3 2 1 26 28 30 32 34 36 48 47 46 45 44 43 40 39 38 a gnd0 to analog ground plane to analog supply plane figure 11.
rev. b ad8381 e15e outline dimensions 48-lead low profile quad flat package [lqfp] (st-48) dimensions shown in millimeters top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc 7.00 bsc sq seating plane 1.60 max 0.75 0.60 0.45 view a 9.00 bsc sq pin 1 0.20 0.09 1.45 1.40 1.35 0.08 max coplanarity view a rotated 90 ccw seating plane 10 6 2 7 3.5 0 0.15 0.05 compliant to jedec standards ms-026bbc
rev. b ?6 c02480??0/03(b) ad8381 revision history location page 10/03?hange from rev. a to rev. b. changes to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9/03?hange from rev. 0 to rev. a. changes to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

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