View AIS2120SXTR_8741400.PDF datasheet online --- IC-ON-LINE

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this is information on a product in full production. january 2017 docid028312 rev 3 1/58 ais1120sx ais2120sx mems automotive acceleration sensor: single/dual-axis with spi interface datasheet - production data features ? aec-q100 qualified ? 3.3 v single supply operation ? 14-bit data output ?? 120 g full scale ? slow and fast offset cancellation ? embedded self-test ? selectable low-pass filter ? spi interface ? ecopack ? compliant ? extended temperature range -40 c to +105 c applications ? airbag systems ? vibrations, impact monitoring description the ais1120sx / ais2120sx is a central acceleration sensor with a single or dual axis sensing element and an ic interface able to provide acceleration information to a master control unit via an spi protocol. the sensing element, capable of detecting the acceleration, is manufactured using a dedicated process developed by st to produce inertial sensors and actuators in silicon. the ic interface is manufactured using a bcd process that allows a high level of integration. the device is factory trimmed to better tune the characteristics of the sensing element with the acceleration information to be supplied. the ais1120sx / ais2120sx has a full scale of ? 120 g. the acquisition chain consists of a c/v converter, a full-differential charge amplifier, a 2 nd order ??? analog-to-digital converter and a digital core, which includes filtering, compensation and interpolation, control logic and spi protocol generation. the differential capacitance of the sensor is proportional to the proof mass displacement; thus, by sensing the differential capacitance, the position of the sensor is determined. then, since the mass position is known, and the position is related to the input acceleration, the input acceleration can be easily deduced. the device is available in a plastic soic8 package and is guaranteed to operate over a temperature range extending from -40 c to +105 c. soic8 table 1. device summary order code g -range sensitivity axes operating temperature range [ ? c] package packing ais1120sxtr 120 g x -40 to +105 soic8n tape and reel AIS2120SXTR 120 g xy -40 to +105 soic8n tape and reel www.st.com
contents ais1120sx / ais2120sx 2/58 docid028312 rev 3 contents 1 block diagrams and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1.1 mechanical element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1.2 sigma-delta converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1.3 filter architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.1.4 decimation filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.1.5 low-pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1.6 signal compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.1.7 linear interpolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.1.8 signal delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.1.9 offset cancellation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.1.10 state machine and on-chip-oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.1.11 power domain block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2 customer accessible data arrays (registers) . . . . . . . . . . . . . . . . . . . . 17 2.1 reg_ctrl_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2 reg_ctrl_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3 reg_config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.4 reg_status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.5 reg_chid_revid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.6 reg_acc_chx_low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.7 reg_acc_chx_high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.8 reg_acc_chy_low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.9 reg_acc_chy_high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.10 reg_osc_counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.11 reg_id_sensor_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.12 reg_id_veh_manuf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.13 reg_id_sensor_manuf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.14 reg_id_lot_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.15 reg_id_lot_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.16 reg_id_lot_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
docid028312 rev 3 3/58 ais1120sx / ais2120sx contents 58 2.17 reg_id_lot_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.18 reg_id_wafer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.19 reg_id_coor_x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.20 reg_id_coor_y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.21 reg_reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.22 off_chx_high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.23 off_chx_low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.24 off_chy_high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.25 off_chy_low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.26 other addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3 power-on phase and initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.1 initialization procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.2 phase1 (t1): power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.3 phase2 (t2): configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.4 phase 3 (t3): fast offset cancellation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.5 phase 4 (t4): test phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.6 phase 5 (t5): normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4 mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . 36 4.1 mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.3 digital blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.4 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.5 factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5 interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.1 32-bit communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.1.1 acceleration commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.1.2 non-acceleration commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.1.3 spi crc polynomial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.2 32-bit spi bit information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.3 timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.4 error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
contents ais1120sx / ais2120sx 4/58 docid028312 rev 3 6 recommendations for operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7.1 soic8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
docid028312 rev 3 5/58 ais1120sx / ais2120sx list of tables 58 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 3. reg_ctrl_0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 4. reg_ctrl_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 5. reg_config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 6. reg_status_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 7. reg_status_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 8. reg_status_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 9. reg_chid_revid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 10. reg_acc_chx_low. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 11. reg_acc_chx_high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 12. reg_acc_chy_low. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 13. reg_acc_chy_high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 14. reg_osc_counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 15. reg_id_sensor_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 16. reg_id_veh_manuf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 17. reg_id_sensor_manuf. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 18. reg_id_lot_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 19. reg_id_lot_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 20. reg_id_lot_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 21. reg_id_lot_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 22. reg_id_wafer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 23. reg_id_coor_x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 24. reg_id_coor_y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 25. reg_reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 26. off_chx_high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 27. off_chx_low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 28. off_chy_high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 29. off_chy_low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 30. timing delay by block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 31. temperature sensor data example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 32. mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 33. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 34. digital range and levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 35. 400 hz digital filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 36. 800 hz digital filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 37. 1600 hz digital filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 38. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 39. acceleration data example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 40. acceleration commands function of sdi bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 41. acceleration commands function of sdo bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 42. error codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 43. sdo bit examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 44. non-acceleration command function of sdi bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 45. non-acceleration commands function of sdo bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 46. 32-bit spi command: bits from 31 to 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 47. 32-bit spi command: bits from 15 to 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 9 table 48. bit decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
list of tables ais1120sx / ais2120sx 6/58 docid028312 rev 3 table 49. spi timing table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 50. error flags and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 51. soic8 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 52. revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
docid028312 rev 3 7/58 ais1120sx / ais2120sx list of figures 58 list of figures figure 1. ais1120sx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2. ais2120sx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. differential capacitive system (dual axis) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 4. 2nd order sigma-delta modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 5. filter architecture diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6. fir vs. 4th and 6th order bessel filter for amplitude frequency response . . . . . . . . . . . . . 11 figure 7. fir vs. 3rd and 4th order bessel filter for group delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 8. 8-to-1 interpolation timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 9. signal delay of reading-chain blocks with 400 hz filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 10. signal delay of reading-chain blocks with 800 hz filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 11. signal delay of reading-chain blocks with 1600 hz filter. . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 12. offset cancellation block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 13. offset cancellation flag monitoring flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 14. power domain block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 15. detectable accelerations and pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 16. accessible registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 17. power-up flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 18. power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 19. phase 2 state flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 20. cap-loss detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 21. phase 3 state flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 22. spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 23. spi timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 24. acceleration commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 25. non-acceleration commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 figure 26. spi timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 27. additional spi timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 28. soic8 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 29. soic8 package marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 30. soic8 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
block diagrams and pin description ais1120sx / ais2120sx 8/58 docid028312 rev 3 1 block diagrams and pin description 1.1 block diagrams figure 1. ais1120sx block diagram figure 2. ais2120sx block diagram
docid028312 rev 3 9/58 ais1120sx / ais2120sx block diagrams and pin description 58 1.1.1 mechanical element a proprietary process is used to create a surface micromachined accelerometer. this technology allows processing suspended silicon structures which are attached to the substrate in few points called anchors and are free to move in the direction of the sensed acceleration thanks to flexible springs. in order to be compatible with standard packaging techniques, a cap is placed at wafer level on the top of the sensing element. from an electrical point of view, the sensor can be represented as a differential capacitive system (see below for a dual-axis element). when the acceleration is applied to the sensor, the proof mass displaces from its nominal position, causing an unbalance in the capacitive half-bridge. this unbalance is measured using charge integration in response to a voltage pulse applied to the sense capacitor: figure 3. differential capacitive system (dual axis) the differential capacitive change towards acceleration can be expressed, in small displacements approximation, as: where c 0 is the at-rest capacitance, m is the inertial mass, a the acceleration, k stiffness of the springs and g the distance between capacitor electrodes. 1.1.2 sigma-delta converter a 2 nd order sigma-delta modulator is used to convert the differential voltage that comes from the charge-to-voltage converter to a pulse-density modulated (pdm) data stream. the data stream will be further processed through on-chip digital filters. figure 4. 2 nd order sigma-delta modulator &rpsdudwru ,qwhjudwru ,qwhjudwru [ \ '$& ] ] ] ] $ % $ %
block diagrams and pin description ais1120sx / ais2120sx 10/58 docid028312 rev 3 1.1.3 filter architecture figure 5. filter architecture diagram the architecture of the digital filters allows selecting 3 different cut-off frequencies based on 2 bits in the register map: fir_bw_sel[1:0]. the cut-off frequencies are 400 hz, 800 hz, and 1600 hz. for the 1600 hz filter, the noise level is higher and the enob is 10/11 bits, and not 12 bits. the cut-off frequency has to be selected for each axis during the initialization phase. once the initialization phase is finished and the end of the initialization bit is set, the cut-off frequency is locked and any attempt to change it during normal mode will generate an spi error. the cut-off frequencies can be selected as described below: fir_bw_sel[1:0]: = "00" fir with f3db = 400 hz is selected (default); = "01" fir with f3db = 800 hz is selected; = "10" fir with f3db = 1600 hz is selected (enob is 10/11bits in this mode); = "11" fir with f3db = 400 hz is selected. 1.1.4 decimation filter differential delay: d=1 number of sections: n=3 decimation factor: ? m = 32 if fir_bw_sel[1:0] = "00" (400 hz) ? m = 16 if fir_bw_sel[1:0] = "01" (800 hz) ? m = 8 if fir_bw_sel[1:0] = "10" (1600 hz)
docid028312 rev 3 11/58 ais1120sx / ais2120sx block diagrams and pin description 58 1.1.5 low-pass filter h_lpf (z) is a fir digital filter with 26 coefficients (k = 25): figure 6 and figure 7 shows the comparison between the fir filter and an analog bessel filter when the cut-off frequency is 400 hz. figure 6. fir vs. 4 th and 6 th order bessel filter for amplitude frequency response figure 7. fir vs. 3 rd and 4 th order bessel filter for group delay
block diagrams and pin description ais1120sx / ais2120sx 12/58 docid028312 rev 3 1.1.6 signal compensation on-chip eeprom bits are used to compensate sensitivity error and offset error. 1.1.7 linear interpolation the device features an l-to-1 linear data interpolation computed from the present and the previous samples. l depends on the cut-off frequency selected: interpolation factor: ? l = 16 if fir_bw_sel[1:0] = "00" or ?11? ? l = 8 if fir_bw_sel[1:0] = "01" ? l = 4 if fir_bw_sel[1:0] = "10" the data interpolation helps reduce sample jitter. the digital result will have a latency of one sample time before being sent to the spi bus. the maximum jitter will be 62.5 ? s/16 = 3.9 ? s. figure 8 shows an interpolation example. figure 8. 8-to-1 interpolation timing
docid028312 rev 3 13/58 ais1120sx / ais2120sx block diagrams and pin description 58 1.1.8 signal delays figure 9. signal delay of reading-chain blocks with 400 hz filter figure 10. signal delay of reading-chain blocks with 800 hz filter figure 11. signal delay of reading-chain blocks with 1600 hz filter 1.1.9 offset cancellation the offset cancellation is performed in the last step of the digital signal processing and includes two modes: 1. slow offset cancellation 2. fast offset cancellation the digital low-pass filter with selectable bandwidth (fast, slow cancellation) is controlled by a state machine. fast offset cancellation is used after power-on. slow offset cancellation, for continuously running offset cancellation, operates in normal mode. offset cancellation uses a moving average filter with a fixed update limit. fast offset cancellation occurs after power up while eoi = 0. slow offset cancellation occurs after eoi is set to 1. the offset cancellation error flag is set when the offset is outside the offset correction range (1020 lsb) during slow offset cancellation. a hardware error is indicated based on this flag being set for the affected axis. the flow chart for the offset cancellation block is shown in the following figure.
block diagrams and pin description ais1120sx / ais2120sx 14/58 docid028312 rev 3 figure 12. offset cancellation block diagram figure 13. offset cancellation flag monitoring flow 1.1.10 state machine and on-chip-oscillator there is an on-chip oscillator implemented. the clock frequency is trimmed to 16.384 mhz at room temp. this clock is used for the digital core. one 1024 khz clock divided from this main clock is used for the sigma-delta convertor and digital signal processing module (dsp). 1.1.11 power domain block diagram figure 14 shows the power domain of the device. a pre-regulator is implemented to improve power supply sensitivity and psrr of the device. the pre-regulator provides power to an on-chip bandgap reference and the eeprom. 325 <)dvw 2iivhw &dqfhoodwlrq ;)dvw 2iivhw &dqfhoodwlrq (2, <6orz 2iivhw &dqfhoodwlrq ;6orz 2iivhw &dqfhoodwlrq <)/$* 0$; 6(767b<6 7b< 6(72))b&$1&b&+<b(55 6(76)b< 5hfryhu " 6325ru &<&/( 32:(5 6(767b;67b; 6(72))b&$1&b&+;b(55 6(76)b; 5hfryhu " 6325ru &<&/( 32:(5 ;)/$* 0$; (2, <(6 <(6 <(6 <(6 <(6 <(6 12 12 12 12 12 12 12 <(6 <(6
docid028312 rev 3 15/58 ais1120sx / ais2120sx block diagrams and pin description 58 figure 14. power domain block diagram key blocks of the power section are: 1. pre-regulator : based on a self-biased supply-thermal independent structure, which is able to produce an internal stable voltage of 2.8 v 15%, with a maximum output current of 3 ma. the architecture is based on a bandgap cell, which produces a thermal-independent reference, which is used in turn to produce the voltage pre- regulator output; the pre-regulator is powered by vdd, and is designed to supply only some internal low-power blocks. 2. regulator : an on-chip 2.8 v regulator supplies internal power for the device; it should not be used to power other devices via the vreg terminal. a bypass capacitor is required on the vreg pin to keep the regulator stable. 3. bandgap reference : the voltage bandgap is powered by the voltage pre-regulator and is used as voltage reference for all other circuits including the front-end, supervision circuits and a/d converter. 4. charge-to-voltage converter : the c/v converter consists of a fully differential charge integrator with a continuous time icmfb (input common mode feedback) control loop, discrete time icmfb, and a switched capacitor ocmfb (output common mode feedback) control loop. furthermore the c/v converter has one 9-bit dac in order to trim the offset of the measurement chain and mechanical element. 5. self-test charge pump : the self-test charge pump internally generates a voltage higher than the 2.8 v regulated supply voltage. the charge pump is activated when the self-test mode is enabled and provides an excitation voltage of 6.6 v. during the self- test the voltage is applied and disconnected to the sensor according to a duty cycle which allows simulating a well-known force on the sensor.
block diagrams and pin description ais1120sx / ais2120sx 16/58 docid028312 rev 3 1.2 pin description figure 15. detectable accelerations and pinout c1 = 1 f 10%, 10 v (ceramic, vreg capacitor) c2 = 0.1 f 10%, 10 v (ceramic, power supply decoupling capacitor) note: an acceleration of the device in the "+x" or ?+y? directions results in a positive output change, a deceleration in this direction (or acceleration to the opposite side) results in a negative output signal. table 2. pin description pin# name function 1 scl spi clock 2 sdi spi data in 3 sdo spi data out 4 cs spi chip select 5 gnd power supply return pin (ground level) 6 vreg voltage regulator output. a ceramic capacitor of 1.0 f 10% 10 v must be connected to this pin, which should not be used to power other devices. 7 vdd this pin provides power to the device. a ceramic capacitor of 0.1 f 10% 10 v must be connected to this pin. 8 mp connect to gnd
ais1120sx / ais2120sx customer accessible data arrays (registers) docid028312 rev 3 17/58 2 customer accessible data arrays (registers) figure 16. accessible registers $gguhvv 1dph e>@ e>@ e>@ e>@ e>@ e>@ e>@ e>@ ? z'zdz>z ezk&z/e/d ? z'zdz>z ?? z'zke&/' /^zk&&zdkez,z /^zk&&zdkez,y /^zk&&zez,z /^zk&&zez,y ?? z'z^dd h^z d^ddkze> z'zdz>zztzzzzz>d, >k^^wzzzz>d, ezk& zwtzhwz>d, z^dzd/sz>d, ?e z'z^dd h^z ^w/zzz wzkdzzzz>d, k&&zez,zzzz k&&z ez,yzzz z'zke&/'ztzzzzz>d, z'zdz>zztzzzzz>d, ?? z'z^dd h^z? ?z^dz,zzzz ?z^dz,yzzz ,z'zwhdwzzzz >d, sz'z>ktzzz sz'z,/',zzz sz>ktzzz sz,/',zzz ? z'z,/zzs/ ,zzd/s ,yzd/s ? z'zz,yz>kt ?? z'zz,yz,/', $ffho'dwd;/dwfk ?? z'zz,zz>kt ? z'zz,zz,/', $ffho'dwd</dwfk ? z'zk^zkhedz ? z'z/z^e^kzzdzw ? z'z/zs,zdeh& ? z'z/z^e^kzzdeh& ?& z'z/z>kdz ? z'z/z>kdz ? z'z/z>kdz? ?? z'z/z>kdz? ?? z'z/zt&z ?e z'z/zkkzzy ?? z'z/zkkzzz ? z'zz^d ? k&&z,yz,/', ?? k&&z,yz>kt k((?y>?z ?? k&&z,zz,/', ? k&&z,zz>kt k((?z>?z ? e}?? ? e}?? ? e}?? ? z?? ?& z?? ^>&zd^dzd??w? &/zztz^>z,y?w? &/zztz^>z,z?w? ^dd h^?w? /z^e^kzzdeh&?w? k^zkhedz?w? /z^e^kzzdzw?w? zs/??w? z'zz,y?w? /zs,zdeh&??w? z'zz,z?w? /z>kd???w?e? z'zz,z??w?? /z>kd???w? /z>kd?w? /z>kd??w?? r k&&z,y??w? k&&z,z??w? r z'zz,y??w?? /zkkzzz?w? ^k&dzz^d?w? /zt&z?ew? /zkkzzy?w? k&&z,y?w?? k&&z,z?w??
customer accessible data arrays (registers) ais1120sx / ais2120sx 18/58 docid028312 rev 3 2.1 reg_ctrl_0 table 3. reg_ctrl_0 reg_ctrl_0 (address: 0x00) name bit# r/w reset state description 0 [7:1] r 0 end_of_init 0 r/w 0 end of initialization: initialization is the time interval from reset to self-test end: =?0? then device is in initialization phase = ?1? then the device is in end of initialization phase (device is in normal mode) rules : -when end_of_bit="1" then writing operations of reg_ctrl_1 and reg_config bits do not have effect and generate error flags ctrl_reg_1_wr_err="1"/c onfig_reg_wr_err="1". -cannot write eoi='1' if there is ee or he error. -cannot write eoi='1' if device is in +ve or -ve self-test (either chx or chy). doing so, re error (and config_reg_0_wr_err='1') will be produced
docid028312 rev 3 19/58 ais1120sx / ais2120sx customer accessible data arrays (registers) 58 2.2 reg_ctrl_1 table 4. reg_ctrl_1 reg_ctrl_1 (address: 0x01) name bit# r/w reset state description 0 [7:3] r 0 self_test_cmd [2:0] r/w 0 self-test commands: = "000" then device is in 0 g self-test if eoi='0'; = "001" then device starts self-test on channel x with positive voltage; = "010" then device starts self-test on channel x with negative voltage; = "011" then device is in 0 g self-test if eoi='0' = "100" then device is in 0 g self-test if eoi='0' = "101" then device starts self-test on channel y with positive voltage; = "110" then device starts self-test on channel y with negative voltage; = "111" then device is in 0 g self-test if eoi='0' rules : -cannot write if eoi='1' -cannot start a self-test on chx/chy if the channel is not enabled -cannot switch from non-0g(-ve/+ve) self_test to another non-0g self_test(-ve/+ve) without going to 0g self-test note: when starting channel x self-test: channel x acceleration command will read channel x self-test value channel y acceleration command will read temperature sensor value for self-test temperature compensation algorithm. when starting channel y self-test: channel x acceleration command will read temperature sensor value for self-test temperature compensation algorithm. channel y acceleration command will read channel y self-test value
customer accessible data arrays (registers) ais1120sx / ais2120sx 20/58 docid028312 rev 3 2.3 reg_config table 5. reg_config reg_config (address: 0x02) name bit# r/w reset state description fir_bw_sel_chy[1:0] [7:6] r/w 00 channel y fir bandwidth selection bits: if = "00" fir with f3db = 400 hz is selected; if = "01" fir with f3db = 800 hz is selected; if = "10" fir with f3db = 1600 hz is selected (resolution is 10/11bits in this mode); if = "11" fir with f3db = 400 hz is selected. fir_bw_sel_chy[1:0] is writable if end_of_init="0". writing fir_bw_sel_chy[1:0] when end_of_init="1" or when channel y self-test is activated, does not have effect and generates an error: config_reg_wr_err="1". fir_bw_sel_chx[1:0] [5:4] r/w 00 channel x fir bandwith selection bits: if = "00" fir with f3db = 400 hz is selected; if = "01" fir with f3db = 800 hz is selected; if = "10" fir with f3db = 1600 hz is selected (resolution is 10/11bits in this mode); if = "11" fir with f3db = 400 hz is selected. fir_bw_sel_chx[1:0] is writable if end_of_init="0". writing fir_bw_sel_chx[1:0] when end_of_init="1" or when channel x self-test is activated does not have effect and generates an error: config_reg_wr_err="1". dis_off_mon_chy 3 r/w 0 offset monitor channel y disable bit. if = "0" then channel y offset monitor is on; if = "1" then channel y offset monitor is off. dis_off_mon_chy is writable if end_of_init="0". writing dis_off_mon_chy when end_of_init="1" does not have effect and generates an error: config_reg_wr_err="1"
docid028312 rev 3 21/58 ais1120sx / ais2120sx customer accessible data arrays (registers) 58 dis_off_mon_chx 2 r/w 0 offset monitor channel x disable bit. = "0" then channel x offset monitor is on; = "1" then channel x offset monitor is off. dis_off_mon_chx is writable if end_of_init="0". writing dis_off_mon_chx when end_of_init="1" does not have effect and generates an error: config_reg_wr_err="1" dis_off_canc_chy 1 r/w 0 offset cancellation channel y disable bit. = "0" then channel y offset cancellation circuit is on; = "1" then channel y offset cancellation circuit is off. dis_off_canc_chy is writable if end_of_init="0". writing dis_off_canc_chy when end_of_init="1" does not have effect and generates an error: config_reg_wr_err="1" dis_off_canc_chx 0 r/w 0 offset cancellation channel x disable bit. = "0" then channel x offset cancellation circuit is on; = "1" then channel x offset cancellation circuit is off. dis_off_canc_chx is writable if end_of_init="0". writing dis_off_canc_chx when end_of_init="1" does not have effect and generates an error: config_reg_wr_err="1" table 5. reg_config (continued) reg_config (address: 0x02) name bit# r/w reset state description
customer accessible data arrays (registers) ais1120sx / ais2120sx 22/58 docid028312 rev 3 2.4 reg_status table 6. reg_status_0 reg_status_0 (address: 0x03) name bit# r/w reset state description status [1:0] [7:6] r 00 status error bits: if = "00" device is in initialization phase (power-up, configuration, fast offset cancellation); if = "01" device is in normal mode (eoi = 1); if = "10" device is test phase (0 g test or active self test); eoi = 0; if = "11" device is in initialization phase or normal mode and some errors are detected: acceleration data are disregarded due to errors in device. testmode_enabled 5 r 0 ?0?: normal mode; ?1?: test mode reg_ctrl_0_wr_err (1) 4r 0 will be set to '1' if write eoi = '1' attempt is made with the device in +ve or -ve self-test (either chx or chy). not used 3 r 0 ?0? always loss_cap 2 r 0 loss of capacitor: if = "0" then loss of capacitor is not detected (correct behavior); if = "1" then loss of capacitor is detected (wrong behavior). note: 1.loss_cap check is done during the power-up stage (~400 s after por) only. 2.recommended vdd ramp rate >1 v/ms 3.it is recommended that loss_cap flag (and all other hardware flags) be reconfirmed with soft por after power up (end_of_pwrup='1'). end_of_pwrup 1 r 0 ="1": end of power-up sequence; ready for self- test. rst_active 0 r 0 reset active bit: if = "0" then device is out of reset; if = "1" then device has undergone a soft reset sequence. cleared by a read. 1. bit not latched (cleared by any read command).
docid028312 rev 3 23/58 ais1120sx / ais2120sx customer accessible data arrays (registers) 58 table 7. reg_status_1 reg_status_1 (address: 0x04) name bit# r/w reset state description spi_err (1) 7r 0 spi error: if = "0" then spi format data is compliant with specifications (correct behavior); if = "1" then spi format data is not complaint with specifications (wrong behavior). eeprom_err 6 r 0 eeprom error: crc error reading eeprom. if = "0" eeprom reading is correct. if = "1" eeprom reading is wrong. the bit can be cleared by a read if nvm bit errflgcfg='1'. if errflgcfg='0', then this bit can't be cleared. not used 5:4 r 0 "0" always off_canc_chy_err 3 r 0 the sensor sets this flag when the offset is outside the offset monitoring threshold (1020 lsb) during slow offset cancellation for channel y; this also creates hardware failure. when the offset is within the threshold, the flag will be '0' (not latched) off_canc_chx_err 2 r 0 the sensor sets this flag when the offset is outside the offset monitoring threshold (1020 lsb) during slow offset cancellation for channel x; this also creates hardware failure. when the offset is within the threshold, the flag will be '0' (not latched) reg_config_wr_err (1) 1r 0 configuration register writing operation error: if = "0" then a writing operation is not addressed by the spi on reg_config register when end_of_init=1 (correct behavior); if = "1" then a writing operation is addressed by the spi on reg_config register when end_of_init=1 (wrong behavior). reg_ctrl_1_wr_err (1) 0r 0 control register 1 writing operation error: if = "0" then a writing operation is not addressed by the spi on reg_cntr_1 register when end_of_init=1 (correct behavior); if = "1" then a writing operation is addressed by the spi on reg_cntr_1 register when end_of_init=1 (wrong behavior). 1. bit not latched (cleared by any read command).
customer accessible data arrays (registers) ais1120sx / ais2120sx 24/58 docid028312 rev 3 table 8. reg_status_2 reg_status_2 (address: 0x05) name bit# r/w reset state description a2d_sat_chy 7 r 0 if = "1" then chy adc saturation detected (wrong behavior). a2d_sat_chx 6 r 0 if = "1" then chy adc saturation detected (wrong behavior). not used 5 r 0 charge_pump_err 4 r 0 charge pump error: if = "0" then charge pump error is not detected (correct behavior); if = "1" charge pump error is detected (wrong behavior). vreg_low_volt_det 3 r 0 vreg low-voltage detection: if = "0" then regulated voltage vreg is over the minimum supply voltage (correct behavior); = "1" then regulated voltage vreg is under the minimum supply voltage (wrong behavior). this also creates hardware failure (not latched). vreg_high_volt_det 2 r 0 vreg high-voltage detection: if = "0" then regulated voltage vreg is under the maximum supply voltage (correct behavior); if = "1" then regulated voltage vreg is over the maximum supply voltage (wrong behavior). this also creates hardware failure (not latched). vdd_low_volt_det 1 r 0 vdd low-voltage detection: if = "0" then supply voltage vdd is over the minimum supply voltage (correct behavior); if = "1" then supply voltage vdd is under the minimum supply voltage (wrong behavior). this also creates hardware failure (not latched). vdd_high_volt_det 0 r 0 vdd high-voltage detection: if = "0" then supply voltage vdd is under the maximum supply voltage (correct behavior); if = "1" then supply voltage vdd is over the maximum supply voltage (wrong behavior). this also creates hardware failure (not latched).
docid028312 rev 3 25/58 ais1120sx / ais2120sx customer accessible data arrays (registers) 58 2.5 reg_chid_revid table 9. reg_chid_revid 2.6 reg_acc_chx_low table 10. reg_acc_chx_low 2.7 reg_acc_chx_high table 11. reg_acc_chx_high reg_chid_revid (address: 0x06) name bit# r/w reset state description not used 7 r 0 not used 6 r 0 chy_active 5 r 0 = ?1?: chy reading chain enabled (copied nvm bit) chx_active 4 r 0 = ?1?: chx reading chain enabled (copied nvm bit) not used 3 r 0 revid [2:0] r 0 copied nvm bits 0x7c: bit 7 to bit 5 011 for a3 100 for a4 reg_acc_chx_low (address: 0x07) name bit# r/w reset state description reg_acc_chx [7:0] r 0x00 channel x acceleration data lsbs register reg_acc_chx_high (address: 0x08) name bit# r/w reset state description acceldataxlatch 7 r 0 reading reg_acc_chx_low register sets the bit to '1' and reg_acc_chx_high is locked to its corresponding low byte i.e reg_acc_chx_low; cleared when it is read. not used 6 r 0 reg_acc_chx [5:0] r 0 channel x acceleration data msbs register
customer accessible data arrays (registers) ais1120sx / ais2120sx 26/58 docid028312 rev 3 2.8 reg_acc_chy_low table 12. reg_acc_chy_low 2.9 reg_acc_chy_high table 13. reg_acc_chy_high 2.10 reg_osc_counter table 14. reg_osc_counter reg_acc_chy_low (address: 0x09) name bit# r/w reset state description reg_acc_chy [7:0] r 0x00 channel y acceleration data lsbs register reg_acc_chy_high (address: 0x0a) name bit# r/w reset state description acceldataylatch 7 r 0 reading reg_acc_chy_low register sets the bit to '1' and reg_acc_chy_high is locked to its corresponding low byte, i.e. reg_acc_chy_low; cleared when it is read. not used 6 r 0 reg_acc_chy [5:0] r 0 channel y acceleration data msbs register reg_osc_counter (address: 0x0b) name bit# r/w reset state description osc_counter [7:0] r 0x00 free run oscillator counter to verify oscillator is running. the counter is updated every 8 khz. to verify oscillator frequency, the ecu can compare the oscillator counter by reading the ecu clock.
docid028312 rev 3 27/58 ais1120sx / ais2120sx customer accessible data arrays (registers) 58 2.11 reg_id_sensor_type table 15. reg_id_sensor_type 2.12 reg_id_veh_manuf table 16. reg_id_veh_manuf 2.13 reg_id_sensor_manuf table 17. reg_id_sensor_manuf 2.14 reg_id_lot_0 reg_id_sensor_type (address: 0x0c) name bit# r/w reset state description id_sensor_type [7:0] r 0x00 0x1a for single axis sensor; 0x2a for dual axis sensor. reg_id_veh_manuf (address: 0x0d) name bit# r/w reset state description not used [7:4] r 0 id_veh_manuf [3:0] r 0x00 vehicle manufacturer id number ?0x00? reg_id_sensor_manuf (address: 0x0e) name bit# r/w reset state description id_sensor_manuf [7:0] r 0x00 sensor manufacturer id number lsbs (?0x00?) table 18. reg_id_lot_0 reg_id_lot_0 (address: 0x0f) name bit# r/w reset state description id_lot[7:0] [7:0] r 0 asic lot id number [7:0]
customer accessible data arrays (registers) ais1120sx / ais2120sx 28/58 docid028312 rev 3 2.15 reg_id_lot_1 2.16 reg_id_lot_2 2.17 reg_id_lot_3 2.18 reg_id_wafer table 19. reg_id_lot_1 reg_id_lot_1 (address: 0x10) name bit# r/w reset state description id_lot[15:8] [7:0] r 0 asic lot id number [15:8] table 20. reg_id_lot_2 reg_id_lot_2 (address: 0x11) name bit# r/w reset state description id_lot[23:16] [7:0] r 0 asic lot id number [23:16] table 21. reg_id_lot_3 reg_id_lot_3 (address: 0x12) name bit# r/w reset state description not used [7:6] r 0 id_lot[29:24] [5:0] r 0 asic lot id number [29:24] table 22. reg_id_wafer reg_id_wafer (address: 0x13) name bit# r/w reset state description not used [7:5] r 0 id_wafer [4:0] r 0 asic wafer id number
docid028312 rev 3 29/58 ais1120sx / ais2120sx customer accessible data arrays (registers) 58 2.19 reg_id_coor_x 2.20 reg_id_coor_y table 24. reg_id_coor_y 2.21 reg_reset table 25. reg_reset 2.22 off_chx_high table 26. off_chx_high table 23. reg_id_coor_x reg_id_coor_x (address: 0x14) name bit# r/w reset state description id_coor_x [7:0] r 0x00 die coordinate x reg_id_coor_y (address: 0x15) name bit# r/w reset state description id_coor_y [7:0] r 0x00 die coordinate y reg_reset (address: 0x16) name bit# r/w reset state description not used [7:3] r 0 soft_rst [1:0] r/w 00 software reset: device is caused to go under reset if 3 consecutive spi write operations are executed in the following sequence: 1. soft_rst[1:0]=10; 2. soft_rst[1:0]=01; 3. soft_rst[1:0]=10. off_chx_high (address: 0x17) name bit# r/w reset state description off_chx[10:3] [7:0] r 0x00 channel x offset correction data msb register
customer accessible data arrays (registers) ais1120sx / ais2120sx 30/58 docid028312 rev 3 2.23 off_chx_low table 27. off_chx_low 2.24 off_chy_high table 28. off_chy_high 2.25 off_chy_low table 29. off_chy_low 2.26 other addresses 0x1b: not used 0x1c: not used 0x1d: not used 0x1e: reserved 0x1f: reserved off_chx_low (address: 0x18) name bit# r/w reset state description offdataxlatch 7 r 0 reading off_chx_high register sets the bit to ?1? and off_chx_low is locked to its corresponding high byte i.e. off_chx_high; cleared when it is read. not used [6:3] r 0 off_chx[2:0] [2:0] r 0 channel x offset correction data lsb register off_chy_high (address: 0x19) name bit# r/w reset state description off_chy[10:3] [7:0] r 0x00 channel y offset correction data msb register off_chy_low (address: 0x1a) name bit# r/w reset state description offdataylatch 7 r 0 reading off_chy_high register sets the bit to ?1? and off_chy_low is locked to its corresponding high byte i.e. off_chy_high; cleared when it is read. not used [6:3] r 0 off_chy[2:0] [2:0] r 0 channel y offset correction data lsb register
docid028312 rev 3 31/58 ais1120sx / ais2120sx power-on phase and initialization 58 3 power-on phase and initialization 3.1 initialization procedure figure 17. power-up flowchart 1. user initiated 9''3rzhuxs 935(6wduwxs ((3520grzqordglqj %$1'*$35hdg\ 95(*6wduwxs 325qdvvhuwhgorzuhvhw 9huli\2iivhwjwhvw 9huli\3rvlwlyh6hoi7hvw jwhvw 9huli\2iivhwjwhvw 9huli\1hjdwlyh6hoi7hvw jwhvw 9huli\2iivhwjwhvw 6hw(qgri,qlwldol]helw 1rupdo2shudwlrq 7 3rzhu8s7lph 7 &rqiljxudwlrq 7 )dvw2iivhw &dqhoodwlrq 7 7hvw3kdvh 7 1rupdo2shudwlrq 6xshuylvru\&lufxlw(qdeohg 325b935(dvvhuwhg )dvw2iivhw&dqfhoodwlrq(qdeohg 6orzriivhw&dqfhoodwlrq(qdeohg 'ljlwdo&ruhvwduw %$1'*$395(*dgmxvw ,qlwldol]h5hjlvwhuvwr'hidxow 26&vwduw 26&$gmxvw 63,ixqfwlrqvwduw 95(* s9uhdfkhg
power-on phase and initialization ais1120sx / ais2120sx 32/58 docid028312 rev 3 3.2 phase1 (t1): power-up timing the power domain block diagram is shown in section 1.1.11 . power-up timing and sequence are shown in figure 18. once vdd has ramped up, vpre follows that. after vpre reaches a threshold value, internal signal npor_vpre is asserted. the signal resets the eeprom registers. therefore, eeprom settings are ready for bandgap and regulator output (vreg). then, another por circuit will monitor the output vreg. if it reaches a target threshold, npor will be asserted. npor is used to reset all the registers of the main digital core. the device waits for regulator and bandgap to be at appropriate levels (regulator >2.6 v, bandgap >1.1 v) before it starts executing its state machine (starting with eeprom download). the device starts its state machine approximately 5 s (deglitch time) after the bandgap and regulator reach their threshold levels. figure 18. power-up timing table 30 shows the typical timing delay for each block: table 30. timing delay by block timing condition (vdd rising time of 100 s) delay [ s] t pre vpre settles down to 90% 90 t bg vref settles down to 90% 250 t por 190 t reg vreg settles down to 90% 250 t eeprom 450 t osc 195
docid028312 rev 3 33/58 ais1120sx / ais2120sx power-on phase and initialization 58 3.3 phase2 (t2): configuration once npor is asserted, the device will initialize the registers to the default settings and start asic diagnostic procedure. if an error is detected, the corresponding error bit will be set in devstat register. this phase is characterized by (st1:st0 = "00"). figure 19. phase 2 state flow the diagnostic procedure in this stage includes cap-loss detection, charge pump check for self-test, and vreg/vcc low-voltage monitoring. cap-loss mode is initiated after eeprom download where the regulator is disabled 1 s. without a load cap the regulator voltage would fall below the uv threshold and the device latches it as cap-loss flag. figure 20. cap-loss detection
power-on phase and initialization ais1120sx / ais2120sx 34/58 docid028312 rev 3 3.4 phase 3 (t3): fast offset cancellation after the configuration/initialization phase (t2), the device will start fast offset cancellation which takes max. 345 ms. also there is 6 ms window for self-test calibration. during phase 3 (t3), sensor data is still available through the spi but the nd flag (see section 5.1.1: acceleration commands ) will be used and st1:st0 is still kept "00" if no error occurs until phase t4. figure 21. phase 3 state flow 3.5 phase 4 (t4): test phase after phase 3 the device is still in the programming phase. offset is close to 0. this phase is characterized by (st1:st0 = "10"). the device can be programmed to execute the active self-test. the actuation of transducer will be controlled through spi command. the active self-test applies an electrostatic force to the mechanical sensor. when the self- test mode is activated, the voltage between the rotor and stator is changed. this generates an attractive electrostatic force and causes the rotor to move towards the stator. the displacement of the rotor will be measured at the output of the adc. note: for the 2-axis version the self-test has to be executed sequentially. when starting channel x self-test: a) channel x acceleration command will read channel x self-test value b) channel y acceleration command will read temperature sensor value for self-test temperature compensation algorithm. when starting channel y self-test: a) channel x acceleration command will read temperature sensor value for self-test temperature compensation algorithm. b) channel y acceleration command will read channel y self-test value the acceleration data is given in 14-bit format (bit 25-12 of sdo data frame). its msb (d13) represents the sign bit and the negative value is in two's complementary format.
docid028312 rev 3 35/58 ais1120sx / ais2120sx power-on phase and initialization 58 when configured/read as a temperature sensor value, the 14-bit output is unsigned data. its value could be estimated as: adc_out = -16 x (temp - 25) + 7280 the following table shows a few examples of temperature sensor data. temperature compensation is only enabled during the active self-test phase. 3.6 phase 5 (t5): normal operation after the programming phase the ecu will set the end-of-initialization (eoi) bit and the device will start normal operation. st1:st0 is switched to "01". table 31. temperature sensor data example temp. (c) d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 -40 10000010000000 25 01110001110000 105 01011101110000
mechanical and electrical specifications ais1120sx / ais2120sx 36/58 docid028312 rev 3 4 mechanical and electrical specifications 4.1 mechanical characteristics 3.13 v ? v dd ? 3.47 v, -40c ? t op ? 105c, acceleration = 0 g , over lifetime, unless otherwise noted. table 32. mechanical characteristics symbol parameter test conditions min. typ. max. unit fs full-scale range (1) offset cancellation on 114 120 g s 0 sensitivity 68 lsb/ g s e sensitivity error v dd = 3.3 v t = 25c frequency = 0 hz at time t = 0 including ratiometric error -5 +5 % s re sensitivity ratiometricity error v dd = 3.6 v to pd threshold -1 +1 % tcs o sensitivity change vs temperature -40c ? t op ? 105c 0.02 lsb/ g /c s o _drift sensitivity drift over lifetime 1 % dnl differential non linearity 4 lsb off_raw 1 zero-g level offset (2) including ratiometric error, excluding noise effects, offset cxl disabled -680 680 lsb off_cxl 1 zero-g level offset including ratiometric error, excluding noise effects, offset cxl enabled -2 2 lsb off_mon_ th offset monitor threshold signed value -1020 1020 lsb off_mon_ hdd offset monitor headroom -400 400 lsb nl non linearity of sensitivity (1) best fit straight line +2 % fs crax cross axis (1) package alignment error -5 +5 % cut_off mems cutoff frequency (-3 db) 13.7 15.86 18.94 khz f 0 mems resonant frequency 10.25 11.34 12.45 khz gclip g-cell clipping 951 1108 1231 g t op operating temperature range -40 +105 c 1. guaranteed by design, verified at characterization level 2. 14-bit data, equivalent to 170 lsb on 12 bits
docid028312 rev 3 37/58 ais1120sx / ais2120sx mechanical and electrical specifications 58 4.2 electrical characteristics 3.13 v ?? v dd ?? 3.47 v, -40c ?? t op ?? 105c, acceleration = 0 g , over lifetime, unless otherwise noted. table 33. electrical characteristics symbol parameter test conditions min. typ. max. unit v dd supply voltage -5% 3.3 +5% v vreg -5% 2.8 +5% v i ss supply current single axis 3 6 ma i sd supply current dual axis 4 8 ma offset cancellation (1) avg averaging period -5% 1024 +5% ms off_cvu offset correction value per update -1 +1 lsb off_dspe default startup phase enable time time to guarantee the internal offset is removed 317 334 351 (2) ms off_fast fast offset cancellation -5% 8000 +5% lsb/s off_slow slow offset cancellation 0.8 1 1.2 lsb/s self-test st self-test output change v dd = 3.30 v, t = 25c, frequency = 0 hz 1632 lsb st_tol self-test tolerance across temp, over life time -15 15 % st_ton_ toff self-test turn-on/off time specification reached for a 400 hz 3-pole filter 2ms noise nois_rms output noise rms +4 lsb nois_p2p output noise peak-to-peak +16 lsb angular acceleration sensitivity (3) aas angular acceleration sensitivity 5*10 -6 g*s 2 / rad sdo pin load (4) load capacitive load drive 60 pf oscillator frequency f osc oscillator frequency -5% 16.384 +5% mhz power supply rejection ratio psrr power supply rr 1*fsw, 2*fsw, 3*fsw, 4*fsw, 5*fsw, 6*fsw 0.5 lsb/mv
mechanical and electrical specifications ais1120sx / ais2120sx 38/58 docid028312 rev 3 clipping dig_clip digital output -5% 120 +5% g low-pass filter cut_off cut-off frequency (400 hz filter) 370 400 430 hz 1. offset cancellation can vary with oscillator frequency 2. internal offset is removed in max. 345 ms; another 6 ms are needed for self-test calibration. during this phase, spi will report nd flag if acceleration command being sent. 3. based on simulation and characterization 4. guaranteed by design table 33. electrical characteristics (continued) symbol parameter test conditions min. typ. max. unit
docid028312 rev 3 39/58 ais1120sx / ais2120sx mechanical and electrical specifications 58 4.3 digital blocks table 34. digital range and levels symbol parameter conditions min typ max unit bit adc resolution 14 bit acc_rng range for acceleration data -8192 +8191 lsb out_hi logic output high (sdo pin) max static current = 2 ma v dd -0.6 v dd v out_low logic output low (sdo pin) max static current = 2 ma 0.0 0.6 v in_hi logic input high (all inputs) 2 v dd v in_low logic input low (all inputs) 0.0 1 v c in1 input capacitance at high impedence (sdo pin) 2pf c in2 input capacitance at cs/sdi/sck pin 10 pf i_pull_d internal pull-down current (sdi, sck) vin = vcc to 0 v 10 27 50 a i_pull_u internal pull-up current (cs) vin = vcc to 0 v 10 27 50 a uvt_vdd undervoltage threshold (v dd ) 2.7 2.9 3.1 v uvt_vreg undervoltage threshold (vreg) 2.1 2.3 2.5 v uv_det1 under/overvoltage detection time vdd below threshold vreg below threshold 6 1.5 25 5 40 10.5 s s hard_res hard reset threshold (vreg) 1.8 2.1 2.2 v res_t reset activation time after spi command 1.5 2 s rec_t reset recovery time reset to first spi access 1ms
mechanical and electrical specifications ais1120sx / ais2120sx 40/58 docid028312 rev 3 table 37. 1600 hz digital filter table 35. 400 hz digital filter symbol parameter conditions min typ max unit signal delay (1) overall signal delay 0.84 0.976 1.0 ms sampling rate (1) interpolation output 256 khz 1. based on simulations table 36. 800 hz digital filter symbol parameter conditions min typ max unit signal delay (1) overall signal delay 0.4 0.507 0.6 ms sampling rate (1) interpolation output 256 khz 1. based on simulations symbol parameter conditions min typ max unit signal delay (1) 1. based on simulations overall signal delay 0.19 0.273 0.32 ms sampling rate (1) interpolation output 256 khz
docid028312 rev 3 41/58 ais1120sx / ais2120sx mechanical and electrical specifications 58 4.4 absolute maximum ratings stresses above those listed as ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. this device is sensitive to mechanical shock, improper handling can cause permanent damage to the part. this device is sensitive to electrostatic discharge (esd), improper handling can cause permanent damage to the part. 4.5 factory calibration the ic interface is factory calibrated for sensitivity (s 0 ) and zero- g level (off_raw). the trimming values are stored inside the device in a non-volatile structure. when the device is turned on, the trimming parameters are downloaded into the registers to be employed during normal operation which allows the device to be used without further cali- bration. table 38. absolute maximum ratings symbol ratings value unit v dd supply voltage -0.3 to 7.0 (1) 1. not for continued operation v vreg -03. to 3.0 v sck,sdi -0.3 to v dd v a unp mechanical shock with device unpowered 2000 g h drop drop shock survivability (concrete floor) 1.2 m esd esd protection hbm (low-voltage pins) 2 kv cdm 750 v t stg storage temperature range -55 to +150 c t j operating temperature range -40 to +105 c
interface description ais1120sx / ais2120sx 42/58 docid028312 rev 3 5 interface description the ais1120sx / ais2120sx provides a bi-directional 3.3 v spi interface for communication with the mcu at a 32-bit data word size. each transfer consists of two frames of 32 clocks per frame. the sensor always operates in slave mode whereas the mcu provides the master function. the interface consists of 4 ports as shown below. figure 22. spi serial clock (sck): input for master clock signal. this clock determines the speed of data transfer and all receiving and sending is done synchronous to this clock. chip select (cs): cs activates the spi interface. as long as cs is high, the ic does not accept the clock signal or data and the output sdo is in high impedance. whenever cs is in a low logic state, data can be transferred from and to the microcontroller. serial input (sdi): accelerometer data in is latched by the rising edge of scl (see figure 23: spi timings ). serial output (sdo): accelerometer data out is set by the falling edge of scl (see figure 23: spi timings ). 5.1 32-bit communication protocol the communication between slave and master is transmitted by 32-bit data word, msb first. an off-frame protocol is used meaning that each transfer is completed through a sequence of 2 phases. the answer of a given request is sent within the very next frame. the acceleration data for the x-axis, y-axis channel will be frozen at the rising edge of cs of the request and submitted during the response (see figure 23 ).
docid028312 rev 3 43/58 ais1120sx / ais2120sx interface description 58 figure 23. spi timings cs is the chip select and it is controlled by the spi master. it goes low at the start of the transmission and goes back high at the end of a phase. scl is the serial port clock and it is controlled by the spi master. it is stopped high when cs is high (no transmission). sdi is serial data input and sdo is serial data output. sdi is captured at the rising edge of scl and sdo is driven at the falling edge of scl. the spi instructions used can be subdivided into two classes, acceleration and non- acceleration commands. 5.1.1 acceleration commands these commands are used to request sensor data for channel x or y. the acceleration data is given in 14-bit format (bit 25-12 of sdo data frame). the msb (d13) represents the sign bit and the negative value is in two's complementary format. the following table shows a few examples of full range and 0 g offset: table 39. acceleration data example each 32-bit frame can request one of two channels (x or y), see definition of bits ch1:ch0. ? 00 x data ? 01 y data accel [ g ] d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 120.4 01111 111111111 -120.5 10000 000000000 0.015 00000 000000001 -0.015 11111 111111111
interface description ais1120sx / ais2120sx 44/58 docid028312 rev 3 the format of the acceleration commands is shown below. figure 24. acceleration commands the function of the individual bits of sdi and sdo is shown in table 40 and table 41 . table 40. acceleration commands function of sdi bits name bit position description definition ch1:ch0 [31:30] channel select sensor channel source for data: 00: x-data (ch1) 01: y -data (ch2) 10: ch3 11: ch4 sen 29 sen bit identifies sensor data request: 1: sensor data 0: non-sensor data p 28 parity bit odd parity bit, cover bit 31-8 not used [27:8] n/a always 0 c7:c0 [7:0] crc crc bits for sdi table 41. acceleration commands function of sdo bits name bit position description definition sen 31 sen bit identifies sensor data request: 1: sensor data 0: non-sensor data ch1-ch0 [30:29] channel select sensor channel source for data: 00: x-data (ch1) 01: y -data (ch2) 10: ch3 11: ch4 p 28 parity bit odd parity bit, cover bit 31-8
docid028312 rev 3 45/58 ais1120sx / ais2120sx interface description 58 error codes are to be interpreted as follows: eeprom error (ee) : any error related to internal eeprom e.g. mismatch of internal crc. spi error (se) : any violation of spi format e.g. incorrect number of clocks during the frame, or parity mismatch of sdi, or crc mismatch of sdi. request error (re) : set when unexpected or invalid command is received by sensor, locked registers are read or written during any undefined state of sensor. condition not correct (cnc) : set when data for undefined channel (for single axis sensor), ch3 or ch4 are requested. no data available (nd) : set when data is requested during power-up sequence (cap- loss/charge pump/fast offset cancel). x channel hardware error (x_he) : set when there is cap-loss error, charge pump error, vdd_low, vreg_low or x offset cancel saturate (after eoi) occurs. y channel hardware error (y_he) : set when there is cap loss error, charge pump error, vdd_low, vreg_low or y offset cancel saturate (after eoi) occurs. test mode (te) : set when the part is in test mode. priority of error codes : ee (highest) -> se -> re -> cnc -> nd -> he -> te (lowest) st1:st0 [27:26] status type of data: 00: initialization 01: normal mode 10: self-test mode 11: error data d13:d0 [25:12] data sensor data / self-test data (14 bit) sf3-sf0 [11:8] status flag bits 0000: no error 0001: eeprom error (ee) 0010: spi error (se) 0011: request error (re) 0100: condition not correct (cnc) 0101: no data available (nd) 0110: hardware error (he) 1000: adc saturation error (as) 1111: in test mode (te) c7:c0 [7:0] crc crc error bits for sdo table 42. error codes st1:st0 sf flags 11 ee = 0001 nvm crc error 11 se = 0010 frame crc error 11 re = 0011 request error (register 03, bit4 shows this error also) table 41. acceleration commands function of sdo bits (continued) name bit position description definition
interface description ais1120sx / ais2120sx 46/58 docid028312 rev 3 table 43 provides some examples of sdo bit sequence interpretation. notes: 1.once the device finishes fast offset cancellation (and self-test calibration), it automatically enters into the programming phase (st1:st0 status "10") until the eoi command has been sent. during this phase, if there is not any self-test initialization command from spi, 0 g in self-test phase on both channels could be read from the acceleration commands. 2.when starting channel x self-test: a.channel x acceleration command will read channel x self-test value b.channel y acceleration command will read temperature sensor value for self-test temperature compensation algorithm. 3.when starting channel y self-test: c.channel x acceleration command will read temperature sensor value for self-test temperature compensation algorithm. d.channel y acceleration command will read channel y self-test value 11 cnc = 0100 condition not correct error 11 nd = 0101 no data error 11 he = 0110 (cap loss error + charge pump error + vdd undervoltage + vreg undervoltage + vdd overvoltage + vreg overvoltage + slow offset max) 00 as = 1000 (adc internal > 160g) table 43. sdo bit examples 31 30 29 28 27 26 [25:12] [11:8] [7:0] definition sen ch1 ch0 p st1 st2 d11:d2/error sf3:sf0 crc device status 1 0 0 0 0 x, init no st 0101 crc init, self test off 1 0 1 0 0 y, init no st 0101 crc init, self test off 1 0 0 0 1 x data 0000 crc normal mode 1 0 1 0 1 y data 0000 crc normal mode 1 0 0 1 0 x data 0000 crc self-test mode 1 0 1 1 0 y data 0000 crc self-test mode 1 0 0 1 1 x data status flag crc error response 1 0 1 1 1 y data status flag crc error response table 42. error codes (continued)
docid028312 rev 3 47/58 ais1120sx / ais2120sx interface description 58 5.1.2 non-acceleration commands these commands are used to write/read control and status registers. figure 25. non-acceleration commands the function of the individual bits of sdi and sdo are shown in table 44 and table 45 . table 44. non-acceleration command function of sdi bits name bit position description definition op1:op0 [31:30] opcode operation type: 00: n/a 01: write 10: n/a 11: read sen 29 sen bit sensor data request type: 1: sensor data 0: non-sensor data p 28 parity bit odd parity bit, cover bit 31-8 not used [27:26] n/a always 0 a4:a0 [25:21] address register address for r/w operations d7:d0 [20:13] data data for write not used [12:8] n/a always 0 c7:c0 [7:0] crc crc bits for sdi
interface description ais1120sx / ais2120sx 48/58 docid028312 rev 3 table 45. non-acceleration commands function of sdo bits error codes are to be interpreted as follows: eeprom error (ee) : any error related to internal eeprom e.g. mismatch of internal crc. spi error (se) : any violation of spi format e.g. incorrect number of clocks during the frame, parity mismatch of sdi, or crc mismatch of sdi. request error (re) : set when unexpected or invalid command is received by sensor, locked registers are read or written during any undefined state of sensor. test mode (te) : set when the part is in test mode priority of error codes : ee (highest) -> se -> re -> te (lowest) 5.1.3 spi crc polynomial to check the integrity of the sensor signals (so) and commands (si) to the sensor, an 8-bit crc (cyclic redundancy check, baicheva c2) is used. the applied polynomial is: x 8 +x 5 +x 3 +x 2 +x+1 = 0x97 with: hd = 4 for 32-bit data initial value = 0000 0000b target value = 0x00 name bit position description definition sen 31 sen bit sensor data request type: 1: sensor data 0: non-sensor data op1:op0 [30:29] opcode copied from sdi request if accepted 00: n/a 01: write 10: n/a 11: read p 28 parity bit odd parity bit, cover bit 31-8 not used [27:26] n/a always 0 a4:a0 25:21 address register address for r/w operations d7:d0 20:13 data read data / error code not used 12 n/a always 0 sf3:sf0 [11:8] status flag bits 0000: no error 0001: eeprom error (ee) 0010: spi error (se) 0011: request error (re) 1111: in test mode (te) c7:c0 [7:0] crc crc bits for sdo
docid028312 rev 3 49/58 ais1120sx / ais2120sx interface description 58 5.2 32-bit spi bit information table 47. 32-bit spi command: bits from 15 to 0 table 46. 32-bit spi command: bits from 31 to 16 acceleration bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 sdi ch1 ch0 sen p 0 0 0 0 0 0 0 0 0 0 0 0 sdo sen ch1 ch0 p st1 st0 d13 d12 d1 1 d10 d9 d8 d7 d6 d5 d4 non-acceleration bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 sdi op1 op0 sen p 0 0 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 sdo sen op1 op0 p 0 0 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 acceleration bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdi 0 0 0 0 0 0 0 0 c7 c6 c5 c4 c3 c2 c1 c0 sdo d3 d2 d1 d0 sf3 sf2 sf1 sf0 c7 c6 c5 c4 c3 c2 c1 c0 non-acceleration bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdi d2d1 d0 0 0 0 0 0 c7c6c5c4c3c2c1c0 sdo d2 d1 d0 0 sf3 sf2 sf1 sf0 c7 c6 c5 c4 c3 c2 c1 c0 table 48. bit decoding ch[1:0] op[1:0] sen st[1:0] sf[3:0] 000 x data n/a non-sensor initialization no error 001 y data write sensor normal mode eeprom error 010 n/a n/a selt-test mode spi error (se) 011 n/a read error data request error (re) 100 condition not correct (cnc) 101 no data (nd) 110 hardware error (he) 1000 adc saturation (as) 1111 in test mode (te)
interface description ais1120sx / ais2120sx 50/58 docid028312 rev 3 5.3 timing parameters figure 26. spi timing parameters figure 27. additional spi timing parameters
docid028312 rev 3 51/58 ais1120sx / ais2120sx interface description 58 timing reference: 0.2 vs - 0.8 vs (vs = v vddd -d gnd ) explanation: c) q: sck stable (low or high) before cs falling d) p: sck stable (low or high) after cs rising table 49. spi timing table no. parameter symbol min. max. unit - spi operating frequency fop - 5 mhz a clock (sck) high time t wsckh 49 - ns b clock (sck) low time t wsckl 95 - ns c sck period t sck 200 - ns d clock (sck) and cs fall time t f 5.5 50 ns e clock (sck) and cs rise time t r 5.5 50 ns f data input (mosi) setup time t su 10 - ns g data input (mosi) hold time t hi 10 - ns h data output (miso) access time t a - 60 ns i data output (miso) valid after sck t v - 60 ns k data output (miso) disable time t dis - 100 ns l enable (ss) lead time t lead 10 - ns m enable (ss) lag time t lag 25 - ns n sequential transfer delay t td 1.9 - s p clock enable time t cle 10 - ns q clock disable time t cld 10 - ns
interface description ais1120sx / ais2120sx 52/58 docid028312 rev 3 5.4 error management the device replies with an error response if one of the following errors has occurred: table 50. error flags and description flags description reg_ctrl_0_wr_err ?1?: when there is a request error writing the reg_ctrl_0(address=0x00) register losscap ?1?: when there a loss of cap on vreg pad (set only during power-up) end_of_pwrup ?1?: when power-up sequencer has finished initialization (completed charge pump test, cap-loss test, fast offset cancel); rst_active ?1?: when soft reset is issued spi_err ?1?: when spi error occurs eeprom_err ?1?: when eeprom error (e.g mismatch in crc) occurs during power-up off_canc_chy_err ?1?: when offset cancellation error for chy occur off_canc_chx_err ?1?: when offset cancellation error for chx occurs reg_config_wr_err ?1?:when there is a request error writing the reg_config (address=0x012) register reg_ctrl_1_wr_err ?1?: when there is a request error writing the reg_ctrl_1 (address=0x01) register a2d_sat_chy ?1?: when a2d saturates for chy a2d_sat_chx ?1?: when a2d saturates for chx charge_pump_err ?1?: when charge pump test fails at power-up vreg_low_err ?1?: when vreg falls below its low threshold vreg_high_err ?1?: when vreg goes above its high threshold vdd_low_err ?1?: when vdd falls below its low threshold vdd_high_err ?1?: when vdd goes above its high threshold
docid028312 rev 3 53/58 ais1120sx / ais2120sx recommendations for operation 58 6 recommendations for operation 1. it's recommended to power up vdd first, then provide spi logic signals. this is recommended to avoid the potential of powering the device via the spi pins when vdd is not in the specified operating range. 2. recommended vdd ramp rate > 1 v/ms 3. it is recommended that all flags be reconfirmed with soft por after power-up.
package information ais1120sx / ais2120sx 54/58 docid028312 rev 3 7 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 7.1 soic8 package information figure 28. soic8 package outline b
docid028312 rev 3 55/58 ais1120sx / ais2120sx package information 58 figure 29. soic8 package marking table 51. soic8 package mechanical data ref. databook (mm) min. typ. max. a 1.75 a1 0.10 0.25 a2 1.25 b 0.31 0.51 c 0.10 0.25 d 4.80 4.90 5.00 e 5.80 6.00 6.20 e1 3.80 3.90 4.00 e 1.27 h 0.25 0.50 l 0.40 1.27 l1 1.04 l2 0.25 k0 8 ccc 0.10
package information ais1120sx / ais2120sx 56/58 docid028312 rev 3 figure 30. soic8 recommended footprint b
docid028312 rev 3 57/58 ais1120sx / ais2120sx revision history 58 8 revision history table 52. revision history date revision changes 18-sep-2015 1 initial release 19-aug-2016 2 updated section 5.1.3: spi crc polynomial 20-jan-2017 3 document status promoted to production data updated sdo pin load in table 33: electrical characteristics updated t sck and t v in table 49: spi timing table
ais1120sx / ais2120sx 58/58 docid028312 rev 3 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2017 stmicroelectronics ? all rights reserved

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