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sense & control data sheet revision 1.1, 2012-10-15 tli4961-1l TLI4961-1M hall effect latch for industrial applications
edition 2012-10-15 published by infineon technologies ag 81726 munich, germany ? 2012 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infine on technologies hereby disclaims any and all warranties and liabilities of any kind, including witho ut limitation, warranties of non-infrin gement of intellectua l property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies compon ents may be used in life-su pport devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
tli4961-1l TLI4961-1M data sheet 3 revision 1.1, 2012-10-15 trademarks of infineon technologies ag aurix?, c166?, canpak?, ci pos?, cipurse?, econopac k?, coolmos?, coolset?, corecontrol?, crossave?, dave?, easypim?, econobridge?, econ odual?, econopim?, eicedriver?, eupec?, fcos?, hitfet?, hybridpack?, i2rf?, isoface?, isopack?, mipaq?, modstack?, my-d?, novalithic?, optimos?, or iga?, primarion?, prim epack?, primestack?, pro-sil?, profet?, rasic?, reversave?, satric?, sieget?, sindrion?, sipmos?, smartlewis?, solid flash?, tempfe t?, thinq!?, trench stop?, tricore?. other trademarks advance design system? (ads) of agilent te chnologies, amba?, arm?, multi-ice?, keil?, primecell?, realview?, thumb?, vision? of arm limited, uk. autosar? is licensed by autosar development partnership. bluetooth? of bluetooth sig inc. cat-iq? of dect forum. colossus?, firstgps? of trimble navigation ltd. emv? of emvc o, llc (visa holdings in c.). epcos? of epcos ag. flexgo? of microsoft corp oration. flexray? is licensed by flexray consortium. hyperterminal? of hilgraeve incorporated. iec? of commission electrot echnique internationale. irda? of infrared data association corporation. iso? of international organization for standardization. matlab? of mathworks, inc. maxim? of maxim integrated products, inc. microtec?, nucleus? of mentor graphics corporation. mifare? of nx p. mipi? of mipi alliance, inc. mips? of mips technologies, inc., usa. murata? of murata manufacturing co., microwave offi ce? (mwo) of applied wave research inc., omnivision? of omnivision technologies, inc. open wave? openwave systems inc. red hat? red hat, inc. rfmd? rf micro devices, inc. sirius? of sirius sate llite radio inc. solaris? of sun microsystems, inc. spansion? of spansion llc ltd. symbian? of sy mbian software limited. taiyo yuden? of taiyo yuden co. teaklite? of ceva, inc. t ektronix? of tektroni x inc. toko? of toko kabushiki kaisha ta. unix? of x/open company limited. verilog?, palladium? of cadence design systems, inc. vlynq? of texas instruments inco rporated. vxworks?, wind river? of wind river systems, inc. zetex? of diodes zetex limited. last trademarks update 2011-02-24 revision history page or item subjects (major changes since previous revision) revision 1.1, 2012-10-15 ducument derivative added: tli4961-1l with pg-sso-3-2 package
tli4961-1l TLI4961-1M table of contents data sheet 4 revision 1.1, 2012-10-15 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1 product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3 target applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.5 functional block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6 default start-up behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4 electrical and magnetic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 package outline pg-sot23-3-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2 packing information pg-sot23-3-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3 footprint pg-sot23-3-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.4 package outline pg-sso-3-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.5 pg-sot23-3-15 distance between chip and package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.6 pg-sso-3-2 distance between chip and package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.7 package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table of contents
tli4961-1l TLI4961-1M list of figures data sheet 5 revision 1.1, 2012-10-15 figure 1-1 image of tli4961-1 in the pg-sot23-3-15 (l eft hand) and pg-sso-3-2 package (right hand) . . . 7 figure 2-1 pin configuration and center of sensitive area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2-2 functional block diagram tli4961-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 2-3 timing diagram tli4961-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 2-4 output signal tli4961-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 2-5 illustration of the start-up behavior of the tli4961- 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 3-1 application circuit 1: with external resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 3-2 application circuit 2: without exte rnal resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 3-3 definition of magnetic fiel d direction pg-sot23-3-15 (left hand ) and pg-sso-3-2 (right hand) . 15 figure 4-1 pg-sot23-3-15 package outline (all dimensions in mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 4-2 packing of the pg-sot23-3-15 in a tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 4-3 footprint pg-sot23-3-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 4-4 pg-sso-3-2 package outline (all dimensions in mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 4-5 distance between chip and package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 4-6 distance between chip and package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 4-7 marking of TLI4961-1M. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 4-8 marking of tli4961-1l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 list of figures
tli4961-1l TLI4961-1M list of tables data sheet 6 revision 1.1, 2012-10-15 table 1-1 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2-1 pin description pg-sot23-3-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 2-2 pin description pg-sso-3-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3-1 absolute maximum rating parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 3-2 esd protection (ta = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 3-3 operating conditions parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3-4 general electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3-5 magnetic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 list of tables
tli4961-1l TLI4961-1M product description data sheet 7 revision 1.1, 2012-10-15 1 product description 1) 1.1 overview figure 1-1 image of tli4961-1 in the pg-sot23-3-15 (left hand) and pg-sso-3-2 package (right hand) 1.2 features ? 3.0 v to 32 v operating supply voltage ? operation from unregulated power supply ? reverse polarity protection (-18 v) ? overvoltage capability up to 42 v without external resistor ? output overcurrent & overtemperature protection ? active error compensation ? high stability of magnetic thresholds ? low jitter (typ. 0.35 s) ? high esd performance ? leaded, non halogen-free package pg-sso-3-2 (tli4961-1l) ? small, halogen-free smd package pg-sot23-3-15 (TLI4961-1M) for automotive applications please refer to the infineon tle hall switches series. 1.3 target applications target applications for the tl i496x hall switch family are all applications which require a high precision hall switch with an operating temperature range from -40c to 125c. its superior supply voltage range from 3.0 v to 32 v with overvoltage capability up to 42 v with out external resistor makes it ideally suited for indust rial applications. the magnetic behavior as a latch and switching thresholds of typical 2 mt make the device especially suited for the use with a pole wheel for index counting applications and for rotor position detection as in brushless dc motor commutation. 1) only the pg-sot23-3-15 package (TLI4961-1M) is halogen-free. characteristic supply voltage supply current sensitivity interface temperature bipolar hall effect latch 3.0~32 v 1.6 ma b op :2 mt b rp :-2 mt open drain output -40c to 125c table 1-1 ordering information product name product type ordering code package tli4961-1l hall latch sp001052198 pg-sso-3-2 TLI4961-1M hall latch sp001031008 pg-sot23-3-15
tli4961-1l TLI4961-1M functional description data sheet 8 revision 1.1, 2012-10-15 2 functional description 2.1 general the tli4961-1 is an integrated hall effect designed spec ifically for highly accurate applications with superior supply voltage capability, and temperature stability of the magnetic thresholds. 2.2 pin configuration (top view) figure 2-1 pin configuration and center of sensitive area 2.3 pin description table 2-1 pin description pg-sot23-3-15 pin no. symbol function 1 vdd supply voltage 2 q output 3 gnd ground table 2-2 pin description pg-sso-3-2 pin no. symbol function 1 vdd supply voltage 2 gnd ground 3 q output center of sensitive area 3 2 1 pg-sso-3-2 2.08 0.1 1.35 0.1 1 1.45 0.1 0.65 0.1 2 3 sot23
tli4961-1l TLI4961-1M functional description data sheet 9 revision 1.1, 2012-10-15 2.4 block diagram figure 2-2 functional block diagram tli4961-1 2.5 functional block description the chopped hall ic switch comprises a hall probe, bias generator, compensation circ uits, oscillator and output transistor. the bias generator provides currents for the hall probe and the active circui ts. compensation circuits stabilize the temperature behavior and reduce influence of technology variations. the active error compensation (chopping technique) reje cts offsets in the signal path and the influence of mechanical stress to the hall probe caused by molding and soldering processes and other thermal stress in the package. the chopped measurement principle together with the threshold generator and the comparator ensures highly accurate and temperature stable magnetic thresholds. the output transistor has an integrated overcurrent and overtemperature protection. voltage regulator bias and compensation circuits oscillator and sequencer to all subcircuits spinning hall probe chopper multiplexer amplifier demodulator low pass filter comparator with hysteresis control overtemperature & overcurrent protection gnd q v dd reference
tli4961-1l TLI4961-1M functional description data sheet 10 revision 1.1, 2012-10-15 figure 2-3 timing diagram tli4961-1 figure 2-4 output signal tli4961-1 applied magnetic field 90% 10% v q t f t d t r t d b op b rp v q b op b rp 0 b
tli4961-1l TLI4961-1M functional description data sheet 11 revision 1.1, 2012-10-15 2.6 default start-up behavior the magnetic thresholds exhibit a hysteresis b hys =b op -b rp . in case of a power-on with a magnetic field b within hysteresis (b op >b>b rp ) the output of the sensor is set to the pull up voltage level (v q ) per default. after the first crossing of b op or b rp of the magnetic field the internal decision logic is set to the corresponding magnetic input value. v dda is the internal supply voltage which is following the external supply voltage v dd . this means for b > b op the output is switching, for b < b rp and b op >b>b rp the output stays at v q . figure 2-5 illustration of the start-up behavior of the tli4961-1 t 3v t t v q t b > b op b < b rp b op > b > b rp magnetic field above threshold magnetic field below threshold magnetic field in hysteresis power on ramp the device always applies v q level at start -up independent from the applied magnetic field ! v q v q v dda t pon
tli4961-1l TLI4961-1M specification data sheet 12 revision 1.1, 2012-10-15 3 specification 3.1 application circuit the following figure 3-1 shows one option of an application circ uit. as explained above the resistor r s can be left out (see figure 3-2 ). the resistor r q has to be in a dimension to match the applied v s to keep i q limited to the operating range of maximum 25 ma. e.g.: v s = 12 v i q = 12 v/1200 ? = 10 ma figure 3-1 application circuit 1: with external resistor figure 3-2 application circuit 2: without external resistor tli496x gnd vs r q = 1.2k c dd = 47nf v dd q tvs diode e.g. esd24vs2u r s = 100 note: the tvs diode is only required for esd robustness >4kv tli496x gnd vs r q = 1. 2k c dd = 47nf v dd q tvs diode e.g. esd24vs2u note: the tvs diode is only required for esd robustness >4kv
tli4961-1l TLI4961-1M specification data sheet 13 revision 1.1, 2012-10-15 3.2 absolute maximum ratings attention: stresses above the max. values listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. calculation of the dissipated power p dis and junction temperature t j of the chip (sot23 example): e.g. for: v dd = 12 v, i s = 2.5 ma, v qsat = 0.5 v, i q = 20 ma power dissipation: p dis = 12 v x 2.5 ma + 0.5 v x 20 ma = 30 mw + 10 mw = 40 mw temperature ? t = r thja x p dis = 300 k/w x 40 mw = 12 k for t a = 50 c: t j = t a + ? t = 50 c + 12 k = 62 c table 3-1 absolute maxi mum rating parameters parameter symbol values unit note / test condition min. typ. max. supply voltage 1) 1) this lifetime statem ent is an anticipation based on an extrapolation of in fineon?s qualification test results. the actual lif etime of a component depends on its form of applic ation and type of use etc. and may de viate from such st atement. the lifetime statement shall in no event extend the agreed warranty period. v dd -18 32 42 v 10h, no external resistor required output voltage v q -0.5 32 v reverse output current i q -70 ma junction temperature 1) t j -40 150 c for 2000h storage temperature t s -40 150 c thermal resistance junction ambient r thja 200 300 k/w for pg-sso-3-2 (2s2p) for pg-sot23-3-15 (2s2p) thermal resistance junction lead r thjl 150 100 k/w for pg-sso-3-2 for pg-sot23-3-15 table 3-2 esd protection 1) (ta = 25c) 1) characterization of esd is carried out on a sample basis, not subject to production test. parameter symbol values unit note / test condition min. typ. max. esd voltage (hbm) 2) 2) human body model (hbm) tests acco rding to ansi/esda/jedec js-001. v esd -4 4 kv r = 1.5 k ? , c = 100 pf esd voltage (cdm) 3) 3) charge device model (cdm) tests according to jesd22-c101. -1 1 esd voltage (system level) 4) 4) gun test (2k ? / 330pf or 330 ? / 150pf) according to iso 10605-2008. -15 15 with circuit shown in figure 3-1 & figure 3-2
tli4961-1l TLI4961-1M specification data sheet 14 revision 1.1, 2012-10-15 3.3 operating range the following operating conditions must not be exceeded in order to ensure correct operation of the tli4961-1. all parameters specified in the followi ng sections refer to these operating conditions unless otherwise mentioned. 3.4 electrical and magnetic characteristics product characteristics involve the spread of values guaranteed within the specified voltage and ambient temperature range. typical characteristics are th e median of the production and correspond to v dd = 12 v and ta = 25c. the below listed specification is valid in combination with the application circuit shown in figure 3-1 and figure 3-2 table 3-3 operating conditions parameters parameter symbol values unit note / test condition min. typ. max. supply voltage v dd 3.0 32 1) 1) latch-up test with factor 1.5 is not covered. please see max ratings also. v output voltage v q -0.3 32 v junction temperature t j -40 125 c output current i q 025ma magnetic signal input frequency 2) 2) for operation at the maximum switching fr equency the magnetic input signal must be 1.4 times higher than for static fields. this is due to the -3db corner frequency of the internal low-pass filter in the signal path. f sw 010khz table 3-4 general electrical characteristics parameter symbol values unit note / test condition min. typ. max. supply current i s 1.11.62.5ma reverse current i sr 0.05 1 ma for v dd = -18 v output saturation voltage v qsat 0.2 0.5 v i q = 20 ma 0.24 0.6 v i q = 25 ma output leakage current i qleak 10 a output current limitation i qlimit 30 56 70 ma internally limited & thermal shutdown output fall time 1) 1) not subject to production test, ve rified by design/characterization. t f 0.17 0.4 1 s1.2k ? / 50 pf, see figure 2-3 output rise time 1) t r 0.4 0.5 1 s1.2k ? / 50 pf, see figure 2-3 output jitter 1)2) 2) output jitter is the 1 value of the output switching distribution. t qj 0.35 1 s for square wave signal with 1 khz delay time 1)3) 3) systematic delay between magnetic threshold reached and output switching. t d 12 15 30 ssee figure 2-3 power-on time 1)4) 4) time from applying v dd = 3.0 v to the sensor until the output is valid. t pon 80 150 sv dd =3v,b b rp -0.5mtor b b op +0.5mt chopper frequency 1) f osc 350 khz
tli4961-1l TLI4961-1M specification data sheet 15 revision 1.1, 2012-10-15 field directio n definition positive magnetic fields are defi ned with the south pole of the magne t to the branded side of package. figure 3-3 definition of magnetic field direction pg-sot23-3-15 (left hand) and pg-sso-3-2 (right hand) table 3-5 magnetic characteristics parameter symbol t (c) values unit note / test condition min. typ. max. operating point b op -40 0.6 2.1 3.6 mt 25 0.5 2.0 3.5 125 0.3 1.8 3.2 release point b rp -40 -3.6 -2.1 -0.6 mt 25 -3.5 -2.0 -0.5 125 -3.2 -1.8 -0.3 hysteresis b hys -40 2.5 4.2 5.9 mt 25 2.4 4.0 5.6 125 2.1 3.2 5.0 effective noise value of the magnetic switching points 1) 1) the magnetic noise is normal distributed and can be assu med as nearly independent to fr equency without sampling noise or digital noise effects. the typical value represen ts the rms-value and corresponds therefore to a 1 probability of normal distribution. consequently a 3 value corresponds to 99.7% probability of appearance. b neff 25 62 t temperature compensation of magnetic thresholds 2) 2) not subject to production test, ve rified by design/characterization. t c -1200 ppm/k n s branded side n s
tli4961-1l TLI4961-1M package information data sheet 16 revision 1.1, 2012-10-15 4 package information the tli4961-1 is available in the small halogen free smd package pg-sot23-3-15 and the through-hole leaded package pg-sso-3-2. 4.1 package outline pg-sot23-3-15 figure 4-1 pg-sot23-3-15 package outline (all dimensions in mm) 4.2 packing information pg-sot23-3-15 figure 4-2 packing of the pg-sot23-3-15 in a tape 0.25 m bc 1.9 -0.05 +0.1 0.4 0.1 2.9 0.95 c b 0. . . 8 0.2 a 0.1 max. 10 max. 0 . 0 8 . . . 0 . 1 5 1.3 0.1 10 max. m 2.4 0.15 0.1 1 a 0.15 min. 1) 1) lead width can be 0.6 max. in dambar area 12 3 sot23-tp v02 3.15 4 2.65 2.13 0.9 8 0.2 1.15 pin 1
tli4961-1l TLI4961-1M package information data sheet 17 revision 1.1, 2012-10-15 4.3 footprint pg-sot23-3-15 figure 4-3 footprint pg-sot23-3-15 reflow soldering wave soldering 0.8 0.8 1.2 0. 9 1. 3 0.9 0.8 0.8 1.2 1. 6 1. 4 min 1. 4 min
tli4961-1l TLI4961-1M package information data sheet 18 revision 1.1, 2012-10-15 4.4 package outline pg-sso-3-2 figure 4-4 pg-sso-3-2 package outline (all dimensions in mm) total tolerance at 10 pitches 1 1) no solder function area 0.3 0.4 6.35 12.7 12.7 1 0.5 0.5 4 0.3 9 -0.15 0.1 tape adhesive tape 0.25 0.39 0.5 a 18 6 23.8 0.5 38 max. -1 1 13 2 1.27 0.6 max. 0.4 0.05 1) 1max. 0.15 max 1.9 max. 4.06 0.08 4.16 0.05 0.08 3.29 3 0.06 0 . 2 (0.25) x45 ? 2 0.8 0.1 7 ? 2 x45 ? 2 0.1 0.35 0.2 +0.04 7 2 ? (0.79) a 2 1.52 0.05 b 0.5 3x b c 2 c 2x
tli4961-1l TLI4961-1M package information data sheet 19 revision 1.1, 2012-10-15 4.5 pg-sot23-3-15 distance between chip and package figure 4-5 distance between chip and package 4.6 pg-sso-3-2 distance between chip and package figure 4-6 distance between chip and package 4.7 package marking figure 4-7 marking of TLI4961-1M pg-sso-3-2 : 0.64 d : distance chip to upper side of ic mm 0.05 hall-probe branded side d year (y) = 0...9 month ( m) = 1...9 , o-october n-november d-december y m i11
tli4961-1l TLI4961-1M package information data sheet 20 revision 1.1, 2012-10-15 figure 4-8 marking of tli4961-1l year (y) = 0...9 calendar week (ww) = 01 ...52 yyww i11
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