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i ntegrated c ircuits d ivision ds-ix21844-r01 www.ixysic.com 1 driver characteristics features ? floating channel for bootst rap operation to +600v with an absolute maximum rating of +700v ? programmable dead-time ? outputs can source 1.4a and sink 1.8a ? gate drive supply range from 10v to 20v ? tolerant to negative voltage transients: dv/dt immune ? 3.3v and 5v logic compatible ? undervoltage lockout for both high-side and low-side outputs ? matched propagation delays applications ? switch mode power supply ? motor driver inverter ? dc/dc converter ? uninterruptible power supplies (ups) description the ix21844 is a high voltage ic that can drive high speed mosfets and igbts that operate up to +600v. the ix21844 is configured with dependent high-side and low side referenced output channels which can source 1.4a and sink 1.8a. the floating high-side channel can dr ive an n-channel power mosfet or igbt 600v from the common reference. manufactured on ixys integrated circuits division's proprietary high-voltage bcdmos on soi (silicon on isolator) process, the ix21844 is extremely robust and virtually immune to negative transients. the uvlo circuit prevents the turn-on of the mosfet or igbt until there is sufficient v bs or v cc supply voltage. a programmable dead-time can be set between 400ns and 5us to insure that both the high-side and low-side power mosfet or igbt are not enabled at the same time. propagation delays are matched for use in high frequency applications. the ix21844 is available in 14-pin dip and 14-pin soic (narrow body) packages. the 14-pin soic (narrow body) package is also available in tape & reel. ordering information ix21844 functional block diagram parameter rating units v offset 600 v i o +/- (source/sink) 1.4 / 1.8 a v bias 10-20 v part description ix21844g 14-pin dip (25/tube) ix21844n 14-pin soic (narrow body) (50/tube) IX21844NTR 14-pin soic (narrow body) (2000/reel) level shift v ss / com ls delay control level shift v ss / com uvlo high voltage level shift uvlo pulse generator r r s q buffer in dt v ss v b ho v s v cc lo com input & dead-time control logic buffer +5v sd ix21844 high voltage half-bridge gate driver
i ntegrated c ircuits d ivision ix21844 2 www.ixysic.com r01 1. specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 package pino u t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 pin description (dip & soic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 absol u te maxim u m ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.5 static electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.6 dynamic electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.7 test wa v eforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2. performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3. manufacturing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 moist u re sensiti v ity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 esd sensiti v ity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 reflow profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 board wash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.5 mechanical dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
i ntegrated c ircuits d ivision ix21844 r01 www.ixysic.com 3 1 specifications 1.1 package pinout 1.2 pin description (dip & soic) in 1 v cc 7 v ss 3 com 5 lo 6 dt 4 14 n/c 8 n/c 13 v b 12 ho 10 n/c 9 n/c 11 v s sd 2 pin# name description 1i n logic input for both high-side gate drive output (ho) and low-side gate drive output (lo). in phase with ho. 2sd shut-down logic input. active low. 3 v ss logic ground 4dt programmable dead-time input 5com low-side return 6lo low-side gate drive output 7 v cc low-side and logic supply 8 n /c no connection 9 n /c no connection 10 n /c no connection 11 v s high-side floating supply return 12 ho high-side gate drive output 13 v b high-side floating supply 14 n /c no connection
i ntegrated c ircuits d ivision 4 www.ixysic.com r01 ix21844 1.3 absolute maximum ratings absolute maximum ratings indicate sustained limits be yond which damage to the device may occur. all voltage parameters are absolute voltages referenced to com. 1.4 recommended operating conditions for proper operation, the device should be used within the recommended conditions. the v s and v ss offset ratings are tested with all supplies biased at a 15v differential. parameter symbol min max units high-side floating absol u te v oltage v b -0.3 700 v high-side floating s u pply offset v oltage v s v b -20 v b +0.3 high-side floating o u tp u t v oltage v ho v s -0.3 v b +0.3 low-side and logic fixed s u pply v oltage v cc -0.3 20 low-side o u tp u t v oltage v lo -0.3 v cc +0.3 programmable dead-time pin v oltage dt v ss -0.3 v cc +0.3 logic inp u t v oltage v i n , v sd v ss -0.3 v cc +0.3 logic gro u nd v ss v cc -20 v cc +0.3 allowable offset s u pply v oltage transient d v s /dt -5 0v / n s package power dissipation @ t a ? 25c 14-pin pdip pd -1 . 6 w 14-pin soic -1 thermal resistance, j u nction to ambient 14-pin pdip r ? ja -7 5 c/w 14-pin soic -1 2 0 j u nction temperat u re t j -1 5 0 c storage temperat u re t s -50 150 lead temperat u re (soldering, 10 seconds) t l -3 0 0 parameter symbol min max units high-side floating s u pply absol u te v oltage v b v s +10 v s +20 v high-side floating s u pply offset v oltage v s -5 600 high-side floating o u tp u t v oltage v ho v s v b low-side and logic fixed s u pply v oltage v cc 10 20 low-side o u tp u t v oltage v lo 0 v cc logic inp u t v oltage v i n , v sd v ss v ss + 5 programmable dead-time pin v oltage dt v ss v cc logic gro u nd v ss -5 5 ambient temperat u re t a -40 +125 c
i ntegrated c ircuits d ivision ix21844 r01 www.ixysic.com 5 1.5 static electrical characteristics v bias (v cc , v bs )=15v, v ss =com, dt=v ss , and t a =25c unless otherwise specified. the v il , v ih , and i in parameters are referenced to v ss /com and are applicable to the respective input leads: in and sd . v o and i o are referenced to com and are applicable to the respective output leads: ho and lo. 1.6 dynamic electrical characteristics v bias (v cc , v bs )=15v, c l =1000pf, t a =25c, dt=v ss , and v ss =com unless otherwise specified. parameter conditions symbol min typ max units logic ?1? inp u t v oltage v cc =10 v to 20 v v ih 2-- v logic ?0? inp u t v oltage v il --0.8 sd inp u t positi v e going threshold v sd,th+ 2-- sd inp u t n egati v e going threshold v sd,th- --0.8 high le v el o u tp u t v oltage, v bias - v o i o =0a v oh --2.5 low le v el o u tp u t v oltage, v o i o =20ma v ol --0.2 offset s u pply leakage c u rrent v b = v s =600 v i lk -3360 ? a q u iescent v bs s u pply c u rrent v i n =0 v or 5 v i qbs 20 87 150 q u iescent v cc s u pply c u rrent i qcc 0.4 1.8 2.2 ma logic ?1? inp u t bias c u rrent i n =5 v i i n + -3560 ? a logic ?0? inp u t bias c u rrent i n =0 v i i n - --1 sd logic ?1? inp u t bias c u rrent v sd =5 v i sd+ --30 ? a sd logic ?0? inp u t bias c u rrent v sd =0 v i sd- -1560 ? a v cc and v bs s u pply under-v oltage positi v e going threshold - v ccu v + v bsu v + 88.69.8 v v cc and v bs s u pply under-v oltage n egati v e going threshold v ccu v - v bsu v - 7.4 7.9 9 hysteresis v ccu v h v bsu v h 0.3 0.7 - o u tp u t high short circ u it p u lsed c u rrent v o =0 v , pw< 10 ? s i o + 1.4 2.2 - a o u tp u t low short circ u it p u lsed c u rrent v o =15 v , pw< 10? s i o - 1.8 2.5 - parameter conditions symbol min typ max units t u rn-on propagation delay v s =0 v t on -560900 ns t u rn-off propagation delay v s =0 v or 600 v t off -200400 sh u tdown propagation delay - t sd -225400 delay matching, hs & ls t u rn-on mton - 0 90 delay matching, hs & ls t u rn-off mtoff - 0 40 t u rn-on rise time v s =0 v t r -2360 t u rn-off fall time t f -1435 dead-time: lo t u rn-off to ho t u rn-on (dt lo-ho ) & ho t u rn-off to lo t u rn-on (dt ho-lo ) r dt =0 ? dt 280 355 520 r dt =200k ? 456 ? s dead-time matching: (dt lo-ho ) - (dt ho-lo ) r dt =0 ? mdt -050 ns r dt =200k ? -0600
i ntegrated c ircuits d ivision 6 www.ixysic.com r01 ix21844 1.7 test waveforms 1.7.1 switching time test circ u it 1.7.2 inp u t/o u tp u t timing diagram 1.7.3 sh u tdown wa v eform definition 1.7.4 dead-time wa v eform definition 1.7.5 delay matching wa v eform definitions 1.7.6 switching time wa v eform definitions 1.7.7 tr u th table 1 2 3 v ss 4 dt 5 com 6 7 v cc 14 13 12 v s 11 10 9 8 10 f0.1 f c l 10 f0.1 f c l in sd lo v cc =15v v b =15v ho in sd ho lo sd ho lo 50% 90% t sd in ho lo 50% 50% 10% 10% 90% 90% dt lo-ho dt ho-lo mdt= dt lo-ho - dt ho-lo in sd ho lo 11 hl 01 lh x0 ll lo ho mt mt 10% 90% lo ho in (lo) in (ho) 50% 50% in (lo) in (ho) lo ho 50% 50% 10% 10% 90% 90% t off t on t r t f
i ntegrated c ircuits d ivision ix21844 r01 www.ixysic.com 7 2 performance characteristics temperature (oc) -50 0 50 100 150 delay (ns) 300 400 500 600 700 800 900 1000 turn-on propa g ation delay vs. temperature -25 25 75 125 supply volta g e (v) 10 12 14 16 1 8 20 delay (ns) 300 400 500 600 700 800 900 1000 turn-on propa g ation delay vs. v bias supply volta g e supply volta g e (v) 10 12 14 16 1 8 20 delay (ns) 0 100 200 300 400 500 turn-off propa g ation delay vs. v bias supply volta g e supply volta g e (v) 10 12 14 16 1 8 20 rise time (ns) 0 10 20 30 40 50 turn-on rise time vs. v bias supply volta g e temperature (oc) delay (ns) 0 100 200 300 400 500 turn-off propa g ation delay vs. temperature -50 0 50 100 150 -25 25 75 125 temperature (oc) rise time (ns) 0 10 20 30 40 50 turn-on rise time vs. temperature -50 0 50 100 150 -25 25 75 125 temperature (oc) fall time (ns) 0 10 20 30 40 50 turn-off fall time vs. temperature -50 0 50 100 150 -25 25 75 125 supply volta g e (v) 10 12 14 16 1 8 20 fall time (ns) 0 10 20 30 40 50 turn-off fall time vs. v bias supply volta g e supply volta g e (v) 10 12 14 16 1 8 20 deadtime (ns) 0 100 200 300 400 500 600 deadtime vs. v bias supply volta g e (r dt =0) r dt (k) 0 50 100 150 200 deadtime (s) 0 1 2 3 4 5 6 deadtime vs. r dt temperature (oc) deadtime (ns) 0 100 200 300 400 500 600 deadtime vs. temperature (r dt =0) -50 0 50 100 150 -25 25 75 125 supply volta g e (v) 10 12 14 16 1 8 20 delay (ns) 0 50 100 150 200 250 300 350 400 sd propa g ation delay vs. v bias supply volta g e
i ntegrated c ircuits d ivision 8 www.ixysic.com r01 ix21844 supply volta g e (v) 10 12 14 16 1 8 20 threshold (v) 0 1 2 3 4 5 sd input positive goin g threshold vs. v bias supply volta g e temperature (oc) delay (ns) 0 50 100 150 200 250 300 350 400 sd propa g ation delay vs. temperature -50 0 50 100 150 -25 25 75 125 temperature (oc) threshold (v) 0 1 2 3 4 5 sd input positive goin g threshold vs. temperature -50 0 50 100 150 -25 25 75 125 temperature (oc) threshold (v) 0 1 2 3 4 5 sd input negative going threshold vs. temperature -50 0 50 100 150 -25 25 75 125 supply volta g e (v) 10 12 14 16 1 8 20 threshold (v) 0 1 2 3 4 5 sd input negative going threshold vs. v bias supply volta g e temperature (oc) uv threshold (-) (v) v cc and v bs undervolta g e threshold (-) vs. temperature -50 0 50 100 150 -25 25 75 125 0 3 6 9 12 15 supply volta g e (v) 10 12 14 16 1 8 20 supply current ( a) 0 50 100 150 200 250 v bs floating supply current vs. v bs floating supply volta g e temperature (oc) uv threshold (+) (v) 0 3 6 9 12 15 v cc and v bs undervolta g e threshold (+) vs temperature -50 0 50 100 150 -25 25 75 125 temperature (oc) supply current ( a) 0 50 100 150 200 250 v bs supply current vs. temperature -50 0 50 100 150 -25 25 75 125 temperature (oc) supply current (ma) 0 1 2 3 4 5 v cc supply current vs. temperature (v cc =15v) -50 0 50 100 150 -25 25 75 125 supply volta g e (v) 10 12 14 16 1 8 20 supply current (ma) 0 1 2 3 4 5 v cc supply current vs. v cc supply volta g e temperature (oc) leaka g e current (a) 0 25 50 75 100 offset supply leaka g e current vs. temperature -50 0 50 100 150 -25 25 75 125
i ntegrated c ircuits d ivision ix21844 r01 www.ixysic.com 9 temperature (oc) bias current (a) 0 20 40 60 80 100 logic "1" input bias current vs. temperature -50 0 50 100 150 -25 25 75 125 supply volta g e (v) 10 12 14 16 1 8 20 bias current (a) 0 20 40 60 80 100 logic "1" input bias current vs. v cc supply volta g e supply volta g e (v) 10 12 14 16 1 8 20 bias current (a) 0 1 2 3 4 5 logic "0" input bias current vs. v cc supply volta g e supply volta g e (v) 10 12 14 16 1 8 20 input volta g e (v) 0 1 2 3 4 5 6 log ic "1" input volta g e vs. v cc supply volta g e temperature (oc) bias current (a) 0 1 2 3 4 5 logic "0" input bias current vs. temperature -50 0 50 100 150 -25 25 75 125 temperature (oc) input volta g e (v) 0 1 2 3 4 5 6 log ic "1" input volta g e vs. temperature -50 0 50 100 150 -25 25 75 125 temperature (oc) input volta g e (v) 0 1 2 3 4 5 6 log ic "0" input volta g e vs. temperature -50 0 50 100 150 -25 25 75 125 supply volta g e (v) 10 12 14 16 1 8 20 input volta g e (v) 0 1 2 3 4 5 6 log ic "0" input volta g e vs. v cc supply volta g e supply volta g e (v) 10 12 14 16 1 8 20 output volta g e (v) 0 1 2 3 4 5 hig h level output (v bias -v o ) vs. v bias supply volta g e supply volta g e (v) 10 12 14 16 1 8 20 output volta g e (v) 0 0.2 0.4 0.6 0.8 1.0 low level output volta g e (v o ) vs. v bias supply volta g e temperature (oc) output volta g e (v) 0 1 2 3 4 5 hig h level output volta g e (v bias - v o ) vs. temperature -50 0 50 100 150 -25 25 75 125 temperature (oc) -50 0 50 100 150 output volta g e (v) 0.0 0.2 0.4 0.6 0.8 1.0 low level output volta g e (v o ) vs. temperature -50 0 50 100 150 -25 25 75 125
i ntegrated c ircuits d ivision 10 www.ixysic.com r01 ix21844 supply volta g e (v) 10 12 14 16 1 8 20 output sink current (a) 0 1 2 3 4 5 output sink current vs. v bias supply volta g e temperature (oc) -50 -25 0 25 50 75 100 125 150 output source current (a) 0 1 2 3 4 5 output source current vs. temperature supply volta g e (v) 10 12 14 16 1 8 20 output source current (a) 0 1 2 3 4 5 output source current vs. v bias supply volta g e temperature (oc) -50 -25 0 25 50 75 100 125 150 output source current (a) 0 1 2 3 4 5 output sink current vs. temperature
i ntegrated c ircuits d ivision ix21844 r01 www.ixysic.com 11 figure 1. typical connection diagram v cc v cc in in dt v ss v ss com lo v s v b ho load up to 600v sd sd r dt
i ntegrated c ircuits d ivision 12 www.ixysic.com r01 ix21844 3 manufacturing information 3.1 moisture sensitivity all plastic encapsulated semiconductor packages are susc eptible to moisture ingression. ixys integrated circuits division clas sified all of its plastic encapsulated devices for moisture sensitivity according to the latest version of the joint industry standard, ipc/jedec j-std-020 , in force at the time of product evaluation. we test all of our products to the maximum conditions set forth in the standard, and guarantee proper operation of our devices when handled according to the limitations and information in that standard as well as to any limitations set forth in the information or standards referenced below. failure to adhere to the warnings or limitations as establ ished by the listed specificati ons could result in reduced product performance, reduction of operable life, and/or reduction of overall reliability. this product carries a moisture sensitivity level (msl) rating as shown below, and should be handled according to the requirements of the latest version of the joint industry standard ipc/jedec j-std-033 . 3.2 esd sensitivity this product is esd sensitive , and should be handled according to the industry standard jesd-625 . 3.3 reflow profile this product has a maximum body temperature and time rating as shown below. all other guidelines of j-std-020 must be observed. 3.4 board wash ixys integrated circuits division recommends the use of no-clean flux formulations. however, board washing to remove flux residue is acceptable, and the use of a short drying bake may be necessary. chlorine-based or fluorine-based solvents or fluxes should not be used. clean ing methods that employ ultrasonic energy should not be used. device moisture sensitivity level (msl) rating ix21844g / ix21844 n msl 1 device maximum temperature x time ix21844g (dip) 245c for 30 seconds ix21844 n (soic) 260c for 30 seconds
i ntegrated c ircuits d ivision ix21844 r01 www.ixysic.com 13 3.5 mechanical dimensions 3.5.1 ix21844g 14-pin dip package 3.5.2 ix21844 n 14-pin soic ( n arrow body) package n otes: 1. jedec o u tline: ms-001 aa. 2. this dimension does not incl ude mold flash or protr u sions. mold flash or protr usions shall not exceed 0.254 (0.010). 3. meas ured at the lead tips with the leads u nconstrained. 4. pointed or ro u nded lead tips are preferred to ease insertion. 5. distance betw een leads including dam bar protr usions to be 0.127 (0.005). 6. dat um plane h coincident with the bottom of lead w here lead exits b ody. dimensions (min / max) mm (inches) pin 1 8.509 / 9.525 (0.335 / 0.375) see note 3 7.62 bsc (0.300 bsc) 18.542 / 19.050 (0.730 / 0.750) see note 2 2.921 / 3.810 (0.115 / 0.150) 0.381 min (0.015 min) 0.457 typ (0.018 typ) 2.542 (0.100) 3.175 / 3.429 (0.125 / 0.135) 1.524 typ (0.06 typ) 6.223 / 6.477 (0.245 / 0.255) see note 2 pcb hole pattern 7.62 (0.300) 2.54 (0.100) 1.35 (0.053) 0.85 (0.0335) hole size = 5.334 max (0.210 max) h seating plane 0o / 15o n otes: 1. jedec o u tline: ms-012 ab re v f. (reference) 2. molded package dimension do not incl ude mold flash, protr u sions, or gate bu rrs. mold flash, protr u sions, and gate bu rrs shall not exceed 0.15 (0.006) per side. 3. lead dimensions do not incl ude inter-lead flash or protr u sions. inter-lead flash and protr usions shall not exceed 0.25 (0.010) per side. dimensions min / max mm (inches) pcb pattern 5.98 / 6.02 (0.235 / 0.237) 8.65 bsc (0.341 bsc) see note 2 0.4 / 0.95 (0.016 / 0.037) 1.27 typ (0.05 typ) 0.15 / 0.25 (0.006 / 0.010) 0.37 x 45o (0.015 x 45o) 0.31 / 0.51 (0.012 / 0.020) 3.90 bsc (0.154 bsc) see note 3 1.25 min (0.049 min) 0.10 / 0.25 (0.004 / 0.010) 1.75 max (0.069 max) 0o / 8o 5.30 (0.209) 1.50 (0.059) 0.60 (0.024) 1.27 (0.05)
i ntegrated c ircuits d ivision 14 www.ixysic.com r01 ix21844 3.5.3 ix21844 n tr tape & reel packaging n otes: 1. all dimensions in millimeters 2. 10 sprocket hole pitch c um ulativ e tolerance 0.20. 3. carrier cam ber is within 1mm in 250mm. 4. tape material : black cond uctiv e polystyrene alloy. 5. all dimensions meet eia-4 81-c requ irements. 6. thickness : 0.30 0.05mm. 7.50 0.10 16.00 0.30 1.75 0.10 8.00 0.10 4.00 0.10 2.00 0.10 9.65 0.10 6.50 1.20 2.85 0.10 2.35 0.10 6.55 0.10 3.50 ?1.50 +0.1, -0 ?1.50 min embossment emb ossed carrier top co v er tape thickness 0.102 max. (0.004 max.) 330.2 dia. (13.00 dia.) for additional information please visit our website at: www.ixysic.com ixys integrated circuits division makes no representations or wa rranties with respect to the a ccuracy or completeness of the co ntents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. neither circuit patent licenses nor indemnity ar e expressed or implied. except as set forth in ixys integrated circuits division?s standard terms and condit ions of sale, ixys integrated circuits division assumes no liability whatsoever, a nd disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringem ent of any intellectual property right. the products described in this document are not designed, intended, authorized or warranted for use as components in systems in tended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of ixys integrated circuits division?s product may resul t in direct physical harm, injury, or death to a person or severe property or environmental damage. ixys integrated circuits divisi on reserves the right to discontinue or make changes to its pr oducts at any time without notice. specification: ds-ix21844-r01 ?copyright 2013, ixys integrated circuits division all rights reserved. printed in usa. 12/19/2013

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