cystech electronics corp. spec. no. : c064n3 issued date : 2016.08.16 revised date : page no. : 1/9 mta040p02kn3 cystek product specification -20v p-channel enhancement mode mosfet mta040p02kn3 bv dss -20v i d @ v gs =-4.5v , t a =25 c -4.3a r dson @v gs =-4.5v, i d =-4a 37.5m (typ) r dson @v gs =-2.5v,i d =-4a 52.4m (typ) r dson @v gs =-1.8v,i d =-2a 76.6m (typ) features ? for load switch application only ? compact and low profile sot-23 package ? advanced trench process technology ? high density cell design for ultra low on resistance ? esd protected gate ? pb-free lead plating package symbol outline ordering information device package shipping MTA040P02KN3-0-T1-G sot-23 (pb-free lead plating and halogen-free package) 3000 pcs / tape & reel mta040p02kn3 sot-23 d g gate s source d drain g s environment friendly grade : s for rohs compliant products, g for rohs compliant and green compound products packing spec, t1 : 3000 pcs / tape & reel, 7? reel product rank, zero for no rank products product name
cystech electronics corp. spec. no. : c064n3 issued date : 2016.08.16 revised date : page no. : 2/9 mta040p02kn3 cystek product specification absolute maximum ratings (ta=25 c) parameter symbol limits unit drain-source voltage v ds -20 gate-source voltage v gs 8 v continuous drain current @ t a =25 c , v gs =-4.5v (note 4) -4.3 continuous drain current @ t a =70 c, v gs =-4.5v (note 4) i d -3.4 pulsed drain current (notes 1, 2) i dm -30 a esd susceptibility (note 3) v esd 1500 v p d 1.25 w maximum power dissipation (note 4) linear derating factor 0.01 w/ c operating junction and storage temperature range tj ; tstg -55~+150 c note : 1. pulse width limited by maximum junction temperature. 2. pulse width 300 s, duty cycle 2%. 3. human body model, 1.5k in series with 100pf 4. surface mounted on 1 in2 copper pad of fr-4 board; 270 c/w when mounted on minimum copper pad thermal performance parameter symbol limit unit thermal resistance, junction-to-ambient(pcb mounted) r ja 100 c/w note : surface mounted on 1 in2 copper pad of fr-4 board; 270 c/w when mounted on minimum copper pad electrical characteristics (tj=25 c, unless otherwise noted) symbol min. typ. max. unit test conditions static bv dss -20 - - v v gs =0v, i d =-250 a ? bv dss / ? tj - 0.01 - v/ c reference to 25c, i d =-250 a v gs(th) -0.5 - -1.0 v v ds =v gs , i d =-250 a i gss - - 2 10 v gs = 2 8v, v ds =0v - - -1 v ds =-16v, v gs =0v i dss - - -10 a v ds =-16v, v gs =0v (tj=70 c) - 37.5 50 i d =-4a, v gs =-4.5v - 52.4 75 i d =-4a, v gs =-2.5v *r ds(on) - 76.6 155 m i d =-2a, v gs =-1.8v *g fs - 8.4 - s v ds =-10v, i d =-4a source-drain diode *v sd - -0.79 -1 v v gs =0v, i s =-1a trr - 8.6 - ns qrr - 3.1 - nc v gs =0v, i f =-4a, di f /dt=100a/ s *pulse test : pulse width 300 s, duty cycle 2%
cystech electronics corp. spec. no. : c064n3 issued date : 2016.08.16 revised date : page no. : 3/9 mta040p02kn3 cystek product specification recommended soldering footprint
cystech electronics corp. spec. no. : c064n3 issued date : 2016.08.16 revised date : page no. : 4/9 mta040p02kn3 cystek product specification typical characteristics typical output characteristics 0 5 10 15 20 25 30 012345 -v ds , drain-source voltage(v) -i d , drain current(a) 10v,9v,8v,7v,6v,5v,4.5v,4v,3.5v 2.5v -v gs =1.5v 2v brekdown voltage vs ambient temperature 0.4 0.6 0.8 1.0 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature(c) -bv dss , normalized drain-source breakdown voltage i d =-250 a, v gs =0v static drain-source on-state resistance vs drain current 0 10 20 30 40 50 60 70 80 90 100 0.01 0.1 1 10 -i d , drain current(a) r ds(on) , static drain-source on-state resistance(m) v gs =-4.5v v gs =-2.5v v gs =-3v reverse drain current vs source-drain voltage 0.2 0.4 0.6 0.8 1.0 1.2 024681 -i dr , reverse drain current(a) -v sd , source-drain voltage(v) static drain-source on-state resistance vs gate-source voltage 0 100 200 300 400 500 024681 0 0 tj=25c tj=150c v gs =0v drain-source on-state resistance vs junction tempearture 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature(c) r ds(on) , normalized static drain- source on-state resistance -v gs , gate-source voltage(v) r ds(on ), static drain-source on- state resistance(m) v gs =-4.5v, i d =-4a i d =-4a r ds( on) @tj=25c : 37.5m typ
cystech electronics corp. spec. no. : c064n3 issued date : 2016.08.16 revised date : page no. : 5/9 mta040p02kn3 cystek product specification typical characteristics(cont.) threshold voltage vs junction tempearture 0.2 0.4 0.6 0.8 1.0 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature(c) -v gs(th) , normalized threshold voltage i d =-250 a i d =-1ma maximum safe operating area 0.01 0.1 1 10 100 0.1 1 10 100 -v ds , drain-source voltage(v) -i d , drain current (a) r ds( on) limited dc 10ms 100ms 1ms 100 s 1s t a =25c, tj=150c, v gs =-4.5v, r ja =100c/w, single pulse maximum drain current vs junction temperature 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 25 50 75 100 125 150 175 tj, junction temperature(c) -i d , maximum drain current(a) v gs =-4.5v, tj(max)=150c, r ja =100c/w, single pulse typical transfer characteristics 0 5 10 15 20 25 30 012345 -v gs , gate-source voltage(v) -i d , drain current(a) v ds =-5v forward transfer admittance vs drain current 0.01 0.1 1 10 0.001 0.01 0.1 1 10 -i d , drain current(a) g fs , forward transfer admittance(s) v ds =-10v pulsed ta=25c single pulse power rating, junction to case 0 50 100 150 200 250 300 0.0001 0.001 0.01 0.1 1 10 100 pulse width(s) power (w) t j(max) =150c t a =25c r ja =100c/w
cystech electronics corp. spec. no. : c064n3 issued date : 2016.08.16 revised date : page no. : 6/9 mta040p02kn3 cystek product specification typical characteristics(cont.) power derating curve 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 0 25 50 75 100 125 150 175 t a , ambient temperature() p d , power dissipation(w) transient thermal response curves 0.001 0.01 0.1 1 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 1.e+02 1.e+03 t 1 , square wave pulse duration(s) r(t), normalized effective transient thermal resistance single pulse 0.01 0.02 0.05 0.1 0.2 d=0.5 1.r ja (t)=r(t)*r ja 2.duty factor, d=t 1 /t 2 3.t jm -t a =p dm *r ja (t) 4.r ja =100c/w
cystech electronics corp. spec. no. : c064n3 issued date : 2016.08.16 revised date : page no. : 7/9 mta040p02kn3 cystek product specification reel dimension carrier tape dimension
cystech electronics corp. spec. no. : c064n3 issued date : 2016.08.16 revised date : page no. : 8/9 mta040p02kn3 cystek product specification recommended wave soldering condition soldering time product peak temperature pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow pb-free assembly profile feature sn-pb eutectic assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds time maintained above: ? temperature (t l ) ? time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of the package, measured on the package body surface.
cystech electronics corp. spec. no. : c064n3 issued date : 2016.08.16 revised date : page no. : 9/9 mta040p02kn3 cystek product specification sot-23 dimension inches millimeters inches millimeters dim min. max. min. max. dim min. max. min. max. a 0.1102 0.1204 2.80 3.04 j 0.0032 0.0079 0.08 0.20 b 0.0472 0.0669 1.20 1.70 k 0.0118 0.0266 0.30 0.67 c 0.0335 0.0512 0.89 1.30 l 0.0335 0.0453 0.85 1.15 d 0.0118 0.0197 0.30 0.50 s 0.0830 0.1161 2.10 2.95 g 0.0669 0.0910 1.70 2.30 v 0.0098 0.0256 0.25 0.65 h 0.0000 0.0040 0.00 0.10 l1 0.0118 0.0197 0.30 0.50 notes: 1.controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing spec ification or packing method, please cont act your local cystek sales office. material: ? lead: pure tin plated. ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitab le for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance . marking: te a4p2 xx device code date code 3-lead sot-23 plastic surface mounted package cystek package code: n3 style: pin 1.gate 2.source 3.drain
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