supertex inc. www.supertex.com hv7350 supertex inc. doc.# dsfp-hv7350 a011314 features ? hvcmo s technology for high performance ? high density integrated ultrasound transmitter ? 0 to 60v output voltage ? 1.0a source and sink current in pulse mode ? 1.0a source and sink current in rtz mode ? up to 20mhz operating frequency ? matched delay times ? optional clock re-alignment ? 3.3v cmos logic interface and reference ? +3.3v low voltage supply for v dd ? built-in linear regulators for loating gate driver ? built-in output drain diodes & bleed resistors application ? portable medical ultrasound imaging ? piezoelectric transducer drivers ? pulse waveform generator general descriptionthe supertex hv7350 is an eight channel monolithic high voltage high- speed pulse generator with built-in fast return to zero damping fets. this high voltage and high-speed integrated circuit is designed for portable medical ultrasound image devices. hv7350 consists of a controller logic interface circuit, level translators, mosfet gate drives, and high current power p-channel and n-channel mosfets as the output stage for each channel. the output peak currents of each channel are guaranteed to be over 1.0a with up to 60v pulse swings as well as return-to-zero (rtz) mode. the gate drivers for the output mosfets are powered by built-in linear 5.0v regulators referenced to v pp and v nn . this direct coupling topology of the gate drivers not only saves four loating voltage supplies or ac coupling capacitors per channel, but also makes the pcb layout smaller and easier. an input clock pin is available to realign all the logic input control lines to a master clock. precise logic timing is always essential in any ultrasound systems. typical application circuit eight-channel, high speed, 60v, 1.0a, ultrasound rtz pulser cpf vdd +3.3 v 3.3v logic rgnd hv ou t 1 x1 vpp +10 to +60v -10 to -60v p-drive r n-driver 1 of 8 channels logic & level translator -5.0 v rgnd rgnd dm p 1.0 f vp f vn f rb lr p cpos gn d gn d sub ren oen pin1 nin1 pin8 nin8 clk dap lr p gn d lr n gn d vn f vp f lr n gn d gnd cneg cnf vnn +5.0 v -5.0 v 1.0 f 1.0 f 1.0 f1 .0f tx1 1.0 f 1.0 f vll +3.3 v 0.1 f +5.0 v downloaded from: http:///
2 hv7350 supertex inc. www.supertex.com doc.# dsfp-hv7350 a011314 absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. pin conigurationpackage marking 1 56 l = lot number yy = year sealed ww = week sealed a = assembler id c = country of origin = ?green? packaging hv7350k6lllllllll yyw w aaa cc c 56-lead qfn 56-lead qfn (top view) package may or may not include the following marks: si or parameter value vsub, substrate voltage is gnd 0v v ll , positive logic supply -0.5v to +5.5v v dd , positive logic and level translator supply -0.5v to +5.5v c pos to gnd, positive level translator circuit -0.5v to +5.5v c neg to gnd, negative level translator circuit +0.5v to -5.5v (v pp - c pf ), positive gate driver circuit -0.5v to +5.5v (c nf - v nn ), negative gate driver circuit -0.5v to +5.5v (v pp - v nn ) differential high voltage supply +130v v pp , high voltage positive supply -0.5v to +65v v nn , high voltage negative supply +0.5v to -65v all logic input pin x , nin x , oen and ren voltages -0.5v to +5.5v operating temperature -40c to 125c storage temperature -65c to 150c ordering information part number package packing HV7350K6-G 56-lead (8x8) qfn 250/ tray HV7350K6-G m937 56-lead (8x8) qfn 2000/reel typical thermal resistance package ja 56-lead (8x8) qfn 21 o c/w -g denotes a lead (pb)-free / rohs compliant package power-up sequence step description 1 v ll with logic signal low 2 v dd 3 ren = 1 (external supplies on) 4 v pp and v nn 5 logic control signals active power-down sequence step description 1 all logic signals go to low 2 v pp and v nn 3 ren = 0 (external supplies off) 4 v dd 5 v ll note: powering up/down in any arbitrary sequence will not cause any damage to the device. the powering up/down sequence is only recommended in order to minimize possible inrush current. output current & r on i sc r onp r onn i dmp r ondp r ondn 1.5a 13 6.5 1.5a 13 8.0 esd sensitive device notes: 1.v pp /v nn = +/-60v, v dd = +3.3v; ren = 1 2. i sc is current into 1.0 to gnd; 3. i dmp is current from +/-30v connected to t x pin. 4. max pulse width for current measurement on t x pin is 100ns. downloaded from: http:///
3 hv7350 supertex inc. www.supertex.com doc.# dsfp-hv7350 a011314 operating supply voltages and current (eight active channels) (operating conditions, unless otherwise speciied, v ll = +3.3v, v dd = +3.3v, v pp = +60v ,v nn = -60v, v clk = +3.3v, t a = 25c) sym parameter min typ max units conditions v dd v dd voltage supply 2.97 3.30 5.20 v --- uvlo dd v dd uvlo 2.30 2.60 2.80 v --- v ll logic voltage reference 2.50 3.30 5.00 v --- uvlo ll v ll uvlo 1.30 1.55 1.70 v --- v pp positive high voltage supply +10 - +60 v --- v nn negative high voltage supply -60 - -10 v --- i llq v ll current - 8.0 - a oen = ren = 0 i ddq v dd current - 1.0 - i ppq v pp current - 5.0 10 i nnq v nn current - 5.0 10 i llen v ll current - 13 20 a oen = ren = 15.0ms after f = 0mhz i dden v dd current - 480 700 i ppen v pp current - 220 350 i nnen v nn current - 300 400 i ddcw v dd current - 2.3 - ma f = 5.0mhz, continuous, no loads, for calculation reference only. i ppcw v pp current - 80 - i nncw v nn current - 80 - i ll,clk v ll current - 33 - a f clk = 10mhz, pin = nin = 0 electrical characteristics(operating conditions, unless otherwise speciied, v ll = +3.3v, v dd = +3.3v, v pp = +60v ,v nn = -60v, v clk = +3.3v, t a = 25c) pulser p-channel mosfet sym parameter min typ max units conditions i out output saturation current 1.0 1.5 - a --- r on channel resistance - 13.2 - i sd = 100ma pulser n-channel mosfet sym parameter min typ max units conditions i out output saturation current 1.0 1.5 - a --- r on channel resistance - 8.0 - i sd = 100ma damping p-channel mosfet sym parameter min typ max units conditions i out output saturation current 1.0 1.5 - a --- r on channel resistance - 13 - i sd = 100ma damping n-channel mosfet sym parameter min typ max units conditions i out output saturation current 1.0 1.5 - a --- r on channel resistance - 9.0 - i sd = 100ma downloaded from: http:///
4 hv7350 supertex inc. www.supertex.com doc.# dsfp-hv7350 a011314 logic inputs sym parameter min typ max units conditions v ih input logic high voltage 0.7 ? v ll - v ll v v ll = 2.5 to 3.3v v il input logic low voltage 0 - 0.3 ? v ll v v ih input logic high voltage 0.8 ? v ll - v ll v v ll = 5.0v v il input logic low voltage 0 - 0.2 ? v ll v i ih input logic high current - - 10 a --- i il input logic low current -10 - - a --- c in input logic capacitance - - 5.0 pf --- mosfet drain bleed resistor sym parameter min typ max units conditions r b1~8 output bleed resistance 12 17 25 k --- p rb1~8 bleed resistors power limit - - 50 mw --- ac electrical characteristics(operating conditions, unless otherwise speciied, v ll = +3.3v, v dd = +3.3v, v pp = +60v ,v nn = -60v, v clk = +3.3v, t a = 25c) sym parameter min typ max units conditions t r output rise time - 30 - ns 330pf//2.5k load 10 - 90% t f output fall time - 30 - ns t en enable time - 300 500 s cap value see page 1 diagram.oen = ren t dis disable time - 2.8 10 s t d1 delay time on pin x rise - 12 - ns 1.0 resistor load, d%<1%(see timing diagram) 50% inputs to 50% t x current t d2 delay time on nin x rise - 12 - t d3 delay time on damping rise - 12 - t d4 delay time on damping fall - 12 - t dc delay time on clk rise - 9.0 - t delay delay time matching - 3.0 - ns p to n, channel to channel t j delay jitter on rise or fall - tbd - ps v pp /v nn = +/-25v, input tr 50% to hv out t r or t f 50%, with 330pf//2.5k load t rr rtz fets drain diode t rr - 25 - ns i f = 1.0a, i r = 1.0a, r l = 10 f clk re-timing clock frequency 10 220 - mhz --- t rc , t fc re-timing clock rise & fall times - 0.5 5.0 ns --- t su set-up time, pin/nin to clk 2.0 - - ns --- t h hold time, clk to pin/nin 1.0 - - ns --- t clk_lo clock time low 2.0 - 100 ns clk input must have at least one pulse before pin and nin inputs are not zero. be sure to return inputs to zero before stopping clock. t clk_hi clock time high 2.0 - 100 ns t clk_rec clock recognition time - 2.0 - ns t clk_rls clock release time 150 300 800 ns f out output frequency range - - 20 mhz 100 resistor load hd2 second harmonic distortion - -40 - db c oss output capacitance - 50 - pf v ds = 25v, f = 1.0mhz , of t x pin total downloaded from: http:///
5 hv7350 supertex inc. www.supertex.com doc.# dsfp-hv7350 a011314 switching time diagram cl k pinn(ninn = 0) ninn(pinn = 0) ninn(pinn = 0) cl kc lk cl k tx n tx n 0a tx n0 a 50% 50% 50% 50% t d1 t d4 t d2 t d3 i ou t i ou t i ou t i ou t t dc t dc t dc t dc 50% 50% 0a 0a tx n synchronous mode asynchronous mode pinn(ninn = 0) truth table logic inputs tx n output oen clk pin x nin x vpp vnn rgnd note 1 vll 0 0 off off on asynchronous mode output change on pin/nin 1 vll 1 0 on off off 1 vll 0 1 off on off 1 vll 1 1 off off off 1 0 0 off off on synchronous mode output change at retiming clock(clk) rising edge, registered by pin/nin 1 1 0 on off off 1 0 1 off on off 1 1 1 off off off 0 x x x off off off disabled downloaded from: http:///
6 hv7350 supertex inc. www.supertex.com doc.# dsfp-hv7350 a011314 pin description pin name description 1 pin2 input logic control of high voltage output p-fet for channel 2, hi = on, low = off. (see logic table) 2 nin2 input logic control of high voltage output n-fet for channel 2, hi = on, low = off. (see logic table) 3 pin3 input logic control of high voltage output p-fet for channel 3, hi = on, low = off. (see logic table) 4 nin3 input logic control of high voltage output n-fet for channel 3, hi = on, low = off. (see logic table) 5 pin4 input logic control of high voltage output p-fet for channel 4, hi = on, low = off. (see logic table) 6 nin4 input logic control of high voltage output n-fet for channel 4, hi = on, low = off. (see logic table) 7 oen output enable hi = on, low = off. see logic truth table 8 ren built-in positive and negative 5v voltage regulators enable. hi = on, low = off. if ren = 0, exter- nal loating 5v power supplies may be supplied across cpf, cnf cpos and cneg capacitors 9 pin5 input logic control of high voltage output p-fet for channel 5, hi = on, low = off. (see logic table) 10 nin5 input logic control of high voltage output n-fet for channel 5, hi = on, low = off. (see logic table) 11 pin6 input logic control of high voltage output p-fet for channel 6, hi = on, low = off. (see logic table) 12 nin6 input logic control of high voltage output n-fet for channel 6, hi = on, low = off. (see logic table) 13 pin7 input logic control of high voltage output p-fet for channel 7, hi = on, low = off. (see logic table) 14 nin7 input logic control of high voltage output n-fet for channel 7, hi = on, low = off. (see logic table) 15 pin8 input logic control of high voltage output p-fet for channel 8, hi = on, low = off. (see logic table) 16 nin8 input logic control of high voltage output n-fet for channel 8, hi = on, low = off. (see logic table) 17 vll logic supply voltage and reference input (+3.3v) 18 gnd logic and circuit return ground (0v) 19 vdd positive voltage power supply (+3.3v) 20 vpp positive high voltage power supply (+10 to +60v) 21 vpp 22 vpp 23 cpf built-in linear voltage vpf regulator output decoupling capacitor pin, 1uf from vpp to cpf per each 24 cnf built-in linear voltage vnf regulator output decoupling capacitor pin, 1uf from cnf to vnn per each 25 vnn negative high voltage power supply (-10 to -60v) 26 vnn 27 vnn 28 tx8 t x pulser channel 8 output 29 rgnd damping ground and bleed resistors common return ground 30 tx7 t x pulser channel 7 output 31 rgnd damping ground and bleed resistors common return ground 32 tx6 t x pulser channel 6 output downloaded from: http:///
7 hv7350 supertex inc. www.supertex.com doc.# dsfp-hv7350 a011314 pin description (cont.) pin name description 33 rgnd damping ground and bleed resistors common return ground 34 tx5 t x pulser channel 5 output 35 cneg built-in linear voltage -5v regulator output decoupling capacitor pin, 1.0uf from cneg to gnd 36 cpos built-in linear voltage +5v regulator output decoupling capacitor pin, 1.0uf from cpos to gnd 37 tx4 t x pulser channel 4 output 38 rgnd damping ground and bleed resistors common return ground 39 tx3 t x pulser channel 3 output 40 rgnd damping ground and bleed resistors common return ground 41 tx2 t x pulser channel 2 output 42 rgnd damping ground and bleed resistors common return ground 43 tx1 t x pulser channel 1 output 44 vnn negative high voltage power supply (-10 to -60v) 45 vnn 46 vnn 47 cnf built-in linear voltage vnf regulator output decoupling capacitor pin, 1uf from cnf to vnn per each 48 cpf built-in linear voltage vpf regulator output decoupling capacitor pin, 1uf from vpp to cpf per each 49 vpp positive high voltage power supply (+10 to +60v) 50 vpp 51 vpp 52 vdd positive voltage power supply (+3.3v) 53 gnd logic and circuit return ground (0v) 54 clk re-timing register clock input. connect to v ll to disable the re-timing function 55 pin1 input logic control of high voltage output p-fet for channel 1, hi = on, low = off. (see logic table) 56 nin1 input logic control of high voltage output n-fet for channel 1, hi = on, low = off. (see logic table) vsub (thermal pad) substrate bottom is internally connected to the central thermal pad on the bottom of package. it must be connected to gnd (0v) externally downloaded from: http:///
supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate ?product liability indemnification insurance agreement.? supertex inc . does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry and specifications are subject to change without notice. for the latest product specifications refer to the supertex inc . (website: http//www .supertex.com) ?2014 supertex inc. all rights reserved. unauthorized use or reproduction is prohibited. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www.supertex.co m 8 hv7350 (the package drawing(s) in this data sheet may not relect the most current speciications. for the latest package outline information go to http://www.supertex.com/packaging.html .) doc.# dsfp-hv7350 a011314 56-lead qfn package outline (k6) 8.00x8.00mm body, 1.00mm height (max), 0.50mm pitch symbol a a1 a3 b d d2 e e2 e l l1 dimension (mm) min 0.80 0.00 0.20 ref 0.18 7.85* 2.75 7.85* 2.75 0.50 bsc 0.30 0.00 0 o nom 0.90 0.02 0.25 8.00 5.70 8.00 5.70 0.40 - - max 1.00 0.05 0.30 8.15* 6.70 ? 8.15* 6.70 ? 0.50 0.15 14 o jedec registration mo-220, variation vlld-2, issue k, june 2006. * this dimension is not speciied in the jedec drawing. ? this dimension differs from the jedec drawing. drawings are not to scale. supertex doc.#: dspd-56qfnk68x8p050, version a031010. notes: 1. a pin 1 identiier must be located in the index area indicated. the pin 1 identiier can be: a molded mark/identiier; an embedded metal marker; or a printed indicator. 2. depending on the method of manufacturing, a maximum of 0.15mm pullback (l1) may be present. 3. the inner tip of the lead may be either rounded or square. seating plane top vi ew side view bottom view d e d2 e2 view b vi ew b 1 note 3 note 2 56 1 56 note 1 (index are a d/2 x e/2) note 1 (index are a d/2 x e/2) eb l l1 a a1 a3 downloaded from: http:///
|
