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| rev. 1.0 11/14 copyright ? 2014 by silicon laboratories SI53307 SI53307 2:2 l ow j itter u niversal b uffer /l evel t ranslator features applications description the SI53307 is an ultra-low jitter two output differential buffer with pin-selectable output clock signal format an d 2:1 input clock mux. th e SI53307 utilizes silicon labs' advanced cmos technology to f anout clocks from 1 to 725 mhz with guaranteed low additive jitter, low skew, and low propagation delay variability. the SI53307 features minimal cross-talk and pr ovides superior supply noise rejection, simplifying low jitter clock distributi on in noisy environments. independent core and output bank supply pins provide int egrated level translation without the need for external circuitry. functional block diagram ? 2 differential or 4 lvcmos outputs ? ultra-low additive jitter: 45 fs rms ? wide frequency range: 1 to 725 mhz ? any-format input with pin selectable output formats: lvpecl, low power lvpecl, lvds, cml, hcsl, lvcmos ? synchronous output enable ? 2:1 input mux with glitchless input clock switching ? independent v dd and v ddo : 1.8/2.5/3.3 v ? small size: 16-qfn (3 mm x 3 mm) ? rohs compliant, pb-free ? industrial temperature range: ?40 to +85 c ? high-speed clock distribution ? ethernet switch/router ? optical transport network (otn) ? sonet/sdh ? pci express gen 1/2/3 ? storage ? telecom ? industrial ? servers ? backplane clock distribution patents pending ordering information: see page 26. pin assignments sfout0 gnd pad 9 11 10 12 5 6 7 8 16 15 14 13 4 2 3 1 clk1 clk1 clk_sel gnd q0 q0 q1 q1 clk0 clk0 v ddo oe sfout1 v dd gnd
SI53307 2 rev. 1.0 SI53307 rev. 1.0 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 2.1. universal, any-format i nput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2. input bias resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3. universal, any-format output buff er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4. synchronous output enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.5. glitchless clock i nput switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6. input mux and outp ut enable logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.7. power supply (v dd and v ddo ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.8. output clock terminati on options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 2.9. ac timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.10. typical phase noise performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.11. power supply noise rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3. pin description: 16-pin qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5. package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6. pcb land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 7. top marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.1. SI53307 top marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.2. top marking explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 SI53307 4 rev. 1.0 1. electrical specifications table 1. recommended operating conditions parameter symbol test condition min typ max unit ambient operating temperature t a ?40 ? 85 c supply voltage range* v dd lvds, cml 1.71 1.8 1.89 v 2.38 2.5 2.63 v 2.97 3.3 3.63 v lvpecl, low power lvpecl, lvcmos 2.38 2.5 2.63 v 2.97 3.3 3.63 v hcsl 2.97 3.3 3.63 v output buffer supply voltage* v ddo lvds, cml, lvcmos 1.71 1.8 1.89 v 2.38 2.5 2.63 v 2.97 3.3 3.63 v lvpecl, low power lvpecl 2.38 2.5 2.63 v 2.97 3.3 3.63 v hcsl 2.97 3.3 3.63 v *note: core supply v dd and output buffer supplies v ddo are independent. table 2. input clock specifications (v dd =1.8 v ? 5%, 2.5 v ? 5%, or 3.3 v ? 10%, t a =?40 to 85 c) parameter symbol test condition min typ max unit differential input common mode voltage v cm v dd =2.5v ? 5%, 3.3 v ? 10% 0.05 ? ? v differential input swing (peak-to-peak) v in 0.2 ? 2.2 v lvcmos input high volt- age v ih v dd =2.5v ? 5%, 3.3 v ? 10% v dd x 0.7 ? ? v lvcmos input low volt- age v il v dd =2.5v ? 5%, 3.3 v ? 10% ? ? v dd x 0.3 v input capacitance c in clk pins with respect to gnd ? 5 ? pf SI53307 rev. 1.0 5 table 3. dc common characteristics (v dd =v ddo =1.8v ?? 5% , 2.5 v ? 5%, or 3.3 v ?? 10%,t a = ?40 to 85 c) parameter symbol test condition min typ max unit supply current i dd ?65100ma output buffer supply current (per clock output) @100 mhz (diff) @200 mhz (cmos) i ddo lvpecl (3.3 v) ? 40 ? ma low power lvpecl (3.3 v)* ? 35 ? ma lvds (3.3 v) ? 20 ? ma cml (3.3 v) ? 60 ? ma hcsl, 100 mhz, 2 pf load (3.3 v) ?35?ma cmos (2.5 v, sfout = open/0), per output, c l =5pf, 200mhz ?10?ma cmos (3.3 v, sfout = 0/1), per output, c l =5pf, 200mhz ?20?ma input high voltage v ih sfoutx, oe 0.8 x vdd ? ? v input mid voltage v im sfoutx, 3-level input pins 0.45 x vdd 0.5 x vdd 0.55 x vdd v input low voltage v il sfoutx, oe ? ? 0.2 x vdd v internal pull-down resistor r down sfout, clk_sel ? 25 ? k ? internal pull-up resistor r up sfoutx, oe ? 25 ? k ? *note: low-power lvpecl mode supports an output termina tion scheme that will reduce overall system power. SI53307 6 rev. 1.0 table 4. output characteristics (lvpecl) (v dd = v ddo = 2.5 v 5%, or 3.3 v 10%,ta = ?40 to 85 c) parameter symbol test condition min typ max unit output dc common mode voltage v com v ddo ?1.595 ? v ddo ?1.245 v single-ended output swing* v se 0.55 0.80 1.050 v *note: unused outputs can be left floating. do not short unused outputs to ground. table 5. output characteristics (low power lvpecl) (v dd = v ddo = 2.5 v 5%, or 3.3 v 10%,ta = ?40 to 85 c) parameter symbol test condition min typ max unit output dc common mode voltage v com r l = 100 ?? across qn and qn v ddo ?1.895 v ddo ?1.275 v single-ended output swing* v se r l = 100 ?? across qn and qn 0.25 0.60 0.85 v *note: r l = 100 ? across qn and qn . table 6. output characteristics?cml (v dd = v ddo =1.8v ?? 5% , 2.5 v ? 5%, or 3.3 v ?? 10%,t a = ?40 to 85 c) parameter symbol test condition min typ max unit single-ended output swing v se terminated as shown in figure 8 (cml termination). 300 400 550 mv table 7. output characteristics?lvds (v dd = v ddo =1.8v ?? 5% , 2.5 v ? 5%, or 3.3 v ?? 10%,t a = ?40 to 85 c) parameter symbol test condition min typ max unit single-ended output swing* v se r l =100 ? across q n and q n 247 410 490 mv output common mode voltage (v ddo =2.5v or 3.3 v) v com1 v ddo = 2.38 to 2.63 v, 2.97 to 3.63 v, r l =100 ? across q n and q n 1.10 1.25 1.35 v output common mode voltage (v ddo =1.8v) v com2 v ddo = 1.71 to 1.89 v, r l =100 ? across q n and q n 0.85 0.97 1.25 v *note: typical specification based upon 156.25 mhz output frequency and v ddo = 3.3 v. SI53307 rev. 1.0 7 table 8. output characteristics?lvcmos (v dd = v ddo =1.8v ?? 5% , 2.5 v ? 5%, or 3.3 v ?? 10%,t a = ?40 to 85 c) parameter symbol test condition min typ max unit output voltage high * v oh 0.75 x v ddo ?? v output voltage low * v ol ? ? 0.25 x v ddo v *note: i oh and i ol per the output signal format table for specific v ddo and sfoutx settings. table 9. output characteristics?hcsl (v dd = v ddo = 3.3 v 10%, ta = ?40 to 85 c) parameter symbol test condition min typ max unit output voltage high v oh r l =50 ? to gnd 550 700 850 mv output voltage low v ol r l =50 ? to gnd ?150 0 150 mv single-ended output swing v se r l =50 ? to gnd 550 700 850 mv crossing voltage v c r l =50 ? to gnd 250 350 550 mv table 10. ac characteristics (v dd = v ddo =1.8v ?? 5% , 2.5 v ? 5%, or 3.3 v ?? 10%,t a = ?40 to 85 c) parameter symbol test condition min typ max unit frequency f lvpecl, low power lvpecl, lvds, cml, hcsl 1?725mhz lvcmos 1 ? 200 mhz duty cycle note: 50% input duty cycle. d c 200 mhz, 20/80% ? t r /t f <10% of period (lvcmos) (12 ma drive) 40 50 60 % 20/80% t r /t f <10% of period (differential) 48 50 52 % minimum input clock slew rate sr required to meet prop delay and additive jitter specifications (20?80%) 0.75 ? ? v/ns notes: 1. hcsl measurements were made with receiv er termination. see figure 8 on page 18. 2. output to output skew specified for outputs with an identical configuration. 3. defined as skew between any output on different devices operating at the same supply voltages, temperatures, and equal load conditions. using the same type of inputs on each device, the outputs are measur ed at the differential cross points. 4. measured for 156.25 mhz carrier frequency. sine-wave noise added to v ddo (3.3 v = 100 mv pp ) and noise spur amplitude measured. see application not e, ?an491: power supply rejection for low jitter clocks? for further details. SI53307 8 rev. 1.0 output rise/fall time t r /t f lvpecl, lvds, cml, hcsl 1 , low- power lvpecl 20/80% ??350ps 200 mhz, 20/80%, 2 pf load (lvcmos), 12 ma ??750ps minimum input pulse width t w 500 ? ? ps additive jitter (differential clock input) jv dd =v ddo = 2.5/3.3 v, lvpecl/ lvds, f = 725 mhz, 0.75 v/ns input slew rate ?5065fs propagation delay t plh, t phl lvpecl 675 875 1075 ps lvds 675 875 1075 ps output enable time t en f=1mhz ? 1500 ? ns f = 100 mhz ? 20 ? ns f = 725 mhz ? 5 ? ns output disable time t dis f=1mhz ? 2000 ? ns f = 100 mhz ? 35 ? ns f = 725 mhz ? 5 ? ns output to output skew 2 t sk lvcmos, drive 12 ma to 2 pf ? 50 120 ps lvpecl ? 30 75 ps lvds ? 40 85 ps part to part skew 3 t ps differential ? ? 150 ps power supply noise rejection 4 psrr 10 khz sinusoidal noise ? ?72.5 ? dbc 100 khz sinusoidal noise ? ?70 ? dbc 500 khz sinusoidal noise ? ?67.5 ? dbc 1 mhz sinusoidal noise ? ?62.5 ? dbc table 10. ac characteristics (continued) (v dd = v ddo =1.8v ?? 5% , 2.5 v ? 5%, or 3.3 v ?? 10%,t a = ?40 to 85 c) parameter symbol test condition min typ max unit notes: 1. hcsl measurements were made with receiv er termination. see figure 8 on page 18. 2. output to output skew specified for outputs with an identical configuration. 3. defined as skew between any output on different devices operating at the same supply voltages, temperatures, and equal load conditions. using the same type of inputs on each device, the outputs are measur ed at the differential cross points. 4. measured for 156.25 mhz carrier frequency. sine-wave noise added to v ddo (3.3 v = 100 mv pp ) and noise spur amplitude measured. see application not e, ?an491: power supply rejection for low jitter clocks? for further details. SI53307 rev. 1.0 9 table 11. additive jitter, differential clock input v dd input 1,2 output additive jitter (fs rms, 12 khz to 20 mhz) 3 freq (mhz) clock format amplitude v in (single-ended, peak-to-peak) differential 20%?80% slew rate (v/ ns) clock format typ max 3.3 725 differential 0.15 0.637 lvpecl 45 65 3.3 725 differential 0.15 0.637 lvds 50 65 3.3 156.25 differential 0.5 0.458 lvpecl 160 185 3.3 156.25 differential 0.5 0.458 lvds 150 200 2.5 725 differential 0.15 0.637 lvpecl 45 65 2.5 725 differential 0.15 0.637 lvds 50 65 2.5 156.25 differential 0.5 0.458 lvpecl 145 185 2.5 156.25 differential 0.5 0.458 lvds 145 195 notes: 1. for best additive jitter results, use the fastest slew rate possible. see application note, ?an766: understanding and optimizing clock buffer?s additive jitte r performance? for more information. 2. ac-coupled differential inputs. 3. measured differentially using a balun at the phase noise analyzer input. see figure 1. SI53307 10 rev. 1.0 figure 1. differential measurement method using a balun table 12. additive jitter, single-ended clock input v dd input 1,2 output additive jitter (fs rms, 12 khz to 20 mhz) 3 freq (mhz) clock format amplitude v in (single-ended, peak to peak) se 20%-80% slew rate (v/ns) clock format typ max 3.3 200 single-ended 1.70 1 lvcmos 4 120 160 3.3 156.25 single-en ded 2.18 1 lvpecl 160 185 3.3 156.25 single-ended 2.18 1 lvds 150 200 3.3 156.25 single-ended 2.18 1 lvcmos 4 130 180 2.5 200 single-ended 1.70 1 lvcmos 5 120 160 2.5 156.25 single-en ded 2.18 1 lvpecl 145 185 2.5 156.25 single-ended 2.18 1 lvds 145 195 2.5 156.25 single-ended 2.18 1 lvcmos 5 140 180 notes: 1. for best additive jitter results, use the fastest slew ra te possible. see ?an766: understanding and optimizing clock buffer?s additive jitter perfo rmance? for more information. 2. dc-coupled single-ended inputs. 3. measured differentially using a balun at t he phase noise analyzer input (see figure 1). lvcmos jitter is measured single-ended. 4. drive strength: 12 ma, 3.3 v (sfout = 11). 5. drive strength: 9 ma, 2.5 v (sfout = 11). pspl 5310a clkx /clkx 50 50 balun 50ohm ag e5052 phase noise analyzer si533xx dut pspl 5310a clk synth sma103a balun SI53307 rev. 1.0 11 table 13. thermal conditions parameter symbol test condition value unit thermal resistance, junction to ambient ? ja still air 57.6 c/w thermal resistance, junction to case ? jc still air 41.5 c/w table 14. absolute maximum ratings parameter symbol test condition min typ max unit storage temperature t s ?55 ? 150 ? c supply voltage v dd ?0.5 ? 3.8 v input voltage v in ?0.5 ? v dd + 0.3 v output voltage v out ??v dd + 0.3 v esd sensitivity hbm 100 pf, 1.5 k ? ? ? 2000 v esd sensitivity cdm ? ? 500 v peak soldering reflow temperature t peak pb-free; solder reflow profile per jedec j-std-020 ? ? 260 ? c maximum junction temperature t j ? ? 125 ? c note: stresses beyond those listed in this table may caus e permanent damage to the device. functional operation specification compliance is not implied at these conditi ons. exposure to maximum rating conditions for extended periods may affect device reliability. SI53307 12 rev. 1.0 2. functional description the SI53307 is a low jitter, low skew 2:2 differential buffer with an integrated 2:1 input clock mux. the device has a universal input that accepts most common differential or lv cmos input signals. a clock se lect pin is used to select the active input clock. the SI53307 features control pi ns for synchronous output enable, output signal format selection and lvcmos drive strength. 2.1. universal, any-format input the SI53307 has a universal input stage that enables simple interfacing to a wide variety of clock formats, including lvpecl, low-power lvpecl, lvcmos, lvds, hcsl, and cml. tables 15 and 16 summarize the various ac- and dc-coupling options supported by the device. figures 2, 3, and 4 show the recommended input clock termination options. for the best high-speed performance, the use of differential formats is recommended. for both single- ended and differential input clocks, the fastest possible slew rate is recommended since low slew rates can increase the noise floor and degrade jitter performance. th ough not required, a minimum slew rate of 0.75 v/ns is recommended for differential formats and 1.0 v/ns for single -ended formats. for more information, see application note, ?an766: understanding and optimizing clock buffer additive jitter performance?. figure 2. differential hcsl, lvpecl, low-pow er lvpecl, lvds, cml ac-coupled input termination figure 3. lvcmos dc-coupled input termination table 15. lvpecl, lvcmos, and lvds lvpecl lvcmos lvds ac-couple dc-couple ac-couple d c-couple ac-couple dc-couple 1.8 v n/a n/a no no yes no 2.5/3.3 v yes yes no yes yes yes table 16. hcsl and cml hcsl cml ac-couple dc-couple ac-couple dc-couple 1.8 v no no yes no 2.5/3.3 v yes (3.3 v) yes (3.3 v) yes no si533xx 0.1 f 0.1 f clkx /clkx 100 ? si533xx v dd 1 k ? cmos driver v term = v dd /2 clkx = 3.3 v or 2.5 v v ddo /clkx 50 rs 1 k ? SI53307 rev. 1.0 13 figure 4. differential dc-coupled input terminations v dd si533xx r 1 v ddo r 2 r 1 r 2 ?standard? lvpecl driver v term = v ddo ? 2 v r 1 // r 2 = 50 ? clkx = 3.3 v or 2.5 v v ddo 3.3 v lvpecl: r 1 = 127 ? , r 2 = 82.5 ? 2.5 v lvpecl: r 1 = 250 ? , r 2 = 62.5 ? dc-coupled lvpecl termination scheme 1 /clkx 50 50 v dd si533xx 50 50 v term = v ddo ? 2 v = 3.3 v or 2.5 v v ddo 50 50 ?standard? lvpecl driver clkx /clkx dc-coupled lvpecl termination scheme 2 v dd si533xx 50 50 dc-coupled lvds termination = 3.3 v or 2.5 v v ddo 100 standard lvds driver clkx /clkx v dd si533xx 50 50 dc-coupled hcsl source termination scheme = 3.3 v v ddo standard hcsl driver 50 50 33 33 clkx /clkx note: 33 ? series termination is optional depending on the location of the receiver. si533xx 50 50 dc-coupled hcsl receiver termination scheme v dd standard hcsl driver 50 ? q qn v ddo = 3.3 v 50 ? SI53307 14 rev. 1.0 2.2. input bias resistors internal bias resistors ensure a differential output low co ndition in the event that the clock inputs are not connected. the noninverting input is biased with a 18.75 k ? pulldown to gnd and a 75 k ? pullup to v dd . the inverting input is biased with a 75 k ? pullup to v dd . figure 5. input bias resistors 2.3. universal, an y-format output buffer the SI53307 has highly fl exible output drivers that support a wide rang e of clock signal formats, including lvpecl, low power lvpecl, lvds , cml, hcsl, and lvcmos. sf out1 and sfout0 are 3-leve l inputs that can be pin- strapped to select the output clock signal formats. this feature enables the device to be used for format translation in addition to clock distribution, minimizing the number of unique buffer part numbers required in a typical application and simplifying design reuse. for emi reductio n applications, four lvcmos drive strength options are available for each v ddo setting. table 17. output signal format selection sfout1 sfout0 v ddo =3.3v v ddo =2.5v v ddo =1.8v open* open* lvpecl lvpecl n/a 0 0 lvds lvds lvds 0 1 lvcmos, 24 ma drive lvcmos, 18 ma drive lvcmos, 12 ma drive 1 0 lvcmos, 18 ma drive lvcmos, 12 ma drive lvcmos, 9 ma drive 1 1 lvcmos, 12 ma drive lvcmos, 9 ma drive lvcmos, 6 ma drive open* 0 lvcmos, 6 ma drive lvcmos, 4 ma drive lvcmos, 2 ma drive open* 1 lvpecl low power lvpecl low power n/a 0 open* cml cml cml 1 open* hcsl n/a n/a *note: sfout x are 3-level input pins. tie low for ?0? setting. tie high for ?1? setting. when left open, the pin floats to v dd /2. r pu clk0 or clk1 r pu r pu = 75 k ? r pd = 18.75 k ? r pd + ? v dd SI53307 rev. 1.0 15 2.4. synchronous output enable the SI53307 features a synchronous output enable (disable ) feature. output enable is sampled and synchronized on the falling edge of the input clock. this feature prevents runt pulses from being generated when the outputs are enabled or disabled. when oe is low, q is held low and q is held high for differential output formats. for lvcmos output format options, both q and q are held low when oe is set low. the device outputs are enabled when the output enable pin is unconnected. see table 10, ?ac ch aracteristics,? on page 7 for output enable and output disable times. 2.5. glitchless cl ock input switching the SI53307 featur es glitchless switching between two valid in put clocks. figure 6 illust rates that switching between input clocks does not generate ru nt pulses or glitches at the output. figure 6. glitchless input clock switch the SI53307 supports glitchless switching between clocks at the same frequency. in addition, the device supports glitchless switching between 2 input clocks that are up to 10x different in frequency. when a switchover to a new clock is made, the output will disable low after two or three clock cycles of the previously -selected input clock. the outputs will remain low for up to three clock cycles of the newly-selecte d clock, after which the outputs will start from the newly-selected input. in the case a switchover to an absent clock is made, the output will glitchlessly stop low and wait for edges of the newly selected clock. a swit chover from an absent clo ck to a live clock will also be glitchless. note that the clk_ sel input should not be toggled faster than 1/250th the frequency of the slower input clock. clk1 clk0 clk_sel qn note 1 note 2 notes: 1. q n continues with clk0 for 2-3 falling edges of clk0. 2. q n is disabled low for 2-3 falling edges of clk1 . 3. q n starts on the first ri sing edge after 1 + 2. note 3 SI53307 16 rev. 1.0 2.6. input mux and output enable logic the si53301 provides two clock inputs for applications that need to select between one of two clock sources. the clk_sel pin selects the active clock input. table 18 summarizes the input and output clock based on the input mux and output enable pin settings. 2.7. power supply (v dd and v ddo ) the device includes separate core (v dd ) and output driver supplies (v ddo ). this feature allows the core to operate at a lower voltage than v ddo , reducing current consumption in mi xed supply applications. the core v dd supports 3.3 v, 2.5 v, or 1.8 v. the outputs have their own supply, v ddo , supporting 3.3 v, 2.5 v, or 1.8 v. table 18. input mux and output enable logic clk_sel clk0 clk1 oe 1 q 2 llxhl lhxhh hxlhl hxhhh xxxll 3 notes: 1. output enable active high 2. on the next negative transition of clk0 or clk1. 3. single-end: q = low, q =low differential: q = low, q =high SI53307 rev. 1.0 17 2.8. output clo ck termination options the recommended output clock termination options are show n below. unused outputs can be left floating. do not short unused outputs to ground. figure 7. lvpecl output termination si533xx r 1 v ddo r 2 r 1 r 2 50 50 lvpecl receiver v term = v ddo ? 2 v r 1 // r 2 = 50 ? q qn = 3.3 v or 2.5 v v ddo 3.3 v lvpecl: r 1 = 127 ? , r 2 = 82.5 ? 2.5 v lvpecl: r 1 = 250 ? , r 2 = 62.5 ? dc-coupled lvpecl termination scheme 1 v dd = v ddo si533xx 50 50 lvpecl receiver v term = v ddo ? 2 v q qn = 3.3 v or 2.5 v v ddo 50 50 v dd = v ddo dc-coupled lvpecl termination scheme 2 si533xx r 1 v dd r 2 r 1 r 2 50 50 v bias = v dd ? 1.3 v r 1 // r 2 = 50 ? rb rb 0.1 uf ac-coupled lvpecl termination scheme 1 q qn 0.1 uf = 3.3 v or 2.5 v v dd lvpecl receiver = 3.3 v or 2.5 v v dd 3.3 v lvpecl: r 1 = 82.5 ? , r 2 = 127 ? , rb = 120 ? 2.5 v lvpecl: r 1 = 62.5 ? , r 2 = 250 ? , rb = 90 ? 50 50 rb rb 0.1 uf ac-coupled lvpecl termination scheme 2 q qn 0.1 uf = 3.3 v or 2.5 v v ddo lvpecl receiver = 3.3 v or 2.5 v v dd 50 50 3.3 v lvpecl: rb = 120 ? 2.5 v lvpecl: rb = 90 ? v bias = v dd ? 1.3 v SI53307 18 rev. 1.0 figure 8. lvds, cml, hcsl, and low-power lvpecl output termination 50 50 0.1 uf ac-coupled lvds and low-power lvpecl termination 0.1 uf v dd 50 50 si533xx q qn v ddo = 3.3 v or 2.5 v or 1.8 v (lvds only) lvds receiver 50 50 dc-coupled hcsl source termination v dd standard hcsl receiver 86.6 86.6 42.2 42.2 si533xx q qn = 3.3 v v ddo 50 50 0.1 uf ac-coupled cml termination 0.1 uf v dd 100 si533xx q qn = 3.3 v or 2.5 v or 1.8 v v ddo cml receiver 50 50 dc-coupled hcsl receiver termination v dd standard hcsl receiver 50 50 si533xx q qn = 3.3 v v ddo 50 50 dc-coupled lvds and low-power lvpecl termination v dd 100 lvds receiver si533xx q qn v ddo = 3.3 v, 2.5 v, or 1.8 v (lvds only) SI53307 rev. 1.0 19 figure 9. lvcmos output termination table 19. recommended lvcmos r s series termination sfout1 sfout0 r s ( ? ) 3.3v 2.5v 0 1 33 33 1 0 33 33 1 1 33 33 open000 50 rs si533xx cmos driver zout cmos receivers zo SI53307 20 rev. 1.0 2.9. ac timing waveforms figure 10. ac waveforms q n q m t sk t sk t plh t r t f q q clk q t phl output-output skew propagation delay rise/fall time vpp/2 vpp/2 vpp/2 vpp/2 20% vpp 80% vpp 80% vpp 20% vpp SI53307 rev. 1.0 21 2.10. typical phase noise performance each of the following three figures shows three p hase noise plots superimpos ed on the same diagram. source jitter : reference clock phase noise. total jitter (se) : combined source and clock buffer phase noise measured as a single-ended output to the phase noise analyzer and integrated from 12 khz to 20 mhz. total jitter (diff'l) : combined source and clock buffer phase noise measured as a differentia l output to the phase noise analyzer and integrated from 12 khz to 20 mhz. the differential mea surement as shown in each figure is made using a balun. see figure 1 on page 10. note: to calculate the total rms phase jitter when adding a buffer to your clock tree, use the root-sum-square (rss). the total jitter is a measure of the source plus the buffer's additive phase jitter. the additive jitter (rms) of the buffer can then be calculated (via root-sum-square addition). figure 11. source, additive, and total jitter (156.25 mhz) frequency (mhz) diff?l input slew rate (v/ns) source jitter (fs) total jitter (se) (fs) additive jitter (se) (fs) total jitter (diff) (fs) additive jitter (diff) (fs) 156.25 1.0 38 14 14 118 112 source jitter = 38.2fs total jitter (diff) = 118fs additive jitter (diff) = 112fs total jitter (se) = 147.8fs additive jitter (se) = 142.8fs SI53307 22 rev. 1.0 figure 12. source, additive, and total jitter (312.5 mhz) frequency (mhz) diff input slew rate (v/ns) source jitter (fs) total jitter (se) (fs) additive jitter (se) (fs) total jitter (diff) (fs) additive jitter (diff) (fs) 312.5 1.0 33 94 8 8 7 source jitter = 33.1fs total jitter (diff) = 8 fs additive jitter (diff) = 77fs total jitter (se) = 94fs additive jitter (se) = 88fs SI53307 rev. 1.0 23 figure 13. source, additive, and total jitter (625 mhz) 2.11. power supply noise rejection the device supports on-chip supply voltage regulation to reject noise present on the power supply, simplifying low jitter operation in real-world environments. this feat ure enables robust operation alongside fpgas, asics, and socs and may reduce board-level filtering requirements. for more information, see application note, ?an491: power supply rejection for low jitter clocks?. frequency (mhz) diff input slew rate (v/ns) source jitter (fs) total jitter (se) (fs) additive jitter (se) (fs) total jitter (diff) (fs) additive jitter (diff) (fs) 625 1.0 23 5 5 5 5 source jitter = 23.4fs total jitter (diff) = 5 fs additive jitter (diff) = 5 fs total jitter (se) = 5 fs additive jitter (se) = 5 fs SI53307 24 rev. 1.0 3. pin description: 16-pin qfn table 20. pin description pin name description 1 vdd core voltage supply. bypass with 1.0 f capacitor and place as close to the v dd pin as possible. 2 clk1 input clock. 3clk1 input clock (complement). when the clk is driven by a single-ended input, connect /clk to vdd/2. see figure 1, ?differential measurement method using a balun,? on page 10. 4 gnd ground. 5 vddo output clock supply voltage. 6 clk0 input clock. 7clk0 input clock (complement). when the clk is driven by a single-ended input, connect /clk to vdd/2. see figure 1, ?differential measurement method using a balun,? on page 10. 8 sfout1 output signal format control pin 1. three-level input control. internally biased at v dd /2. can be left floating or tied to ground or v dd . sfout0 gnd pad 9 11 10 12 5 6 7 8 16 15 14 13 4 2 3 1 clk1 clk1 clk_sel gnd q0 q0 q1 q1 clk0 clk0 v ddo oe sfout1 v dd gnd SI53307 rev. 1.0 25 9q1 output clock 1 (complement). 10 q1 output clock 1. 11 q0 output clock 0 (complement). 12 q0 output clock 0. 13 sfout0 output signal format control pin 0. three-level input control. internally biased at v dd /2. can be left floating or tied to ground or v dd . 14 clk_sel mux input select pin: clock inputs are switched without the introduction of glitches. when clk_sel is high, clk1 is selected. when clk_sel is low, clk0 is selected. clk_sel contains an internal pull-down resistor. 15 gnd ground. 16 oe output enable. when oe = high, all outputs are enabled. when oe = low, q is held low, and q is held high for differential formats. for lvcmos, both q and q are held low when oe is set low. oe contains an internal pull-up resistor. gnd pad gnd ground. table 20. pin description (continued) pin name description SI53307 26 rev. 1.0 4. ordering guide part number package pb-free, rohs-6 temperature SI53307-b-gm 16-qfn yes ?40 to 85 ? c si53301/4-evb na yes ?40 to 85 ? c SI53307 rev. 1.0 27 5. package outline figure 14 shows the package dimensions for the 3x3 mm 16-pin qfn package. table 21 lists the values for the dimensions shown in the illustration. figure 14. SI53307 3x3 mm 16-qfn package diagram table 21. package diagram dimensions dimension min nom max a 0.80 0.85 0.90 a1 0.00 0.02 0.05 b 0.18 0.25 0.30 d 3.00 bsc. d2 1.65 1.70 1.75 e 0.50 bsc. e 3.00 bsc. e2 1.65 1.70 1.75 l 0.30 0.40 0.50 aaa ? ? 0.10 bbb ? ? 0.10 ccc ? ? 0.08 ddd ? ? 0.10 eee ? ? 0.05 notes: 1. all dimensions shown are in mil limeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. SI53307 28 rev. 1.0 6. pcb land pattern figure 15 shows the pcb land pattern dimensions for t he 3x3 mm 16-pin qfn package. table 22 lists the values for the dimensions show n in the illustration. figure 15. SI53307 3x3 mm 16-qfn package land pattern table 22. pcb land pattern dimensions dimension mm c1 3.00 c2 3.00 e0.50 x1 0.30 y1 0.80 x2 1.75 y2 1.75 notes: general 1. all dimensions shown are in millimeters (mm). 2. this land pattern design is based on the ipc-7351 guidelines. 3. all dimensions shown are at maximum material condition (mmc). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. solder mask design 4. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 5. a stainless steel, laser-cut and electro-polished stenci l with trapezoidal walls should be used to assure good solder paste release. 6. the stencil thickness should be 0.125 mm (5 mils). 7. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 8. a 2x2 array of 0.65 mm square openings on a 0.90 mm pitch should be used for the center ground pad. card assembly 9. a no-clean, type-3 solder paste is recommended. 10. the recommended card reflow profile is per the je dec/ipc j-std-020 specification for small body components. SI53307 rev. 1.0 29 7. top marking 7.1. SI53307 top marking 7.2. top marking explanation mark method: laser font size: 0.635 mm (25 mils) right-justified line 1 marking: product id 3307 line 2 marking: tttt = mfg code manufacturing code from the assembly purchase order form. line 3 marking circle = 0.5 mm diameter (bottom-left justified) pin 1 identifier yww = date code corresponds to the last digit of the current year (y) and the workweek (ww) of the mold date. disclaimer silicon laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the silicon laboratories products. characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "typical" parameters provided can and do vary in different applications. application examples described herein are for illustrative purposes only. silicon laboratories reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. silicon laboratories shall have no liability for the consequences of use of the information supplied herein. this document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits. the products must not be used within any life support system without the specific written consent of silicon laboratories. a "life support system" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. silicon laboratories products are generally not intended for military applications. silicon laboratories products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons. trademark information silicon laboratories inc., silicon laboratories, silicon labs, silabs and the silicon labs logo, cmems?, efm, efm32, efr, energy micro, energy micro logo and combinations thereof, "the world?s most energy friendly microcontrollers", ember?, ezlink?, ezmac?, ezradio?, ezradiopro?, dspll?, isomodem ?, precision32?, proslic?, siphy?, usbxpress? and others are trademarks or registered trademarks of silicon laboratories inc. arm, cortex, cortex-m3 and thumb are trademarks or registered trademarks of arm holdings. keil is a registered trademark of arm limited. all other products or brand names mentioned herein are trademarks of their respective holders. http://www.silabs.com silicon laboratories inc. 400 west cesar chavez austin, tx 78701 usa clockbuilder pro one-click access to timing tools, documentation, software, source code libraries & more. available for windows and ios (cbgo only). www.silabs.com/cbpro timing portfolio www.silabs.com/timing sw/hw www.silabs.com/cbpro quality www.silabs.com/quality support and community community.silabs.com |
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