n2806 ms pc 20060927-s00009 no.a0534-1/7 http://onsemi.com semiconductor components industries, llc, 2013 august, 2013 LV5044V overview the LV5044V is a high efficiency, 2-channel, step-down, dc-dc converter controller ic adopting a synchronous rectifying system. incorporating numerous functions on a si ngle chip with easy external setting, it can be used for a wide variety of applications. the device is optimal for use in multi-output power supply systems which are used in lcd-tvs, dvd recorders, game mach ines, high-end office products, etc. features ? provides dual step-down dc-dc converter cont roller circuits integrated on the same chip. ? provides an input uvlo circuit, an overcurrent detection function, an overtemperature detection function, soft start/soft stop functions, and a startup delay circuit. ? output voltage monitoring functions (power good as well as ovp and uvp with timer latch functions) ? 180 interleaved operation between phase 1 and phase 2 (supports multiphase drive in 2-phase parallel operation mode). ? supports synchronous operation between different device s (supports master/slave operation when multiple devices are used). specifications absolute maximum ratings at ta = 25 c parameter symbol conditions ratings unit supply voltage v in 18 v peak output current i out 1.0 a allowable power dissipation pd max *1 1w operating temperature topr -20 to +85 c storage temperature tstg -55 to +150 c allowable pin voltage *2 1 hdrv1,2 cboot1,2 18 v 2 hdrv1,2 ,cboot1,2 to sw 6.5 v 3 v in , ilim1,2 rsns1,2, sw1,2 pgood1,2 18 v 4 vlin5 v dd , ldrv1,2 6.5 v 5 comp1,2, fb1,2 ss1,2, uv_delay td1,2, ct clko vlin5+0.3 v *1 board size: 114.3 76.1 1.6mm 3 , glass epoxy board. *2 allowable pin voltages are referenced to the sgnd and pgnd pins, excluding no.2. no.2 voltages are referenced to the sw pin. orderin g number : ena0534 bi-cmos ic 2ch step-down circuit dc-dc converter controller stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty.
LV5044V no.a0534-2/7 recommended operating conditions at ta = 25 c parameter symbol conditions ratings unit v in v in and vlin open. 7.5 to 16 v supply voltage v in v in and vlin short. 4.5 to 6.0 v electrical characteristics at ta = 25 c, v in = 12v ratings parameter symbol conditions min typ max unit system comparator reference voltage v ref 0.818 0.826 0.834 v current drain 1 i cc 1 td1, td2 = 5v (excluding ciss charge.) 2 4 6 ma current drain 2 i cc 2 td1, td2 = 0v 0.3 0.6 1.2 ma 5v supply voltage vlin5 i vlin5 = 0 to 10ma 4.75 5.00 5.25 v overcurrent detection comparator offset v cl os -5 +5 mv overcurrent detection reference current i cl v in = 10 to 14v 7.47 8.30 9.13 a soft start source current i ss sc td1, td2 = 5v -1.8 -3.5 -7.0 a soft start sink current i ss sk td1, td2 = 0v 0.2 1.0 ma soft start clamp voltage v ss to 1.2 1.6 2.0 v uv_delay source current i sc uvd uv_delay = 2v -4.3 -8.6 -17.2 a uv_delay sink current i sk uvd uv_delay = 2v 0.2 1.0 ma uv_delay threshold voltage v uvd 1.5 2.4 3.5 v uv_delay operating voltage v uvd op 100% at v fb = vref 87 92 97 % vuvp detection hysteresis vuvp 2 % overvoltage detection v o vp 100% at v fb = vref 112 117 122 % overvoltage detection delay time v o dly 1.0 s output discharge transistor on-resistance v sw on 5 10 20 output block cboot leakage current i cboot v cboot = v sw + 6.5v 10 a hdrvx and ldrvx source current i sc drv 1.0 a hdrvx and ldrvx sink current i sk drv 1.0 a hdrvx low side on-resistance r h drv i out =500ma 1.5 2.5 ldrvx low side on-resistance r l drv i out =500ma 1.5 2.5 simultaneous on prevention dead time 1 t dead 1 ldrv off hdrv on 50 ns simultaneous on prevention dead time 2 t dead 2 hdrv off ldrv on 120 ns continued on next page.
LV5044V no.a0534-3/7 continued from preceding page. ratings parameter symbol conditions min typ max unit oscillator oscillator frequency f osc ct = 130pf 280 330 380 khz oscillator frequency range f osc op 250 1100 khz maximum on duty d on max ct = 130pf 82 % minimum on time t on min ct = 130pf 100 ns sawtooth wave high side voltage v saw h f osc = 300khz 2.2 2.6 v sawtooth wave low side voltage v saw l f osc = 300khz 1 1.2 v on time difference between channels 1 and 2 t dead 5 % error amplifier error amplifier input current i fb -200 -100 200 na comp pin source current i comp sc -100 -18 a comp pin sink current i comp sk 18 100 a error amplifier gm gm 500 700 900 mho current detection amplifier gain g i sns 1.5 2.0 2.5 db logic output sink current in the power good low state i pwrgd l v pgood = 0.4v 0.5 1.0 ma leakage current in the power good high state i pwrgd h v pgood = 12v 10 a td pin threshold level v on td when the td pin is stepped up 1.5 2.4 3.5 v td pin open voltage v td h v in ? vlin5 open. 4.5 5.0 5.5 v td pin source current during charge i td sc -1.8 -3.5 -7.0 a td pin sink current during discharge i td sk 0.8 2 5 ma clko high-level voltage v clko h i clko = 1ma 0.7vlin5 v clko low-level voltage v clko l i clko = 1ma 0.3vlin5 v protection functions v in uvlo release voltage v uvlo 3.5 4.1 4.3 v uvlo hysteresis v uvlo 0.2 v package dimensions unit : mm 3191b 9.75 5.6 7.6 0.22 0.65 (0.33) 1 15 16 30 0.5 0.15 1.5max 0.1 (1.3) sanyo : ssop30(275mil) -20 0 20 40 60 80 100 1.00 0.52 0 0.2 0.4 0.6 0.8 1.0 1.2 pd max -- ta omg0618 ambient temperture, ta -- c allowable power dissipation, pd max -- w specified substrate (114.3 76.1 1.6mm 3 ) glass epoxy.
LV5044V no.a0534-4/7 pin assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LV5044V top view v dd ldrv1 hdrv1 sw1 cboot1 vlin5 comp1 fb1 rsns1 ilim1 td1 ss1 pgood1 uv_delay v in ldrv2 hdrv2 sw2 cboot2 sgnd comp2 fb2 rsns2 ilim2 td2 ss2 pgood2 ct clko pgnd
LV5044V no.a0534-5/7 block diagram and sample application circuit
LV5044V no.a0534-6/7 pin functions pin no. pin function 1 v dd gate drive power supply for the external low side mosfets. connect this pin to vlin5 through a filter. 2 ldrv1 channel 1 external low side mosfet gate drive. this pin is also used as the signal input for short through prevention for the high and low side mosfets. hdrv cannot be turned on unless this pin's voltage goes below 1v. 3 hdrv1 channel 1 external high side mosfet gate drive. 4 sw1 this pin is connected to the channel 1 switching node. the external high side mosfet source and the low side mosf et drain are connected to this pin.this pin becomes the return current route of pin hdrv. the drain of the discharging mosfet used for the soft stop function is connected internal in the ic (typ.15 ). this pin is also used as the signal input for short through prevention for the high and low side mosfets. ldrv cannot be turned on unless this pin's voltage goes below 1v referenced to pgnd. 5 cboot1 channel 1 bootstrap capacitor connection. the high side mosfet gate drive power is suppli ed from this pin. this pin is connected to v dd through a diode and to sw1 through the bootstrap capacitor. 6 vlin5 internal 5v regulator output. the current is supplied from v in . the power supply for the ic internal control circuits is also supplied from this pin. a bypass capacitor (6.8 f) is required between this pin and sgnd. this pin is monitored by the uvlo function and the ic starts operating when it first rises above 4.0v. (after starting, the ic will only stop if this voltage falls below 3.8v.) 7 comp1 channel 1 phase compensation. the output of the internal transconductanc e amplifier is connected to this pin. t he external phase compensation circuit between this pin and sgnd. 8 fb1 channel 1 feedback input. the transconductance amplifier inverting ( ? ) input is connected to this pin. provide the feedback potential to this pin by voltage dividing the output voltage. the conv erter operates so that this pin goes to the internal reference voltage vref, 0.8v. this pin is also monitored by both the uvp comparator and the ovp comparator. if this pin voltage falls to under 87% of the set voltage, the pgood1 pin will go low and the uv_t imer will operate. if this pin voltage rises to over 117% of the set voltage, the ic w ill latch in the off state. 9 rsns1 input for the channel 1 side overcurrent detection compar ator and current detection amplifier. when resistor detection is used, connect the low side of the current detection resistor inserted between v in and the drain of the external high side mosfet to this pin. these connections must be wired ind ependently so that the shared impedance with the main current with respect to the detected voltage does not affect this circuit. 10 ilim1 connection to the channel 1 ov ercurrent detection trip point. a 8.3 a (ilim) sink constant-current supply is connected internal in the ic, and the overcurr ent detection voltage ilim rlim is generated by connecting the re sistor rlim between this pin and v in . the voltage between v in and ilim is compared to the voltage across the terminals of either the cu rrent detection resistor rsns or the high side mosfet to detect the overcurrent state. 11 td1 channel 1 startup delay connection. the time until the ic starts up after the power-on reset (por ) is cleared is set by the capacitor connected between this pin and sgnd. after the por state is cleared, the external capacitor is charged by a 3.5 a constant current supplied internally by the ic. the ic starts operation when the voltage on this pin exceeds 2.4v. the ic goes to the standby state when the voltage on this pin is under 2.4v. if no external capacit or is connected to this pin, the ic will start as soon as the power-on reset is cleared. 12 ss1 channel 1 soft start capacitor connection. after the power-on reset (por) is cleared and the td pin voltage exceeds 2.4v, this capa citor is charged by a 3.5 a internal constant current suppl y from the ss1 pin. this pin is connected to the transconductance amplifier's noninverting ( + ) input, and the ramp waveform of the ss1 pin is reflected in the ramped-up output waveform. after the uv_delay time out and the por operates, this capacitor is discharged by the ss pin. 13 pgood1 channel 1 power good pin. an ic internal 28v mosfet open drain is connected to this pi n. this pin outputs a low level if the channel 1 output voltage falls more than -13% relative to the set voltage. there is a hysteresis of about vref 1.5%. 14 uv_delay channel 1 and channel 2 common uvp delay connection. the time until the ic switches off after the uvp state is detected is set by the capacitor connected between this pin and sgnd. if either the channel 1 or channel 2 output voltage fa lls under -80% of the set voltage, an ic internal 8.6 a constant current source charges the exter nal capacitor connected to this pin. when the voltage on this pin exceeds 2.4v, the ic switches off. if no external capacitor is connected, the ic turn s off immediately upon detection of the uvp state. 15 v in ic power supply. 16 clko clock output. this pin outputs a clock signal synchronized with the ct pi n oscillator waveform. when two or more LV5044V chips are operated in synchronization, connect the ct pin of the slave de vice to the slko pin of the master device. if two or more devices are operated in synchronization and the td pin is used to change the startup timing between the devices, the device that starts the soonest will be the master. continued on next page.
LV5044V ps no.a0534-7/7 continued from preceding page. pin no. pin function 17 ct connection for the oscillato r circuit's external capacitor. connect that capacitor between this pin and ground. when ct i s 130pf, f osc will be 330khz. if an external clock is applied to this pin, the pwm control functions will operate at that clock frequency. if an external clock is provided, that signal must be a square wave with a low level of 0v and a high level between 3.3 and 5.0v. the square wave generator must have a fanout drive capac ity of at least 1ma.and uv_delay function doesn't operate when this pin is grounded. 18 pgood2 channel 2 power good pin. 19 ss2 channel 2 soft start func tion capacitor connection. 20 td2 channel 2 startup delay connection. 21 ilim2 channel 2 overcurrent detection trip point setting. 22 rsens1 channel 2 overcurrent detection comparator input. 23 fb2 channel 2 feedback input. 24 comp2 channel 2 phase compensation. 25 sgnd ic system ground. the reference voltage is generated referenced to this pi n. the system ground must be connected to this pin. 26 cboot2 channel 2 bootstrap capacitor connection. 27 sw2 this pin is connected to the channel 2 switching node. 28 hdrv2 channel 2 external high side mosfet gate drive. 29 ldrv2 channel 2 external low side mosfet gate drive. 30 pgnd power system ground. this pin is used as the current return path for the ldrv pin. on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability ar ising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorize d for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other appli cation in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws a nd is not for resale in any manner.
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