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| t c 62 d 7 22 c fg / c fng 2011 - 09- 24 1 toshiba c d mos integrated circuit silicone monolithic t c 62d 722 c f g, t c 62d 72 2 c fng 16- output constant current led driver with the o utput gain control function and the pwm grayscale function feature the t c 62 d 722 series are led drivers which have the sink - type constant current output. this ic is most suitable for lighting the led module and the display. the o utput gain control function of 8 - bit and the pwm grayscale function of 16, 14, 12, and 10 - bit are built into this ic. o utput current value of 16 channels is set by one external resistance. in addition, the t hermal shutdown function , the output open de tection function , and the output short detection function are built in. characteristics ? supply voltage : v dd = 3.0 to 5.5 v ? 16- output built - in ? output current setup range : i out = 1.5 to 9 0 ma ? constant current output accuracy ( @ r ext = 1.2 k? , v out = 1.0 v, v dd = 3.3 v, 5.0 v ) : s rank between outputs 1 .5 % ( max ), between devices: 1 .5 % ( max ) : n rank between outputs 2 .5 % ( max ), between devices: 2 .5 % ( max ) ? output voltage : v out = 17 v ( max ) ? i/o interface : c mos interfaces (input o f a schmitt trigger) ? data transfer frequency : f sck = 3 0 mhz ( max ) ? pwm frequency : f pwm = 3 3 mhz ( max ) ? operatio n temperature range : t opr = ? 40 to 85 c ? 8 - bit (256 steps) o utput gain control function built - in . ? pwm gray scale function built - in . ( pwm reso lution is sel ectable ) 16- bit ( 65536 steps), 14- bit ( 16384 steps) 12- bit ( 4096 steps), 10- bit ( 1024 steps) ? t hermal shutdown function (tsd) built - in . ? output error detection function built - in . this function has the automatic operation and the command input ma nual operation. outp ut open detection function (ood) and outpu t short detection function (osd) built - in . ? power - on- reset function built - in . ( when the power supply is turned on, internal data is reset ) ? s tand - by function built - in . (i dd =1a at standby mode) ? ou tput delay fun ction built - in . ( output switching noise is reduced) ? package c fg type : ssop24 - p - 300- 1.00b c fng type : p - h tssop24 - 0508 - 0.65 - 001 please ask toshiba sales dept or agent for details for products name. tc 62d 722c fg ssop24 - p - 300- 1.00b t c 62d 722c fng p - h tssop24 - 0508- 0.65 - 001 weight ssop24 -p-300- 1.00b : 0.32 g ( typ. ) p - htssop24 -0508- 0.65- 001: 0.10 g ( typ. )
t c 62 d 7 22 c fg / c fng 2011 - 09- 24 2 block diagram out0 out1 out15 sin sck vdd gnd rext sout constant current output circuit pwm count e r 8 - bit dac reference v oltage pwmclk trans error detection result data register 16 - bit 2 s tate setting register 16 16 - bit shift regist e r 6 ?? 16- bit pwm data for 0 out data transfer control circuit 16 16 16 16 8 ?????? ???? ????????????? 16 15 - bit 0 - bit 16 pod circuit comparator 16 - bit pwm data for 0 out 16 - bit pwm data for 1 out 16 - bit pwm data for 15 out 16 ????????????? output o n /o ff setting data register 15- bit 0 - bit tsd circuit 16 ?? 16- bit pwm data for 1 out 6 ?? 16- bit pwm data for 15 out pwm data register por circuit 16 f/f sout s election circuit output open/short d etection circuit comparator comparator 16 s0 (s1) s1 s2 s3 (s1) s4 s5 (s6) 16 - bit pwm data for 0 out 16 - bit pwm data for 1 out 16 - bit pwm data for 15 out ????????????? 16 16 16 16 16 16 16 16 16 16 16 16 register 2 for synchronous register 3 for output register 1 output delay circuit command c ontrol circuit t c 62 d 7 22 c fg / c fng 2011 - 09- 24 3 pin assignment (top view) pin description pin no pin name i/o function 1 gnd ? the ground pin. 2 sin i the serial data input pin. 3 sck i the serial data transfer clock input pin. 4 trans i the data transfer comm and input pin. 5 0 out o the s ink type constant current output pin. 6 1 out o the sink type constant current output pin. 7 2 out o the sink type constant current output pin. 8 3 out o the sink type constant current output pin. 9 4 out o the sink type constant current output pin. 10 5 out o the sink type constant current output pin. 11 6 out o the sink type consta nt current output pin. 12 7 out o the sink type constant current output pin. 13 8 out o the sink type constant current output pin. 14 9 out o the sink type constant current output pin. 15 10 out o the sink type constant current output pin. 16 11 out o the sink type constant current output pin. 17 12 out o the sink type constant current output pin. 18 13 out o the sin k type constant current output pin. 19 14 out o the sink type constant current output pin. 20 15 out o the sink type constant current output pin. 21 pwmclk i the r eference clock input pin for pwm grayscale control. one cycle of the input clock becomes a minimum pulse width of the pwm output. 22 sout o the serial data output pin. 23 r ext ? the constant current value setting resistor connection pin. 24 v dd ? the power supply input pin. gnd sin sck 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7 out vdd rext sout pwmclk 15 out 14 out 13 out 12 out 11 out 10 out 9 out t rans 8 out t c 62 d 7 22 c fg / c fng 2011 - 09- 24 4 equivalent circuit of input a nd output 1. sck, sin 2. pwmclk, trans 3 . sout 4 . out0 to out15 0 out to 15 out gnd v dd sout gnd (sck) (sin) gnd v dd gnd (pwmclk) (trans) v dd t c 62 d 7 22 c fg / c fng 2011 - 09- 24 5 1 . e xplanation of the function ( basic data input pattern) d ata input is done with the sin pin and the sck pin . c ommand sel ection is done with the sck pin and the trans pin . about the operation of each command command number of sck pulses at trans=h note 3 ,4 o peration s0 0,1 the pwm data in the 16 - bit shift register is transmitted to the pwm data register 1 . s1 2,3 1. the pwm data in the pwm data register 1 is transmitted to the pwm data register 2 or 3. note 1 2. t he automatic o u tput open/short detection result data is transmitted to the 16- bit shift register. note 2 3. pwm output start. s2 7,8 input of the output on/off da ta. ( when this function is not used, this input is unnecessary.) s3 9,10 the manual o utput open/short detection function s are exec uted. note 2 the manual o utput open/short detection result data is transmitted to the 16 - bit shift register. note 2 s4 11,12 r eset of the internal pwm counter . s5 13,14 input of the state setting data (1) . s6 15,16 input of the state setting data (2) . note1: t ransmitted register changes by a pwm counter synchronization setting. note2: this operation is performed when the outpu t open/short detection function is active setting. note3: other sck numbers are disregarded. n o te4: if sck is "l" when changing trans into "h", please make scl "l" when changing trans into "l" if sck is " h " when changing trans into " h ", please make scl " h " when changing trans into "l" ? s0 command ( the pwm data is transmitted to the pwm data register 1.) sck trans sin pwm data number of sck pulses at trans="h" is 0 or 1 . ? s1 command ( the pwm data is transmitted to the pwm data register 2 or 3.) sck trans sin data input of the 16-bit shift register is unnecessary. 2 3 number of sck pulses at trans ="h" is 2 or 3 ? s2 command ( in put of the output on/off data. ) sck trans sin output on / off data 2 3 4 5 6 7 8 number of sck pulses at trans =" h " is 7 or 8 ? s 3 command ( the o utput open /short detection function s manual operation is executed. ) sck trans sin data input of the 16 - bit shift register is unnecessary . 2 3 4 5 6 7 8 9 10 number of sck pulses at trans =" h " is 9 or 10 ? s 4 command ( reset of the internal pwm counter . ) sck trans sin data input of the 16 -bit shift register is unnecessary. 2 3 4 5 6 7 8 9 10 11 12 number of sck pulses at trans ="h" is 11 or 12 ? s5 command ( input of the state setting data (1). ) sck trans sin state setting data ( 1 ) 2 3 4 5 6 7 8 9 10 11 12 13 14 number of sck pulses at trans =" h " is 13 or 14 ? s 6 command ( input of the state setting data ( 2 ). ) sck trans sin state setting data ( 2 ) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 number of sck pulses at trans =" h " is 1 5 or 1 6 t c 62 d 7 22 c fg / c fng 2011 - 09- 24 6 2 . about the operation of each command 2 - 1 - 1 ) s0 command ( the pwm data is transmitted to the pwm data register 1.) operation ) in t he number of sck pulses at trans="h" is 0 or 1 , the following operation is executed. the pwm data in the 16- bit shift register is transmitted to the pwm data register 1 . it is necessary to repeat this command 16 times to input the pwm data of 0 out to 15 out . the order of the pwm data transfer is the following. 15 out 14 out 13 out 12 out 11 out 10 out 9 out 8 out 7 out 6 out 5 out 4 out 3 out 2 out 1 out 0 out basic input pattern of s 0 comman d) sck trans sin sout d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 repetition pattern ~ out 0 is input by repeating this pattern 16 times . the period of trans =" h " does not receive the data input from sin . sout is operation at the time of s 6 command n 0 = 0 conditions . t c 62 d 7 22 c fg / c fng 2011 - 09- 24 7 2 - 1 - 2 ) input form of the pwm data pwm resolution is set by the s5 command. default setting is 16 - bit . 1. 16- bit pwm setting msb lsb d15 d14 d13 d12 d11 d10 d9 d 8 d7 d6 d5 d4 d3 d2 d1 d0 pwm setting (reference) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/65535 ( default ) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1/65535 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2/65535 ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 65533/65535 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 65534/65535 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 65535/65535 d15 to d0 is serial - data - inputted at msb first. 2 . 1 4 - bit pwm setting msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 pwm setting (reference) dont care 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/16383(default) 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1/16383 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2/16383 ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? 1 1 1 1 1 1 1 1 1 1 1 1 0 1 16381/16383 1 1 1 1 1 1 1 1 1 1 1 1 1 0 16382/16383 1 1 1 1 1 1 1 1 1 1 1 1 1 1 16383/16383 d15 to d0 is serial - data - inputted at msb first. 3 . 1 2 - bit pwm settin g msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 pwm setting (reference) dont care 0 0 0 0 0 0 0 0 0 0 0 0 0/4095(default) 0 0 0 0 0 0 0 0 0 0 0 1 1/4095 0 0 0 0 0 0 0 0 0 0 1 0 2/4095 ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? 1 1 1 1 1 1 1 1 1 1 0 1 4093/ 4095 1 1 1 1 1 1 1 1 1 1 1 0 4094/4095 1 1 1 1 1 1 1 1 1 1 1 1 4095/4095 d15 to d0 is serial - data - inputted at msb first. 4 . 1 0 - bit pwm setting msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 pwm setting (reference) dont care 0 0 0 0 0 0 0 0 0 0 0/ 1023(default) 0 0 0 0 0 0 0 0 0 1 1/1023 0 0 0 0 0 0 0 0 1 0 2/ 1023 ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? 1 1 1 1 1 1 1 1 0 1 1021/ 1023 1 1 1 1 1 1 1 1 1 0 1022 / 1023 1 1 1 1 1 1 1 1 1 1 1023 / 1023 d15 to d0 is serial - data - inputted at msb first. t c 62 d 7 22 c fg / c fng 2011 - 09- 24 8 2 - 2 - 1 ) s1 command ( the pwm data is transmitted to the pwm data register 2 or 3.) operation ) in t he number of sck pulses at trans="h" is 2 or3 , the following operation is executed. 1. the pwm data in the pwm data register 1 is transmitted to the pwm data register 2 or 3. 2. the automatic o utput open/short detection result data is trans mitt ed to the 16- bit shift register. note 1 when internal pwm count is 1 to 21, the out put open/ short detection automatic operation is done. during detection, th e detection current flows to the 0 out ~ 15 out terminal. the d etection current is about 4 a . 3. the pwm output start. in the input of this command, the pwm output is turn ed on once. wh en restarting b y sam e pwm data, please input this command again. about the output operation when this command is input while pwm output. 1. when the pwm counter is the synchronous mode. note 2 after the present pwm out put has ended, pwm output is started by new pwm data. 2 . when the pwm counter is the a synchronous mode. note 2 the present pwm output is canceled and a pwm output is immediately started by new pwm data. basic input pattern of s1 comman d) sck trans 0 pwmclk sout 1 21 20 t he output open/short detection automatic operation is done previous data e 15 e14 e13 command execution 2 3 x sout is operation at the time of s 6 command n0=0 conditions. the first sck (signal x) aft er s1 command is used for transmission of the output open/short detection result data. the input from sin is not received. note 1 when internal pwm count is 1 to 21, the output open/ short detection automatic opera tion is done. t he detection current flows to the 0 out ~ 15 out terminal. the d etection current is about 4 a . note1 note1: this operation is performed when the output open/short detection function is active setting. the output open/short detection function s are set by s6 command. d efault setting is not active . note2: pwm output synchronization pwm resolution is set by the s 6 command. d efault setting is s ynchronous mode . t c 62 d 7 22 c fg / c fng 2011 - 09- 24 9 2 - 2 - 2 ) o utput form of the o utput op en /shor t detection result data it is transmitted to 16 bit - shift register in the following form. msb lsb e 15 e 14 e 13 e 12 e 11 e 10 e 9 e 8 e 7 e 6 e 5 e 4 e 3 e 2 e 1 e 0 15 out 14 out 13 out 12 out 11 out 10 out 9 out 8 out 7 out 6 out 5 out 4 out 3 out 2 out 1 out 0 out e 15 to e 0 is serial - data - out putted at msb first. error code (when output open detection function is effective) the state of output error code condition of output v ood v out 0 open v ood < v out 1 normal error code (when o utput short detection function is effective) the state of output error code condition of output v o s d 1/2 v out 0 short - circuit v o s d 1/2 > v out 1 normal error code (when output open/ short detection function is effective) the state of output error code co ndition of output v ood v out or v o s d 1/2 v out 0 open or short - circuit v ood < v out or v o s d 1/2 > v out 1 normal when both output error detection function is effective, open and short - circuit are undistinguishable. when internal pwm count is 1 to 21, th e output open/ short detection automatic operation is done. when the output is off during the output open/ s hort detection execution , the error code becomes "1". setting of pwm output mode setting of pwm bit s number the pwm step that becomes error code "1" w ithout relat ions in the state of the output pin . normal pwm output mode 16 bit pwm setting 0 t o 20 pwm stepsetting 1 4 bit pwm setting 1 2 bit pwm setting 1 0 bit pwm setting division pwm output mode 16 bit pwm setting 0 t o 2560 pwm stepsetting 1 4 bit pwm setting 1 2 bit pwm setting 1 0 bit pwm setting 0 t o 960 pwm stepsetting the above table is unrelated at the time of the output open/ short detection manual operation by s3 c ommand . t c 62 d 7 22 c fg / c fng 2011 - 09- 24 10 2 - 3 - 1 ) s2 command ( input of the output on/off data. ) when this function is not used, this input is unnecessary. operation ) in t he number of sck pulses at trans="h" is 7 or 8 , the following operation is executed. input of the output on/off data. even if pwm data is not changed to 0 settings, o n / off of the output can be controlled. about the output operation when this command is input while pwm output. 1. when the pwm counter is the synchronous mode. note 1 the setting of this command is reflected in the next pwm output. 2. when the pwm counter is the a synchronou s mode. note 1 the setting of this command is reflected immediately. basic input pattern of s 2 comman d) the period of trans="h" does not receive the data input from sin. sout is operation at the time of s6 command n0=0 conditions. note1: pwm output synchronization pwm resolution is set by the s 6 command. d efault setting is s ynchronous mode . 2 - 3 - 2) i n put form of the output on/off data msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 15 out 14 out 13 out 12 out 11 out 10 out 9 out 8 out 7 out 6 out 5 out 4 out 3 out 2 out 1 out 0 out d15 to d0 is serial - data - inputted at msb first. the o utput on/off data setting input data setting 1 output operates according to pwm data setting. (default) 0 output turn off t c 62 d 7 22 c fg / c fng 2011 - 09- 24 11 2 - 4) s3 command ( th e manual o u tput open /short detection function s are executed. ) operation ) in t he number of sck pulses at trans="h" is 9 or 10 , the following operation is executed. the manual output open/short detection functi ons are executed. note1 the output is compulso rily turned on during t on(s3) w ith about 6 0 a . and detection is done. the manual o utput open/short detection result data is trans mitt ed to the 16- bit shift register. t on(s3) is about 800ns. for the period of t on(s3) , please set sck and trans to l. when inputting this command during pwm output, the manual o utput open/short det ection function s are executed after the pwm output. in this case, t on(s3) occurs after a pwm output. basic input pattern of s3 comman d) sck trans outn sout e 15 previous data command execution 2 e 14 e 13 e 11 e 12 e 10 e 9 e 7 e 8 e 6 e 5 e 3 e 4 e 2 e 1 t on ( s 3 ) off on 9 10 x sout is operation at the time of s 6 command n 0 = 0 conditions . the first sck (signal x) after this command is used for transmission of the output open /short detection result data. the input from sin is not receive d. note 1 note1: this operation is performed when the output open/short detection function is active setting. the output open/short detection function s are set by s6 command. d efault setting is not active . 2 - 5) s 4 command ( reset of the internal pwm counter . ) operation ) in t he number of sck pulses at trans="h" is 11 or 12 , the following operation is executed. the in t ernal pwm counter is reset. when the internal pwm counter is reset, the ou tput is turned off. it is necessary to input s1 command to turn on the output again. basic input pattern of s4 comman d) sck trans pwmclk sout command execution 2 11 12 off on n 0 0 0 0 t c 62 d 7 22 c fg / c fng 2011 - 09- 24 12 2 - 6 - 1 ) s5 command ( input of the state setting data (1). ) operation ) in t he number of sck pulses at tran s="h" is 13 or 14 , the following operation is executed. the s tate setting data (1) in the 16- bit shift register is transmitted to the state setting register. basic input pattern of s5 comman d) d 15 a 7 d 14 a 6 d 13 a 5 d 12 a 4 d 11 a 3 d 10 a 2 d 9 a 1 d 8 a 0 d 7 - d 6 - d 5 - d 4 - d 3 b 1 d 2 b 0 d 1 h 0 d 0 l 0 previous data d14 d13 d12 d15 d15 command execution previous data the period of trans="h" does not receive the data input from sin. sout is operation at the time of s6 command n0=0 conditions. sout (h0=0) sout (h0=1) 2 - 6 - 2) in put form of the stat e setting data (1) msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a7 a6 a5 a4 a3 a2 a1 a0 - - - - b1 b0 h0 l0 d15 to d0 is serial - data - inputted at msb first. please input "l" data to d7 to d4. the s tate setting data (1) setting setting b it outline of command input data (default) 0 1 a7 setting of o utput gain control range high set ting mode 47.5 % to 20 2.7 % low set ting mode 8.46 % to 43.96 % 47.5 % to 20 2.7 % a6 to a0 setting of o utput gain control data please refer to 1 3 1 4 page. 100.0 % b1 to b0 setting of pwm resolution please refer to 1 5 page. 16- bit h0 setting of initialization function not active active not active l0 setting of standby mode (1) function not active active not active t c 62 d 7 22 c fg / c fng 2011 - 09- 24 13 2 - 6 - 3 ) details of each setting a setting (set ting of o utput gain control data r eference value ) 1. in the case of the high setting mode ( 47.5 % to 20 2.7 %) a[6] a[5] a[4] a[3] a[2] a[1] a[0] current g ain (%) a[6] a[5] a[4] a[3] a[2] a[1] a[0] current g ain (%) 1 1 1 1 1 1 1 202.7 0 1 1 1 1 1 1 124.5 1 1 1 1 1 1 0 201.5 0 1 1 1 1 1 0 123.3 1 1 1 1 1 0 1 200.3 0 1 1 1 1 0 1 122.0 1 1 1 1 1 0 0 199.1 0 1 1 1 1 0 0 120.8 1 1 1 1 0 1 1 197.8 0 1 1 1 0 1 1 119.6 1 1 1 1 0 1 0 196.6 0 1 1 1 0 1 0 118.4 1 1 1 1 0 0 1 195.4 0 1 1 1 0 0 1 117.2 1 1 1 1 0 0 0 194.2 0 1 1 1 0 0 0 115.9 1 1 1 0 1 1 1 193.0 0 1 1 0 1 1 1 114.7 1 1 1 0 1 1 0 191.7 0 1 1 0 1 1 0 113.5 1 1 1 0 1 0 1 190.5 0 1 1 0 1 0 1 112.3 1 1 1 0 1 0 0 189.3 0 1 1 0 1 0 0 111.0 1 1 1 0 0 1 1 188.1 0 1 1 0 0 1 1 109.8 1 1 1 0 0 1 0 186.8 0 1 1 0 0 1 0 108.6 1 1 1 0 0 0 1 185.6 0 1 1 0 0 0 1 107.4 1 1 1 0 0 0 0 184.4 0 1 1 0 0 0 0 106.2 1 1 0 1 1 1 1 183.2 0 1 0 1 1 1 1 104.9 1 1 0 1 1 1 0 181.9 0 1 0 1 1 1 0 103.7 1 1 0 1 1 0 1 180.7 0 1 0 1 1 0 1 102.5 1 1 0 1 1 0 0 179.5 0 1 0 1 1 0 0 101.3 1 1 0 1 0 1 1 178.3 0 1 0 1 0 1 1 100.0 (default) 1 1 0 1 0 1 0 177.1 0 1 0 1 0 1 0 98.8 1 1 0 1 0 0 1 175.8 0 1 0 1 0 0 1 97.6 1 1 0 1 0 0 0 174.6 0 1 0 1 0 0 0 96.4 1 1 0 0 1 1 1 173.4 0 1 0 0 1 1 1 95.2 1 1 0 0 1 1 0 172.2 0 1 0 0 1 1 0 93.9 1 1 0 0 1 0 1 170.9 0 1 0 0 1 0 1 92.7 1 1 0 0 1 0 0 169.7 0 1 0 0 1 0 0 91.5 1 1 0 0 0 1 1 168.5 0 1 0 0 0 1 1 90.3 1 1 0 0 0 1 0 167.3 0 1 0 0 0 1 0 89.0 1 1 0 0 0 0 1 166.1 0 1 0 0 0 0 1 87.8 1 1 0 0 0 0 0 164.8 0 1 0 0 0 0 0 86.6 1 0 1 1 1 1 1 163.6 0 0 1 1 1 1 1 85.4 1 0 1 1 1 1 0 162.4 0 0 1 1 1 1 0 84.2 1 0 1 1 1 0 1 161.2 0 0 1 1 1 0 1 82.9 1 0 1 1 1 0 0 159.9 0 0 1 1 1 0 0 81.7 1 0 1 1 0 1 1 158.7 0 0 1 1 0 1 1 80.5 1 0 1 1 0 1 0 157.5 0 0 1 1 0 1 0 79.3 1 0 1 1 0 0 1 156.3 0 0 1 1 0 0 1 78.0 1 0 1 1 0 0 0 155.1 0 0 1 1 0 0 0 76.8 1 0 1 0 1 1 1 153.8 0 0 1 0 1 1 1 75.6 1 0 1 0 1 1 0 152.6 0 0 1 0 1 1 0 74.4 1 0 1 0 1 0 1 151.4 0 0 1 0 1 0 1 73.2 1 0 1 0 1 0 0 150.2 0 0 1 0 1 0 0 71.9 1 0 1 0 0 1 1 148.9 0 0 1 0 0 1 1 70.7 1 0 1 0 0 1 0 147.7 0 0 1 0 0 1 0 69.5 1 0 1 0 0 0 1 146.5 0 0 1 0 0 0 1 68.3 1 0 1 0 0 0 0 145.3 0 0 1 0 0 0 0 67.0 1 0 0 1 1 1 1 144.1 0 0 0 1 1 1 1 65.8 1 0 0 1 1 1 0 142.8 0 0 0 1 1 1 0 64.6 1 0 0 1 1 0 1 141.6 0 0 0 1 1 0 1 63.4 1 0 0 1 1 0 0 140.4 0 0 0 1 1 0 0 62.1 1 0 0 1 0 1 1 139.2 0 0 0 1 0 1 1 60.9 1 0 0 1 0 1 0 137.9 0 0 0 1 0 1 0 59.7 1 0 0 1 0 0 1 136.7 0 0 0 1 0 0 1 58.5 1 0 0 1 0 0 0 135.5 0 0 0 1 0 0 0 57.3 1 0 0 0 1 1 1 134. 3 0 0 0 0 1 1 1 56.0 1 0 0 0 1 1 0 133.1 0 0 0 0 1 1 0 54.8 1 0 0 0 1 0 1 131.8 0 0 0 0 1 0 1 53.6 1 0 0 0 1 0 0 130.6 0 0 0 0 1 0 0 52.4 1 0 0 0 0 1 1 129.4 0 0 0 0 0 1 1 51.1 1 0 0 0 0 1 0 128.2 0 0 0 0 0 1 0 49.9 1 0 0 0 0 0 1 126.9 0 0 0 0 0 0 1 48.7 1 0 0 0 0 0 0 125.7 0 0 0 0 0 0 0 47.5 t c 62 d 7 22 c fg / c fng 2011 - 09- 24 14 2 . in the case of the low setting mode ( 8.46 % to 43.96 %) a[6] a[5] a[4] a[3] a[2] a[1] a[0] current g ain (%) a[6] a[5] a[4] a[3] a[2] a[1] a[0] current g ain (%) 1 1 1 1 1 1 1 43.96 0 1 1 1 1 1 1 2 6.07 1 1 1 1 1 1 0 43.68 0 1 1 1 1 1 0 25.79 1 1 1 1 1 0 1 43.40 0 1 1 1 1 0 1 25.51 1 1 1 1 1 0 0 43.12 0 1 1 1 1 0 0 25.23 1 1 1 1 0 1 1 42.84 0 1 1 1 0 1 1 24.95 1 1 1 1 0 1 0 42.56 0 1 1 1 0 1 0 24.67 1 1 1 1 0 0 1 42.28 0 1 1 1 0 0 1 24.39 1 1 1 1 0 0 0 42.00 0 1 1 1 0 0 0 24.11 1 1 1 0 1 1 1 41.72 0 1 1 0 1 1 1 23.83 1 1 1 0 1 1 0 41.44 0 1 1 0 1 1 0 23.55 1 1 1 0 1 0 1 41.16 0 1 1 0 1 0 1 23.27 1 1 1 0 1 0 0 40.89 0 1 1 0 1 0 0 23.00 1 1 1 0 0 1 1 40.61 0 1 1 0 0 1 1 22.72 1 1 1 0 0 1 0 40.33 0 1 1 0 0 1 0 22.44 1 1 1 0 0 0 1 40.05 0 1 1 0 0 0 1 22.16 1 1 1 0 0 0 0 39.77 0 1 1 0 0 0 0 21.88 1 1 0 1 1 1 1 39.49 0 1 0 1 1 1 1 21.60 1 1 0 1 1 1 0 39.21 0 1 0 1 1 1 0 21.32 1 1 0 1 1 0 1 38.93 0 1 0 1 1 0 1 21.04 1 1 0 1 1 0 0 38.65 0 1 0 1 1 0 0 20.76 1 1 0 1 0 1 1 38.37 0 1 0 1 0 1 1 20.48 1 1 0 1 0 1 0 38.09 0 1 0 1 0 1 0 20.20 1 1 0 1 0 0 1 37.81 0 1 0 1 0 0 1 19.92 1 1 0 1 0 0 0 37.53 0 1 0 1 0 0 0 19.64 1 1 0 0 1 1 1 37.25 0 1 0 0 1 1 1 19.36 1 1 0 0 1 1 0 36.97 0 1 0 0 1 1 0 19.08 1 1 0 0 1 0 1 36.69 0 1 0 0 1 0 1 18.80 1 1 0 0 1 0 0 36.41 0 1 0 0 1 0 0 18.52 1 1 0 0 0 1 1 36.13 0 1 0 0 0 1 1 18.24 1 1 0 0 0 1 0 35.85 0 1 0 0 0 1 0 17.96 1 1 0 0 0 0 1 35.57 0 1 0 0 0 0 1 17.68 1 1 0 0 0 0 0 35.29 0 1 0 0 0 0 0 17.40 1 0 1 1 1 1 1 35.02 0 0 1 1 1 1 1 17.13 1 0 1 1 1 1 0 34.74 0 0 1 1 1 1 0 16.85 1 0 1 1 1 0 1 34.46 0 0 1 1 1 0 1 16.57 1 0 1 1 1 0 0 34.18 0 0 1 1 1 0 0 16.29 1 0 1 1 0 1 1 33.90 0 0 1 1 0 1 1 16.01 1 0 1 1 0 1 0 33.6 2 0 0 1 1 0 1 0 15.73 1 0 1 1 0 0 1 33.34 0 0 1 1 0 0 1 15.45 1 0 1 1 0 0 0 33.06 0 0 1 1 0 0 0 15.17 1 0 1 0 1 1 1 32.78 0 0 1 0 1 1 1 14.89 1 0 1 0 1 1 0 32.50 0 0 1 0 1 1 0 14.61 1 0 1 0 1 0 1 32.22 0 0 1 0 1 0 1 14.33 1 0 1 0 1 0 0 31.94 0 0 1 0 1 0 0 14.05 1 0 1 0 0 1 1 31.66 0 0 1 0 0 1 1 13.77 1 0 1 0 0 1 0 31.38 0 0 1 0 0 1 0 13.49 1 0 1 0 0 0 1 31.10 0 0 1 0 0 0 1 13.21 1 0 1 0 0 0 0 30.82 0 0 1 0 0 0 0 12.93 1 0 0 1 1 1 1 30.54 0 0 0 1 1 1 1 12.65 1 0 0 1 1 1 0 30.26 0 0 0 1 1 1 0 12.37 1 0 0 1 1 0 1 29.98 0 0 0 1 1 0 1 12.09 1 0 0 1 1 0 0 29.70 0 0 0 1 1 0 0 11.81 1 0 0 1 0 1 1 29.42 0 0 0 1 0 1 1 11.53 1 0 0 1 0 1 0 29.15 0 0 0 1 0 1 0 11.26 1 0 0 1 0 0 1 28.87 0 0 0 1 0 0 1 10.98 1 0 0 1 0 0 0 28.59 0 0 0 1 0 0 0 10.70 1 0 0 0 1 1 1 28.31 0 0 0 0 1 1 1 10.42 1 0 0 0 1 1 0 28.03 0 0 0 0 1 1 0 10.14 1 0 0 0 1 0 1 27.75 0 0 0 0 1 0 1 9.86 1 0 0 0 1 0 0 27.47 0 0 0 0 1 0 0 9.58 1 0 0 0 0 1 1 27.19 0 0 0 0 0 1 1 9.30 1 0 0 0 0 1 0 26.91 0 0 0 0 0 1 0 9. 02 1 0 0 0 0 0 1 26.63 0 0 0 0 0 0 1 8.74 1 0 0 0 0 0 0 26.35 0 0 0 0 0 0 0 8.46 t c 62 d 7 22 c fg / c fng 2011 - 09- 24 15 b settin g ( s ettin g of pwm resolution ) b[1] b[0] s etting 0 0 16 - bit (65536 steps ) setting . (default) 0 1 14 - bit (16384 steps) setting . 1 0 12 - bit (4096 steps) setting . 1 1 10 - bit (1024 steps) setting . h setting ( setting of initializati on function h [0] setting 0 the initialization function becomes not active (default) it's normal operation mode. 1 the initialization function becomes active . all data in ic is initi alized. after data initialization, it becomes normal operation mode. l setting (setting of standby mode (1) function ) l[0] setting 0 the standby mode (1) function becomes not active . (default) it's normal operation mode. 1 the standby mode (1) functio n becomes active . the circuits other than the logic circuit are turned off. and power supply current is reduced. ( all the data of the ic are stored. data input is possible. ) when s 0 command is input ted at the standby mode (1) , ic returns to normal operatio n mode. return time to the normal operation mode is about 30 s. t c 62 d 7 22 c fg / c fng 2011 - 09- 24 16 2 - 7 - 1 ) s6 co mmand ( input of the state setting data ( 2 ). ) operation ) in t he number of sck pulses at trans="h" is 15 or 1 6 , the following operation is executed. the s tate setting data ( 2 ) in the 16- bit shift register is transmitted to the state setting register. basic input pattern of s 6 comman d) sck trans sin d 15 c 0 d 14 d 0 d 13 e 0 d 12 f 0 d 11 g 0 d 10 i 0 d 9 j 0 d 8 k 0 d 7 m 0 d 6 n 0 d 5 - d 4 - d 3 - d 2 - d 1 - d 0 - previous data d14 d13 d12 d15 command execution previous data 2 15 16 d14 d13 d15 the period of trans="h" does not receive the data input from sin. sout (n0=0) sout (n0=1) 2 - 7 - 2) in pu t form of the state setting data ( 2 ) msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 c0 d 0 e0 f0 g0 i0 j0 k0 m0 n0 - - - - - - d15 to d0 is serial - data - inputted at msb first. please input "l" data to d 5 to d 0 . the s tate setting data ( 2 ) setting setting bit outline of command input data (default) 0 1 c0 setting of t hermal shutdown functi on ( tsd ) active not active active d0 setting of pwmclk open detecti on function (po d ) active not active active e0 setting of o utput open detection function ( ood ) not active active not active f0 setting of o utput short detection function ( o s d ) not active active not active g0 setting of pwm output synchronization synchronous asynchronous synchronous i0 setting of pwm output system normal output division output normal output j0 setting of standby mode ( 2 ) function this function becomes active only at the time of the 16 - bit pwm set ting . not active active not active k0 setting of o utput short detection voltage v osd1 v os d 2 v os d 1 m0 setting of o utput d e l ay function active not active active n0 setting of sck trigger of sout up edge trigger mode down edge tr igger mode up edge trigger mode t c 62 d 7 22 c fg / c fng 2011 - 09- 24 17 2 - 7 - 3) details of each setting c setting ( setting of t hermal shutdown function ( tsd ) ) c[0] setting 0 thermal shutdown function becomes active . (default) 1 thermal shutdown function becomes not active . d setting ( setti ng of pwmclk open detecti o n function (po d ) ) d[0] setting 0 pwmclk open detection function becomes active . (default) when it was the state that a pwmclk signal isn't input by breaking of wiring, it's the function which prevents pwm output keeping stopping by on state. when pwmclk is not inputted for about 1 second after it is inputted even once, all output is turned off compulsorily. output compulsion off is released by the initialization function of s5 command. in addition, the output compulsion off is rem oved by inputting pwmclk again. 1 pwmclk open detection function becomes not active . e setting ( setting of o utput open detection function ( ood ) ) e[0] setting 0 output open detection function becomes not active . (default) 1 output open detection functi on becomes active . f setting ( setting of o utput short detection function ( o s d ) ) f[0] setting 0 output short detection function becomes not active . (default) 1 output short detection function becomes active . g setting ( setting of pwm output synchroniz ation ) g[0] setting 0 pwm output synchronous mode . (default) 1 pwm output asynchronous mode. i setting ( setting of pwm outp ut system ) i[0] setting 0 normal pwm output mode. (default) 1 division pwm output mode. t c 62 d 7 22 c fg / c fng 2011 - 09- 24 18 j setting ( setting of standby mode ( 2 ) ) j[0] setting 0 the standby mode ( 2 ) function becomes not active . (default) it's normal operation mode. 1 the standby mode ( 2 ) function becomes active . a state changes according to the data in a pwm data register. condit ion 1: all data in the pwm dat a register 1 and the pwm data register 3 are "l". it becomes standby mode (2) . the circuits other than the logic circuit are turned off. and power supply current is reduced. ( all the data of the ic are stored. data input is possible. ) condition 2: excluding condition 1. it becomes pre standby mode. it is the same operation as normal operation mode. r eturn time from standby mode (2) to pre standby mode is about 30 s. this function becomes active only at the time of the 16 - bit pwm set ting . k setting ( setting of o utput short detection voltage ) k[0] setting 0 v osd 1 setting. (default) 1 v osd 2 setting. m setting ( setting of o utput d e l ay function ) m[0] set ting 0 output delay function becomes active . (default) 1 output delay function becomes not active . n setting ( setting of sck trigger of sout ) n[0] setting 0 it becomes up edge trigger mode. (default) data output trigger from sout, becomes up edge of sck 1 it becomes down edge trigger mode. data output trigger from sout, becomes down edge of sck t c 62 d 7 22 c fg / c fng 2011 - 09- 24 19 3 . input of pwm setting data 3 - 1) normal input mode ( s0 command : 16 times) it commands the pwm data input only. the pwm data for 0 out to 15 out are transferred to the pwm data resister by repeating the pwm data input to the 16 - bit shift register and s0 command input 16 times. unless s1 command is input, the pwm data for 0 out to 15 out is not reflected on output. normal input mode) s0 command 16 times 0 0 0 s 1 command the pwm d ata for out 15 ~ out 0 are reflect ed on output s 0 command data is transmitted to out 15. s 0 command data is transmitted to out 14. s 0 command data is transmitted to out 0 . 3 - 2) speed input mode ( s0 command 15 times + s1 command once) it commands pwm data input and r eflecting the pwm data on output at the same time. the pwm data for 0 out to 15 out are reflec ted in the output by inputting s 1 command after repeating the pwm data input to the 16 - bit shift register and s0 command input 15 times. normal input mode should be used to input pwm data only. speed input mode) s0 command 15 times + s1 command once 0 0 0 s 0 command data is transmitted to out 15. s 0 command data is transmitted to out 14. s 1 command 1 . data is transmitted to out 0 . 2 . the pwm d ata for out 15 to out 0 are reflect ed on output t c 62 d 7 22 c fg / c fng 2011 - 09- 24 20 4 . about operation of a pwm output the pwm output is outputted once to one s1 command. command s 0 s 0 s 1 outn pwm output period pwm output with the pwm data a . pwm data a is input . when doing pwm output once again, i t's necessary to input s1 command. command s 0 s 0 s 1 outn pwm output period pwm output with the pwm data a . pwm data a is input . s1 pwm output with the pwm data a . pwm g when s1 command is inputted during a pwm output by pw m output asynchronous mode , the present pwm output is canceled and a pwm output is immediately started by new pwm data. command s 0 s 0 s 1 outn pwm output period pwm output with the pwm data a . pwm data a is input . s 0 s 0 s 1 pwm data b is input . pwm output with the pwm data b . when s1 command is inputted during a pwm output by p wm output synchronous mode , after the present pwm output has ended , a pwm output is started by new pwm data. command s 0 s 0 s 1 outn pwm output period pwm output with the pwm data a . pwm data a is input . s0 s0 s1 pwm data b is input . pwm output with the pwm data b. if s1 command is inputted two or more times du ring a pwm ou tput by pwm output synchronous m o d e , after the present pwm output has ended , a pwm output will be started by the pwm data inputted at the end. command s 0 s 0 s 1 outn pwm output period pwm output with the pwm data a . pwm data a is input . s0 s0 s1 pwm data b is input . pwm output with the pwm data c. s0 s0 s1 pwm data c is input. t c 62 d 7 22 c fg / c fng 2011 - 09- 24 21 5 . pwm output 5 - 1 ) normal pwm output mode. output waveform of 16 - bit pwm. 1 2 3 511 512 513 514 16, 382 16, 383 16, 384 16, 385 16,386 16, 387 32, 766 32, 767 32, 768 32, 769 32,770 32, 771 49, 150 49, 151 49, 152 49, 153 49,154 49, 155 65,023 65,024 65,025 65,026 65,534 65,535 65,536 trans (s1 command) pwmclk outn pwmdata=0000h off on off on outn pwmdata=0001h off on outn pwmdata=0002h off on outn pwmdata=0003h off on outn pwmdata=0201h off on outn pwmdata=4001h off on outn pwmdata=8001h off on outn pwmdata=c001h off on outn pwmdata=fe01h off on outn pwmdata=ffffh 0 t c 62 d 7 22 c fg / c fng 2011 - 09- 24 22 5 - 2 ) division pwm output mode. pwm output period is divided into 128 pieces. because turn on time of output is not biased, it is effective in the flicker prevention on the display. output waveform of 16 - bit pwm. 1 2 3 511 512 513 514 16 , 382 16 , 383 16 , 384 16 , 385 16 , 386 16 , 387 32 , 766 32 , 767 32 , 768 32 , 769 32 , 770 32 , 771 49 , 150 49 , 151 49 , 152 49 , 153 49 , 154 49 , 155 65 , 023 65 , 024 65 , 025 65 , 026 65 , 534 65 , 535 65 , 536 trans ( s 1 command ) pwmclk outn pwmdata = 0000 h off on off on period 1 period 2 ~ period 32 period 33 ~ period 64 period 65 ~ period 96 period 97 ~ period 127 period 128 outn pwmdata = 0001 h off on outn pwmdata = 0002 h off on outn pwmdata = 0003 h off on outn pwmdata = 0004 h off on outn pwmdata = 0080 h off on outn pwmdata = 0081 h outn pwmdata = 0081 h off on off on outn pwmdata = ffc 0 h off on outn pwmdata = ffc 1 h off on outn pwmdata = ffc 2 h off on outn pwmdata = fffdh off on outn pwmdata = fffeh off on outn pwmdata = ffffh 0 t c 62 d 7 22 c fg / c fng 2011 - 09- 24 23 6 . thermal shutdown circuit (tsd) when the temperature of internal ic exceeds 150 c , all constant current outputs are turned off by this function. the constant current is outputted again when the temperature decreases to the ratin g. the thermal shutdown function of this ic aims at stopping the influence (emitting smoke, ignition) on the circumference (led and substrate) to the minimum, when it is used on the conditions beyond not a function but the maximum rating for preventing destruction of ic and ic results in destruction. calculation of heat take care not to let the temperature of the internal ic exceed 150 by referring to the formula below. consumption power ( ic output) [ w ] = ( led supply voltage [ v ] - minimum of v f of led [ v] ) output current [ a] number of output ( on duty [% ] / 100 ) consumption power ( ic supply) [ w ] = ic supply voltage [ v] ic supply current [ a] total of consumption power [w ] = consumption power (ic output) [ w ] + consumption power (ic supply) [ w ] he at value of internal ic [ c ] = thermal resistance [ c / w ] total of power consumption [ w ] temperature of internal ic [ c ] = heat value of internal ic [ c ] + ambient temperature [ c ] in case used led supply voltage is high, and heat value of internal ic is large. heat value of internal ic can be reduced by decreasing the voltage with the external resistance shown below. setting method of resistance for heat protection voltage that should decre ase by external resistance [ v] = led supply voltage [ v] - maximum of v f of led [ v] - output voltage [ v] resistance for he a t protection [? ] = voltage that should decrease by external resistance [ v ] / output current [ a] 7 . output delay function this functi on is intended to have the effect of reducing switching noise by reducing the di/dt when all outputs are on or off at the same time.there is a switching time lag between output s. a switching time lag between output s is put in order of the following. 0 out 15 out 7 out 8 out 1 out 14 out 6 out 9 out 2 out 13 out 5 out 10 out 3 out 12 out 4 out 11 out v dd v led controller sck sin vdd out0 out7 out15 sout gnd r ext trans pwmclk resistance for he a t protection t c 62 d 7 22 c fg / c fng 2011 - 09- 24 24 8 . power on reset (por) it avoids the malfunction by resetting all internal data of ic and setting default in startup. por circuit operates only whe n v dd rises from 0 v. to restart por, v dd should be 0. 1 v or less. as for the voltage of storing the internal data, it is guaranteed after v dd reaches 3.0 v or more once. v dd waveform por working range b eyond por working range por working range v dd =2.8 v v dd =0.1 v v dd =0 v e nd of por v dd voltage for end of reset v dd =3.0v v dd voltage for guaranteed data t c 62 d 7 22 c fg / c fng 2011 - 09- 24 25 application circuit ( dynam ic lighting ) sck sin v dd out0 out7 out15 sout gnd r ext trans pwmclk sck sin v dd out0 out7 out15 sout gnd r ext trans pwmclk sck sin v dd out0 out7 out15 sout gnd r ext v dd v led trans pwmclk controller t c 62 d 7 22 c fg / c fng 2011 - 09- 24 26 absolute maximum ratings (t a = 25c) characteristics symbol rating note 1 unit supply v oltage v dd ? 0. 3 to 6.0 v output c urrent i out 95 ma logic i nput v oltage v in ? 0.3 to v dd + 0.3 note 2 v output v oltage v out ? 0. 3 to 17 v operating temperature t opr ? 40 to 85 c storage temperature t stg ? 55 to 150 c thermal r esistance r th(j - a) c fg 94 note 3 c/w c fn g 45.47 note 4 power dissipation p d c fg 1.32 note 5 w c fng 2.74 note 5 note1: voltage is ground referenced. note2: 6v must not be exceeded. note3: pcb condition is 76.2 mm 114.3 mm 1.6 mm cu=30% ( semi conformi ng) note 4 : pcb condition is jedec 2s2p not e 5 : w hen ambien t temperature is 25 c or more . every time ambient temperature exceeded 1 c , please decrease 1/ r th(j - a) . operating condition dc characteristics ( u nless otherwise noted, v dd = 3.0 v to 5.5 v , t a = - 40 to 85 c ) characteristics symbol te s t c o nditions min typ. max unit supply v oltage v dd ? 3.0 ? 5.5 v high level logic input voltage v ih t est terminal is sin, sck, trans, pwmclk 0.7 v dd ? v dd v low level logic input voltage v il t est terminal is sin, sck, trans, pwmclk gnd ? 0.3 v dd v high leve l sout output current i oh ? ? ? ? 1 ma low level sout output current i ol ? ? ? 1 ma constant current output i out t est terminal is outn 1.5 ? 90 ma t c 62 d 7 22 c fg / c fng 2011 - 09- 24 27 ac characteristics 1 ( u nless otherwise noted, v dd = 5.0 v, t a = 25 c ) characteristics symbol test conditions min typ. max unit serial data transfer frequency f sck up edge trigger mode cascade connect ? ? 30 mhz d own edge trigger mode ? ? 2 5 sck pulse width t w sck sck = h or l 15 20 ? ns pwm clk pulse width t w pwm pwm = h or l , r e xt = 200 to 12 k 15 20 ? ns trans pulse width t w trans trans = h 20 ? ? ns serial data setup time t setup1 sin - sck 1 ? ? ns t setup 2 trans - sck 5 ? ? t setup 3 trans - sck 5 ? ? t setup 4 trans - sck 2 ? ? t setup5 rans - pwmc l k 5 ? ? serial data hold t ime t hold1 sin - sck 3 ? ? ns t hold2 trans - sck 7 ? ? t hold 3 trans - sck 7 ? ? t hold 4 trans - sck 2 ? ? t hold 5 trans - pwm c l k 5 ? ? ac characteristics 2 ( u nless otherwise noted, v dd = 3.3 v, t a = 25 c ) characteristics symbol test conditions min typ. max unit serial data transfer frequency f sck up edge trigger mode cascade connect ? ? 30 mhz d own edge trigger mode ? ? 2 5 s c k pulse width t w sck sck = h or l 15 20 ? ns pwm clk pulse width t w pwm pwm = h or l , r ext = 200 to 12 k 15 20 ? ns trans pulse width t w trans trans = h 20 ? ? ns serial data setup time t setup1 sin - sck 1 ? ? ns t setup 2 trans - sck 5 ? ? t setup 3 trans - sck 5 ? ? t setup 4 trans - sck 2 ? ? t setup5 rans - pwmc l k 5 ? ? serial data hold time t hold1 sin - sck 3 ? ? ns t hold2 trans - sck 7 ? ? t hold 3 trans - sck 7 ? ? t hold 4 trans - sck 2 ? ? t hold 5 trans - pwm c l k 5 ? ? t c 62 d 7 22 c fg / c fng 2011 - 09- 24 28 electrical characteristics electrical characteristics 1 ( u nless otherwise noted, v dd = 5.0 v, t a = 25 c ) characteristics s ymbol t est c ircuit test conditions min typ. max unit high level sout output voltage v oh 1 t a = -40 to +85 c i oh = ? 1ma v dd ? 0.3 ? v dd v low leve l sout output voltage v ol 1 i o l = + 1ma gnd ? 0.3 v high level logic in put current i ih 2 v i n = v dd t est terminal is sin, sck ? ? 1 a low level logic in put current i il 3 v i n = gnd t est terminal is pwmclk, sin, sck , trans ? ? -1 a power supply current i dd1 4 stand - by mode (1) or (2) v out = 17 v, sck=l ? ? 1.0 a i dd2 4 v out =1.0v, r ext = 1.2 k ? all output off ? ? 7.0 ma constant current error (ic to ic) s rank ? i out (ic) 5 v out =1.0v , r ext = 1.2 k ? 0 out to 15 out , 1ch output on ? 1.0 1.5 % constant current error (ch to ch) s rank ? i out (c h ) 5 v out =1.0v , r ext = 1.2 k ? 0 out to 15 out , 1ch output on ? 1.0 1.5 % constant current error (ic to ic) n rank ? i out (ic) 5 v out =1.0v , r ext = 1.2 k ? 0 out to 15 out , 1ch output on ? 1.0 2 .5 % constant current error (ch to ch) n rank ? i out (c h ) 5 v out =1.0v , r ext = 1.2 k ? 0 out to 15 out , 1ch output on ? 1.0 2 .5 % output off leak current i ok 5 v out =1 7 v, r ext = 1.2 k ? , outn off ? ? 0. 5 a constant current output power supply voltage regulation %v dd 5 v dd =4.5 to 5.5v, v out =1.0v r ext = 1.2 k ? 0 out to 15 out , 1ch output on ? 1 5 %/v constant current output output voltage regulation %v out 5 v out =1.0 to 3.0v, r ext = 1.2 k ? 0 out to 15 out , 1ch output on ? 0.1 0.5 %/v pull - down resistor r down 2 t est terminal is trans , pwmclk 2 5 0 5 00 750 k ? ood voltage v ood 6 r ext = 200 to 12 k 0.2 0.3 0.4 v osd voltage v osd 1 6 r ext = 200 to 12 k v dd ? 1.3 v dd ? 1.4 v dd ? 1. 5 v v osd 2 6 r ext = 200 to 12 k 0. 5 v dd 0. 525 v dd 0. 55 v dd tsd s tart t emperature t tds (on) ? junction temperature 150 ? ? c t s d r elease tem perature t t sd( of f ) ? junction temperature 100 ? ? c t c 62 d 7 22 c fg / c fng 2011 - 09- 24 29 electrical characteristics 2 ( u nless otherwise noted , v dd = 3.3 v, t a = 25 c ) characteristics symbol t est c ircuit test conditions min typ. max unit high level sout output voltage v oh 1 t a = -40 to +85 c i oh = ? 1ma v d d ? 0.3 ? v dd v low leve l sout output voltage v ol 1 i o l = + 1ma gnd ? 0.3 v high level logic in put current i ih 2 v i n = v dd t est terminal is sin, sck ? ? 1 a low level logic in put current i il 3 v i n = gnd t est terminal is pwmclk, sin, sck , trans ? ? -1 a power supply current i dd1 4 stand - by mode (1) or (2) v out = 17 v, sck=l ? ? 1.0 a i dd2 4 v out =1.0v, r ext = 1.2 k ? all output off ? ? 7.0 ma constant current error (ic to ic) s rank ? i out (ic) 5 v out =1.0v , r ext = 1.2 k ? 0 out to 15 out , 1ch output on ? 1.0 1.5 % constant current error (ch to ch) s rank ? i out (c h ) 5 v out =1.0v , r ext = 1.2 k ? 0 out to 15 out , 1ch output on ? 1.0 1.5 % constant current error (ic to ic) n rank ? i out (ic) 5 v out =1.0v , r ext = 1.2 k ? 0 out to 15 out , 1ch output on ? 1.0 2 .5 % constant current error (ch to ch) n rank ? i out (c h ) 5 v out =1.0v , r ext = 1.2 k ? 0 out to 15 out , 1ch output on ? 1.0 2 .5 % output off leak current i ok 5 v out =1 7 v, r ext = 1.2 k ? , outn off ? ? 0. 5 a constant current output power supply voltage regulation %v dd 5 v dd = 3.0 to 3.6 v, v out =1.0v r ext = 1.2 k ? 0 out to 15 out , 1ch outpu t on ? 1 5 %/v constant current output output voltage regulation %v out 5 v out =1.0 to 3.0v, r ext = 1.2 k ? 0 out to 15 out , 1ch output on ? 0.1 0.5 %/v pull - down resistor r down 2 t est terminal is trans , pwmclk 2 5 0 5 00 750 k ? ood voltage v ood 6 r ext = 200 to 12 k 0.2 0.3 0.4 v osd voltage v osd 1 6 r ext = 200 to 12 k v dd ? 1.3 v dd ? 1.4 v dd ? 1. 5 v v osd 2 6 r ext = 200 to 12 k 0. 5 v dd 0. 525 v dd 0. 55 v dd tsd s tart t emperature t tds (on) ? junction temperature 150 ? ? c t s d r elease tem perature t t sd( off ) ? junction temperature 100 ? ? c t c 62 d 7 22 c fg / c fng 2011 - 09- 24 30 switching characteristics switching characteristics 1 (unless otherwise specified , v dd = 5.0 v, t a = 25 c ) characteristics symbol t est c ircuit test conditions min typ. max unit pr opagation d elay sck - sout t pd1u 7 up edge trigger mode 6 16 30 ns sck - sout t pd1d 7 down edge trigger mode 2 10 14 pwm clk - 0 out t pd2 7 r ext = 1.2 k ? ? 30 40 constant c urrent o utput r ise t ime t or 7 10 90% at voltage waveform of outn r ext = 1.2 k ? ? 10 2 0 ns constant c urrent o utput f all t ime t of 7 9 0 1 0% at voltage waveform of outn r ext = 1.2 k ? ? 10 2 0 ns constant c urrent o utput d elay t ime t dly(on) 7 r ext = 1.2 k ? 1 4 9 ns t dly(off) 7 r ext = 1.2 k ? 1 4 9 ns switching characteristics 2 (unless otherwise specified , v dd = 3.3 v, t a = 25 c ) characteristics symbol t est c ircuit test conditions min typ. max unit propagation d elay sck - sout t pd1u 7 up edge trigger mode 6 16 30 ns sck - sout t pd1d 7 down edge trigger mode 2 1 3 1 8 pwm clk - 0 out t pd2 7 r ext = 1.2 k ? ? 30 40 constant c urrent o utput r ise t ime t or 7 10 to 90% at voltage waveform of outn r ext = 1.2 k ? ? 10 2 0 ns constant c urrent o utput f all t ime t of 7 9 0 to 1 0% at voltage waveform of outn r ext = 1.2 k ? ? 10 2 0 ns constant c urrent o utput d elay t ime t dly(on) 7 r ext = 1.2 k ? 2 6 12 ns t dly(off) 7 r ext = 1.2 k ? 2 6 12 ns t c 62 d 7 22 c fg / c fng 2011 - 09- 24 31 test ci rcuit test circuit 1 : high level sout output voltage / low level sout output voltage test circuit 2 : high level logic input current / pull - down resistance test circuit 3 : low level logi c input current i o = - 1ma to 1ma c l = 10.5 pf v dd = 3.3 v, 5.0 v v sck sin vdd out0 out7 out15 sout gnd r ext trans pwmclk v dd = 3.3 v, 5.0 v v ih = v dd a a a a sck sin vdd out0 out7 out15 sout gnd r ext trans pwmclk v dd = 3.3 v, 5.0 v a a a a sck sin vdd out0 out7 out15 sout gnd r ext trans pwmclk v il = gnd controller t c 62 d 7 22 c fg / c fng 2011 - 09- 24 32 r ext = 1.2k ? test circuit 4 : power supply current v dd = 3.3 v, 5.0 v a sck sin vdd out0 out7 out15 sout gnd r ext trans pwmclk v out = 1 v, 17 v te s t circuit 5 : constant current error / output off leak current constant current output power supply voltage regulation constant current output output voltage regulation v out = 1 to 3 v, 17 v v dd = 3.0 to 3.3 v, 4.5 to 5.5 v a a r ext = 1.2k ? a sck sin vdd out0 out7 out15 sout gnd r ext trans pwmclk controller controller t c 62 d 7 22 c fg / c fng 2011 - 09- 24 33 te s t c i rcuit 6 : ood voltage / osd voltage all output is set to turning on . o nly one output is connected with the v out 2 power supply , and o ther outputs are connect ed with the v out 1 power supply. v out2 is changed and ood voltage / osd voltage is checked in the error detection result from each output terminal voltage and sout. v dd = 3.3 v, 5.0 v r ext = 200 ? , 12 k ? v out1 = 1.0 v v v v v out2 sck sin vdd out0 out7 out15 sout gnd r ext trans pwmclk sck sin v dd out0 r l c l out7 c l r l out15 c l r l sout gnd r ext c l = 10.5 pf v dd = 3.3 v, 5.0 v test circuit 7 : switching characteristics v ih = v dd v il = gnd t r = t f = 10 ns (10 to 90%) v led = 5 .0 v r ext = 1.2k ? trans pwmclk r l = 200 ? c l = 10.5 pf controller controller t c 62 d 7 22 c fg / c fng 2011 - 09- 24 34 timing waveform 1. sck , trans, sin, sout , pwmclk sin sck trans t setup1 t hold1 t wsck t wtrans sout sout (up edge trigger mode) (down edge trigger mode) t pd1u t pd1d t wsck t hold2 t setup2 t setup3 t hold3 t hold4 t setup4 trans sck if sck is "l" when changing trans into "h", please make scl "l" when chang ing trans into "l" if sck is " h " when changing trans into " h ", please make scl " h " when changing trans into "l" t hold 5 trans pwmclk t setup5 2. outn outn t or t of off on ( voltage waveform) t c 62 d 7 22 c fg / c fng 2011 - 09- 24 35 3. pwmclk, 0 out to 15 out t pd2 t wpwm t dly(on) t dly(on) t dly(on) t dly(on) t dly(on) t dly(on) t dly(on) t dly(on) t dly(on) t dly(on) t dly(on) t dly(on) t dly(on) t dly(on) t dly(on) t pd2 t dly(off) t dly(off) t dly(off) t dly(off) t dly(off) t dly(off) t dly(off) t dly(off) t dly(off) t dly(off) t dly(off) t dly(off) t dly(off) t dly(off) t dly(off) pwmclk out 0 out 15 out 7 out 8 out 1 out 14 out 6 out 9 out 2 out 13 out 5 out 10 out 3 out 12 out 4 out 11 on off on off on off on off on off on off on off on off on off on off on off on off on off on off on off on off t wpwm outn is a voltage waveform. t c 62 d 7 22 c fg / c fng 2011 - 09- 24 36 reference data this data is provided for reference only. so, in designing for mass production, take enough care in evaluating ic operation. output current (i out ) C c onstant current output setting resistance ( r ext ) the o utput gain control data is default . i out - r ext 0 10 20 30 40 50 60 70 80 90 0 1000 2000 3000 4000 5000 r ext () i out (ma) theoretical formula i out (a) = (1. 03 (v) r ext ( ? )) 1 6.5 v dd = 3.0v to 5 .5 v v out =1.0v t a = 25 c t c 62 d 7 22 c fg / c fng 2011 - 09- 24 37 reference data this data is provided for reference only. so, in designing for mass production, take enough care in evaluating ic operation. output cur rent (i out ) C output voltage (v out ) i ou t - v out v dd =3.3v,ta=25 ,1chon 0 10 20 30 40 50 60 70 80 90 100 0 0.5 1 1.5 2 2.5 3 v ou t (v) i out (ma) i out - v out v dd =5.0v,ta=25 ,1chon 0 10 20 30 40 50 60 70 80 90 100 0 0.5 1 1.5 2 2.5 3 v out (v) i out (ma) t c 62 d 7 22 c fg / c fng 2011 - 09- 24 38 notes on design of ics 1 . regarding decoupling capacitor between power supply and gnd it is recommended that decoupling capacitor between power supply and gnd should place as near ic as possible. 2 . regarding resistors for setting of output current when resistors for setting of output current (r ext ) are used commonly by many ic s , in designing for mass production, take enough care in evaluating ic operation. 3 . regarding pcb layout there is only one gnd termi nal on this device when the inductance in the gnd line and the resistor are large, the device may malfunction due to the gnd noise when output switching by the circuit board pattern and wiring. therefore, take care when designing the circuit board pattern layout and the wiring from the controller. 4 . please check the latest technical material at the time of mass production . t c 62 d 7 22 c fg / c fng 2011 - 09- 24 39 package dimension tc62d72 2fg: ssop24 - p - 300- 1.00b w e ight : 0.32 g (typ.) unit : mm t c 62 d 7 22 c fg / c fng 2011 - 09- 24 40 tc62d722fng : p - h tssop 24 - 0508 - 0.65 - 001 w e ight : 0.10 g (typ.) unit : mm t c 62 d 7 22 c fg / c fng 2011 - 09- 24 41 n otes on contents 1. block diagrams some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes. 2. equivalent circuits the equivalent cir cuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. 3. timing charts timing charts may be simplified for explanatory purposes. 4. application circuits the application circuits shown in this document are provided for reference purposes only. thorough evaluation is required, especially at the mass production design stage. toshiba does not grant any license to any industrial property rights by providing these examples of application circuits. 5. test circuits comp onents in the test circuits are used only to obtain and confirm the device characteristics. these components and circuits are not guaranteed to prevent malfunction or failure from occurring in the application equipment. t c 62 d 7 22 c fg / c fng 2011 - 09- 24 42 ic usage considerations notes on h andling of ics [1 ] the a bsolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded, even for a moment. do not exceed any of these ratings. exceeding the rating(s) may cause the device breakdown, damage or deterioration , and may result injury by explosion or combustion. [ 2 ] use an appropriate power supply fuse to ensure that a large current does not continuously flow in case of over current and/or ic failure. the ic will fully break down when used under conditions that e xceed its absolute maximum ratings, when the wiring is routed improperly or when an abnormal pulse noise occurs from the wiring or load, causing a large current to continuously flow and the breakdown can lead smoke or ignition. to minimize the effects of t he flow of a large current in case of breakdown, appropriate settings, such as fuse capacity, fusing time and insertion circuit location, are required. [ 3 ] if your design includes an inductive load such as a motor coil, incorporate a protection circuit in to the design to prevent device malfunction or breakdown caused by the current resulting from the inrush current at power on or the negative current resulting from the back el ectromotive force at power off. ic breakdown may cause injury, smoke or ignition. use a stable power supply with ics with built - in protection functions. if the power supply is unstable, the protection function may not operate, causing ic breakdown. ic breakdown may cause injury, smoke or ignition. [4] do not insert devices in the wro ng orientation or incorrectly. make sure that the positive and negative terminals of power supplies are connected properly. otherwise, the current or power consumption may exceed the absolute maximum rating, and exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion. in addition, do not use any device that is applied the current with inserting in the wrong orientation or incorrectly even just one time. [ 5 ] carefully select external components (such as inputs and negative feedback capacitors) and load components (such as speakers), for example, power amp and regulator. if there is a large amount of leakage current such as input or negative feedback condenser, the ic output dc voltage will increase. if this output voltage is connected to a speaker with low input withstand voltage, overcurrent or ic failure can cause smoke or ignition. (the over current can cause smoke or ignition from the ic itself.) in particular, please pay attention when using a bridge tied load (btl) connection type ic that inputs output dc voltage to a speaker directly. points to remember on handling of ics ( 1 ) heat radiation design in using an ic with large current flow such as power amp, regulator or driver, p lease design the device so that heat is appropriately radiated, not to exceed the specified junction temperature (t j ) at any time and condition. these ics generate heat even during normal use. an inadequate ic heat radiation design can lead to decrease in ic life, deterioration of ic characteristics or ic breakdown. in addition, please design the device taking into considerate the effect of ic heat radiation with peripheral components. (2 ) back - emf when a motor rotates in the reverse direction, stops or slo ws down abruptly , a current flow back to the motor s power supply due to the effect of back - emf. if the current sink capability of the power supply is small, the device s motor power supply and output pins might be exposed to conditions beyond maximum rati ngs. to avoid this problem, take the effect of back - emf into consideration in system design. (3) thermal shutdown circuit thermal shutdown circuits do not necessarily protect ics under all circumstances. if the thermal shutdown circuits operate against the over temperature, clear the heat generation status immediately. depending on the method of use and usage conditions, such as exceeding absolute maximum ratings can cause the thermal shutdown circuit to not operate properly or ic breakdown before operation . t c 62 d 7 22 c fg / c fng 2011 - 09- 24 43 restrictions on product use ? toshiba corporation, and its subsidiaries and affiliates (collectively toshiba), reserve the right to make changes to the i nformation in this document, and related hardware, software and systems (collectively product) w ithout notice. ? this document and any information herein may not be reproduced without prior written permission from toshiba. even with toshibas written permission, reproduction is permissible only if reproduction is without alteration/omission. ? though toshiba works continually to improve products quality and reliability, product can malfunction or fail. customers are responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, softwar e and syste ms which minimize risk and avoid situations in which a malfunction or failure of product could cause loss of human life, bodi ly injury or damage to property, including data loss or corruption. before customers use the product, create designs including t he product, or incorporate the product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant toshiba information, including without limitation, this document, the specifications, the data sheets and application notes for product and the precautions and conditions set forth in the toshiba semiconductor reliability handbook and (b) the instruct ions for the application with which the product will be used with or for. customers are solely responsible fo r all aspects of their own product design or applications, including but not limited to (a) determining the appropriateness of the use of this product in such d esign or applications; (b) evaluating and determining the applicability of any information conta ined in this document, or in charts, diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating parame ters for such designs and applications. toshiba assumes no liability for customers product design or applications. ? product is intended for use in general electronics applications (e.g., computers, personal equipment, office equipment, measu ring equipment, industrial robots and home electronics appliances) or for specific applications a s expressly stated in this document. product is neither intended nor warrant ed for use in equipment or systems that require extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or serious public impact (unintended us e). unintended use includes, without limitation, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signal ing equipment, equipm ent used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and equipment used in finance - related fields. do not use product for unintended use unless specifically permitted in this document. ? do not disassemble, analyze, reverse - engineer, alter, modify, translate or copy product, whether in whole or in part. ? product shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited unde r any app licable laws or regulations. ? the information contained herein is presented only as guidance for product use. no responsibility is assumed by toshiba for a ny infringement of patents or any other intellectual property rights of third parties that may resul t from the use of product. no license to any intellectual property right is granted by this document, whether express or implied, by estoppel or otherwise. ? absent a written signed agreement, except as provided in the relevant terms and conditions of sale for product, and to the maximum extent allowable by law, toshiba (1) assumes no liability whatsoever, including without limitation, indirect, consequential, special, or incidental damages or loss, including without limitation, loss of profits, loss of opp ortunities, business interruption and loss of data, and (2) disclaims any and all express or implied warranties and conditions related to sale, use of product, or information, including warranties or conditions of merchantability, fitness for a particular purpose, accuracy of information, or noninfringement. ? do not use or otherwise make available product or related software or technology for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). product and related software and technology may be controlled under the japanese foreign exchange and foreign trade law and the u.s. export administrati on regulations. export and re - export of product or related software or technology are strictly prohibited except in compliance with all applicable export laws and regulations. ? please contact your toshiba sales representative for details as to environment al matters such as the rohs compatibility of product. please use product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled su bstances, including without limitation, the eu rohs directive. toshiba assume s no liability for damages or losses occurring as a result of noncompliance with applicable laws and regulations. |
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