 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| ds92ck16 www.ti.com snas044c ? november 1999 ? revised april 2013 ds92ck16 3v blvds 1 to 6 clock buffer/bus transceiver check for samples: ds92ck16 1 features description the ds92ck16 1 to 6 clock buffer/bus transceiver 2 ? master/slave clock selection in a backplane is a one to six cmos differential clock distribution application device utilizing bus low voltage differential signaling ? 125 mhz operation (typical) (blvds) technology. this clock distribution device is ? 100 ps duty cycle distortion (typical) designed for applications requiring ultra low power dissipation, low noise, and high data rates. the ? 50 ps channel to channel skew (typical) blvds side is a transceiver with a separate channel ? 3.3v power supply design acting as a return/source clock. ? glitch-free power on at clki/o pins the ds92ck16 accepts lvds (300 mv typical) ? low power design (20 ma @ 3.3v static) differential input levels, and translates them to 3v ? accepts small swing (300 mv typical) cmos output levels. an output enable pin oe , when high, forces all clk out pins high. differential signal levels ? industrial temperature operating range (-40 c the device can be used as a source synchronous to +85 c) driver. the selection of the source driving is controlled by the crdclk in and de pins. this device ? available in 24-pin tssop packaging can be the master clock, driving the inputs of other clock i/o pins in a multipoint environment. easy master/slave clock selection is achieved along a backplane. function diagram and truth table table 1. receive mode truth table input output oe de crdclk in (clki/o+) ? (clki/o ? ) clk out h h x x h l h x vid 0.07v h l h x vid ? 0.07v l 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 all trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 1999 ? 2013, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
ds92ck16 snas044c ? november 1999 ? revised april 2013 www.ti.com table 2. driver mode truth table input output oe de crdclk in clk/i/o+ clki/o ? clk out l l l l h l l l h h l h h l l l h h h l h h l h h h x z z h connection diagram tssop package see package number pw (r-pdso-g24) tssop package pin descriptions pin name pin # type description clki/o+ 6 i/o true (positive) side of the differential clock input. clki/o ? 7 i/o complementary (negative) side of the differential clock input. oe 2 i oe; this pin is active low. when high, this pin forces all clk out pins high. when low, clk out pins logic state is determined by either the crdclk in or the vid at the clk/i/o pins with respect to the logic level at the de pin. this pin has a weak pullup device to v cc . if oe is floating, then all clk out pins will be high. de 11 i de; this pin is active low. when low, this pin enables the cardclk in signal to the clki/o pins and clk out pins. when high, the driver is tri-state, the clki/o pins are inputs and determine the state of the clk out pins. this pin has a weak pullup device to v cc . if de is floating, then clki/o pins are tri-state. clk out 13, 15, 17, o 6 buffered clock (cmos) outputs. 19, 21, 23 crdclk in 9 i input clock from card (cmos level or ttl level). v cc 16, 20, 24 power v cc ; analog v cca (internally separate from v cc , connect externally or use separate power supplies). no special power sequencing required. either v cca or v cc can be applied first, or simultaneously apply both power supplies. gnd 1, 12, 14, 18, ground gnd 22 v cca 4 power analog v cca (internally separate from v cc , connect externally or use separate power supplies). no special power sequencing required. either v cca or v cc can be applied first, or simultaneously apply both power supplies. gnda 5, 8 ground analog ground (internally separate from ground must be connected externally). nc 3, 10 no connects 2 submit documentation feedback copyright ? 1999 ? 2013, texas instruments incorporated product folder links: ds92ck16 ds92ck16 www.ti.com snas044c ? november 1999 ? revised april 2013 these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. absolute maximum ratings (1) (2) supply voltage (v cc ) ? 0.3v to +4v enable input voltage ( de, oe, crdclk in ) ? 0.3v to +4v voltage (clk out ) ? 0.3v to (v cc + 0.3v) voltage (clki/o ) ? 0.3v to +4v driver short circuit current momentary receiver short circuit current momentary maximum package power dissipation at +25 c pw package 1500 mw derate pw package 8.2 mw/ c above +25 c ja 95 c/w jc 30 c/w storage temperature range ? 65 c to +150 c lead temperature range (soldering, 4 sec.) 260 c esd ratings: hbm (3) > 3000v cdm (3) > 1000v machine model (3) > 200v (1) ? absolute maximum ratings ? are those values beyond which the safety of the device cannot be verified. these ratings are not meant to imply that the devices should be operated at these limits. the table of ? electrical characteristics ? specifies conditions of device operation. (2) if military/aerospace specified devices are required, please contact the ti sales office/ distributors for availability and specifications. (3) esd rating: esd qualification is performed per the following: hbm (1.5 k ? , 100 pf), machine model (250v, 0 ? ), iec 1000-4-2. all vcc pins connected together, all ground pins connected together. recommended operating conditions min typ max units supply voltage (v cc ) +3.0 +3.3 +3.6 v crdclk in , de, oe input voltage 0 v cc v operating free air temperature (t a ) ? 40 25 +85 c dc electrical characteristics over supply voltage and operating temperature ranges, unless otherwise specified (1) (2) . symbol parameter conditions pin min typ max units v th input threshold high clki/o+, 25 +70 mv clki/o ? v tl input threshold low ? 70 -35 mv vcmr common mode voltage vid = 250 mv pk to pk |vid|/2 2.4 - |vid|/2 v range (3) i in input current v in = 0v to v cc , de = v cc , oe = ? 20 5 +20 a v cc , other input = 1.2v 50 mv (1) current into device pins is defined as positive. current out of device pins is defined as negative. all voltages are referenced to ground except vid, vod, vth, and vtl. (2) all typicals are given for: v cc = +3.3v and t a = +25 c. (3) the vcmr range is reduced for larger vid. example: if vid=400 mv, then vcmr is 0.2v to 2.2v a vid up to |v cc ? 0v| may be applied between the clki/o+ and clki/o ? inputs, with the common mode set to v cc /2. copyright ? 1999 ? 2013, texas instruments incorporated submit documentation feedback 3 product folder links: ds92ck16 ds92ck16 snas044c ? november 1999 ? revised april 2013 www.ti.com dc electrical characteristics (continued) over supply voltage and operating temperature ranges, unless otherwise specified (1) (2) . symbol parameter conditions pin min typ max units v oh1r output high voltage vid = 250 mv, i oh = ? 1.0 ma clk out v cc ? 0.4 2.9 v v oh2r output high voltage vid = 250 mv, i oh = ? 6 ma v cc ? 0.8 2.5 v v ol1r output low voltage i ol = 1.0 ma, vid = ? 250 mv 0.06 0.3 v v ol2r output low voltage i ol = 6 ma, vid = ? 250 mv 0 0.4 v i odhr clk out dynamic output vid = +250 mv, v out = v cc ? 1v ? 8 -16 -30 ma current (4) i odlr clk out dynamic output vid = ? 250 mv, v out = 1v 10 21 35 ma current (4) v ih input high voltage de, oe, 2.0 v cc v crdclk in v il input low voltage gnd 0.8 v i ih input high current v in = v cc or 2.4v oe, de ? 10 ? 2 +10 a i il input low current v in = gnd or 0.4v ? 20 ? 5 +20 a i incrd input current v in = 0v to v cc , oe = v cc crdclk in ? 5 +5 a v cl input voltage clamp i out = ? 1.5 ma oe, de, ? 0.8 v crdclk in i cc no load supply current oe = de = 0v, v cc outputs enabled, no vid crdclk in = v cc or gnd, 13 ma applied clki/o ( ) = open clk out (0:5) = open circuit i cc1 no load supply current oe = gnd outputs enabled, vid over de = v cc common mode voltage crdclk in = v cc or gnd, 10 ma range vid = 250 mv (0.125v vcm 2.275v), clk out (0:5) = open circuit i ccd driver loaded supply de = oe = 0v, current crdclk in = v cc or gnd, r l = 37.5 ? between clki/o+ and 20 25 ma clki/o ? , clk out (0:5) = open circuit v od driver output differential r l = 37.5 ? , figure 5 clki/o+, 250 350 450 mv voltage de = 0v clki/o ? v od driver v od magnitude 10 20 mv change v os driver offset voltage 1.1 1.29 1.5 v v os driver offset voltage 5 20 mv magnitude change v ohd driver output high 1.35 1.8 v v old driver output low 0.80 1.05 v i os1d driver differential short crdclk in = v cc or gnd, vod = 0v, |30| |50| ma circuit current (5) (outputs shorted together) de = 0v i os2d driver output short circuit crdclk in = gnd, de = 0v, clki/o+ 36 70 ma current to v cc (5) = v cc i os3d driver output short circuit crdclk in = v cc , de = 0v, clki/o ? 34 70 ma current to v cc (5) = v cc i os4d driver output short circuit crdclk in = v cc , de = 0v, clki/o+ ? 47 ? 70 ma current to gnd (5) = 0v i os5d driver output short circuit crdclk in = gnd, de = 0v, clki/o ? ? 50 ? 70 ma current to gnd (5) = 0v i off power off leakage current v cc = 0v or open, 20 a v applied = 3.6v (4) only one output should be momentarily shorted at a time. do not exceed package power dissipation rating. (5) only one output should be momentarily shorted at a time. do not exceed package power dissipation rating. 4 submit documentation feedback copyright ? 1999 ? 2013, texas instruments incorporated product folder links: ds92ck16 ds92ck16 www.ti.com snas044c ? november 1999 ? revised april 2013 switching characteristics over supply voltage and operating temperature ranges, unless otherwise specified (1) (2) . symbol parameter conditions min typ max units differential receiver characteristics t phldr differential propagation delay high to low. clki/o to clk out c l = 15 pf 1.3 2.8 3.8 ns vid = 250 mv t plhdr differential propagation delay low to high. clki/o to clk out 1.3 2.9 3.8 ns figure 1 figure 2 t sk1r duty cycle distortion (3) (pulse skew) 100 400 ps |t plh ? t phl | t sk2r channel to channel skew; same edge (4) 30 80 ps t sk3r part to part skew (5) 2.5 ns t tlhr transition time low to high (6) 0.4 1.4 2.4 ns (20% to 80% ) t thlr transition time high to low (6) 0.4 1.3 2.2 ns (80% to 20% ) t plhoer propagation delay low to high c l = 15 pf 1.0 3 4.5 ns ( oeto clk out ) figure 3 figure 4 t phloer propagation delay high to low 1.0 3 4.5 ns ( oe to clk out ) f max maximum operating frequency (7) 100 125 mhz differential driver timing requirements t phldd differential propagation delay high to low. crdclk in to c l = 15 pf 0.5 1.8 2.5 ns clki/o r l = 37.5 ? figure 6 figure 7 t plhdd differential propagation delay low to high. crdclk in to 0.5 1.8 2.5 ns clki/o t phlcrd crdclk in to clk out propagation delay high to low c l = 15 pf 2.0 4.5 6.0 ns figure 8 figure 9 t plhcrd crdclk in to clk out propagation delay low to high 2.0 4.5 6.0 ns t sk1d duty cycle distortion (pulse skew) 600 ps |t plh ? t phl | (8) t sk2d differential part-to-part skew (9) 2.0 ns t tlhd differential transition time (6) 0.4 0.75 1.4 ns (20% to 80% ) t thld differential transition time (6) 0.4 0.75 1.4 ns (80% to 20% ) t phzd transition time high to tri-state. de to clki/o 10 ns t plzd transition time low to tri-state. de to clki/o v in = 0v to v cc 10 ns c l = 15 pf, t pzhd transition time tri-state to high. de to clki/o 32 ns r l = 37.5 ? t pzld transition time tri-state to low. de to clki/o 32 ns figure 10 figure 11 f max maximum operating frequency (7) 100 125 mhz (1) c l includes probe and fixture capacitance. (2) generator waveform for all tests unless otherwise specified: f = 25 mhz, zo = 50 ? , t r = 1 ns, t f = 1 ns (10% ? 90%). to ensure fastest propagation delay and minimum skew, clock input edge rates should not be slower than 1 ns/v; control signals not slower than 3 ns/v. in general, the faster the input edge rate, the better the ac performance. (3) t sk1r is the difference in receiver propagation delay (|t plh ? t phl |) of one device, and is the duty cycle distortion of the output at any given temperature and v cc . the propagation delay specification is a device to device worst case over process, voltage and temperature. (4) t sk2r is the difference in receiver propagation delay between channels in the same device of any outputs switching in the same direction. this parameter is specified by design and characterization. (5) t sk3r, part-to-part skew, is the difference in receiver propagation delay between devices of any outputs switching in the same direction. this specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. t sk3r is defined as max ? min differential propagation delay.this parameter is specified by design and characterization. (6) all device output transition times are based on characterization measurements and are specified by design. (7) generator input conditions: t r /t f < 1 ns, 50% duty cycle, differential (1.10v to 1.35v pk-pk). output criteria: 60%/40% duty cycle, v ol (max) 0.4v, v oh (min) 2.7v, load = 7 pf (stray plus probes). (8) t sk1d is the difference in driver propagation delay (|t plh ? t phl |) and is the duty cycle distortion of the clki/o outputs. (9) t sk2d part-to-part skew, is the difference in driver propagation delay between devices of any outputs switching in the same direction. this specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. t sk2d is defined as max ? min differential propagation delay. copyright ? 1999 ? 2013, texas instruments incorporated submit documentation feedback 5 product folder links: ds92ck16 ds92ck16 snas044c ? november 1999 ? revised april 2013 www.ti.com parameter measurement information figure 1. receiver propagation delay and transition time test circuit generator waveform for all test unless otherwise specified: f = 25 mhz, 50% duty cycle, zo = 50 ? , t tlh = 1 ns, t thl = 1 ns. figure 2. receiver propagation delay and transition time waveforms figure 3. output enable ( oe) delay test circuit figure 4. output enable ( oe) delay waveforms 6 submit documentation feedback copyright ? 1999 ? 2013, texas instruments incorporated product folder links: ds92ck16 ds92ck16 www.ti.com snas044c ? november 1999 ? revised april 2013 figure 5. differential driver dc test figure 6. driver propagation delay test circuit figure 7. driver propagation delay and transition time waveforms figure 8. crdclk in propagation delay time test circuit copyright ? 1999 ? 2013, texas instruments incorporated submit documentation feedback 7 product folder links: ds92ck16 ds92ck16 snas044c ? november 1999 ? revised april 2013 www.ti.com figure 9. crdclk in propagation delay time waveforms figure 10. driver tri-state test circuit figure 11. driver tri-state waveforms 8 submit documentation feedback copyright ? 1999 ? 2013, texas instruments incorporated product folder links: ds92ck16 ds92ck16 www.ti.com snas044c ? november 1999 ? revised april 2013 applications information general application guidelines and hints for blvds/lvds transceivers, drivers and receivers may be found in the following application notes: lvds owner's manual, an805( snoa233 ), an807( snla027 ), an808( snla028 ), an903( snla034 ), an905( snla035 ), an916( snla219 ), an971( snla165 ), an977( snla166 ) . blvds drivers and receivers are intended to be used in a differential backplane configuration. transceivers or receivers are connected to the driver through a balanced media such as differential pcb traces. typically, the characteristic differential impedance of the media (zo) is in the range of 50 to100 . two termination resistors of zo each are placed at the ends of the transmission line backplane. the termination resistor converts the current sourced by the driver into a voltage that is detected by the receiver. the effects of mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise margin limits, and total termination loading must be taken into account. the ds92ck16 differential line driver is a balanced current source design. a current mode driver, generally speaking has a high output impedance (100 ohms) and supplies a constant current for a range of loads (a voltage mode driver on the other hand supplies a constant voltage for a range of loads). current is switched through the load in one direction to produce a logic state and in the other direction to produce the other logic state. the output current is typically 9.330 ma. the current changes as a function of load resistor. the current mode requires (as discussed above) that a resistive termination be employed to terminate the signal and to complete the loop. unterminated configurations are not allowed. the 9.33 ma loop current will develop a differential voltage of about 350mv across 37.5 (double terminated 75 ? differential transmission backplane) effective resistance, which the receiver detects with a 280 mv minimum differential noise margin neglecting resistive line losses (driven signal minus receiver threshold (350 mv ? 70 mv = 280 mv)). the signal is centered around +1.2v (driver offset, v os ) with respect to ground. note that the steady-state voltage (v ss ) peak-to-peak swing is twice the differential voltage (v od ) and is typically 700 mv. the current mode driver provides substantial benefits over voltage mode drivers, such as an rs-422 driver. its quiescent current remains relatively flat versus switching frequency. whereas the rs-422 voltage mode driver increases exponentially in most case between 20 mhz ? 50 mhz. this is due to the overlap current that flows between the rails of the device when the internal gates switch. whereas the current mode driver switches a fixed current between its output without any substantial overlap current. this is similar to some ecl and pecl devices, but without the heavy static i cc requirements of the ecl/pecl designs. lvds requires > 80% less current than similar pecl devices. ac specifications for the driver are a tenfold improvement over other existing rs-422 drivers. the tri-state function allows the driver outputs to be disabled, thus obtaining an even lower power state when the transmission of data is not required. power decoupling recommendations bypass capacitors must be used on power pins. high frequency ceramic (surface mount is recommended) 0.1 f in parallel with 0.01 f, in parallel with 0.001 f at the power supply pin as well as scattered capacitors over the printed circuit board. multiple vias should be used to connect the decoupling capacitors to the power planes. a 4.7 f (35v) or greater solid tantalum capacitor should be connected at the power entry point on the printed circuit board. pc board considerations use at least 4 pcb layers (top to bottom); blvds signals, ground, power, ttl signals. isolate ttl signals from blvds signals, otherwise the ttl may couple onto the blvds lines. it is best to put ttl and blvds signals on different layers which are isolated by a power/ground plane(s). keep drivers and receivers as close to the (blvds port side) connectors as possible to create short stub lengths. copyright ? 1999 ? 2013, texas instruments incorporated submit documentation feedback 9 product folder links: ds92ck16 ds92ck16 snas044c ? november 1999 ? revised april 2013 www.ti.com differential traces use controlled impedance traces which match the differential impedance of your transmission medium (ie. backplane or cable) and termination resistor(s). run the differential pair trace lines as close together as possible as soon as they leave the ic . this will help eliminate reflections and ensure noise is coupled as common-mode. in fact, we have seen that differential signals which are 1mm apart radiate far less noise than traces 3mm apart since magnetic field cancellation is much better with the closer traces. plus, noise induced on the differential lines is much more likely to appear as common-mode which is rejected by the receiver. match electrical lengths between traces to reduce skew. skew between the signals of a pair means a phase difference between signals which destroys the magnetic field cancellation benefits of differential signals and emi will result. (note the velocity of propagation, v = c/er where c (the speed of light) = 0.2997mm/ps or 0.0118 in/ps). do not rely solely on the autoroute function for differential traces. carefully review dimensions to match differential impedance and provide isolation for the differential lines. minimize the number or vias and other discontinuities on the line. avoid 90 turns (these cause impedance discontinuities). use arcs or 45 bevels. within a pair of traces, the distance between the two traces should be minimized to maintain common-mode rejection of the receivers. on the printed circuit board, this distance should remain constant to avoid discontinuities in differential impedance. minor violations at connection points are allowable. stub length stub lengths should be kept to a minimum. the typical transition time of the ds92ck16 blvds output is 0.75ns (20% to 80%). the 100 percent time is 0.75/0.6 or 1.25ns. for a general approximation, if the electrical length of a trace is greater than 1/5 of the transition edge, then the trace is considered a transmission line. for example, 1.25ns/5 is 250 picoseconds. let velocity equal 160ps per inch for a typical loaded backplane. then maximum stub length is 250ps/160ps/in or 1.56 inches. to determine the maximum stub for your backplane, you need to know the propagation velocity for the actual conditions (refer to application notes an ? 905( snla035 ) and an ? 808( snla028 )). termination use a resistor which best matches the differential impedance of your loaded transmission line. remember that the current mode outputs need the termination resistor to generate the differential voltage. blvds will not work without resistor termination. surface mount 1% to 2% resistors are best. probing blvds transmission lines always use high impedance ( > 100k ? ), low capacitance ( < 2pf) scope probes with a wide bandwidth (1ghz) scope. improper probing will give deceiving results. cables and connectors, general comments use controlled impedance media. the connectors you use should have a matched differential impedance of about zo ? . they should not introduce major impedance discontinuities. balanced cables (e.g. twisted pair) are usually better than unbalanced cables (ribbon cable, simple coax.) for noise reduction and signal quality. balanced cables tend to generate less emi due to field canceling effects and also tend to pick up electromagnetic radiation a common-mode (not differential mode) noise which is rejected by the receiver. for cable distances < 0.5m, most cables can be made to work effectively. for distances 0.5m d 10m, cat 3 (category 3) twisted pair cable works well, is readily available and relatively inexpensive. 10 submit documentation feedback copyright ? 1999 ? 2013, texas instruments incorporated product folder links: ds92ck16 ds92ck16 www.ti.com snas044c ? november 1999 ? revised april 2013 revision history changes from revision b (april 2013) to revision c page ? changed layout of national data sheet to ti format .......................................................................................................... 10 copyright ? 1999 ? 2013, texas instruments incorporated submit documentation feedback 11 product folder links: ds92ck16 package option addendum www.ti.com 13-apr-2013 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) op temp (c) top-side markings (4) samples ds92ck16tmtc active tssop pw 24 61 tbd call ti call ti -40 to 85 ds92ck16t mtc ds92ck16tmtc/nopb active tssop pw 24 61 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 85 ds92ck16t mtc ds92ck16tmtcx active tssop pw 24 2500 tbd call ti call ti -40 to 85 ds92ck16t mtc ds92ck16tmtcx/nopb active tssop pw 24 2500 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 85 ds92ck16t mtc (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) multiple top-side markings will be inside parentheses. only one top-side marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire top-side marking for that device. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 13-apr-2013 addendum-page 2 tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant ds92ck16tmtcx tssop pw 24 2500 330.0 16.4 6.95 8.3 1.6 8.0 16.0 q1 ds92ck16tmtcx/nopb tssop pw 24 2500 330.0 16.4 6.95 8.3 1.6 8.0 16.0 q1 package materials information www.ti.com 24-apr-2013 pack materials-page 1 *all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) ds92ck16tmtcx tssop pw 24 2500 367.0 367.0 35.0 ds92ck16tmtcx/nopb tssop pw 24 2500 367.0 367.0 35.0 package materials information www.ti.com 24-apr-2013 pack materials-page 2 important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per jesd46, latest issue, and to discontinue any product or service per jesd48, latest issue. buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all semiconductor products (also referred to herein as ? components ? ) are sold subject to ti ? s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in ti ? s terms and conditions of sale of semiconductor products. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. ti assumes no liability for applications assistance or the design of buyers ? products. buyers are responsible for their products and applications using ti components. to minimize the risks associated with buyers ? products and applications, buyers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which ti components or services are used. information published by ti regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of significant portions of ti information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. ti is not responsible or liable for such altered documentation. information of third parties may be subject to additional restrictions. resale of ti components or services with statements different from or beyond the parameters stated by ti for that component or service voids all express and any implied warranties for the associated ti component or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of ti components in its applications, notwithstanding any applications-related information or support that may be provided by ti. buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. buyer will fully indemnify ti and its representatives against any damages arising out of the use of any ti components in safety-critical applications. in some cases, ti components may be promoted specifically to facilitate safety-related applications. with such components, ti ? s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. nonetheless, such components are subject to these terms. no ti components are authorized for use in fda class iii (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. only those ti components which ti has specifically designated as military grade or ? enhanced plastic ? are designed and intended for use in military/aerospace applications or environments. buyer acknowledges and agrees that any military or aerospace use of ti components which have not been so designated is solely at the buyer ' s risk, and that buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. ti has specifically designated certain components as meeting iso/ts16949 requirements, mainly for automotive use. in any case of use of non-designated products, ti will not be responsible for any failure to meet iso/ts16949. products applications audio www.ti.com/audio automotive and transportation www.ti.com/automotive amplifiers amplifier.ti.com communications and telecom www.ti.com/communications data converters dataconverter.ti.com computers and peripherals www.ti.com/computers dlp ? products www.dlp.com consumer electronics www.ti.com/consumer-apps dsp dsp.ti.com energy and lighting www.ti.com/energy clocks and timers www.ti.com/clocks industrial www.ti.com/industrial interface interface.ti.com medical www.ti.com/medical logic logic.ti.com security www.ti.com/security power mgmt power.ti.com space, avionics and defense www.ti.com/space-avionics-defense microcontrollers microcontroller.ti.com video and imaging www.ti.com/video rfid www.ti-rfid.com omap applications processors www.ti.com/omap ti e2e community e2e.ti.com wireless connectivity www.ti.com/wirelessconnectivity mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2013, texas instruments incorporated |
Price & Availability of DS92CK16TMTCNOPB
 |
|||||||||||||||||||||||||||||||||||||||||
|
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |
