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sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 1 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet description features ? elpida memory, inc. 2003-2004 operating frequencies * cl = cas(read) latency standard pc100(cl2) 100mhz 100mhz max. frequency @cl=3 * max. frequency @cl=2 * pc133(cl3) 133mhz 100mhz m2v64s50etp-7i m2v64s50etp-6i M2V64S50ETP-I is a 4-bank x 524,288-word x 32-bit, synchronous dram, with lvttl interface. all inputs and outputs are referenced to the rising edge of clk. the M2V64S50ETP-I achieve very high speed data rate up to 100mhz (-7) , 133mhz (-6), and are suitable for digital consumer products or graphic memory in computer systems. - single 3.3v + 0.3v power supply - max. clock frequency -6:pc133<3-3-3> / -7:pc100<2-2-2> - fully synchronous operation referenced to clock rising edge - single data rate - 4 bank operation controlled by ba0, ba1 (bank address) - /cas latency- 2/3 (programmable) - burst length- 1/2/4/8/full page (programmable) - burst type- sequential / interleave (programmable) - random column access - auto precharge / all bank precharge controlled by a10 - auto refresh and self refresh - 4096 refresh cycles /64ms (4 banks concurrent refresh) (x32) - address input, row address a0-10 / column address a0-7 (x32) - lvttl interface - package type : 0.5mm lead pitch 86-pin tsop(ii) - ambient temperature range:-40 to +85 o c this product became eol in august, 2004.
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 2 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet clk : master clock cke : clock enable /cs : chip select /ras : row address strobe /cas : column address strobe /we : write enable dq0-31 : data i/o dqm0-3 : output disable/ write mask a0-10 : address input ba0,1 : bank address vdd : power supply vddq : power supply for output vss : ground vssq : ground for output (top view) 400mil x875mil 86pin tsop(ii) 0.5mm pin pitch vdd dq0 vddq dq1 dq2 vssq dq3 dq4 vddq dq5 dq6 vssq dq7 nc vdd dqm0 /we /cas /ras /cs nc ba0 ba1 a10/ap a0 a1 a2 dqm2 vdd nc dq16 vssq dq17 dq18 vddq dq19 dq20 vssq dq21 dq22 vddq dq23 vdd vss dq15 vssq dq14 dq13 vddq dq12 dq11 vssq dq10 dq9 vddq dq8 nc vss dqm1 nc nc clk cke a9 a8 a7 a6 a5 a4 a3 dqm3 vss nc dq31 vddq dq30 dq29 vssq dq28 dq27 vddq dq26 dq25 vssq dq24 vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 x32 pin configuration
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 3 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet vddq and vssq are supplied to the output buffers only. power supply vddq, vssq power supply for the memory array and peripheral circuitry. power supply vdd, vss din mask / output disable: when dqm is high in burst write, din for the current cycle is masked. when dqm is high in burst read, dout is disabled at the next but one cycle. input dqm0-3(x32) data in and data out are referenced to the rising edge of clk. input / output dq0-31(x32) bank address: ba0,1 specifies one of four banks to which a command is applied. ba0,1 must be set with act, pre, read, write commands. input ba0,1 a0-11 specify the row / column address in conjunction with ba0,1. the row address is specified by a0-10(x32). the column address is specified by a0-7. a10 is also used to indicate precharge option. when a10 is high at a read / write command, an auto precharge is performed. when a10 is high at a precharge command, all banks are precharged. input a0-11 combination of /ras, /cas, /we defines basic commands. input /ras, /cas, /we chip select: when /cs is high, any command are masked except clk, cke and dqm input /cs clock enable: cke controls internal clock. when cke is low, internal clock for the following cycle is ceased. cke is also used to select auto / self refresh. after self refresh mode is started, cke becomes asynchronous input. self refresh is maintained as long as cke is low. input cke master clock: all other inputs are referenced to the rising edge of clk. input clk pin function
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 4 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet m2 v 64 s 5 0 e tp -6 access item package type process generation interface organization synchronous dram density function mitsubishi dram these rules are only applied to the synchronous dram family . address buffer a0-10 ba0,1 control signal buffer /cs /ras /cas /we clk cke clock buffer control circuitry i/o buffer dq0-31 mode register dqm0-3 memory array bank #0 2048 x256 x32 cell array memory array bank #1 2048 x256 x32 cell array memory array bank #2 2048 x256 x32 cell array memory array bank #3 2048 x256 x32 cell array -6 : 7.5ns (pc133/3-3-3) -7 : 10ns(pc100/2-2-2) tp : tsop (ii) e: 6th gen. reserved for future use 5: x32 64 : 64mbit v : lvttl wg : bga type designation code block diagram i operating temp. i : i version
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 5 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet basic functions activate (act) [/ras =l, /cas =/we =h] act command activates a row in an idle bank indicated by ba. read (read) [/ras =h, /cas =l, /we =h] read command starts burst read from the active bank indicated by ba. first output data appears after /cas latency. when a10 =h at this command, t he bank is deactivated after the burst read (auto- precharge, reada ) write (write) [/ras =h, /cas =/we =l] write command starts burst write to the active bank indicated by ba. total data length to be written is set by burst length. when a10 =h at this command, the bank is deactivated after the burst write (auto-precharge, writea ). precharge (pre) [/ras =l, /cas =h, /we =l] pre command deactivates the active bank indicated by ba. this command also terminates burst read /write operation. when a10 =h at this command, all banks are deactivated (precharge all, prea ). auto-refresh (refa) [/ras =/cas =l, /we =cke =h] refa command starts auto-refresh cycle. refresh address are generated internally. after this command, the banks are precharged automatically. /cs /ras /cas /we cke a10 clk chip select : l=select, h=deselect command command command refresh option @refresh command precharge option @precharge or read/write command define basic commands the M2V64S50ETP-I provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. each command is defined by control signals of /ras, /cas and /we at clk rising edge. in addition to 3 signals, /cs ,cke and a10 are used as chip select, refresh option, and precharge option, respectively. to know the deta iled definition of commands, please see the command truth table.
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 6 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet command truth table h=high level, l=low level, v=valid, x=don't care, n=clk cycle number note:a7-9=l, a0-a6 =mode address (x32) command mnemonic cke n-1 cke n /cs /ras /cas /we ba0,1 a10 /ap a0-9, 11 deselect desel h x h x x x x x x no operation nop h x l h h h x x x row address entry & bank activate act h x l l h h v v v single bank precharge pre h x l l h l v l x precharge all banks prea h x l l h l h x column address entry & write write h x l h l l v l v column address entry & write with auto-precharge writea h x l h l l v h v column address entry & read read h x l h l h v l v column address entry & read with auto-precharge reada h x l h l h v h v auto-refresh refa h h l l l h x x x self-refresh entry refs h l l l l h x x x self-refresh exit refsx lhhxxxxxx lh lhhhxxx burst terminate tbst h x l h h l x x x mode register set mrs h x l l l l l l v x note 1
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 7 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet current state /cs /ras /cas /we address command action idle h x x x x desel nop lhhhx nop nop l h h l x tbst illegal*2 l h l x ba, ca, a10 read / write illegal*2 l l h h ba, ra act bank active, latch ra l l h l ba, a10 pre / prea nop*4 l l l h x refa auto-refresh*5 ll ll op-code, mode-add mrs mode register set*5 row active h x x x x desel nop lhhhx nop nop l h h l x tbst nop l h l h ba, ca, a10 read / reada begin read, latch ca, determine auto-precharge l h l l ba, ca, a10 write / writea begin write, latch ca, determine auto-precharge l l h h ba, ra act bank active / illegal*2 l l h l ba, a10 pre / prea precharge / precharge all l l l h x refa illegal ll ll op-code, mode-add mrs illegal read h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l x tbst terminate burst l h l h ba, ca, a10 read / reada terminate burst, latch ca, begin new read, determine auto-precharge*3 l h l l ba, ca, a10 write / writea terminate burst, latch ca, begin write, determine auto- precharge*3 l l h h ba, ra act bank active / illegal*2 l l h l ba, a10 pre / prea terminate burst, precharge l l l h x refa illegal ll ll op-code, mode-add mrs illegal function truth table (1/4)
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 8 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet function truth table (2/4) current state /cs /ras /cas /we address command action write h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l x tbst terminate burst l h l h ba, ca, a10 read / reada terminate burst, latch ca, begin read, determine auto- precharge*3 l h l l ba, ca, a10 write / writea terminate burst, latch ca, begin write, determine auto- precharge*3 l l h h ba, ra act bank active / illegal*2 l l h l ba, a10 pre / prea terminate burst, precharge l l l h x refa illegal ll ll op-code, mode-add mrs illegal read with auto precharge h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l x tbst illegal l h l h ba, ca, a10 read / reada illegal for same bank *6 l h l l ba, ca, a10 write / writea illegal for same bank *6 l l h h ba, ra act bank active / illegal*2 l l h l ba, a10 pre / prea illegal*2 l l l h x refa illegal ll ll op-code, mode-add mrs illegal write with auto precharge h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l x tbst illegal l h l h ba, ca, a10 read / reada illegal for same bank *7 l h l l ba, ca, a10 write / writea illegal for same bank *7 l l h h ba, ra act bank active / illegal*2 l l h l ba, a10 pre / prea illegal*2 l l l h x refa illegal ll ll op-code, mode-add mrs illegal
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 9 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet current state /cs /ras /cas /we address command action pre ? charging h x x x x desel nop (idle after trp) l h h h x nop nop (idle after trp) l h h l x tbst illegal*2 l h l x ba, ca, a10 read / write illegal*2 l l h h ba, ra act illegal*2 l l h l ba, a10 pre / prea nop*4 (idle after trp) l l l h x refa illegal ll ll op-code, mode-add mrs illegal row activating h x x x x desel nop (row active after trcd) l h h h x nop nop (row active after trcd) l h h l x tbst illegal*2 l h l x ba, ca, a10 read / write illegal*2 l l h h ba, ra act illegal*2 l l h l ba, a10 pre / prea illegal*2 l l l h x refa illegal ll ll op-code, mode-add mrs illegal write re- covering h x x x x desel nop lhhhx nop nop l h h l x tbst illegal*2 l h l x ba, ca, a10 read / write illegal*2 l l h h ba, ra act illegal*2 l l h l ba, a10 pre / prea illegal*2 l l l h x refa illegal ll ll op-code, mode-add mrs illegal function truth table (3/4)
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 10 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet current state /cs /ras /cas /we address command action re- freshing h x x x x desel nop (idle after trfc) l h h h x nop nop (idle after trfc) l h h l x tbst illegal l h l x ba, ca, a10 read / write illegal l l h h ba, ra act illegal l l h l ba, a10 pre / prea illegal l l l h x refa illegal ll ll op-code, mode-add mrs illegal mode register setting h x x x x desel nop (idle after trsc) l h h h x nop nop (idle after trsc) l h h l x tbst illegal l h l x ba, ca, a10 read / write illegal l l h h ba, ra act illegal l l h l ba, a10 pre / prea illegal l l l h x refa illegal ll ll op-code, mode-add mrs illegal abbreviations: h=high level, l=low level, x=don't care ba=bank address, ra=row address, ca =column address, nop=no operation notes: 1. all entries assume that cke was high during the preceding clock cycle and the current clock cycle. 2. illegal to bank in specified state; function may be legal in the bank indicated by ba, depending on the state of that bank. 3. must satisfy bus contention, bus tu rn around, write recovery requirements. 4. nop to bank precharging or in idle state. may precharge bank indicated by ba. 5. illegal if any bank is not idle. 6. refer to read with auto-precharge in page 17 7. refer to write with auto-precharge in page 18 illegal = device operation and/or data-integrity are not guaranteed. function truth table (4/4)
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 11 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet current state cke n-1 cke n /cs /ras /cas /we add action self- refresh*1 hxxxxxxinvalid l h h x x x x exit self-refresh (idle after trfc) l h l h h h x exit self-refresh (idle after trfc) l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal l l x x x x x nop (maintain self-refresh) power down hxxxxxxinvalid l h x x x x x exit power down to idle l l x x x x x nop (maintain power down) all banks idle*2 h h x x x x x refer to function truth table h l l l l h x enter self-refresh h l h x x x x enter power down h l l h h h x enter power down h l l h h l x illegal h l l h l x x illegal h l l l x x x illegal l x x x x x x refer to current state =power down any state other than listed above h h x x x x x refer to function truth table h l x x x x x begin clk suspend at next cycle*3 l h x x x x x exit clk suspend at next cycle*3 l l x x x x x maintain clk suspend function truth table for cke abbreviations: h=high level, l=low level, x=don't care notes: 1. cke low to high transition will re-enable clk and other inputs asynchronously a minimum setup time must be satisfied before any command other than exit. 2. self-refresh can be entered only from the all banks idle state. 3. must be legal command.
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 12 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet tbst tbst pre pre simplified state diagram automatic sequence command sequence idle pre charge power down read reada write writea ckel ckeh refa mrs ckel ckeh refs ckel ckeh writea reada pre self refresh auto refresh clk suspend write suspend read suspend reada suspend writea suspend row active act write read write read reada reada writea writea ckel ckeh ckel ckeh ckel ckeh mode register set mrs prea power applied pre charge all auto refresh refa ( 2 or more ) refsx power on
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 13 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet power on sequence mode register before starting normal operation, the following power on sequence is necessary to prevent a sdram from damaged or malfunctioning. 1. apply power and start clock. attempt to maintain cke high, dqm high and nop or desel condition at the inputs. 2. maintain stable power, stable clock, and nop or desel input conditions for a minimum of 100us. 3. issue precharge commands for all banks. (pre or prea) 4. after all banks become idle state (after trp), issue 2 or more auto-refresh commands. 5. issue a mode register set command to initialize the mode register. after these sequence, the sdram is idle state and ready for normal operation. burst length, burst type, /cas latency and write mode can be programmed by setting the mode register (mrs) with ba0=ba1=0. the mode register stores these data until the next mrs command, which may be issued when all banks are in idle state. after trsc from a mrs command, the sdram is ready for new command. unused bit a7-a8,a10(x32) have to be programmed to ?0?. r: reserved for future use latency mode cl /cas latency 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 r r 2 3 r r r r burst length bl bt=0 bt=1 1 2 4 8 r r r full page 1 2 4 8 r r r r 0 1 burst type sequential interleaved 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 ba0 ba1 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0000 00 ltmodebt bl wm 0 1 write mode burst write single write /cs /ras /cas /we a11-a0 clk v ba0,ba1
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 14 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet a2 a1 a0 initial address bl sequential interleaved column addressing 000 001 010 011 100 101 110 111 -00 -01 -10 -11 --0 0123456701234567 1234567010325476 2345670123016745 3456701232107654 4567012345670123 5670123454761032 6701234567452301 7012 0123 1230 2301 30 01 7654 0123 1032 2301 32 01 --1 12 10 3456 3210 10 10 8 4 2 command address clk dq /cas latency burst length burst length burst type cl= 3 bl= 4 read y write y q0 q1 q2 q3 d0 d1 d2 d3
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 15 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet clk command a0-9,11 a10 ba0-1 dq operational description bank activate one of four banks is activated by an act command. a bank is selected by ba0-1. a row is selected by a0-10(x32). multiple banks can be active state concurrently by issuing multiple act commands. minimum activation interval bet ween one bank and an other bank is trrd. precharge an open bank is deactivated by a pre command. a bank to be deactivated is designated by ba0-1. when multiple banks are active, a precharge all command (prea, pre + a10=h) deactivates all of open banks at the same time. ba0-1 are "don't care" in this case. minimum delay time of an act command after a pre command to the same bank is trp. read a read command can be issued to any active bank. the start address is specified by a0-7. 1st output data is available after the /cas latency from the read. the consecutive data length is defined by the burst length. the address sequence of the burst data is defined by the burst type. minimum delay time of a read command after an act command to the same bank is trcd. when a10 is high at a read command, auto-prechar ge (reada) is performed. any command (read, write, pre, act,tbst) to the same bank is inhi bited till the internal precharge is complete. the internal precharge starts at the bl after read a. the next act command can be issued after (bl + trp) from the previous reada. in any case, trcd+bl > trasmin must be met. bank activation and precharge all (bl=4, cl=3) act read act pre act xa xb yb xa 1 xa xb 0 00 01 01 00 qb0 qb1 qb2 qb3 trrd trcd trp xa precharge all
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 16 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet clk command dq dq clk command a0-9,11 a10 ba0-1 dq clk command a0-9,11 a10 ba0-1 dq act act xa xa xa 00 00 xa read with auto-precharge (cl=2, bl=4) read ya 1 00 qa0 qa1 qa2 qa3 internal precharge starts act act auto-precharge timing (read, bl=4) read qa0 qa1 qa2 qa3 internal precharge starts qa0 qa1 qa2 qa3 cl=2 cl=3 act read act pre act xa xb yb xa 0 xa xb 0 00 01 01 00 qb0 qb1 qb2 qb3 xa multi bank interleaving read (cl=2, bl=4) read ya 0 00 qa0 qa1 qa2 qa3 00 trcd trcd trp trcd trp bl trcd bl
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 17 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet clk command a0-9,11 a10 ba0-1 dq clk command a0-9,11 a10 ba0-1 dq write a write command can be issued to any active bank.the start address is specified by a0-7. 1st input data is set at the same cycle as the write. the consecutive data length to be written is defined by the burst length. the address sequence of burst data is defined by the burst type. minimum delay time of a write command af ter an act command to the same bank is trcd. from the last input data to the pre command, the writ e recovery time (twr) is required. when a10 is high at a write command, auto-precharge (writea) is performed. any command (read, write, pre, act, tbst) to the same bank is inhibited till the internal precharge is complete. the internal precharge starts at twr after the last input data cycle. the next act command can be issued after (bl + twr -1 +trp) from the previous writea. in any case, trcd + bl + twr -1 > trasmin must be met. act pre act xa xa 0 xa 00 00 xa write (bl=4) write ya 0 00 da0 da1 da2 da3 act act xa xa xa 00 00 xa write with auto-precharge (bl=4) write ya 1 00 da0 da1 da2 da3 internal precharge starts trcd trp bl twr trcd trp bl twr
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 18 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet clk command a0-9,11 a10 ba0-1 dq dqm clk command a0-9,11 a10 ba0-1 dq burst interruption read interrupted by read burst read operation can be interrupted by new read of any active bank. random column access is allowed. read to read interval is minimum 1 clk. read interrupted by write burst read operation can be interrupted by write of any active bank. random column access is allowed. in this case, the dq should be controlled adequately by using the dqm to prevent the bus contention. the output is disabled automatically 2 cycle after write assertion. read yb 0 00 qc0 qc1 qc2 qc3 read interrupted by read (cl=2, bl=4) read ya 0 00 qa0 qa1 qa2 qb0 read yc 0 10 act xa xa 00 read interrupted by write (cl=2, bl=4) read ya 0 00 qa0 da0 da1 da2 write ya 0 00 da3 output disable by dqm by write
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 19 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet clk command dq command dq command dq command dq command dq command dq cl=2 cl=3 read interrupted by precharge a burst read operation can be interrupted by a precharge of the same bank . read to pre interval is minimum 1 clk. a pre command to output disable latency is equivalent to the /cas latency. read interrupted by precharge (bl=4) pre read q0 q1 q2 pre read q0 q1 pre read q0 pre read q0 q1 q2 pre read q0 q1 pre read q0
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 20 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet clk command dq command dq command dq command dq command dq command dq cl=2 cl=3 read interrupted by burst terminate similarly to the precharge, a burst terminate command can interrupt the burst read operation and disable the data output. the terminated bank remains active. read to tbst interval is minimum 1 clk. a tbst command to output disable latency is equivalent to the /cas latency. tbst read q0 q1 q2 tbst read q0 q1 tbst read q0 tbst read q0 q1 q2 tbst read q0 q1 tbst read q0 read interrupted by burst terminate (bl=4)
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 21 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet clk command a0-9,11 a10 ba0-1 dq clk command a0-9,11 a10 ba0-1 dq write interrupted by write burst write operation can be interrupted by new write of any active bank. random column access is allowed. write to write interval is minimum 1 clk. write interrupted by read burst write operation can be interrupted by read of any active bank. random column access is allowed. write to read interval is minimum 1 clk. the input data on dq at the interrupting read cycle is "don't care". write interrupted by write (bl=4) write yb 0 00 dc0 dc1 dc2 dc3 write ya 0 00 da0 da1 da2 db0 write yc 0 10 act xa xa 00 write interrupted by read (cl=2, bl=4) read yb 0 00 da0 da1 qb0 write ya 0 00 qb1 qb2 qb3 don't care
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 22 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet clk command a0-9,11 a10 ba0-1 dq clk command a0-9,11 a10 ba0-1 dq dqm write interrupted by precharge burst write operation can be interrupted by precharge of the same bank. write recovery time (twr) is required from the last data to pre command. during write recovery, data inputs must be masked by dqm. write interrupted by burst terminate burst terminate command can terminate burst write operat ion. in this case, the write recovery time is not required and the bank remains active. write to tbst interval is minimum 1 clk. write ya 0 00 write interrupted by precharge (bl=4) act xa 0 00 da0 da1 pre 0 00 act xa 0 00 write ya 0 00 write interrupted by burst terminate (bl=4) act xa 0 00 da0 da1 tbst write yb 0 00 db0 db1 db2 db3 twr trp
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 23 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet clk command a0-9,11 a10 ba0-1 dq clk command a0-9,11 a10 ba0-1 dq write with auto-precharge interrupted by write / read to different bank burst write with auto-precharge can be interrupted by write or read to different bank. next act command can be issued after (bl+twr-1+trp) from the writea. auto-precharge interruption by a command to the same bank is inhibited. writea interrupted by write to different bank (bl=4) db0 db1 db2 db3 write ya 1 00 da0 da1 write yb 0 10 act xa xa 00 interrupted auto-precharge activate writea interrupted by read to different bank (cl=2, bl=4) write ya 1 00 da0 da1 read yb 0 10 act xa xa 00 interrupted auto-precharge activate qb0 qb1 qb2 qb3 bl twr trp bl twr trp precharge precharge
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 24 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet clk command a0-9,11 a10 ba0-1 dq read with auto-precharge interr upted by read to different bank burst read with auto-precharge can be interrupted by read to different bank. next act command can be issued after (bl+trp) from the reada. auto-precharge interruption by a command to the same bank is inhibited. reada interrupted by read to different bank (cl=2, bl=4) read ya 1 00 qa0 qa1 read yb 0 10 act xa xa 00 interrupted auto-precharge activate qb0 qb1 qb2 qb3 full page burst full page burst length is available for only the sequential burst type. full page burst read / write is repeated until a precharge or a burst terminate command is issued. in case of the full page burst, a read / write with auto-precharge command is illegal. bl trp precharge
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 25 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet auto-refresh clk /cs /ras /cas /we cke a0-11 ba0-1 auto refresh on all banks auto refresh on all banks nop or deselect minimum trfc auto refresh single cycle of auto-refresh is initiated wi th a refa (/cs= /ras= /cas= l, /we= /cke= h) command. the refresh address is generated internally. 4096 refa cycles within 64ms refresh 64mbit memory cells. the auto-refresh is performed on 4 banks concurrently. before performing an auto-refresh, all banks must be in idle state. auto-refresh to auto-refresh interval is minimum trfc. any command must not be issued before trfc from the refa command.
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 26 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet self-refresh clk /cs /ras /cas /we cke a0-11 ba0-1 self refresh self-refresh mode is entered by issuing a refs command (/cs= /ras= /cas= l, /we= h, cke= l). once the self-refresh is init iated, it is maintained as long as cke is kept low. during the self-refresh mode, cke is asynchronous and the only enabled input. all other inputs including clk are disabled and ignored, so that power consumption due to synchr onous inputs is saved. to exit the self-refresh, supplying stable clk inputs, asserting desel or nop command and then asserting cke=h. after trfc from the 1st clk edge following cke=h, all banks are in idle state and a new command can be issued, but desel or nop commands must be asserted till then. self refresh entry self refresh exit x 00 minimum trfc for recovery new command stable clk nop
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 27 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet dq suspend by cke clk command dq cke power down by cke clk command cke command cke clk suspend and power down cke controls the internal clk at the following cycle. figure below shows how cke works. by negating cke, the next internal clk is suspended. the purpose of clk suspend is power down, output suspend or input suspend. cke is a synchronous i nput except during the self-refresh mode. clk suspend can be performed either when the banks are active or idle. a command at the suspended cycle is ignored. prenopnopnop nop nop nop act write read d0 d1 d3 q0 q1 q2 q3 ext.clk cke int.clk tih tis tih tis d2 standby power down active power down
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 28 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet dqm function clk command dq dqm0-3 dqm control dqm* is a dual functional signal defined as the data mask for writes and the output disable for reads. during writes, dqm masks input data word by word. dqm to data in latency is 0. during reads, dqm forces output to hi-z word by word. dqm to output hi-z latency is 2. * dqm: dq0-3 (x32) masked by dqm=h disabled by dqm=h write read d0 d2 d3 q0 q1 q3
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 29 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet absolute maximum ratings recommended operating conditions (ta=-40 to 85 o c, unless otherwise noted) capacitance (ta=-40 to 85 o c, vdd = vddq = 3.3v+ 0.3v, vss = vssq = 0v, unless otherwise noted) o c -65 to 150 storage temperature tstg o c -40 to 85 operating ambient temperature ta mw 1000 ta=25 o c power dissipation pd ma 50 output current io v -0.5 to vdd+0.5 with respect to vssq output voltage vo v -0.5 to vdd+0.5 with respect to vss input voltage vi v -0.5 to 4.6 with respect to vssq supply voltage for output vddq v -0.5 to 4.6 with respect to vss supply voltage vdd unit ratings conditions parameter symbol v 0.8 -0.3 low-level input voltage all inputs vil v vdd+0.3 2.0 high-level input voltage all inputs vih v 0 0 0 supply voltage for output vssq v 3.6 3.3 3.0 supply voltage for output vddq v 0 0 0 supply voltage vss v 3.6 3.3 3.0 supply voltage vdd max. typ. min. unit limits parameter symbol pf 6.0 3.0 ci/o pf 4.0 2.0 input capacitance,i/o pin input capacitance,clk pin ci(k) pf 4.0 2.0 input capacitance,control pin ci(c) pf 4.0 2.0 vi=1.4v f=1mhz vi=25mvrms input capacitance,address pin ci(a) max. min. unit limits test condition parameter symbol
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 30 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet average supply current from vdd (ta=-40 to 85 o c, vdd = vddq = 3.3v+ 0.3v, vss = vssq = 0v, output open, unless otherwise noted) notes 1. addresses are changed 3 times during trc, only 1 bank is active & all other banks are idle 2. all banks are idle 3. input signals are changed one time during 3 x tclk 4. input signals are stable 5. all banks are active ac operating conditio ns and characteristics (ta=-40 to 85 o c, vdd = vddq = 3.3v+ 0.3v, vss = vssq = 0v, unless otherwise noted) symbol parameter test conditions limits min. max. unit voh(dc) vol(dc) ioz il high-level output voltage (dc) low-level output voltage (dc) off-state output current input current ioh=-2ma iol= 2ma q floating vo=0 to vddq vih=0 to vddq+0.3v, other input pins=0v 2.4 0.4 v v ua ua -10 -10 10 10 1.0 140 10 5 10 2 -6 ma cke<0.2v self-refresh current icc6 100 4,5 3,5 2,4 2,3 5 ma ma ma ma ma ma ma 120 20 tclk=min, trfc=min auto-refresh current icc5 tclk=min, bl=4, gapless data burst operating current icc4 tclk=l, cke>vihmin tclk=min, cke>vihmin, /cs> vihmin active standby current in normal mode icc3ns icc3n tclk=l, cke>vihmin tclk=min, cke>vihmin, /cs>vihmin idle standby current in normal mode icc2ns icc2n tclk=l, cke sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 31 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet ac timing requirements (ta=-40 to 85 o c, vdd = vddq = 3.3v+ 0.3v, vss = vssq = 0v, unless otherwise noted) input pulse levels:0.8v to 2.0v input timing measurement level:1.4v ac timing is referenced to the input signal crossing through 1.4v. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms 64 64 10 10 20 15 20 15 20 20 20 20 120000 50 120000 45 80 75 70 67.5 1 2 0.8 1.5 10 1 10 1 3 3 2.5 2.5 10 10 7.5 10 refresh interval time mode register set cycle time act to act delay time write recovery time row precharge time row active time row to column delay refresh cycle time row cycle time input hold time (all inputs) input setup time (all inputs) transition time of clk clk low pulse width clk high pulse width tref trsc trrd twr trp tras trcd trfc trc tih tis tt tcl tch cl=3 cl=2 clk cycle time tclk note unit max. min. max. min. -7i -6i limits parameter symbol clk signal 1.4v 1.4v tclk tis tih
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 32 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet switching characteristics (ta=-40 to 85 o c, vdd = vddq = 3.3v+ 0.3v, vss = vssq = 0v, unless otherwise noted) output load condition note. if tr (clk rising time) is > 1ns, (tr/2 - 0.5ns) should be added to the parameters. 50pf vout tolz tac toh tohz clk dq 1.4v 1.4v ns 6 3 5.4 3 cl=3 cl=2 ns ns ns ns ns ns 6 3 6 3 0 0 3 3 3 3 6 6 5.4 6 cl=3 cl=2 cl=3 cl=2 delay time, output high impedance from clk delay time, output low impedance from clk output hold time from clk access time from clk tohz tolz toh tac max min. max min. -7i -6i unit limits parameter symbol
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 33 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 clk /cs /ras /cas /we cke dqm a0-9,11 a10 ba0,1 dq burst write (single bank) [bl=4] italic parameter shows minimum case act#0 write#0 pre#0 act#0 write#0 pre#0 trc tras trp trcd trcd twr twr 00 0000 d0 d0 d0 d0 d0 d0 d0 d0 xy xy xx timing charts
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 34 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 clk /cs /ras /cas /we cke dqm a0-9,11 a10 ba0,1 dq burst write (multi bank) [bl=4] act#0 write#0 pre#0 act#0 write#0 pre#0 trc tras trp trcd trcd twr twr trc trrd trcd x yxy x y x xx x x 00 0000 1 1 1 d0 d0 d0 d0 d0 d0 d0 d0 d1 d1 d1 d1 act#1 writea#1 (auto-precharge) act#1 italic parameter shows minimum case
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 35 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 clk /cs /ras /cas /we cke dqm a0-9,11 a10 ba0,1 dq burst read (single bank) [cl=2,bl=4] act#0 read#0 pre#0 act#0 read#0 pre#0 trc tras trp trcd trcd 00 0000 q0 q0 q0 q0 q0 q0 q0 q0 xy xy xx tras italic parameter shows minimum case
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 36 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 clk /cs /ras /cas /we cke dqm a0-9,11 a10 ba0,1 dq burst read (multi bank) [cl=2,bl=4] act#0 reada#0 act#0 read#0 pre#0 trc tras trcd trcd trc trrd trcd x yxy x y x xx x x 00 000 1 1 1 q0 q0 q0 q0 q0 q0 q0 q0 q1 q1 q1 q1 act#1 reada#1 act#1 italic parameter shows minimum case
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 37 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 clk /cs /ras /cas /we cke dqm a0-9,11 a10 ba0,1 dq write interrupted by write [bl=4] act#0 write#0 write#0 interrupt same bank pre#0 trrd trcd twr x yx y x y y x x x 0 00 0 1 1 1 0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d1 d1 d1 act#1 act#1 writea#1 interrupt other bank write#0 interrupt other bank italic parameter shows minimum case
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 38 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 clk /cs /ras /cas /we cke dqm a0-9,11 a10 ba0,1 dq read interrupted by read [cl=2,bl=4] act#0 read#0 read#1 interrupt other bank trrd trcd x yx y x y y xx x 0 01 01 1 1 q0 q0 q0 q1 q0 q0 q0 q0 q1 q1 q1 q1 act#1 act#1 reada#1 interrupt same bank read#0 interrupt other bank trcd italic parameter shows minimum case
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 39 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 clk /cs /ras /cas /we cke dqm a0-9,11 a10 ba0,1 dq write interrupted by read, read interrupted by write [cl=2,bl=4] italic parameter shows minimum case act#0 read#1 write#0 pre#1 trrd trcd twr x xy y y 0 11 1 0 1 d0 d0 d1 d1 d1 d1 q1 q1 act#1 write#1 trcd x x
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 40 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 clk /cs /ras /cas /we cke dqm a0-9,11 a10 ba0,1 dq write / read terminated by precharge [cl=2,bl=4] act#0 write#0 pre#0 terminate trp trcd x yx y x act#0 read#0 trcd trc tras trp twr xx x 0 00 00 0 0 d0 d0 q0 q0 pre#0 terminate act#0 italic parameter shows minimum case
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 41 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 clk /cs /ras /cas /we cke dqm a0-9,11 a10 ba0,1 dq write / read terminated by burst terminate [cl=2,bl=4] act#0 write#0 read#0 trcd x yy y tbst write#0 twr x 0 00 00 pre#0 d0 d0 q0 q0 d0 d0 d0 d0 tbst italic parameter shows minimum case
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 42 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 clk /cs /ras /cas /we cke dqm a0-9,11 a10 ba0,1 dq single write burst read [cl=2,bl=4] act#0 write#0 trcd x y y read#0 x 0 00 d0 q0 q0 q0 q0 italic parameter shows minimum case
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 43 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet clk /cs /ras /cas /we cke dqm a0-9,11 a10 ba0,1 dq power-up sequence and initialize power on pre all trp refa 100us trfc trfc trsc x ma x 0 0 0 desel refa refa mrs act#0 minimum 2 refa cycles italic parameter shows minimum case
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 44 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 clk /cs /ras /cas /we cke dqm a0-9,11 a10 ba0,1 dq auto refresh act#0 write#0 trp x y refa x 00 d0 d0 d0 d0 trfc trcd pre all all banks must be idle before refa is issued. italic parameter shows minimum case
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 45 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 clk /cs /ras /cas /we cke dqm a0-9,11 a10 ba0,1 dq self refresh act#0 pre all x x 0 self refresh entry self refresh exit all banks must be idle before refs is issued. trp trfc italic parameter shows minimum case
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 46 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 clk /cs /ras /cas /we cke dqm a0-9,11 a10 ba0,1 dq clk suspension [cl=2, bl=4] act#0 write#0 trcd x yy read#0 x 0 0 0 d0 d0 q0 q0 d0 d0 q0 q0 q0 internal clk suspended internal clk suspended italic parameter shows minimum case
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 47 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 clk /cs /ras /cas /we cke dqm a0-9,11 a10 ba0,1 dq power down act#0 pre all standby power down x x 0 active power down italic parameter shows minimum case
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 48 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet notes for cmos devices 1 precaution against esd for mos devices exposing the mos devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the mos devices operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. mos devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. mos devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor mos devices on it. 2 handling of unused input pins for cmos devices no connection for cmos devices input pins can be a cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. the unused pins must be handled in accordance with the related specifications. 3 status before initialization of mos devices power-on does not necessarily define initial status of mos devices. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the mos devices with reset function have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. mos devices are not initialized until the reset signal is received. reset operation must be executed immediately after power-on for mos devices having reset function. cme0107
sdr sdram e0364m20 (ver.2.0) (previous rev.0.3e) june 2004 (k) japan 49 M2V64S50ETP-I wtr (wide temperature range) 64m single data rate synchronous dram data sheet m01e0107 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of elpida memory, inc. elpida memory, inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of elpida memory, inc. or third parties by or arising from the use of the products or information listed in this document. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of elpida memory, inc. or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. elpida memory, inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [product applications] elpida memory, inc. makes every attempt to ensure that its products are of high quality and reliability. however, users are instructed to contact elpida memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [product usage] design your application so that the product is used within the ranges and conditions guaranteed by elpida memory, inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. elpida memory, inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating elpida memory, inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the elpida memory, inc. product. [usage environment] this product is not designed to be resistant to electromagnetic waves or radiation. this product must be used in a non-condensing environment. if you export the products or technology described in this document that are controlled by the foreign exchange and foreign trade law of japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of japan. also, if you export products/technology controlled by u.s. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. if these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. the information in this document is subject to change without notice. before using this document, confirm that this is the late st version.

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