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1 ps8462 02/22/00 features low on-resistance (100 w typ.) minimizes distortion and error voltages single supply operation (2.7v to 8v) improved second source for max395 spi?/qsi?, microwire?-compatible serial interface split-supply operation (+3v to +8v) on-resistance flatness: 10 w max. on-resistance matching between channels: 5 w max. ttl/cmos logic compatible (w/+5v or 5v supplies) fast switching speed break-before-make action eliminates momentary crosstalk rail-to-rail analog signal range low power consumption narrow soic and qsop packages minimize board area asynchonous reset (rs) input applications data acquisition systems audio switching and routing test equipment pbx, pabx telecommunication systems battery-powered systems description the ps395 eight-channel, serially controlled, single-pole/single- throw (spst) analog switch offers eight separately controlled switches that conduct equally well in either direction. on-resis- tance (100 w max.) is matched between switches to 5 w max. and is flat (10 w max.) over the specified signal range. these cmos devices can operate continuously with dual power supplies ranging from 2.7v to 8v or a single supply between +2.7v and +16v. each switch can handle rail-to-rail analog signals. the off leakage current is only 0.1na at +25c or 5na at +85c. upon power-up, all switches are off, and the internal shift registers are reset to zero. the ps395 is electrically equivalent to two ps391 quad switches controlled by a serial interface, and is pin compat- ible with the ps335. the serial interface is compatible with spi?/qspi? and microwire?. functioning as a shift register, it allows data (at din) to be clocked-in synchronously with the rising edge of clock (sclk). the shift register?s output (dout) enables several ps395s to be daisy chained. all digital inputs have 0.8v to 2.4v logic thresholds, ensuring both ttl- and cmos-logic compatibility when using 5v supplies or a single +5v supply. pin configurations e m a nn o i t c n u f k l ct u p n i l a t i g i d k c o l c l a i r e s + vt u p n i e g a t l o v y l p p u s g o l a n a e v i t i s o p a t a d n i t u p n i l a t i g i d a t a d l a i r e s d n gd n u o r g o n 0 o n ? 7 7 ? 0 s e h c t i w s g o l a n a n e p o y l l a m r o n m o c 0 m o c ? 7 7 ? 0 s e h c t i w s g o l a n a n o m m o c ? vt u p n i e g a t l o v y l p p u s g o l a n a e v i t a g e n a t a d t u o t u p t u o l a t i g i d a t a d l a i r e s s rt u p n i t e s e r ) t e s e r ( s ct u p n i l a t i g i d t c e l e s - p i h c pin description note: no and com pins are identical and interchangeble. either may be considered as an input or an output; signals pass equally well in either direction. ps395 precision 8-ch. 17v, spst switch w/8-bit serial decoded control 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 16 15 14 13 8 1 2 3 4 5 6 7 9 10 11 12 17 24 23 22 21 20 19 18 clk v+ data in gnd no 0 com 0 no 1 com 1 no 2 com 2 no 3 com 3 dip/so en rs data out vC no 7 com 7 no 6 com 6 no 5 com 5 no 4 com 4 8-bit decoding logic spi & qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corporation top view ps395
2 ps8462 02/22/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 ps395 precision 8-ch. 17v, spst switch w/8-bit serial decoded control serial-interface truth table s r s t i b a t a d n o i t c n u f 7 d6 d5 d4 d3 d2 d1 d0 d 0xxxxxxxx 0 = 0 d C 7 d , n e p o s e h c t i w s l l a 10xxxxxxxss e h c t i w7 ) f f o ( n e p o 11xxxxxxx ) n o ( d e s o l c 7 s e h c t i w s 1x0xxxxxx ) f f o ( n e p o 6 s e h c t i w s 1x1xxxxxx ) n o ( d e s o l c 6 s e h c t i w s 10x0xxxxx ) f f o ( n e p o 5 s e h c t i w s 11x1xxxxx ) n o ( d e s o l c 5 s e h c t i w s 1xxx0xxxx ) f f o ( n e p o 4 s e h c t i w s 1xxx1xxxx ) n o ( d e s o l c 4 s e h c t i w s 1xxxx0xxx ) f f o ( n e p o 3 s e h c t i w s 1xxxx1xxx ) n o ( d e s o l c 3 s e h c t i w s 1xxxxx0xx ) f f o ( n e p o 2 s e h c t i w s 1xxxxx1xx ) n o ( d e s o l c 2 s e h c t i w s 1xxxxxx0x ) f f o ( n e p o 1 s e h c t i w s 1xxxxxx1x ) n o ( d e s o l c 1 s e h c t i w s 1xxxxxxx0 ) f f o ( n e p o 0 s e h c t i w s 1xxxxxxx1 ) n o ( d e s o l c 0 s e h c t i w s spdt truth table s r s t i b a t a d n o i t c n u f 7 d6 d5 d4 d3 d2 d1 d0 d 0xxxxxxxx 0 = 0 d C 7 d , n e p o s e h c t i w s l l a 101xxxxxx n o 6 d n a f f o 7 h c t i w s 110xxxxxx n o 7 d n a f f o 6 h c t i w s 1xx01xxxx n o 4 d n a f f o 5 h c t i w s 1xx10xxxx n o 5 d n a f f o 4 h c t i w s 1xxxx01xx n o 2 d n a f f o 3 h c t i w s 1xxxx10xx n o 3 d n a f f o 2 h c t i w s 1xxxxxx01 n o 0 d n a f f o 1 h c t i w s 1xxxxxx10 n o 1 d n a f f o 0 h c t i w s
3 ps8462 02/22/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 ps395 precision 8-ch. 17v, spst switch w/8-bit serial decoded control absolute maximum ratings voltages referenced to gnd v+ ................................................................................ ?0.3v, +17v v? ................................................................................ ?17v, +0.3v v+ to v- ........................................................................ -0.3v, +17v sclk, cs, din, dout, reset ...................... -0.3v to (v+ + 0.3v) no, com ..................................................... (v- - 2v) to (v+ + 2v) continuous current into any terminal ............................. 30ma peak current, no_ or com_ (pulsed at 1ms,10% duty cycle) ....................................... 100ma stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the s pecifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. continuous power dissipation (t a = +70c) narrow plastic dip (derate 13.33mw/c above +70c) ...... 1067mw wide so (derate 11.76mw/c above +70c) ..................... 941mw operating temperature ranges ps395c_ g ................................................................ 0c to +70c ps395e_ g .............................................................. -40c to +85c storage temperature range ................................ -65c to +150c lead temperature (soldering, 10s) .................................... +300c r e t e m a r a pl o b m y ss n o i t i d n o c. n i m ) 2 ( . p y t ) 1 ( . x a m ) 2 ( s t i n u h c t i w s g o l a n a e g n a r l a n g i s g o l a n a ) 3 ( v , m o c v o n e , c? v+ vv e c n a t s i s e r n o o n , m o cr n o , v 5 ? = ? v , v 5 = + v v m o c i , v 3 = o n a m 1 = t a v 5 2 + =0 60 0 1 w e , c5 2 1 h c t a m e c n a t s i s e r n o o n , m o c s l e n n a h c n e e w t e b ) 2 ( d r n o , v 5 ? = ? v , v 5 = + v v m o c i , v 3 = o n a m 1 = t a v 5 2 + =5 e , c0 1 e c n a t s i s e r n o o n , m o c s s e n t a l f ) 2 ( r ) n o ( t a l f i , v 5 ? = ? v , v 5 = + v o n a m 1 = v m o c v 3 , v 0 , v 3 ? = t a v 5 2 + =0 1 e , c5 1 t n e r r u c e g a k a e l f f o o n ) 3 ( i ) f f o ( o n , v 5 . 5 ? = ? v , v 5 . 5 = + v v m o c v , v 5 . 4 ? = o n v 5 . 4 = t a v 5 2 + =?1 . 02 0 0 . 01 . 0 a n e , c0 . 1 ?0 1 , v 5 . 5 ? = ? v , v 5 . 5 = + v v m o c v , v 5 . 4 = o n v 5 . 4 ? = t a v 5 2 + =?1 . 02 0 0 . 01 . 0 e , c0 1 ?0 1 t n e r r u c e g a k a e l f f o m o c ) 3 ( i ) f f o ( m o c , v 5 . 5 ? = ? v , v 5 . 5 = + v v m o c v , v 5 . 4 ? = o n v 5 . 4 = t a v 5 2 + =1 . 0 ?2 0 0 . 01 . 0 e , c0 . 1 ?0 1 , v 5 . 5 ? = ? v , v 5 . 5 = + v v m o c v , v 5 . 4 = o n v 5 . 4 ? = t a v 5 2 + =1 . 0 ?2 0 0 . 01 . 0 e , c0 1 ?0 1 t n e r r u c e g a k a e l n o m o c ) 3 ( i ) n o ( m o c , v 5 . 5 ? = ? v , v 5 . 5 = + v v m o c v = o n v 5 . 4 = t a v 5 2 + =2 . 0 ?1 0 . 02 . 0 e , c0 2 ?0 2 o / i l a t i g i d t u p n i t e s e r , s c , k l c s , n i d h g i h d l o h s e r h t c i g o l e g a t l o v v h i e , c 4 . 2 v t u p n i t e s e r , s c , k l c s , n i d h g i h d l o h s e r h t c i g o l e g a t l o v v l i 8 . 0 t u p n i t e s e r , s c , k l c s , n i d w o l r o h g i h c i g o l t n e r r u c i h i i , l i v n i d v , k l c s v , s c v 4 . 2 r o v 8 . 0 =1 ?3 0 . 01 m a h g i h c i g o l e g a t l o v t u p t u o t u o dv t u o d i t u o d a m 8 . 0 =8 . 2+ v v w o l c i g o l e g a t l o v t u p t u o t u o dv t u o d i t u o d a m 6 . 1 ? =04 . 0 s i s e r e t s y h t u p n i k l c sk l c s t s y h 0 0 1v m electrical specifications - dual supplies (v = +4.5v to +5.5v, v? = 4.5v to ?5.5v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.)
4 ps8462 02/22/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 ps395 precision 8-ch. 17v, spst switch w/8-bit serial decoded control r e t e m a r a pl o b m y ss n o i t i d n o c. n i m ) 2 ( . p y t ) 1 ( . x a m ) 2 ( s t i n u s c i t s i r e t c a r a h c c i m a n y d h c t i w s e m i t n o - n r u tt n o s c f o e g d e g n i s i r m o r f t a v 5 2 + =0 0 20 0 4 n s e , c0 0 5 e m i t f f o - n r u tt f f o t a v 5 2 + =0 90 0 4 e , c0 0 5 y a l e d e k a m - e r o f e b - k a e r bt m b b t a v 5 2 + =55 1 n o i t c e j n i e g r a h c ) 4 ( v e t c c l v , f n 1 = o n r , v 0 = s 0 = w t a v 5 2 + =20 1c p e c n a t i c a p a c f f o o nc ) f f o ( o n v o n = f , d n g =z h m 1e , c2 f p e c n a t i c a p a c f f o m o cc ) f f o ( m o c v m o c = f , d n g =z h m 1t a v 5 2 + =25 1 e c n a t i c a p a c f f o h c t i w sc ) n o ( v m o c v = = o n = f , d n gz h m 1e , c8 n o i t a l o s i f f ov o s i r l 0 5 = w c , l , f p 5 1 = v o n v 1 = s m r z h k 0 0 1 = f , t a v 5 2 + =0 9 ? b d k l a t s s o r c l e n n a h c - o t - l e n n a h cv t c r l 0 5 = w c , l , f p 5 1 = v o n v 1 = s m r z h k 0 0 1 = f , e , c0 9 ? < y l p p u s r e w o p e g n a r y l p p u s - r e w o p? v , + ve , c3 8 v t n e r r u c y l p p u s + v+ i , + v r o v 0 = k l c s = s c = n i d + v r o v 0 = t e s e r t a v 5 2 + =70 2 m a e , c0 3 t n e r r u c y l p p u s ? v? i , + v r o v 0 = k l c s = s c = n i d + v r o v 0 = t e s e r t a v 5 2 + =1 ?1 . 01 e , c2 ?2 electrical specifications - dual supplies (continued) (v = +4.5v to +5.5v, v? = 4.5v to ?5.5v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.)
5 ps8462 02/22/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 ps395 precision 8-ch. 17v, spst switch w/8-bit serial decoded control timing characteristics - dual supplies (v = 4.5v to 5.5v, v? = ?4/5v, t a = t min to t max , unless otherwise noted. typical values are t a = +25c). notes: 1. the algebraic convention is used in this data sheet; the most negative value is shown in the minimum column. 2. d r on = r on(max) - r on(min) . on-resistance match between channels and on-resistance flatness are guaranteed only with specified voltages. flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the specified analog signal range. 3. leakage parameters are 100% tested at maximum rated hot temperature and guaranteed by correlation at room temp. 4. guaranteed by design. 5. leakage testing at single supply is guaranteed by testing with dual supplies. 6. see figure 5. off isolation = 20log10 v com /v no , v com = output. no = input to off switch. 7. between any two switches. see figure 2. r e t e m a r a pl o b m y ss n o i t i d n o c. n i m ) 1 ( . p y t ) 1 ( . x a m ) 1 ( s t i n u e c a f r e t n i l a t i g i d l a i r e s y c n e u q e r f k l c sf k l c s e , c 01 . 2z h m e m i t e l c y ct h c t + l c 0 8 4 s n e m i t d a e l s ct s s c 0 4 2 e m i t g a l s ct 2 h s c 0 4 2 e m i t h g i h k l c st h c 0 9 1 e m i t w o l k l c st l c 0 9 1 e m i t p u t e s a t a dt s d 0 0 27 1 e m i t d l o h a t a dt h d 07 1 ? k l c s g n i l l a f r e t f a d i l a v a t a d n i d ) 4 ( t o d , t u o d f o % 0 1 o t k l c s f o % 0 5 c l f p 0 1 = t a v 5 2 + =5 8 e , c0 0 4 t u o d f o e m i t e s i r ) 4 ( t r d c , + v f o % 0 7 o t + v f o % 0 2 l f p 0 1 = 0 0 1 k l c s , n i d t a e m i t e s i r e l b a w o l l a ) 4 ( t r c s 2s n t u o d f o e m i t l l a f ) 4 ( t f d 0 0 1 m s k l c s , n i d t a e m i t l l a f e l b a w o l l a ) 4 ( t f c s 2 s n h t d i w e s l u p m u m i n i m t e s e rt w r 0 7
6 ps8462 02/22/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 ps395 precision 8-ch. 17v, spst switch w/8-bit serial decoded control electrical characteristics - single 5v supply (v+ = + 5v 10%, v- = 0v, gnd = 0v, v ah = v enh = +2.4, v al = v enl = +0.8v) r e t e m a r a pl o b m y ss n o i t i d n o c. n i m ) 2 ( . p y t ) 1 ( . x a m ) 2 ( s t i n u h c t i w s g o l a n a e g n a r l a n g i s g o l a n a ) 3 ( v , m o c v o n e , c? v+ vv e c n a t s i s e r n o o n , m o cr n o v , v 5 = + v m o c , v 5 . 3 = i o n a m 1 = t a v 5 2 + =5 2 15 7 1 w e , c5 2 2 t n e r r u c e g a k a e l f f o o n ) 5 , 4 ( i ) f f o ( o n v , v 5 . 5 = + v m o c , v 5 . 4 ? = v o n v 0 = t a v 5 2 + =?1 . 02 0 0 . 01 . 0 a n e , c0 1 ?0 1 , v 5 . 5 ? = ? v , v 5 . 5 = + v v m o c v , v 5 . 4 = o n v 5 . 4 ? = t a v 5 2 + =?1 . 02 0 0 . 01 . 0 e , c0 1 ?0 1 t n e r r u c e g a k a e l f f o m o c 5 , 4 ( i ) f f o ( m o c v , v 5 . 5 = + v m o c , v 5 . 4 ? = v o n v 0 = t a v 5 2 + =1 . 0 ?2 0 0 . 01 . 0 e , c0 1 ?0 1 , v 5 . 5 ? = ? v , v 5 . 5 = + v v m o c v , v 5 . 4 = o n v 5 . 4 ? = t a v 5 2 + =1 . 0 ?2 0 0 . 01 . 0 e , c0 1 ?0 1 t n e r r u c e g a k a e l n o m o c ) 5 , 4 ( i ) n o ( m o c v , v 5 . 5 = + v m o c v = o n v 5 . 4 = t a v 5 2 + =2 . 0 ?2 0 . 02 . 0 e , c0 2 ?0 2 o / i l a t i g i d t u p n i t e s e r , s c , k l c s , n i d h g i h d l o h s e r h t c i g o l e g a t l o v v h i e , c 4 . 2 v t u p n i t e s e r , s c , k l c s , n i d w o l d l o h s e r h t c i g o l e g a t l o v v l i 8 . 0 t u p n i t e s e r , s c , k l c s , n i d w o l r o h g i h c i g o l t n e r r u c i h i i , l i v n i d v , k l c s v , s c v 4 . 2 r o v 8 . 0 =1 ?3 0 . 01 m a h g i h c i g o l e g a t l o v t u p t u o t u o dv t u o d i t u o d a m 8 . 0 ? =8 . 2+ v v w o l c i g o l e g a t l o v t u p t u o t u o dv t u o d i t u o d a m 6 . 1 ? =04 . 0 s i s e r e t s y h t u p n i k l c sk l c s t s y h 0 0 1v m s c i t s i r e t c a r a h c c i m a n y d h c t i w s e m i t n o - n r u tt n o s c f o e g d e g n i s i r m o r f t a v 5 2 + =0 0 20 0 4 s n e , c0 0 5 e m i t f f o - n r u tt f f o t a v 5 2 + =0 90 0 4 e , c0 0 5 y a l e d e k a m - e r o f e b - k a e r bt m b b t a v 5 2 + =5 1 n o i t c e j n i e g r a h c ) 4 ( v e t c c l v , f n 1 = o n r , v 0 = s 0 = w t a v 5 2 + =20 1c p n o i t a l o s i f f o ) 6 ( v o s i r l c , f n 1 = l , f p 5 1 = v o n v 1 = s m r ,f 1 = 0 z h k 0 t a v 5 2 + =0 9 ? b d k l a t s s o r c l e n n a h c - o t - l e n n a h c ) 6 ( v t c t a v 5 2 + =0 9 ? < y l p p u s r e w o p t n e r r u c y l p p u s ? v , + v+ i r o v 0 = k l c s = s c = n i d + v r o v 0 = t e s e r , + v t a v 5 2 + =70 2 m a e , c0 3
7 ps8462 02/22/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 ps395 precision 8-ch. 17v, spst switch w/8-bit serial decoded control timing characteristics - single +5v supply (v+ = 4.5v to 5.5v, v? = 0v, t a = t min to t max , unless otherwise noted. typical values are t a = +25c). notes: 1. the algebraic convention is used in this data sheet; the most negative value is shown in the minimum column. 2. d r on = r on(max) - r on(min) . on-resistance match between channels and on-resistance flatness are guaranteed only with specified voltages. flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the specified analog signal range. 3. leakage parameters are 100% tested at maximum rated hot temperature and guaranteed by correlation at room temp. 4. guaranteed by design. 5. leakage testing at single supply is guaranteed by testing with dual supplies. 6. see figure 5. off isolation = 20log10 v com /v no , v com = output. no = input to off switch. 7. between any two switches. see figure 2. r e t e m a r a pl o b m y ss n o i t i d n o c. n i m ) 1 ( . p y t ) 1 ( . x a m ) 1 ( s t i n u e c a f r e t n i l a t i g i d l a i r e s y c n e u q e r f k l c sf k l c s e , c 01 . 2z h m e m i t e l c y c ) 4 ( t h c t + l c 0 8 4 s n e m i t d a e l s c ) 4 ( t s s c 0 4 2 e m i t g a l s c ) 4 ( t 2 h s c 0 4 2 e m i t h g i h k l c s ) 4 ( t h c 0 9 1 e m i t w o l k l c s ) 4 ( t l c 0 9 1 e m i t p u t e s a t a d ) 4 ( t s d 0 0 27 1 e m i t d l o h a t a d ) 4 ( t h d 07 1 ? k l c s g n i l l a f r e t f a d i l a v a t a d n i d ) 4 ( t o d , t u o d f o % 0 1 o t k l c s f o % 0 5 c l f p 0 1 = t a v 5 2 + =5 8 e , c0 0 4 t u o d f o e m i t e s i r ) 4 ( t r d , + v f o % 0 7 o t + v f o % 0 2 c l f p 0 1 = 0 0 1 k l c s , n i d t a e m i t e s i r e l b a w o l l a ) 4 ( t r c s 2s n t u o d f o e m i t l l a f ) 4 ( t f d 0 0 1 m s k l c s , n i d t a e m i t l l a f e l b a w o l l a ) 4 ( t f c s 2 s n h t d i w e s l u p m u m i n i m t e s e rt w r 0 7
8 ps8462 02/22/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 ps395 precision 8-ch. 17v, spst switch w/8-bit serial decoded control electrical characteristics - single +3v supply (v+ = +3.0v + 3.6v, v? = 0v, t min to t max , unless otherwise noted. typical values are at t a = +25c) r e t e m a r a pl o b m y ss n o i t i d n o c. n i m ) 2 ( . p y t ) 1 ( . x a m ) 2 ( s t i n u h c t i w s g o l a n a e g n a r l a n g i s g o l a n a ) 3 ( v , m o c v o n e , c? v+ vv e c n a t s i s e r n o o n , m o cr n o v , 0 . 3 = + v m o c , v 5 . 1 = i o n a m 1 = t a v 5 2 + =0 7 20 0 5 w e , c0 0 6 t n e r r u c e g a k a e l f f o o n ) 5 , 4 ( i ) f f o ( o n v , v 0 . 3 = + v m o c , v 3 = v o n v 0 = t a v 5 2 + =?1 . 02 0 0 . 01 . 0 a n e , c5 ?5 v , v 6 . 3 = + v m o c , v 0 = v o n v 3 = t a v 5 2 + =?1 . 02 0 0 . 01 . 0 e , c5 ?5 t n e r r u c e g a k a e l f f o m o c 5 , 4 ( i ) f f o ( m o c v , v 6 . 3 = + v m o c , v 3 = v o n v 0 = t a v 5 2 + =1 . 0 ?2 0 0 . 01 . 0 e , c5 ?5 v , v 6 . 3 = + v m o c , v 0 = v o n v 3 = t a v 5 2 + =1 . 0 ?2 0 0 . 01 . 0 e , c5 ?5 t n e r r u c e g a k a e l n o m o c ) 5 , 4 ( i ) n o ( m o c v , v 6 . 3 = + v m o c , v 3 = v o n v 0 = t a v 5 2 + =1 . 0 ?2 0 0 . 01 . 0 e , c0 1 ?0 1 v , v 6 . 3 = + v m o c , v 0 = v o n v 3 = t a v 5 2 + =1 . 0 ?2 0 0 . 01 . 0 e , c0 1 ?0 1 o / i l a t i g i d t u p n i t e s e r , s c , k l c s , n i d h g i h d l o h s e r h t c i g o l e g a t l o v v h i e , c 4 . 2 v t u p n i t e s e r , s c , k l c s , n i d w o l d l o h s e r h t c i g o l e g a t l o v v l i 8 . 0 t u p n i , s c , k l c s , n i d w o l r o h g i h c i g o l t n e r r u c i h i i , l i v n i d v , k l c s v , s c v 4 . 2 r o v 8 . 0 =1 ?3 0 . 01 m a h g i h c i g o l e g a t l o v t u p t u o t u o dv t u o d i t u o d a m 1 . 0 ? =8 . 2+ v v w o l c i g o l e g a t l o v t u p t u o t u o dv t u o d i t u o d a m 6 . 1 ? =04 . 0 s i s e r e t s y h t u p n i k l c sk l c s t s y h 0 0 1v m s c i t s i r e t c a r a h c c i m a n y d h c t i w s e m i t n o - n r u tt n o s c f o e g d e g n i s i r m o r f t a v 5 2 + =0 6 20 0 6 s n e , c0 0 8 e m i t f f o - n r u tt f f o t a v 5 2 + =0 90 0 3 e , c0 0 4 y a l e d e k a m - e r o f e b - k a e r bt m b b t a v 5 2 + =5 1 n o i t c e j n i e g r a h c ) 4 ( v e t c c l v , f n 1 = o n r , v 0 = s 0 = w t a v 5 2 + =20 1c p n o i t a l o s i f f o ) 6 ( v o s i r l 0 5 = w c , l , f p 5 1 = v o n v 1 = s m r ,f 1 = 0 z h k 0 t a v 5 2 + =0 9 ? b d k l a t s s o r c l e n n a h c - o t - l e n n a h c ) 7 ( v t c t a v 5 2 + =0 9 ? < y l p p u s r e w o p t n e r r u c y l p p u s ? v , + v+ i r o v 0 = k l c s = s c = n i d v 5 r o v 0 = t e s e r , + v t a v 5 2 + =60 2 m a e , c0 3
9 ps8462 02/22/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 ps395 precision 8-ch. 17v, spst switch w/8-bit serial decoded control r e t e m a r a pl o b m y ss n o i t i d n o c. n i m ) 1 ( . p y t ) 1 ( . x a m ) 1 ( s t i n u e c a f r e t n i l a t i g i d l a i r e s y c n e u q e r f k l c sf k l c s e , c 01 . 2z h m e m i t e l c y c ) 4 ( t h c t + l c 0 8 4 s n e m i t d a e l s c ) 4 ( t s s c 0 4 2 e m i t g a l s c ) 4 ( t 2 h s c 0 4 2 e m i t h g i h k l c s ) 4 ( t h c 0 9 1 e m i t w o l k l c s ) 4 ( t l c 0 9 1 e m i t p u t e s a t a d ) 4 ( t s d 0 0 28 3 e m i t d l o h a t a d ) 4 ( t h d 08 3 ? k l c s g n i l l a f r e t f a d i l a v a t a d n i d ) 4 ( t o d , t u o d f o % 0 1 o t k l c s f o % 0 5 c l f p 0 1 = t a v 5 2 + =0 5 1 e , c0 0 4 t u o d f o e m i t e s i r ) 4 ( t r d , + v f o % 0 7 o t + v f o % 0 2 c l f p 0 1 = 0 0 1 k l c s , n i d t a e m i t e s i r e l b a w o l l a ) 4 ( t r c s 2s n t u o d f o e m i t l l a f ) 4 ( t f d 0 0 3 m s k l c s , n i d t a e m i t l l a f e l b a w o l l a ) 4 ( t f c s 2 s n h t d i w e s l u p m u m i n i m t e s e rt w r t a v 5 2 + =5 0 1 timing characteristics - single +3v supply (v+ = 3.0v to +3.6v, v? = 0v, t a = t min to t max , unless otherwise noted. typical values are t a = +25c). notes: 1. the algebraic convention is used in this data sheet; the most negative value is shown in the minimum column. 2. d r on = r on(max) - r on(min) . on-resistance match between channels and on-resistance flatness are guaranteed only with specified voltages. flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the specified analog signal range. 3. leakage parameters are 100% tested at maximum rated hot temperature and guaranteed by correlation at room temp. 4. guaranteed by design. 5. leakage testing at single supply is guaranteed by testing with dual supplies. 6. see figure 5. off isolation = 20log10 v com /v no , v com = output. no = input to off switch. 7. between any two switches. see figure 2.
10 ps8462 02/22/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 ps395 precision 8-ch. 17v, spst switch w/8-bit serial decoded control detailed description basic operation the ps395?s interface can be thought of as an 8-bit shift register controlled by cs (figure 7). while cs is low, input data appearing at din is clocked into the shift register synchronously with sclk?s rising edge. the data is an 8-bit word, each bit controlling one of eight switches in the ps395. dout is the shift register?s output, with data appearing synchronously with sclk?s falling edge. data at dout is simply the input data delayed by eight clock cycles. when shifting the input data, d7 is the first bit in and out of the shift register. while shifting data, the switches remain in their pre- vious configuration. when the eight bits of data have been shifted in, cs is driven high. this updates the new switch configuration and inhibits further data from entering the shift register. transi- tions at din and sclk have no effect when cs is high, and dout holds the first input bit (d7) at its output. more or less than eight clock cycles can be entered during the cs low period. when this happens, the shift register will contain only the last eight serial data bits, regardless of when they were en- tered. on the rising edge of cs, all the switches will be set to the corresponding states. the ps395?s three-wire serial interface is compatible with spi?, qspi?, and microwire? standards. if inter-facing with a motorola processor serial interface, set cpol = 0. the ps395 is considered a slave device (figures 2 and 7). upon power-up, the shift register contains all zeros, and all switches are off. the latch that drives the analog switch is updated on the rising edge of cs, regardless of sclk?s state. this meets all the spi and qspi requirements. daisy chaining for a simple interface using several ps395s, ?daisy chain? the shift registers as shown in figure 5. the cs pins of all devices are connected together, and a stream of data is shifted through the ps395s in series. when cs is brought high, all switches are up- dated simultaneously. additional shift registers may be included anywhere in series with the ps395 data chain. t csh0 sclk din dout com out t css t cl t ds t dh t do t csh1 t off t csh2 t cll t ch figure 1. timing diagram
11 ps8462 02/22/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 ps395 precision 8-ch. 17v, spst switch w/8-bit serial decoded control 8x1 multiplexer to use the ps395 as an 8x1 multiplexer, connect all common pins together (com0?com7) to form the mux output; the mux inputs are no0?no7. the mux can be programmed normally, with only one channel se- lected for every eight clock pulses, or it can be programmed in a fast mode, where channel changing occurs on each clock pulse. in this mode, the channels are selected by sending a single high pulse (corresponding to the selected channel) at din, and a corre- sponding cs low pulse for every eight clock pulses. as this is clocked through the register by sclk, each switch sequences one channel at a time, starting with channel 7. dual, differential 4-channel multiplexer to use the ps395 as a dual (4x2) mux, connect com0?com3 together and connect com4?com7 together, forming the two outputs. the mux input pairs become no0/no4, no1/no5, no2/ no6, and no3/no7. the mux can be programmed normally, with only one differential channel selected for every eight clock pulses, or it can be pro- grammed in a fast mode, where channel changing occurs on each clock pulse. in fast mode, the channels are selected by sending two high pulses spaced four clock pulses apart (corresponding to the two selected channels) at din, and a corresponding cs low pulse for each of the first eight clock pulses. as this is clocked through the register by sclk, each switch sequences one differential channel at a time, starting with channel 7/0. after the first eight bits have been sent, subsequent channel sequencing can occur by repeating this sequence or, even faster, by sending only one din high pulse and one cs low pulse for each four clock pulses. spdt switches to use the ps395 as a quad, single-pole/double-throw (spdt) switch, connect com0 to no1, com2 to no3, com4 to no5, and com6 to no7, forming the four ?common? pins. program these four switches with pairs of instructions, as shown in spst truth table. reset function reset is the internal reset pin. it is usually connected to a logic signal or v+. drive reset low to open all switches and set the contents of the internal shift register to zero simultaneously. when reset is high, the part functions normally and dout is sourced from v+. reset must not be driven beyond v+ or gnd. sk so si i/o microwire port ps395 cs the dout-si connection is not required for writing to the ps395, but may be used for data-echo purposes. dout din sclk miso mosi sck i/o spi port ps395 cs the dout-miso connection is not required for writing to the ps395, but may be used for data-echo purposes. cpol = 0, cpha = 0 sclk din dout figure 2. connections for microwire figure 3. connections for spi and qspi figure 4. daisy-chained connection cs sclk sclk sclk din din din to other serial devices cs cs
12 ps8462 02/22/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 ps395 precision 8-ch. 17v, spst switch w/8-bit serial decoded control cs din sclk cs1 cs2 cs3 sclk sclk sclk din din din to other serial devices cs cs figure 5. addressable serial interface four clock pulses sw4 din sclk sw0 d4 d0 figure 6. differential multiplexer input control power-supply considerations overview the ps395 construction is typical of most cmos analog switches. it has three supply pins: v+, v-, and gnd. v+ and v- are used to drive the internal cmos switches and to set the limits of the ana- log voltage on any switch. reverse esd-protection diodes are internally connected between each analog signal pin and both v+ and v-. if any analog signal exceeds v+ or v-, one of these diodes will conduct. during normal operation, these (and other) reverse- biased esd diodes leak, forming the only current drawn from v+ or v-. virtually all the analog leakage current is through the esd diodes. although the esd diodes on a given signal pin are identical, and therefore fairly well balanced, they are reverse biased differently. each is biased by either v+ or v- and the analog signal. this means their leakages vary as the signal varies. the difference in the two diode leakages to the v+ and v- pins constitutes the analog sig- nal-path leakage current. all analog leakage current flows to the supply terminals, not to the other switch terminal. this is why both sides of a given switch can show leakage currents of either the same or opposite polarity. there is no connection between the analog signal paths and gnd. v+ and gnd power the internal logic and logic-level translators, and set both the input and output logic limits. the logic-level translators convert the logic levels to switched v+ and v- signals to drive the analog signal gates. this drive signal is the only con- nection between logic supplies (and signals) and the analog sup- plies. v+, and v- have esd-protection diodes to gnd. the logic- level inputs and output have esd protection to v+ and to gnd. the logic-level thresholds are cmos and ttl compatible when v+ is +5v. as v+ is raised, the threshold increases slightly. so when v+ reaches +12v, the threshold is about 3.1v; slightly above the ttl guaranteed high-level minimum of 2.8v, but still compat- ible with cmos outputs. bipolar supplies the ps395 operates with bipolar supplies between 3.0v and 8v. the v+ and v- supplies need not be symmetrical, but their sum cannot exceed the absolute maximum rating of 17v. do not connect the ps395 v+ to +3v and connect the logic-level pins to ttl logic-level signals. this exceeds the absolute maximum ratings and can damage the part and/or external circuits.
13 ps8462 02/22/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 ps395 precision 8-ch. 17v, spst switch w/8-bit serial decoded control addressable serial interface when several serial devices are configured as slaves, addressable by the processor, din pins of each decode logic individually con- trol cs of each slave device. when a slave is selected, its cs pin is driven low, data is shifted in, and cs is driven high to latch the data. typically, only on slave is addressed at a time. dout is not used. applications information multiplexers the ps395 can be used as a multiplexer. single supply the ps395 operates from a single supply between +3v and +16v when v- is connected to gnd. all of the bipolar precautions must be observed. figure 7. three-wire interface t iming d0 d0 d7 sclk din cs dout d6 d5 d4 data bits d3 d2 d1 d0 switches updated d7 d6 d5 d4 d3 d2 d1 data bits from previous data input t r a pe g n a r e r u t a r e p m e te g a k c a p - n i p b n c 5 9 3 s pc 0 7 + o t c 0p i d c i t s a l p w o r r a n 4 2 g w c 5 9 3 s pc 0 7 + o t c 0o s e d i w 4 2 g n e 5 9 3 s pc 0 5 8 + o t c 0 4 ?p i d c i t s a l p w o r r a n 4 2 g w e 5 9 3 s pc 0 5 8 + o t c 0 4 ?o s e d i w 4 2 high-frequency performance in 50 w systems, signal response is reasonably flat up to 50mhz (see typical operating characteristics). above 20mhz, the on- response has several minor peaks that are highly layout depen- dent. the problem is not turning the switch on, but turning it off. the off-state switch acts like a capacitor and passes higher frequencies with less attenuation. at 10mhz, off isolation is about -45db in 50 w systems, becoming worse (approximately 20db per decade) as frequency increases. higher circuit impedances also make off isolation worse. adjacent channel attenuation is about 3db above that of a bare ic socket, and is due entirely to capaci- tive coupling. pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com

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