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61312 sy 20120216-s00002 no.a2070-1/11 http://onsemi.com semiconductor components industries, llc, 2013 july, 2013 LE2416RLBXA overview the LE2416RLBXA is a 2-wire serial interface eeprom. it realizes high speed and a high level reliability by incorporating high performance cmos eeprom technology. this device is compatible with i 2 c memory protocol; therefore it is best suited for application that requires small-scale re-writable nonvolatile parameter memory. functions ? capacity: 16k bits (2k 8 bits) ? single supply voltage: 1.7v to 3.6v (to read) ? operating temperat ure: -40 to +85oc ? interface: two wire serial interface (i 2 c bus*) ? operating clock frequency: 400khz ? low power consumption : standby: 2 a (max) : active (read): 0.5ma (max) ? automatic page write mode: 16 bytes ? read mode: sequential read and random read ? erase/write cycles: 10 5 cycles (page write) ? data retention: 20 years ? pull-up resistance: 5k ? (typ.) on wp pin with a built-in pull-up resister ? high reliability: adopts proprietary symmetr ic memory array configuration (usp6947325) noise filters connected to scl and sda pins incorporates a feature to prohibit write operations under low voltage conditions. ? package : wlfcp6(0.80 1.20) ordering number : ena2070 cmos ic two wire serial interfaceeeprom (16k eeprom) * i 2 c bus is a trademark of philips corporation. * this product is licensed from silicon storage technology, inc. (usa).
LE2416RLBXA no.a2070-2/11 package dimensions unit : mm (typ) 3435 pin assignment pin descriptions pin.a1 v dd power supply pin.a2 v dd 2 power supply for wp pin pin.b1 wp write protect pin pin.b2 v ss ground pin.c1 scl serial clock input pin.c2 sda serial data input/output block diagram i/o buffer input buffer condition detector serial controller address generator x decoder serial-parallel converter y decoder & sense amp eeprom array high voltage generator write controller wp sda scl v dd 2 sanyo : wlfcp6(0.80x1.20) top view side view side view bottom view 0.8 1.2 0.33 max 0.08 (0.19) cb a 0.2 0.4 0.2 12 0.2 0.4 1 2 a top view bottom side view 0.80mm 1.20mm 0.33mm v dd 2 sda bc scl wp v dd v ss 1 2 a b c v dd 2 sda scl wp v dd v ss
LE2416RLBXA no.a2070-3/11 specifications absolute maximum ratings parameter symbol conditions ratings unit supply voltage -0.5 to +4.6 v dc input voltage -0.5 to v dd +0.5 v over-shoot voltage below 20ns -1.0 to v dd +1.0 v storage temperature tstg -65 to +150 c note: if an electrical stress exceeding the maximu m rating is applied, the device may be damaged. operating conditions parameter symbol conditions ratings unit to read 1.7 to 3.6 v operating supply voltage to write 1.8 to 3.6 v operating temperature -40 to +85 c dc electrical characteristics v dd =1.7v to 3.6v parameter symbol conditions min typ max unit supply current at reading i cc 1 f=400khz 0.5 ma supply current at writing i cc 2 f=400khz, t wc =5ms 5 ma standby current i sb wp = v dd 2 = v dd other pin=v dd or gnd 2 a input leakage current (scl) i li v in =gnd to v dd -2.0 +2.0 a output leakage current (sda) i lo v out =gnd to v dd -2.0 +2.0 a input low voltage v il v dd *0.2 v input low voltage (cmos) v ilc 0.2 v input high voltage v ih v dd *0.8 v input high voltage (cmos) v ihc v dd -0.2 v i ol =0.7ma, v dd =1.7v 0.2 v output low voltage v ol i ol =2.0ma, v dd =2.5v 0.4 v capacitance /ta=25 c, f=1mhz parameter symbol conditions max unit in/output pin capacitance c i/o v i/o =0v (sda) 6 pf input pin capacitance c i v in =0v (other than sda) 6 pf note: this parameter is sampled and not 100% tested. pull-up resistance (wp) /ta=-40 to 85 c parameter symbol conditions max. typ. max. unit pull-up resistance r resistance between wp to v dd 2 3.5 5.0 6.5 pf stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty.
LE2416RLBXA no.a2070-4/11 ac electric characteristics input pulse level 0.1 v dd to 0.9 v dd input pulse rise / fall time 20ns output detection voltage 0.5 v dd output load 50pf+pull up resistor 3.0k output load circuit v dd =1.7v to 3.6v parameter symbol min typ max unit slave mode scl clock frequency f scls 0 400 khz scl clock low time t low 1200 ns scl clock high time t high 600 ns sda output delay time t aa 100 900 ns sda data output hold time t dh 100 ns start condition setup time t su.sta 600 ns start condition hold time t hd.sta 600 ns data in setup time t su.dat 100 ns data in hold time t hd.dat 0 ns stop condition setup time t su.sto 600 ns scl sda rise time t r 300 ns scl sda fall time t f 300 ns bus release time t buf 1200 ns noise suppression time t sp 100 ns write cycle time t wc 5 ms r=3.0k v dd c=50pf sda
LE2416RLBXA no.a2070-5/11 bus timing write timing pin functions scl (serial clock input) pin the scl pin is a serial clock input pin that processes signals at the rising and falling edges of scl clock signals. the scl pin must be pulled up by a resistor to the v dd level and wired-ored with an open drain (or open collector) output device for use. sda (serial data input/output) pin the sda pin is used to transfer serial data to the input/output, and it consists of a signal input pin and n-channel transistor open drain output pin. like the scl pin, the sda pin must be pulled up by a resistor to the v dd level and wired-ored with an open drain (or open collector) output device for use. wp (write protect) pin when the wp pin is high, write protection is enabled, and writing into the 16k bit memory areas is prohibited. when the pin is low, writing is possible to all memory areas. r ead operations can be performed regardless of the wp pin status. it is resistance (typ. 5k ? ) between wp to v dd 2 v dd 2 (power supply for wp pin) pin v dd 2 pin is for the pull-up power supply to wp pin. voltag e impression of -0.5 to vdd+0.5v is permitted like other pins about the pin voltage. scl sda/in sda/out t f t su.sta t hd.sta t aa t high t low t hd.dat t hd.sta t dh t r t su.sto t sp t buf t sp scl sda d0 t wc write data acknowledge stop condition start condition
LE2416RLBXA no.a2070-6/11 functional description 1 start condition when the scl line is at the high level, the start condition is established by changing the sda line from high to low. the operation of the eeprom as a slave starts in the start condition. 2 stop condition when the scl line is at the high level, the stop condition is established by changing the sda line from low to high. when the device is set up for the read sequence, the read operation is suspended when th e stop condition is received, and the device is set to standby mode. when it is set up for the write sequence, the capture of the write data is ended when the stop condition is received, and the eeprom internal write operation is started. 3 data transfer data is transferred by changing the sd a line while the scl line is low. when the sda line is changed while the scl line is high, the resulting condition will be recognized as the start or stop condition. 4 acknowledge during data transfer, 8-bits are transferred in succession, and then in th e ninth clock cycle period the device on the system bus receiving the data sets the sda line to low, and sends the acknowledge signal indicating that the data has been received. the ackn owledge signal is not sent during an eeprom internal write operation. 5 device addressing for the purposes of communication, the master device in the system generates the start condition for the slave device. communication with a particular slave device is enabled by sending along the sda bus the device address, which is 7-bits long, and the read/write command code, which is 1 bit long, immediately following the start condition. the upper four bits of the device address are called the device code which, for this product, is fixed as ?1010.? two or more pieces cannot be connected about this ic because there is no slave address. scl sda t su.sta t hd.sta t su.sto start condition stop condition scl sda t su.dat t hd.dat t aa t dh 1 89 scl (eeprom input) sda (master output) sda (eeprom output) start condition acknowledge bit output 1 00 1 a10 a9 a8 r/w msb lsb le2416rlb device code device address word memory address
LE2416RLBXA no.a2070-7/11 6 eeprom write operation 6-1. byte writing when the eeprom receives the 7-bit device address an d write command code "0" after the start condition, it generates an acknowledge signal. after th is, if it receives 4-bit don? t-care bits and a 12-bit word address, generates an acknowledge signal, receives th e 8-bit writing data, and generates an ackn owledge signal when it receives the stop condition, the rewrite operation of the eeprom in the desi gnated memory address will st art. rewriting is completed in the t wc period after the stop condition. during an eeprom rewrite operation, no input is accepted and no acknowledge signals are generated. 6-2. page writing this product enables pages with up to 16 bytes to be written. the basic data transfer procedure is the same as for byte writing: following the start condition, the 7-bit device addr ess and write command code ?0,? word address (n), and data (n) are input in this order while confirming acknowledge ?0? every 9 bits. the page write mode is established if, after data (n) is input, the write data (n+1) is input w ithout inputting the stop condition. after this, the write data equivalent to the largest page size can be received by a continuous process of repeatin g the receiving of the 8-bit write data and generating the acknowledge signals. at the point when the write data (n+1) has been input, the lower 4 bits (a0-a3) of the word addresses are automatically incremented to form the (n +1) address. in this way, the write data can be successively input, and the word address on the page is incremente d each time the write data is input. if th e write data exceeds 16 bytes or the last address of the page is exceeded, the word address on the page is rolled over. write data will be input into the same address two or more times, but in such cases the write data that was input last will take effect. finally, the eeprom internal write operation corresp onding to the page size for which the wr ite data is received starts from the designated memory address when the stop condition is received. 6-3. acknowledge polling acknowledge polling is used to find out when the eeprom internal write operation is completed. when the stop condition is received and the eeprom starts rewriting, all opera tions are prohibited, and no response can be given to the signals sent by the master device. therefore, in orde r to find out when the eeprom internal write operation is completed, the start condition, device address and write command code are sent from the master device to the eeprom (slave device), and the respon se of the slave device is detected. in other words, if the slave device does not send the acknowledge signal, it means that the internal write operation is in progress; conversely, if it does send the acknowledge signal, it means that the internal write operation has been completed. sda start 1 0 1 0 a 10 a9 a8 w r/w no ack start 1 0 1 0 a 10 a9 a8 w r/w no ack start 1 0 1 0 a 10 a9 a8 w r/w ack write timing writing end write timing sda start 1 0 1 0 a 10 a9 a8 w r/w ack memory address a7 a6 a5 a4 a3 a2 a1 a0 ack d7 d6 d5 d4d3 d2 d1 d0 stop data ack sda start 1 0 1 0 a 10 a9 a8 w r/w ack memory address a7 a6 a5 a4 a3 a2 a1 a0 ack d7 d6 d5 d4d3 d2 d1 d0 stop data(n) ack d7 d6 d1 d0 data(n+1) ack ack d7 d6 d1 d0 d7 d6 d1 d0 d7 d6 d1 d0 ack d7 d6 d1 d0 ack data(n+x)
LE2416RLBXA no.a2070-8/11 7 eeprom read operations 7-1. current address reading the address equivalent to the memory address accessed last +1 is held as the internal address of the eeprom for both write* and read operations. theref ore, provided that the master device has recognized the position of the eeprom address pointer, data can be read from the memory address with the current address pointer without specifying the word address. as with writing, current address read ing involves receiving the 7-bit device address and read command code ?1? following the start condition, at which time the eeprom gene rates an acknowledge signal. after this, the 8-bit data of the (n+1) address is output serially starting with the highest bits. after the 8 bits have been output, by not sending an acknowledge signal and inputting the stop condition, the eeprom completes the read operation and is set to standby mode. if the previous read address is the last address, the address for the current address reading is rolled over to become address 0. *: if the write data is 1 or more bytes but less than 16 bytes, the current address after page writing is the address equivalen t to the number of bytes to be written in the specified word address +1. if the write data is 16 or more bytes, it is the designated word address. if th e last address (a3- a0=1111b) on the page has been designated by byte write as the word address, the first address (a3-a0=0000b) on the page serves as the internal address after writing. 7-2. random read random read is a mode in which a selected memory address is specified and its data is read. the address is specified by a dummy write input. first, when the eeprom receives the 7-bit device address and write command code "0" following the start condition, it generates an acknowledge signal. it then receives 4-bit don ?t-care bits and a 12-bit word address and generates an acknowledge signal. these operations ar e used to load the word address to the address counter in the eeprom. next, the start condition is input again, and the current read is performed. this generates the word address data that was input using the dummy write input. after the data is gene rated, if the stop condition is input without the input of an acknowledge signal, reading is completed, and standby mode is established. 7-3. sequential read in this mode, the data is read continuously, and sequential read operations can be performed with both current address read and random read. if, after the 8-bit data has been output, acknowledge ?0? is input and reading is continued without issuing the stop condition, the address is increm ented, and the data of the next address is output. if acknowledge ?0? continues to be input after the data has been output in this way, the data is successively output while the address is incremented. when the last address is reached, it is roll ed over to address 0, and the data continues to be read. as with current address read and random read, the operation is completed by inputting the stop condition without sending an acknowledge signal. sda start 1 0 1 0 a 10 a9 a8 r r/w ack device address ack d7 d6 d1 d0 stop data(n) ack d7 d6 d1 d0 data(n+1) ack d7 d6 d1 d0 data(n+2) d7 d6 d1 d0 data(n+x) ack sda start 1 0 1 0 a 10 a9 a8 r r/w ack device address no ack d7 d6 d5 d4d3 d2 d1 d0 stop data(n+1 address) sda start 1 0 1 0 a 10 a9 a8 w r/w ack memory address a7 a6 a5 a4 a3 a2 a1 a0 ack d7 d6 d1 d0 stop data(n) no ack start 1 0 1 0 a 10 a9 a8 r device address device address r/w ack dummy write current read
LE2416RLBXA no.a2070-9/11 application notes 1) software reset function software reset (start condition + 9 dummy clock cycles + st art condition), shown in the figure below, is executed in order to avoid erroneous operation after power-on and to reset while the command input sequence. during the dummy clock input period, the sda bus must be opened (set to high by a pull-up resistor). since it is possible for the ack output and read data to be output from the eeprom during the dummy clock period, forcibly entering h will result in an overcurrent flow. note that this software reset function does not work during the internal write cycle. 2) pull-up resistor of sda pin due to the demands of the i 2 c bus protocol function, the sda pin must be connected to a pull-up resistor (with a resistance from several k to several tens of k ) without fail. the appropriate value must be selected for this resistance (r pu ) on the basis of the v il and i il of the microcontroller and other devices controlling this product as well as the v ol ?i ol characteristics of the product. generally, when the resistance is too high, the operating frequency will be restricted; conversely, when it is too low, the operating current consumption will increase. r pu maximum resistance the maximum resistance must be set in such a way that the bus potential, which is determined by the sum total (i l ) of the input leaks of the devices connected to the sda bus and by r pu , can completely satisfy the input high level (v ih min) of the microcontroller and eeprom. however, a resistance value that satisfies sda rise time t r and fall time t f must be set. r pu maximum value = (v dd - v ih )/i l example: when v dd =2.5v and i l = 2 a r pu maximum value = (2.5v ? 2.5v 0.8)/2 a = 250k r pu minimum value a resistance corresponding to the low-level output voltage (v ol max) of eeprom must be set. r pu minimum value = (v dd ? v ol )/i ol example: when v dd =2.5v, v ol = 0.4v and i ol = 1ma r pu minimum value = (2.5v ? 0.4)/1ma = 2.1k recommended r pu setting r pu is set to strike a good balance between the operating frequency requirements and power consumption. if it is assumed that the sda load capacitance is 50pf and the sda output data strobe time is 500ns, r pu will be about r pu = 500ns/50pf = 10k . scl sda 1 2 89 dummy clock 9 start condition start condition sda r pu c bus i l eeprom i l master device
LE2416RLBXA no.a2070-10/11 3) notes on write protect operation this product prohibits all 16k bit writing when the wp pin is high. to ensure full write protection, the wp is set high for all periods from the start condition to the stop condition, and the conditions below must be satisfied. v dd =1.7 to 3.6v item symbol min typ max unit wp setup time t su.wp 600 ns wp hold time t hd.wp 600 ns 4) precautions when turning on the power this product contains a power-on reset circuit for prev enting the inadvertent writing of data when the power is turned on. the following conditions must be met in order to ensure stable operation of this circuit. no data guarantees are given in the event of an instantaneous power failure during the internal write operation. v dd =1.7 to 3.6v item symbol min typ max unit power rise time t rise 100 ms power off time t off 10 ms power bottom voltage v bot 0.2 v notes: 1) the sda pin must be set to high and the scl pin to low or high. 2) steps must be taken to ensure that the sda and scl pins are not placed in a high-impedance state. v dd 0v t off t rise v bot scl sda t su.wp t hd.wp wp start condition stop condition
LE2416RLBXA no.a2070-11/11 5) noise filter for the scl and sda pins this product contains a filter circuit for eliminating noise at the scl and sda pins. pulses of 100ns or less are not recognized because of this function. 6) function to inhibit writing when supply voltage is low this product contains a supply voltage monitoring circu it that inhibits inadvertent writing below the guaranteed operating supply voltage range. the data is protected by ensuring that write operations are not started at voltages (typ.) of 1.3v and below. ps on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability ar ising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorize d for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other appli cation in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws a nd is not for resale in any manner.

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