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40414hk 20140325-s00001 no.a2324-1/15 semiconductor components industries, llc, 2014 april, 2014 rev.1.10 http://onsemi.com LE24163LBXA overview the LE24163LBXA (hereinafter referred to as ?this devi ce?) is two-wire serial in terface eeprom (electrically erasable and programmable ro m). this device realizes high speed and a high level reliability by our company?s high performance cmos eeprom technology. this device is compatible with i 2 c memory protocol, therefore it is best suited for application that requires re-writable nonvolatile parameter memory. function ? capacity: 16k bits (2k x 8 bits) ? single supply voltage: 1.7v to 3.6v (read) ? operating temperature: ? 40oc to +85oc ? interface: two wire serial interface (i 2 c bus*) ? operating clock frequency: 400khz ? low power consumption ? : standby: 2 a (max.) : active (read): 0.5 ma (max.) ? automatic page write mode: 16 bytes ? read mode: sequential read and random read ? erase/write cycles: 10 5 cycles (page write) ? data retention: 20 years ? shipped data pattern: ffh ? high reliability: adopts proprietary symmetric memory array configuration (usp6947325) hardware write protect feature noise filters connected to scl and sda pins incorporates a feature to prohibit write operations under low voltage conditions. specifications absolute maximum ratings at ta = 25 ? c parameter symbol conditions ratings unit supply voltage ? 0.5 to +4.6 v dc input voltage ? 0.5 to vcc+0.5 v over-shoot voltage ? 1.0 to vcc+1.0 v storage temperature tstg ? 65 to +150 ? c cmos lsi 16 kb i 2 c cmos serial eeprom ordering information see detailed ordering and shipping informa tion on page 15 of this data sheet. * this product is licensed from silicon storage technology, inc. (usa). * i 2 c bus is a trademark of philips corporation. stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should n ot be assumed, damage may occur and reliability may be affected. orderin g numbe r : ena2324 wlcsp5, 1.20x0.80
LE24163LBXA no.a2324-2/15 recommended operating conditions parameter symbol conditions ratings unit min typ max operating supply voltage (read) 1.7 3.6 v operating supply voltage (write) 1.8 3.6 v operating temperature ? 40 +85 ? c dc electrical characteristics parameter symbol conditions spec. unit min typ max supply current at reading i cc 1 f=400khz, vdd = vdd max 0.5 ma supply current at writing i cc 2 f=400khz, twc=5ms, vdd = vdd max 5 ma standby current i sb v in =vdd or gnd 2 a input leakage current i li v in = gnd to vdd, vdd = vdd max ? 2.0 +2.0 a output leakage current i lo v in = gnd to vdd, vdd = vdd max ? 2.0 +2.0 a input low voltage v il vdd ? 0.2 v input high voltage v ih vdd ? 0.8 v output low voltage v ol i ol =0.7ma, vdd=1.7v 0.2 v i ol =2.0ma, vdd=2.5v 0.4 v capacitance at ta = 25 ? c, f=1mhz parameter symbol conditions max unit in/output pin capacitance c i/o v i/o =0v (sda) 6 pf input pin capacitance c i v in =0v 6 pf functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresses beyond the recomme nded operating ranges limits may affect device r eliab ility.
LE24163LBXA no.a2324-3/15 ac electric characteristics input pulse level 0.1 ? vcc to 0.9 ? vcc input pulse rise / fall time 20ns output detection voltage 0.5 ? vcc output load 50pf + pull up resistor 3.0k ? parameter symbol spec. unit min typ max slave mode scl clock frequency f scls 0 400 khz scl clock low time t low 1200 ns scl clock high time t high 600 ns sda output delay time t aa 100 900 ns sda data output hold time t dh 100 ns start condition setup time t su.sta 600 ns start condition hold time t hd.sta 600 ns data in setup time t su.dat 100 ns data in hold time t hd.dat 0 ns stop condition setup time t su.sto 600 ns scl sda rise time t r 300 ns scl sda fall time t f 300 ns bus release time t buf 1200 ns noise suppression time t sp 100 ns write time t wc 5ms r=3.0k ? sda vcc c=50pf output load circuit product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product per formance may not be indicated by the electrical characteristics if operated under different conditions.
LE24163LBXA no.a2324-4/15 package dimensions unit : mm pin assignment pin descriptions a1 wp write protect a2 vdd power supply b1 scl serial clock input b2 - - c1 sda serial data in/output c2 vss ground wlcsp5, 1.20x0.80 case 567gs issue o seating plane 0.05 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. coplanarity applies to spherical crowns of solder balls. 2x dim a min max ??? millimeters a1 d 1.20 bsc e b 0.15 0.25 e 0.40 bsc 0.33 e d a b pin a1 reference e/2 a 0.05 b c 0.03 c 0.08 c 5x b 12 c b a 0.08 c a a1 a2 c 0.03 0.13 0.80 bsc pitch 0.20 5x dimensions: millimeters *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.40 0.40 0.05 c 2x top view side view bottom view note 3 a2 0.20 ref recommended a1 package outline e pitch e ball side view top view 1 c b 2 a vdd vss wp sda scl 1 a b c 2 vdd vss wp sda scl
LE24163LBXA no.a2324-5/15 block diagram eeprom array x decoder hi g h volta g e g enerator serial-parallel converter address generator y decoder & sense amp condition detector i/o buffer input buffer serial controller scl sda write controller wp
LE24163LBXA no.a2324-6/15 bus timing write timing pin function scl (serial clock) the scl signal is used to control serial input data timi ng. the scl is used to latch input data synchronously at the rising edge and read output dat a synchronously at the falling edge. sda (serial input / output data) the sda pin is bidirectional for serial data transfer. it is an open-drain structure t hat needs to be pulled up by resistor. wp (write protect) when the wp input is high, write protection is enabl ed. when wp input is eit her low or floating, write protection is disabled. the read operation is always activated irrespective of the wp pin status. t buf t su.sto t r scl sda/in sda/out t su.sta t hd.dat t high t low t su.dat t dh t aa t f t hd.sta t sp t sp write data acknowledge stop condition start condition t wc scl sda d0
LE24163LBXA no.a2324-7/15 functional description the device supports the i 2 c protocol. any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to a receiver. the devic e that controls the data transfer is known as the bus master, and the other as the slave device. 1) start condition a start condition needs to start the eeprom operation, it is to set falling edge of the sda while the scl is stable in the high status. 2) stop condition a start condition is identified by rising edge of the sd a signal while the scl is stable in the high status. the device becomes the standby mode from a read oper ation by a stop condition. in a write sequence, a stop condition is trigger to terminate the write data input s and it is trigger to start the internal write cycle. after the internally write cycle time which is sp ecified as twc, the devic e enters a standby mode. 3) data input during data input, the device latches the sda on the ri sing edge of the scl. for correct the operation, the sda must be stable during the rising edge of the scl. stop condition start condition scl sda t su.sta t hd.sta t su.sto scl sda t su.dat t hd.dat
LE24163LBXA no.a2324-8/15 4) acknowledge bit (ack) the acknowledge bit is used to indicate a successful byte data transfer. the receiver sends a zero to acknowledge that it has received each word (device code, slave address etc) from the transmitter. 5) device addressing to transmit between the bus master and slave device (eeprom ), the master must send a start condition to the eeprom. the device address word of the eeprom consists of 7-bit device address code and 1-bit read/write code. by sending these, it becomes possible to communicate between the bus master and the eeprom. the upper 4-bit of the devic e address word are called the device code, the device code of the eeprom uses 1010b fixed code. this devic e does not have the slave address. the 8 th bit is the read/write bit. the bit is set to 1 for read operation and 0 for write operation. if a match occurs on the device code, the corresponding dev ice gives an acknowledgement on sda during the 9 th bit time. if device dose not match the device code, it deselects itself from the bus, and goes into the standby mode. use the random read command when you execute reading after the slave device was switched. 1 0 1 0 a10 a9 a8 r/w device code memory address msb lsb device address word acknowledge bit output start condition 1 scl ( from transmitter ) sda (from transmitter) sda (eeprom output) 8 9 t aa t dh
LE24163LBXA no.a2324-9/15 6) eeprom write operation 6)-1. byte write the write operation requires an 8-bit device address word with the 8 th bit = 0 (write). then the eeprom sends acknowledgement 0 at the 9 th clock cycle. after these, the eeprom receives 8-bit memory address word, and the eeprom outputs acknowledgement 0 at receipt of this memo ry address. then the eeprom receives 8-bit write data, the eeprom outputs acknowledgement 0 af ter receipt of write data. if the eeprom receives a stop condition, the eeprom enters an internally timed (twc) write cycle and terminates receipt of inputs unt il completion of the write cycle. 6)-2. page write the page write allows up to 16 bytes to be written in a single write cycle. the page write is the same sequence as the byte write except for inputting the mo re write data. the page write is initiated by a start condition, device code, device address, memo ry address(n) and write data(n) with every 9 th bit acknowledgement. the device enters the page write operation if this device receives more write data(n+1) instead of receiving a stop condition. the page address (a0 to a3) bits are automatically incremented on receiving write data(n+ 1). the device can continue to rece ive write data up to 16 bytes. if the page address bits reaches the last address of the page, the page addres s bits will roll over to the first address of the same page and previous write data will be overwritten. after these, if the device receives a stop condition, the device enters an internally timed (twc(n+x)) write cycle and terminates receipt of inputs until completion of the write cycle. access from master device sda memory addres 0 1 0 1 w start ac ac ac sto p a9 a8 d7d6d5d4d3d2d1 d0 data r/w a 10 a7 a6 a5 a4 a3 a2 a1 a0 access from master device s d a 0 1 0 1 w start a c k data(n) r/w a c k memory address(n) a 10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7d6d5d4d3d2d1d0 ack stop d7 d6 ~ d1 d0 ack ack data(n+x) a c k ack d7d6 ~ d1d0 d7d6 ~ d1 d0 d7 d6 ~ d1 d0 d7 d6 ~ d1 d0 data(n+1) ack ack
LE24163LBXA no.a2324-10/15 6)-3. acknowledge polling the acknowledge polling operation is used to show if t he eeprom is in an internally timed write cycle or not. this operation is initiated by the stop conditi on after inputting write data. this requires the 8-bit device address word with the 8 th bit = 0 (write) following the start condition during an internally timed write cycle. if the eeprom is busy with the internal wr ite cycle, no acknowledge will be returned. if the eeprom has terminated the internal wr ite cycle, it responds with an acknowledge. the terminated write cycle of the eeprom can be known by this operation. access from master device during write start no ack sda start no ack during write start a c k no write 0 1 0 a9 1 w a 1 0 a8 0 1 0 1 w 0 1 0 1w a9 a 1 0 a8 a9 a 1 0 a8 r/w r/w r/w
LE24163LBXA no.a2324-11/15 7) eeprom read operation 7)-1. current address read the device has an internal address counter. it maintains that last address during the last read or write operation, with incremented by one. the current address read accesses the address kept by the internal address counter. after receiving a start conditi on and the device address word with the 8 th bit = 1 (read), the eeprom outputs the 8-bit current address data from following ac knowledgement 0. if the eeprom receives acknowledgement 1 and a following stop cond ition, the eeprom stops the read operation and is returned to a standby mode. in case the eeprom has accessed the last address of the last page at previous read operation, t he current address will roll over and return s to zero address. in case eeprom has accessed tha last address of the last page at previous write operat ion, the current address roll over within page addressing and returns to the first address in the same page. the current address is valid while power is on. after power on, the current address will be reset (all 0). note: after the page write operation, the current addre ss is the specified memory address in the last page write, if the write data is more than 16-bytes. 7)-2. random read the random read requires a dummy write to set read address. the eeprom receives a start condition and the device address word with the 8 th bit = 0 (write), the memo ry address. the eeprom outputs acknowledgement 0 after receiving memory address t hen enters a current address read with receiving a start condition. the eeprom output s the read data of the address whic h was defined in the dummy write operation. after receiving no ac knowledgement and a following st op condition, the eeprom stops the random read operation and returns to a standby mode. access from master device device address a c k no ack sto p data (n+1) r/w s d a 0 1 0 a9 1 r start a8 d7 d6 d5 d4 d3 d2 d1 d0 a 10 access from master device ack dummy write device address memory address ack data(n) device address a c k no ack sto p current read start sda 0 1 0 1 w a 10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 1 0 1r start d7 d6 ~ d1d0 a 10 a9 a8 r/w r/w
LE24163LBXA no.a2324-12/15 7)-3. sequential read the sequential read operation is initiated by eit her a current address read or random read. if the eeprom receives acknowledgement 0 after 8-bit read data, the re ad address is incr emented and the next 8-bit read data outputs. the current address will not roll over and returns address zero if it reaches the last address of the last page. please don?t access it except the valid addre ss range (000h ~ 7ffh). the sequential read is terminated if the eeprom receives no acknowledgement and a following stop condition. access from master device d7 d6 ~ d1 d0 data(n) s d a device address 0 1 0 1 a8 r start a c k no ack sto p data(n+1) data(n+2) data(n+x) r/w a9 a 10 d7 d6 ~ d1 d0 ack d7 d6 ~ d1 d0 ack d7 d6 ~ d1 d0 a c k
LE24163LBXA no.a2324-13/15 master device eeprom sda c bus r pu i l i l application notes 1) pull-up resistor of sda pin due to the demands of the i 2 c bus protocol function, the sda pin mu st be connected to a pull-up resistor (with a resistance from several k ? to several tens of k ? ) without fail. the appropriate value must be selected for this resistance (r pu ) on the basis of the v il and i il of the microcontroller and other devices controlling this product as well as the v ol ? i ol characteristics of the product. generally, when the resistance is too high, the operating frequency will be restricted; conversely, when it is too low, the operating current consumption will increase. r pu maximum value the maximum resistance must be set in such a way that the bus potential, which is determined by the sum total (i l ) of the input leaks of the devices connected to the sda bus and by r pu , can completely satisfy the input high level (v ih min) of the microcontroller and eeprom. however, a resistance value that satisfies sda rise time tr and fall time tf must be set. r pu maximum value = (vcc - v ih )/i l example: when vcc = 3.0 v and i l = 2 ? a r pu maximum value = (3.0 v ? 3.0 v ? 0.8)/2 ? a = 300 k ? r pu minimum value a resistance corresponding to the low-level output voltage (v ol max) of eeprom must be set. r pu minimum value = (vcc ? v ol )/i ol example: when vcc = 3.0 v, v ol = 0.4 v and i ol = 1 ma r pu minimum value = (3.0 v ? 0.4)/1 ma = 2.6 k ? recommended r pu setting r pu is set to strike a good balance between the operating frequency requirements and power consumption. if it is assumed that the sda load ca pacitance is 50 pf and the sda output data strobe time is 500 ns, r pu will be about r pu = 500 ns/50 pf = 10 k ? .
LE24163LBXA no.a2324-14/15 2) notes on write protect operation this product prohibits all memory array writing when the wp pin is high. to ensure full write protection, the wp is set high for all periods from the start cond ition to the stop condition, and the conditions below must be satisfied. symbol parameter spec. unit min. typ. max. t su.wp wp setup time 600 ? ? ns t hd.wp wp hold time 600 ? ? ns 3) noise filter for the scl and sda pins this product contains a filter circuit for eliminati ng noise at the scl and sda pins. pulses of 100 ns or less are not recognized because of this function. 4) function to inhibit writing when supply voltage is low this product contains a supply voltage monitoring ci rcuit that inhibits inadvertent writing below the guaranteed operating supply voltage range. the data is protected by ensuring that write operations are not started at voltages (typ.) of 1.3 v and below. stop condition start condition scl sda t su.wp t hd.wp wp
LE24163LBXA ps no.a2324-15/15 marking information LE24163LBXA wlcsp5, 1.20x0.80 ordering information device package shipping (qty / packing) LE24163LBXA-sh wlcsp5, 1.20x0.80 (pb-free / halogen free) 5000 / tape & reel on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability ar ising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorize d for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other appli cation in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws a nd is not for resale in any manner. part id: 163 lot number: 3digits 1 6 3 lot

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