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| 1 datasheet 19mhz radiation hardened 40v dual rail-to-rail input-output, low-power operational amplifier ISL70244SEH the ISL70244SEH features two low-power amplifiers optimized to provide maximum dynamic range. these op amps feature a unique combination of rail-to-rail operation on the input and output as well as a slew enhanced front end that provides ultra fast slew rates positively proportional to a given step size; thereby increasing accuracy under transient conditions, whether it?s periodic or momentary. they also offer low power, low offset voltage, and low temperature drift, making it ideal for applications requiring both high dc accuracy and ac performance. with <5s recovery for single event transients (set) (let th = 86.4mev?cm 2 /mg), the number of filtering components needed is drastically reduced. the ISL70244SEH is also immune to single event latch-up as it is fabricated in intersil?s proprietary pr40 silicon on insulator (soi) process. they are designed to operate over a single supply range of 2.7v to 40v or a split supply voltage range of 1.35v to 20v. applications for these amplifiers include precision instrumentation, data acquis ition, precision power supply controls, and process controls. the ISL70244SEH is available in a 10 ld hermetic ceramic flatpack that operates over th e temperature range of -55c to +125c. related literature ? ISL70244SEH evaluation board user?s guide an1888 ? ISL70244SEH single event effects report an1961 ? ISL70244SEH smd 5962-13248 ? ISL70244SEH radiation test report features ? electrically screened to dla smd # 5962-13248 acceptance tested to 50krad(si) (ldr) wafer-by-wafer ? <5s recovery from set (let th = 86.4mev?cm 2 /mg) ? unity gain stable ? rail-to-rail input and output ? wide gainbandwidth product . . . . . . . . . . . . . . . . . . . . 19mhz ? wide single and dual supply range. . . . . . . . 2.7v to 40v max ? low input offset voltage . . . . . . . . . . . . .400v (+25c, max) ? low current consumption (per amplifier) . . . . . . . 1.2ma, typ ? no phase reversal with input overdrive ?slew rate - large signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60v/s ? operating temperature range. . . . . . . . . . . .-55c to +125c ? radiation tolerance - high dose rate (50-300rad(si)/s). . . . . . . . . . . 300krad(si) - low dose rate (0.01rad(si)/s) . . . . . . . . . . . . 100krad(si)* - sel/seb let th (v s = 19v) . . . . . . . . . 86.4mev?cm 2 /mg * product capability established by initial characterization. applications ? precision instruments ? active filter blocks ? data acquisition ?power supply control ? process control figure 1. typical application: single-supply, high-side current sense amplifier figure 2. typical single event transient duration at + 25c let = 60 mev ? cm 2 / mg in unity gain (v s = 18v) + - l o a d v ref v out + - ISL70244SEH r 3 r 4 r 1 r 2 rs r 1 = r 3 = 10k r 2 = r 4 = 100k gain = r 2 /r 1 = 10 v out = v ref + gain(i load * r s ) i load v+ v- v src v+ = 36v; v- = 0v; v ref = 18v 0 200 400 600 800 1000 1200 1400 0 0.2 0.4 0.8 1.0 1.2 1.4 1.6 1.8 2.0 transient duration (s) frequency 5 1 september 22, 2014 fn8592.0 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2014. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
ISL70244SEH 2 fn8592.0 september 22, 2014 submit document feedback pin configuration ISL70244SEH (10 ld flatpack) top view 10 9 8 7 6 2 3 4 5 1 out a -in a +in a nc v - v + out b -in b +in b lid + - + - pin descriptions pin number pin name equivalent esd circuit description 5v - circuit 3 negative power supply 7+in b circuit 1 amplifier b noninverting input 8-in b circuit 1 amplifier b inverting input 9out b circuit 2 amplifier b output 10 v + circuit 3 positive power supply 1out a circuit 2 amplifier a output 2-in a circuit 1 amplifier a inverting input 4 nc - this pin is not electrically connected internally. 3+in a circuit 1 amplifier a noninverting input 6 lid na unbiased, tied to package lid v + v - out circuit 2 circuit 1 v + v - circuit 3 capacitively triggered esd clamp -in v + v - +in 600 600 ISL70244SEH 3 fn8592.0 september 22, 2014 submit document feedback ordering information ordering/smd number ( note 2 ) part number ( note 1 ) temp range (c) package (rohs compliant) pkg. dwg. # 5962f1324801vxc ISL70244SEHvf -55 to +125 10 ld flatpack k10.a 5962f1324801v9a ISL70244SEHvx -55 to +125 die ISL70244SEHf/proto ISL70244SEHf/proto -55 to +125 10 ld flatpack k10.a ISL70244SEHf/sample ISL70244SEHvx/sample -55 to +125 die ISL70244SEHev1z ISL70244SEHev1z evaluation board notes: 1. these intersil pb-free hermetic packaged products employ 100% au plate - e4 termination finish, which is rohs compliant and c ompatible with both snpb and pb-free soldering operations. 2. specifications for rad hard qml devices are controlled by the defense logistics agency land and maritime (dla). the smd numbe rs listed in the ?ordering information? table must be used when ordering. ISL70244SEH 4 fn8592.0 september 22, 2014 submit document feedback absolute maximum ratings thermal information maximum supply voltage differential (v + to v - ) . . . . . . . . . . . . . . . . . . . 42v maximum supply voltage differential (v + to v - ) ( note 5 ) . . . . . . . . . . . 38v maximum differential input current . . . . . . . . . . . . . . . . . . . . . . . . . . 20ma maximum differential input voltage . . . . . . . . 42v or v - - 0.5v to v + + 0.5v min/max input voltage . . . . . . . . . . . . . . . . . . . . 42v or v - - 0.5v to v + + 0.5v max/min input current for input voltage >v + or ISL70244SEH 6 fn8592.0 september 22, 2014 submit document feedback psrr power supply rejection ratio v - = -2.5v; v + = 4.5v to 2.5v; v + = 2.5v; v - = -4.5v to -2.5v - 123 - db v - = -2.5v; v + = 4.5v to 2.5v; v + = 2.5v; v - = -4.5v to -2.5v t a = +125c, t a = +25c or t a = +25c with hdr/ldr rad. 80 -- db v - = -2.5v; v + = 4.5v to 2.5v; v + = 2.5v; v - = -4.5v to -2.5v t a = -55c 70 -- db a vol open-loop gain r l = 10k to ground - 118 - db r l = 10k to ground t a = +125c, t a = +25c or t a = +25c with hdr/ldr rad. 90 -- db r l = 10k to ground t a = -55c 80 -- db v oh output voltage high (v out to v + )r l = no load - 15 85 mv r l = 10k -23 105 mv r l = 600 -- 400 mv v ol output voltage low (v out to v - )r l = no load - 11 85 mv r l = 10k -18 105 mv r l = 600 -- 400 mv i s supply current/amplifier unity gain - 1.2 1.5 ma t a = +25c post hdr/ldr rad - - 1.5 ma t a = -55c to +125c -1.7 2.0 ma ac specifications gbwp gain bandwidth product a v = 1, r l = 10k 15 17 - mhz e n voltage noise density f = 10khz - 12.3 - nv/ hz i n current noise density f = 10khz - 0.313 - pa/ hz sr large signal slew rate a v = 1, r l = 10k ?? v o = 3v p-p -35- v/s electrical specifications v s = 1.35v, v cm = v o = 0v, r l = open, t a = +25c, unless otherwise noted. boldface limits apply over the operating temperature range, -55c to +125c; over a total ionizing dose of 300krad(si) with exposure of a high dose rate of 50 to 300rad(si)/s or over a total ionizing dose of 50krad(s i) with exposure at a low dose rate of <10mrad(si)/s. parameter description test conditions min ( note 6 )typ max ( note 6 )units v os offset voltage v cm = 0v -400 51 400 v v cm = v + to v - -500 80 500 v ? v os input offset channel-to-channel match v cm = v + -79 800 v v cm = v - 119 800 v i b input bias current v cm = 0v -375 110 375 na v cm = v + -375 180 375 na v cm = v - -565 225 565 na v cm = v + - 0.5v -375 180 375 na v cm = v - + 0.5v -565 223 565 na electrical specifications v s = 2.5v, v cm = v o = 0v, r l = open, t a = +25c, unless otherwise noted. boldface limits apply across the operating temperature range, -55c to +125c; over a total ionizing dose of 300krad(si) with exposure of a high dose rate of 50 to 300rad(si)/s or over a total ionizing dose of 50krad(s i) with exposure at a low dose rate of <10mrad(si)/s. (continued) parameter description test conditions min ( note 6 )typ max ( note 6 )units ISL70244SEH 7 fn8592.0 september 22, 2014 submit document feedback i os input offset current v cm = v + to v - -30 0 30 na -50 0 50 na v cmir common mode input voltage range v - - v + v v oh output voltage high (v out to v + )r l = no load - 14 50 mv r l = 10k -19 70 mv v ol output voltage low (v out to v - )r l = no load - 10 50 mv r l = 10k -14 70 mv i s supply current/amplifier unity gain - 1.1 1.5 ma t a = +25c post hdr/ldr rad - - 1.5 ma t a = -55c to +125c -1.6 2.0 ma ac specifications gbwp gain bandwidth product a v = 1, r l = 10k 10 15 - mhz e n voltage noise density f = 10khz - 12 - nv/ hz i n current noise density f = 10khz - 0.312 - pa/ hz note: 6. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. electrical specifications v s = 1.35v, v cm = v o = 0v, r l = open, t a = +25c, unless otherwise noted. boldface limits apply over the operating temperature range, -55c to +125c; over a total ionizing dose of 300krad(si) with exposure of a high dose rate of 50 to 300rad(si)/s or over a total ionizing dose of 50krad(s i) with exposure at a low dose rate of <10mrad(si)/s. (continued) parameter description test conditions min ( note 6 )typ max ( note 6 )units ISL70244SEH 8 fn8592.0 september 22, 2014 submit document feedback typical performance curves unless otherwise specified, v s 18v, v cm = 0, v o = 0v, t a = +25c. figure 3. offset voltage vs common mode voltage figure 4. ibias vs common mode voltage figure 5. ibias vs temperature (v s = 18v) figure 6. ibias vs temperature (v s = 2.5v) figure 7. ibias vs temperature, (v s = 1.5v ) figure 8. ios vs temperature (v s = 18v) -60 -40 -20 0 20 40 60 80 100 120 -20 -15 -10 -5 0 5 10 15 20 common mode voltage (v) offset voltage (v) -300 -200 -100 0 100 200 300 -20 -15 -10 -5 0 5 10 15 20 common mode voltage (v) ibias (na) 0 50 100 150 200 250 300 -100 -50 0 50 100 150 temperature (c) ib+ ib- current (na) 0 50 100 150 200 250 -100 -50 0 50 100 150 temperature (c) ib+ ib- current (na) 0 50 100 150 200 250 300 -100 -50 0 50 100 150 temperature (c) current (na) ib+ ib- 0 0.5 1.0 1.5 2.0 2.5 -100 -50 0 50 100 150 temperature (c) current (na) ios ISL70244SEH 9 fn8592.0 september 22, 2014 submit document feedback figure 9. ios vs temperature (v s = 2.5v) figure 10. ios vs temperature (v s = 1.5v) figure 11. vos vs temperature (v s = 18v) figure 12. vos vs temperature (v s = 2.5v) figure 13. vos vs temperature (v s = 1.5v) figure 14. avol vs temper ature vs supply voltage typical performance curves unless otherwise specified, v s 18v, v cm = 0, v o = 0v, t a = +25c. (continued) 0 0.5 1.0 1.5 2.0 2.5 -100 -50 0 50 100 150 temperature (c) ios current (na) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 -100 -50 0 50 100 150 temperature (c) ios current (na) 0 10 20 30 40 50 60 70 -100 -50 0 50 100 150 temperature (c) voltage (v) vos 0 10 20 30 40 50 60 70 -100 -50 0 50 100 150 temperature (c) voltage (v) vos 0 10 20 30 40 50 -100 -50 0 50 100 150 temperature (c) vos voltage (v) 100 105 110 115 120 125 130 135 -75 -25 25 75 125 temperature (c) 1.5v avol (db) 18v 2.5v ISL70244SEH 10 fn8592.0 september 22, 2014 submit document feedback figure 15. negative supply current vs supply voltage figure 16. positive supply current vs supply voltage figure 17. psrr+ vs temperature vs supply voltage figure 18. psrr- vs temperature vs supply voltage figure 19. cmrr vs temperature vs supply voltage figure 20. short circuit current vs temperature typical performance curves unless otherwise specified, v s 18v, v cm = 0, v o = 0v, t a = +25c. (continued) -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0 10 20 30 40 supply differential (v + to v - ) (v) current (ma) +125c -55c +25c 0.0 0.5 1.0 1.5 2.0 2.5 0 10 20 30 40 supply differential (v + to v - ) (v) current (ma) -55c +125c +25c 100 105 110 115 120 125 130 135 -75 -25 25 75 125 temperature (c) 18v 2.5v 1.5v psrr+ (db) 100 105 110 115 120 125 130 135 -75 -25 25 75 125 temperature (c) psrr- (db) 18v 2.5v 1.5v 40 50 60 70 80 90 100 110 120 -75 -25 25 75 125 temperature (c) cmrr (db) 18v 2.5v 1.5v 0 10 20 30 40 50 60 70 -75 -25 25 75 125 temperature (c) current (ma) 5v 15v 18v 2.5v 1.5v ISL70244SEH 11 fn8592.0 september 22, 2014 submit document feedback figure 21. (v s = 1.5v) v oh vs temperature figure 22. (v s = 2.5v) v oh vs temperature figure 23. (v s = 18v) v oh vs temperature figure 24. (v s = 1.5v) v ol vs temperature figure 25. (v s = 2.5v) v ol vs temperature figure 26. (v s = 18v) v ol vs temperature typical performance curves unless otherwise specified, v s 18v, v cm = 0, v o = 0v, t a = +25c. (continued) 0 10 20 30 40 50 -75 -25 25 75 125 175 temperature (c) (v s+ - v out ) (mv) r l = 2k r l = open r l = 10k 0 10 20 30 40 50 60 70 -75 -25 25 75 125 175 (v s+ - v out ) (mv) temperature (c) r l = 2k r l = open r l = 10k 0 50 100 150 200 250 300 350 -75 -25 25 75 125 175 temperature (c) (v s+ - v out ) (mv) r l = 2k r l = open r l = 10k 0 10 20 30 40 50 temperature (c) (v s- + v out ) (mv) r l = 2k r l = open r l = 10k -75 -25 25 75 125 175 0 10 20 30 40 50 60 70 -75 -25 25 75 125 175 temperature (c) (v s- + v out ) (mv) r l = 2k r l = open r l = 10k 0 50 100 150 200 250 300 350 -75 -25 25 75 125 175 temperature (c) (v s- - v out ) (mv) r l = 2k r l = open r l = 10k ISL70244SEH 12 fn8592.0 september 22, 2014 submit document feedback figure 27. input noise vo ltage spectral density (v s = 18v) figure 28. input nois e current spectral density (v s = 18v) figure 29. open loop frequency response (c l = 0.01pf) figure 30. open loop frequency response (c l = 10pf) figure 31. open loop frequency response (c l = 22pf) figure 32. open loop frequency response (c l = 47pf) typical performance curves unless otherwise specified, v s 18v, v cm = 0, v o = 0v, t a = +25c. (continued) 1 10 100 1,000 10,000 0.01 0.1 1 10 100 1k 10k 100k frequency (hz) input noise voltage (nv/ hz) 0.1 1 10 0.1 1 10 100 1k 10k 100k frequency (hz) input noise current (pa/ hz) -250 -200 -150 -100 -50 0 50 100 150 200 -250 -200 -150 -100 -50 0 50 100 150 200 0 1 10 100 1k 10k 100k 1m 10m 1g frequency (hz) simulation 100m phase gain gain (db) phase () -250 -200 -150 -100 -50 0 50 100 150 200 -250 -200 -150 -100 -50 0 50 100 150 200 0 1 10 100 1k 10k 100k 1m 10m 1g 100m simulation phase gain gain (db) phase () frequency (hz) -250 -200 -150 -100 -50 0 50 100 150 200 -250 -200 -150 -100 -50 0 50 100 150 200 0 1 10 100 1k 10k 100k 1m 10m 100m 1g frequency (hz) simulation phase gain gain (db) phase () -250 -200 -150 -100 -50 0 50 100 150 200 -250 -200 -150 -100 -50 0 50 100 150 200 0 1 10 100 1k 10k 100k 1m 10m 100m 1g frequency (hz) simulation phase gain gain (db) phase () ISL70244SEH 13 fn8592.0 september 22, 2014 submit document feedback figure 33. open loop frequency response (c l = 100pf) figure 34. cmrr vs frequency figure 35. psrr vs frequency figure 36. closed loop gain vs frequency response figure 37. feedback resistance (r f ) vs frequency response figure 38. load resistance vs frequency response typical performance curves unless otherwise specified, v s 18v, v cm = 0, v o = 0v, t a = +25c. (continued) -250 -200 -150 -100 -50 0 50 100 150 200 -250 -200 -150 -100 -50 0 50 100 150 200 0 1 10 100 1k 10k 100k 1m 10m 100m 1g frequency (hz) simulation phase gain gain (db) phase () -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 100 1k 10k 100k 1m 10m 100m frequency (hz) cmrr (db) 1.5v 18v 2.5v -10 0 10 20 30 40 50 60 70 80 90 100 110 120 100 1k 10k 100k 1m 10m 100m frequency (hz) psrr (db) 1.5v 18v 2.5v -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 100 1k 10k 100k 1m 10m 100m frequency (hz) gain (db) g = 10 g = 1000 g = 100 g = 1 -70 -60 -50 -40 -30 -20 -10 0 10 20 100 1k 10k 100k 1m 10m 100m frequency (hz) gain (db) r f = 10k r f = 100 r f = 1k -30 -20 -10 0 10 100 1k 10k 100k 1m 10m 100m frequency (hz) r l = 5k r l = 1k r l = 10k r l = 2k gain (db) ISL70244SEH 14 fn8592.0 september 22, 2014 submit document feedback figure 39. unity gain response vs load capacitance figure 40. supply voltage vs frequency response figure 41. crosstalk rejection vs frequency figure 42. slew rate vs st ep size vs temperature (v s = 1.5v) figure 43. slew rate vs step size vs temperature (v s = 2.5v) figure 44. slew rate vs st ep size vs temperature (v s = 18v) typical performance curves unless otherwise specified, v s 18v, v cm = 0, v o = 0v, t a = +25c. (continued) -50 -40 -30 -20 -10 0 10 100 1k 10k 100k 1m 10m 100m frequency (hz) acl = 1 rl = 10k ? v s = 18v gain (db) 12pf 27pf 47pf 68pf -40 -30 -20 -10 0 10 100 1k 10k 100k 1m 10m 100m frequency (hz) gain (db) 1.5v 18v 2.5v 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 100 1k 10k 100k 1m 10m 100m frequency (hz) crosstalk rejection (db) 1.5v 18v 2.5v 0 5 10 15 20 25 30 35 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 step size (v) slew rate (v/s) -55c +25c +125c 0 10 20 30 40 50 60 70 80 0 1 2 3 4 5 6 step size (v) slew rate (v/s) -55c +25c +125c 0 50 100 150 200 250 300 350 400 450 0 5 10 15 20 25 step size (v) slew rate (v/s) -55c +25c +125c ISL70244SEH 15 fn8592.0 september 22, 2014 submit document feedback figure 45. saturation recovery (v s = 18v) figure 46. saturation recovery (v s = 5v) figure 47. saturation recovery (v s = 2.5v) figure 48. overshoot (%) vs load capacitance figure 49. input overdrive response typical performance curves unless otherwise specified, v s 18v, v cm = 0, v o = 0v, t a = +25c. (continued) 1s/div 200mv/div v s = 18v a v = -100 r l = 2k r f = 100k ? , rg = 1k v in = 400mv p-p (input) (output) 1s/div 200mv/div v s = 5v a v = -100 r l = 1k r f = 100k , rg = 1k v in = 400mv p-p (input) (output) 1s/div 200mv/div a v = -100 r l = 2k r f = 100k ? , rg = 1k v in = 400mv p-p (input) (output) v s = 2.5v 0 5 10 15 20 25 30 35 40 1 10 100 capacitance (pf) overshoot (%) os+ os- v s = 18v r l = 10k a v = 1 v out = 25mv p-p 10s/div 2v/div, input v s = 5v 2v/div, output v in = 12v p-p no output phase reversal ISL70244SEH 16 fn8592.0 september 22, 2014 submit document feedback post high dose rate radiation characteristics unless otherwise specified, v s 19.8v, v cm =0, v o = 0v, t a = +25c. this data is typical mean test data post radiation expo sure at a high dose rate of 50 to 300rad(si)/s. this data is intended to show typical parameter shifts due to high dose rate radiation. these are not limits nor are they guaranteed. figure 50. v os shift vs high dose rate radiation figure 51. i bias+ shift vs high dose rate radiation figure 52. i bias - shift vs high dose rate radiation figure 53. i os shift vs high dose rate radiation figure 54. i+ vs high dose rate radiation figure 55. i- vs high dose rate radiation -10 -8 -6 -4 -2 0 2 4 6 8 10 0 50 100 150 200 250 300 krad(si) v s = 19.8v biased grounded voltage (v) -30 -20 -10 0 10 20 30 0 50 100 150 200 250 300 krad(si) v s = 19.8v biased grounded current (na) -40 -30 -20 -10 0 10 20 30 40 0 50 100 150 200 250 300 krad(si) v s = 19.8v biased grounded current (na) -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 0 50 100 150 200 250 300 krad(si) v s = 19.8v biased grounded current (na) -0.80 -0.60 -0.40 -0.20 0.00 0.20 0.40 0.60 0.80 0 50 100 150 200 250 300 krad(si) v s = 19.8v biased grounded current (ma) -0.80 -0.60 -0.40 -0.20 0.00 0.20 0.40 0.60 0.80 0 50 100 150 200 250 300 krad(si) v s = 19.8v biased grounded current (ma) ISL70244SEH 17 fn8592.0 september 22, 2014 submit document feedback post low dose rate radiation characteristics unless otherwise specified, v s 19.8v, v cm =0, v o = 0v, t a = +25c. this data is typical mean test data post radiation exposure at a low dose rate of <10mrad(si)/s. this data is intended to show typical parameter shifts due to high dose rate radiation. these are not limits nor are they guaranteed. figure 56. v os shift vs low dose rate radiation figure 57. i bias + vs low dose rate radiation figure 58. i bias - vs low dose rate radiation figure 59. i os vs low dose rate radiation figure 60. i + vs low dose rate radiation figure 61. i - vs low dose rate radiation -30 -20 -10 0 10 20 30 0 102030405060708090100 krad(si) v s = 19.8v voltage (v) biased grounded -30 -20 -10 0 10 20 30 0 102030405060708090100 krad(si) v s = 19.8v biased grounded current (na) -40 -30 -20 -10 0 10 20 30 40 0 102030405060708090100 krad(si) biased grounded v s = 19.8v current (na) -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 0 102030405060708090100 krad(si) biased grounded v s = 19.8v current (na) -0.80 -0.60 -0.40 -0.20 0.00 0.20 0.40 0.60 0.80 0 102030405060708090100 krad(si) v s = 19.8v biased grounded current (ma) -0.80 -0.60 -0.40 -0.20 0.00 0.20 0.40 0.60 0.80 0 102030405060708090100 krad(si) biased grounded v s = 19.8v current (ma) ISL70244SEH 18 fn8592.0 september 22, 2014 submit document feedback applications information functional description the ISL70244SEH contains two high speed, low power op amps designed to take advantage of its full dynamic input and output voltage range with rail to rail operation. by offering low power, low offset voltage, and low temperature drift coupled with its high bandwidth and enhanced slew rates upwards of 50v/s, these op amps are ideal for applications requiring both high dc accuracy and ac performance. the ISL70244SEH is manufactured in intersil?s pr40 silicon-on-insulator process, which makes this device immune to single event latch-up and provides excellent radiation tolerance. this makes it the ideal choice for high reliability applic ations in harsh radiation-prone environments. operating voltage range the devices are designed to operate with a split supply rail from 1.35v to 20v or a single supply rail from 2.7v to 40v. the ISL70244SEH is fully characterized in production for supply rails of 5v (2.5v) and 36v (18v). the power supply rejection ratio is typically 120db with a nominal 18v supply. the worst case common mode rejection ratio over temperature is within 1.5v to 2v of each rail. when v cm is inside that range, the cmrr performance is typically >110d b with 18v supplies. the minimum cmrr performance over the -55c to +125c temperature range and radiation is >70db over the full common mode input range for power supply voltages from 2.5v (5v) to 18v (36v). input performance the slew enhanced front end is a block that is placed in parallel with the main input stage and functions based on the input differential voltage. input esd diode protection the input terminals (in+ and in-) have internal esd protection diodes to the positive and negative supply rails, series connected 600 current limiting resistors and an anti-parallel diode pair across the inputs. output short circuit current limiting the output current limit has a worst case minimum limit of 8ma but may reach as high as 100ma. the op amp can withstand a short circuit to either rail for a short duration (<1 second) as long as the maximum operating junction temperature is not violated. this applies to on ly one amplifier at a given time. continued use of the device in these conditions may degrade the long term reliability of the part and is not recommended. figure 20 shows the typical short circuit currents that can be expected. the ISL70244SEH?s current limiting circuitry will automatically lower the current limi t of the device if short circuit conditions carry on for extended periods in time in an effort to protect itself from malfunction, however extended operation in this mode will degrade the output rail-to-rail performance by pulling v oh /v ol away from the rails. output phase reversal output phase reversal is a change of polarity in the amplifier transfer function when the input voltage exceeds the supply voltage. the ISL70244SEH is immu ne to output phase reversal, even when the input voltage is 1v beyond the supplies. this is illustrated in figure 49 . power dissipation it is possible to exceed the +150c maximum junction temperatures under certain load and power supply conditions. it is therefore important to ca lculate the maximum junction temperature (t jmax ) for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. these parameters are related using equation 1 : where: ?p dmaxtotal is the sum of the maximum power dissipation of each amplifier in the package (pd max ) ?pd max for each amplifier can be calculated using equation 2 : where: ?t max = maximum ambient temperature ? ? ja = thermal resistance of the package ?pd max = maximum power dissipation of 1 amplifier ?v s = total supply voltage ?i qmax = maximum quiescent supply current of 1 amplifier ?v outmax = maximum output voltage swing of the application figure 62. input esd diode current limiti ng, unity gain - + r l v in v out v+ v- 600 ? 600 ? t jmax t max ? ja xpd maxtotal + = (eq. 1) pd max v s i qmax v s ? - v outmax ? v outmax r l ---------------------------- ? + ? = (eq. 2) ISL70244SEH 19 fn8592.0 september 22, 2014 submit document feedback unused channel configuration the ISL70244SEH is a dual op amp. if the application does not require the use of both op amps, the user must configure the unused channel to prevent it from oscillating. the unused channel will oscillate if the input and output pins are floating. this results in higher-than-expe cted supply currents and possible noise injection into the active ch annel. the proper way to prevent oscillation is to short the output to the inverting input, and ground the positive input ( figure 63 ). figure 63. preventing oscillations in unused channels - + ISL70244SEH 20 fn8592.0 september 22, 2014 submit document feedback die characteristics die dimensions 2410m x 1961m (95mils x 77mils) thickness: 483m 25m (19mils 1 mil) interface materials glassivation type: nitrox thickness: 15k? top metallization type: alcu (99.5%/0.5%) thickness: 30k? backside finish silicon process pr40 assembly related information substrate potential floating additional information worst case current density < 2 x 10 5 a/cm 2 transistor count 365 weight of packaged device 0.3958 grams (typical) lid characteristics finish: gold potential: unbiased, tied to package pin 6 case isolation to any lead: 20 x 10 9 (min) metallization mask layout ISL70244SEH 21 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8592.0 september 22, 2014 for additional products, see www.intersil.com/en/products.html submit document feedback about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support table 1. die layout x-y coordinates pad name pad number x (m) y (m) dx (m) dy (m) bond wires per pad outb 1 1015.5 664.0 110 110 1 v+ 2 557.0 664.0 110 110 1 outa 3 -317.0 664.0 110 110 1 -ina 4 -1015.5 658.0 110 110 1 +ina 5 -1015.5 270.5 110 110 1 v- 12 -1015.5 -918.0 110 110 1 +inb 21 1015.5 62.0 110 110 1 -inb 22 1015.5 449.5 110 110 1 note: 7. origin of coordinates is the centroid of the die. revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o the web to make sure that you have the latest revision. date revision change september 22, 2014 fn8592.0 initial release. ISL70244SEH 22 fn8592.0 september 22, 2014 submit document feedback ceramic metal seal fl atpack packages (flatpack) notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. alternately, a tab (dimension k) may be used to identify pin one. 2. if a pin one identification mark is used in addition to a tab, the lim- its of dimension k do not apply. 3. this dimension allows for off- center lid, meniscus, and glass overrun. 4. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. the maximum lim- its of lead dimensions b and c or m shall be measured at the cen- troid of the finished lead surfac es, when solder dip or tin plate lead finish is applied. 5. n is the maximum number of terminal positions. 6. measure dimension s1 at all four corners. 7. for bottom-brazed lead packages, no organic or polymeric mate- rials shall be molded to the bottom of the package to cover the leads. 8. dimension q shall be measured at the point of exit (beyond the meniscus) of the lead from t he body. dimension q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when sol- der dip lead finish is applied. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling dimension: inch. -d- -c- 0.004 h a - b m d s s -a- -b- 0.036 h a - b m d s s e e a q l a e1 seating and l e2 e3 e3 base plane -h- b c s1 m c1 b1 (c) (b) section a-a base lead finish metal pin no. 1 id area a m d k10.a mil-std-1835 cdfp3-f10 (f-4a, configuration b) 10 lead ceramic metal seal flatpack package symbol inches millimeters notes min max min max a 0.045 0.115 1.14 2.92 - b 0.015 0.022 0.38 0.56 - b1 0.015 0.019 0.38 0.48 - c 0.004 0.009 0.10 0.23 - c1 0.004 0.006 0.10 0.15 - d - 0.290 - 7.37 3 e 0.240 0.260 6.10 6.60 - e1 -0.280-7.11 3 e2 0.125 - 3.18 - - e3 0.030 - 0.76 - 7 e 0.050 bsc 1.27 bsc - k 0.008 0.015 0.20 0.38 2 l 0.250 0.370 6.35 9.40 - q 0.026 0.045 0.66 1.14 8 s1 0.005 - 0.13 - 6 m - 0.0015 - 0.04 - n10 10- rev. 0 3/07 |
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