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features ? phase locked output frequency control intrinsically low jitter crystal oscillator lvpecl outputs with disable function dual 10 khz input references lor & lol combined alarm output force free run function automatic free run operation on loss of both references a & b input duty cycle tolerant 3.3v dc power supply small size: 1 square inch SCG4540 synchronous clock generators pll 2111 comprehensive drive aurora, illinois 60505 phone: 630-851-4722 fax: 630-851-5040 www.conwin.com bulletin sg053 page 1 of 16 revision p01 date 5 aug 02 issued by mbatts
preliminary data sheet #: sg053 p age 2 of 16 rev: p01 date: 08/05/02 ? copyright 2002 the connor-winfield corp. all rights reserved specifications subject to change without notice general description the SCG4540 is a mixed-signal phase locked loop generating lvpecl outputs from an intrinsically low jitter, voltage controlled, crystal oscillator. the lvpecl outputs may be disabled. the SCG4540 can lock to one of two 10 khz, external references, which is selectable using the sel ab input select pin. the unit has a fast acquisition time of about 1 second and it is tolerant of different reference duty cycles. the SCG4540 includes an alarm output that indicates deviations from normal operation. if a loss- of-reference (lor) or loss-of-lock (lol) is detected the alarm with indicate the need for a reference rearrangement. if both references a and b are absent the module will enter free run operation. the fr status pin will indicate that the module is in free run operation. frequency stability during free run operation is guaranteed to 20 ppm. additionally the free run mode may be entered manually. the package dimensions are 1? x 1.025? x .45? on a 6 layer fr4 board with castellated pins. parts are assembled using high temperature solder to withstand 63/37 alloys, 180c surface mount reflow processes. maximum dimension package outline figure 1 model comparison table table 1 dual max lvpecl model input duty oscillator output notes ref freq cycle (pins 16 & 18) scg4500 8 khz/8 khz 40/60 77.76 mhz,155.52 mhz,125 mhz basic model scg4510 1.544 mhz/1.544 mhz 40/60 155.52 mhz scg4520 19.44 mhz/19.44 mhz 40/60 77.76 mhz,155.52 mhz SCG4540 10 khz/10 khz 40/60 163.84 mhz *features which differentiate a model from the base model (scg4500) are highlighted in boldface color and in the notes column. block diagram figure 2 phase aligner refb refa sel ab analog filter q qn 1 / n alarm low jitter vcxo free run status optional reference output force free run enable/ tri-state dpfd
preliminary data sheet #: sg053 p age 3 of 16 rev: p01 date: 08/05/02 ? copyright 2002 the connor-winfield corp. all rights reserved specifications subject to change without notice notes: 1.0 operation of the device at these or any other condition beyond those listed under operating specifications is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. 2.0 requires external regulation and supply decoupling. (22 uf, 330 pf) 3.0 3db loop response. 4.0 from a 20 ppm step in reference frequency at 25c @ 3.3v 5.0 50-ohm load biased to 1.3 volts. 6.0 entry into free run doesn?t meet requirement for initial 2.33 seconds of self-timing. 7.0 if the selected reference is removed system response to the alarm must be less than 100ns. absolute maximum rating table 2 symbol parameter minimum nominal maximum units notes v cc power supply voltage -0.5 - +4.0 volts 1.0 v i input voltage -0.5 - +5.5 volts 1.0 t s storage temperature -65.0 - +100 c 1.0 operating specifications table 4 symbol parameter minimum nominal maximum units notes v cc power supply voltage 3.135 3.3 3.465 volts 2.0 i cc power supply current 170 230 280 ma 5.0 t o temperature range 0 - 70 c f fr free run frequency -20 - 20 ppm f cap capture/pull-in range -25 - 25 ppm f bw jitter filter bandwidth - - 10 hz 3.0 t jtol input jitter tolerance 1 - - s (input jitter frequencies 10 hz) t aq acquisition time - 1 - s 4.0 t rf output rise and fall time (20% 80%) 100 225 350 ps 5.0 dc output duty cycle 40 50 60 % mtie sr mtie at synchronization rearrangement gr-253-core.1999 r5-136 6.0, 7.0 output jitter specifications table 5 jitter bw 10 hz - 1 mhz sonet jitter bw 12 khz - 20 mhz frequency (mhz) ps (rms) m ui ps (rms) m ui 163.84 10 typ. 1.638 ty p. 1 max. 0.164 max. input and output frequencies table 3 parameter frequency input reference frequency dual 10 khz available output frequencies 163.84 mhz optional reference output frequencies not available
preliminary data sheet #: sg053 p age 4 of 16 rev: p01 date: 08/05/02 ? copyright 2002 the connor-winfield corp. all rights reserved specifications subject to change without notice notes: a active fr free run mode na not active ra locked to reference a rb locked to reference b u unstable (due to conditions shown, switch to active reference or free run) x don?t care input and output characteristics table 6 symbol parameter minimum nominal maximum units notes cmos input and output characteristics v ih high level input voltage 2.0 - 5.5 v v il low level input voltage 0.0 - 0.8 v t io i/o to output valid - - 10 ns c l output capacitance - - 10 pf v oh high level output voltage 2.4 - - v v ol low level output voltage - - 0.4 v t ir input reference pulse width 12.5 - - ns pecl output characteristics v oh high level pecl voltage 2.27 2.34 2.52 v v ol low level pecl voltage 1.49 1.51 1.68 v c l output capacitance - - 10 pf t skew differential output skew - 50 - ps input selection / output response table 7 inputs outputs note reset enable sel ab ref a ref b fr fr status alarm q qn 1 0xxxx 1 xxxfr x 1xxxx x x01 0 0xxx1 1 xxxfr 000aa0 00xxra 001aa0 00xxrb 000naa0 01xxu 001naa0 00xxrb 001ana0 01xxu 000ana0 00xxra 00xnana0 11xxfr
preliminary data sheet #: sg053 p age 5 of 16 rev: p01 date: 08/05/02 ? copyright 2002 the connor-winfield corp. all rights reserved specifications subject to change without notice pin description table 8 pin # pin name pin information note 1 enable/tri-state vcxo enable. (enable = 0, disable = 1 = cmos outputs tri-stated) 9.0 2 tck no connection, internal factory programming input. 8.0 3 tdo no connection, internal factory programming input. 8.0 4 ref a 10 khz, ttl/cmos reference frequency input. 5 sel ab input reference select pin. (refa = 0, refb = 1) 9.0 6 reset reset. (reset = 1) 9.0 7 ref b 10 khz, ttl/ cmos reference frequency input. 8v ee ground. 9fr status free run status. (fr = 1) 10 v cc supply voltage relative to ground. 11 n/c no connection. (optional reference output available) 8.0, 8.1 12 alarm loss of reference / lock alarm. (alarm = 1) 13 fr force free run. (phase lock = 0, free run = 1) 9.0 14 tdi no connection, internal factory programming input. 8.0 15 tms no connection, internal factory programming input. 8.0 16 qn lvpecl complementary output. 17 v ee ground. 18 q lvpecl output. circuit board footprint & keepout recommendations figure 3 0.8400 [21.34 mm] 1.0400 [26.42 mm] 0.8650 [21.97 mm] 0.1000 [2.54 mm] 0.0350 [0.89 mm] 0.0650 [1.65 mm] 0.1000 [2.54 mm] keep out area 1.0700 [27.18 mm] notes 8.0 do not connect pin 8.1 contact a sales representative for availibilty and use of optional reference output 9.0 input pulled to ground
preliminary data sheet #: sg053 p age 6 of 16 rev: p01 date: 08/05/02 ? copyright 2002 the connor-winfield corp. all rights reserved specifications subject to change without notice lol (internal signal) phase detector (internal signal) external reference (selected input a or b) internal reference (internal signal) lor (internal signal) 4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 2 start-up region 1 1 alarm output (lor + lol) start-up region 1 10 khz reference input < 1 sec > 1 sec 1 sec 2 3 4 124 sec(min) to 374 sec(max) after lol minimum pulse width = 2 s during start-up, the lol alarm will pulse during the few seconds of operation 5 loss of reference condition alarm timing figure 4 alarmtiming legend use for all alarm timing diagrams table 9
preliminary data sheet #: sg053 p age 7 of 16 rev: p01 date: 08/05/02 ? copyright 2002 the connor-winfield corp. all rights reserved specifications subject to change without notice lol (internal signal) phase detector (internal signal) external reference (selected input a or b) internal reference (internal signal) lor (internal signal) 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 2 1 5 alarm output (lor + lol) loss of lock condition alarm timing figure 5
preliminary data sheet #: sg053 p age 8 of 16 rev: p01 date: 08/05/02 ? copyright 2002 the connor-winfield corp. all rights reserved specifications subject to change without notice ref a ref b alarm sel a/b new reference qualification time lol portion of alarm is blanked 0.5 sec switch from a to b when both are good signals figure 6 r ef a r ef b a larm s el a/b ~8ns switch from a to b when reference b is lost figure 7
preliminary data sheet #: sg053 p age 9 of 16 rev: p01 date: 08/05/02 ? copyright 2002 the connor-winfield corp. all rights reserved specifications subject to change without notice switch from a to b after reference a is lost figure 8 switch from a to b when a is out of range figure 9 156.25 s (8 khz ref units) 126 s (19.44 mhz ref units) ref a ref b alarm sel a/b new reference qualification time alarm blanked ref a ref b alarm sel a/b new reference qualification time out of range in range alarm blanked
preliminary data sheet #: sg053 p age 10 of 16 rev: p01 date: 08/05/02 ? copyright 2002 the connor-winfield corp. all rights reserved specifications subject to change without notice switch from a to b when b is out of range figure 10 ref a ref b alarm sel a/b switch from a to b when b is out of range new reference qualification time 0.5 sec. out of range in range alarm blanked switch from a to b after auto free run due to loss of both references figure 11 ref a ref b alarm sel a/b new reference qualification time alarm blanked free run status
preliminary data sheet #: sg053 p age 11 of 16 rev: p01 date: 08/05/02 ? copyright 2002 the connor-winfield corp. all rights reserved specifications subject to change without notice typical mtie measurement figure 12 typical tdev measurement figure 13
preliminary data sheet #: sg053 p age 12 of 16 rev: p01 date: 08/05/02 ? copyright 2002 the connor-winfield corp. all rights reserved specifications subject to change without notice recommended pecl termination figure 14 50 scgxxx lvpecl output q qn vcc gnd 50 ohm transmission line 3.3 vdc 82 50 ohm transmission line lvpecl input d dn vcc gnd vcc - 2 vdc 3.3 vdc scgxxx lvpecl output q qn vcc gnd lvpecl input d dn vcc gnd 50 130 82 3.3 vdc lvpecl input d dn vcc gnd 3.3 vdc 3.3 vdc 50 ohm transmission line 50 3.3 vdc 50 ohm transmission line 3.3 vdc scgxxx lvpecl output q qn vcc gnd vcc - 2 vdc 100 50 ohm transmission line 130 3.3 vdc 50 ohm transmis sion line 50 150 150 if pecl outputs do not drive a long line (< 0.5?), a single 150 ? termination resistor to ground may be used for each pin.
preliminary data sheet #: sg053 p age 13 of 16 rev: p01 date: 08/05/02 ? copyright 2002 the connor-winfield corp. all rights reserved specifications subject to change without notice tape and reel packaging figure 15
preliminary data sheet #: sg053 p age 14 of 16 rev: p01 date: 08/05/02 ? copyright 2002 the connor-winfield corp. all rights reserved specifications subject to change without notice solder profile figure 16 te m p 0 100 150 200 250 50 12345678 time(minutes) (c?) recommended reflow profile peak temp:217c? maxriseslope:1.5 c?/sec time above150c?:100sec ordering information scg{xxxx}-{fff.fff}{m} xxxx equals a specific model (4540) fff.fff equals the oscillator output frequency (163.84 mhz) m equals mhz and is added to all part numbers example: to order an SCG4540 with an oscillator output of 163.84 mhz, order part number 4540-163.84m please contact connor-winfield for other frequencies that may be available.
preliminary data sheet #: sg053 p age 15 of 16 rev: p01 date: 08/05/02 ? copyright 2002 the connor-winfield corp. all rights reserved specifications subject to change without notice
revision revision date note p00 07/08/02 preliminar y informational release p01 08/05/02 advanced to ver 3

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Price & Availability of SCG4540

Part #	Manufacturer	Description	Price	BuyNow Qty.
SCG4540-163.84M	Connor-Winfield		16: USD259.29 11: USD276.576 1: USD302.505	25

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