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myson technology mtd981a 10/100 ethernet transceiver this datasheet contains new product information. myson technology reserves the rights to modify the product specification without notice. no liability is assumed as a result of the use of this product. no rights under any patent accompany the sale of the product. mtd981a revision 1. 2 0 2 / 19 /200 1 1/ 18 features 10base-t, 100base-tx, and 100base-fx ieee-802.3 compliant transmit and receive functions ieee 802.3u clause 28 compliant auto-negotiation function full duplex operation capable baseline wander compensation supports 1:1 or 1.25:1 transmit transformer output waveform shaping ? no external filter required led indicators: link, tx, rx, col, 100, 10, fdx single 3.3-v power supply with 5v tolerant i/o 100-pin pqfp package general descriptions the mtd981a is a highly integrated analog interface ic for twisted pair ethernet applications. it provides the active circuitry to interface ieee 802.3 media independent interface (mii) compliant controllers to 10base-t or 100base-tx media. it also provides an ecl-type interface for use with 100base-fx fiber networks. the mtd981a supports full duplex operation at 10 and 100 mbps. its operating condition can be set by using auto-negotiation, parallel detection, or manual control. the mtd981a is ideal as a media interface for 10base-t/100base-tx network interface cards, motherboards, 10/100 repeaters, switching hubs, and external phys. block diagram mii reg- isters & interface logic 4b/5b encoder, scrambler, parallel/serial parallel/serial, manchester encoder manchester decoder, serial/ parallel serial/parallel descrambler, 5b/4b decoder carrier sense, collision det ect nrz/nrzi, mlt3 encoder tx clock generator clock recovery clock ref- erence pulse shaper & filter auto nego- tiation adaptive eq. baseline wander corrector, mlt3 decoder, nrzi /nrz utp receiver utp driver leds txop txon rxip rxin link tx rx collisio n 100x 100m 10m 10m 100m transmit receive mii serial manage- ment & cont rol vcc ground
myson technology mtd981a mtd981a revision 1. 2 0 2 / 19/ 200 1 2 pin connection 40 MTD981AF MTD981AF 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 nc12 nc13 nc14 nc15 nc16 col crs mdint ledspd_ ledcol_ ledrx_ ledtx_ ledlnk_ ovdd ognd gndcrv vaacrv sel2 sel1 sel0 anen led10_ ledfd_ vaafq vaaeq nc17 nc18 nc19 nc20 nc21 nc11 nc10 nc9 nc8 nc7 tp125 mode1 phyad0 phyad1 phyad2 phyad3 phyad4 ovdd ognd gndpll vaapll pd rst_ test rmiisel ckin gndt iso isodef mode0 nc6 nc5 nc4 nc3 nc2 rptr sdp rxin rxip gndeq fin fip test2 fop fon gndref rbias vaaref nc0 nc1 gndt txop txon vaat vaat txd3 txd2 txd1 txd0 cvdd cgnd txen txclk txer rxer rxclk rxdv ognd ovdd rxd0 rxd1 rxd2 rxd3 mdc mdio 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
myson technology mtd981a mtd981a revision 1. 2 0 2 / 19/ 200 1 3 mtd981ag 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 col crs mdint ledspd_ ledcol_ ledrx_ ledtx_ ledlnk_ ovdd ognd gndcrv vaacrv sel2 sel1 sel0 anen led10_ ledfd_ vaafq vaaeq tp125 mode1 phyad0 phyad1 phyad2 phyad3 phyad4 ovdd ognd gndpll vaapll pd rst_ test rmiisel ckin gndt iso isodef mode0 rptr sdp rxin rxip gndeq fin fip test2 fop fon gndref rbias vaaref nc0 nc1 gndt txop txon vaat vaat txd3 txd2 txd1 txd0 cvdd cgnd txen txclk txer rxer rxclk rxdv ognd ovdd rxd0 rxd1 rxd2 rxd3 mdc mdio 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
myson technology mtd981a mtd981a revision 1. 2 0 2 / 19/ 200 1 4 pin description name io pin # (80) pin # (100) description txd3 i 40 50 transmit data bit 3. txd2 i 39 49 transmit data bit 2. txd1 i 38 48 transmit data bit 1. txd0 i 37 47 transmit data bit 0. txen i 34 44 transmit enable. txclk o 33 43 transmit clock. txer i 32 42 transmit error. rxd3 o 23 33 receive data bit 3. rxd2 o 24 34 receive data bit 2. rxd1 o 25 35 receive data bit 1. rxd0 o 26 36 receive data bit 0. rxdv o 29 39 receive data valid. rxer o 31 41 receive data error. rxclk o 30 40 receive clock. col o 41 56 collision detect. crs o 42 57 carrier sense. mdc i 22 32 mii management clock. mdio io,u 21 31 mii management data input/output. weakly pull up. mdint o 43 58 mii management interrupt. txop o 77 97 twisted-pair output positive node. txon o 78 98 twisted-pair output negative node. rxip i 64 84 twisted-pair input positive node. rxin i 63 83 twisted-pair input negative node. fop o 69 89 fiber output positive node. fon o 70 90 fiber output negative node. fip i 67 87 fiber input positive node. fin i 66 86 fiber input negative node. sdp i 62 82 signal detect positive node. used only in fiber mode. led spd _ i o,u 44 59 100bt led. 0 = 100basetx ; 1 = other connection. when rst_ is low, this pin works as fiber_desel to select the fiber mode. weakly pull up led10_ o 57 72 10bt led. 0 = 10basetx ; 1 = other connection. ledtx_ o 47 62 transmit led. toggles when there is transmit activities. ledrx_ o 46 61 receive led. toggles when there is receive activities. ledfd_ o 58 73 full-duplex led. 0 = full duplex ; 1 = half duplex. ledlnk_ o 48 63 link led. 0 = link on ; 1 = link off. ledcol_ io ,u 45 60 collision led. 0 = collision ; 1 = no collision. weakly pull up. when rst_ is low, this pin will load the scram_sel to enable/disable the scrambler and descrambler set. test i,d 7 12 test mode select. weakly pull down. ckin i 5 10 oscillator input. if rmii is selected, only 50mhz oscillator can be used. in mii mode, a 25mhz oscillator can be used. rbias i 72 92 bias control resister, to provide the internal voltage control. pd i,d 9 14 power down control. 1 = power down mode ; 0 or floating = normal. weakly pull down. rptr i,d 61 81 repeater mode select.
myson technology mtd981a mtd981a revision 1. 2 0 2 / 19/ 200 1 5 1 = repeater mode ; 0 or floating = normal. weakly pull down. isodef i,d 2 7 isolate default 1 =isolation ; 0 or floating = normal. weakly pull down. iso i,d 3 8 isolate 1 =isolation ; 0 or floating = normal. weakly pull down. rst_ i,u 8 13 pin reset select. 0=reset ; 1or floating = normal. weakly pull up rmiisel i,d 6 11 rmii mode select. 1 = rmii mode ; 0 or floating = normal (mii mode). weakly pull down. when rmii mode is selected, mtd981a will assume the 50mhz oscillator is used as base clock. anen i,u 56 71 auto-negotiation enable 1 = enable auto-negotiation ; 0 = disable auto-negotiation. weakly pull up. sel2 i,u 53 68 operation mode select, bit 2. used only when autonegotiation is disabled. weakly pull up. sel2 sel1 sel0 operation mode x 0 0 mode select by mii registers 0 0 1 10baset, half duplex 0 1 x 100baset, half duplex 1 0 1 10baset, full duplex 1 1 x 100baset, full duplex sel1 i,u 54 69 operation mode select, bit 1. weakly pull up. sel0 i,u 55 70 operation mode select, bit 0. weakly pull up. phyad0 i,u 18 23 phy address bit 0. weakly pull up. phyad1 i,u 17 22 phy address bit 1. weakly pull up. phyad2 i,u 16 21 phy address bit 2. weakly pull up. phyad3 i,u 15 20 phy address bit 3. weakly pull up. phyad4 i,u 14 19 phy address bit 4. weakly pull up. tp125 io,d 20 25 value latched in while reset to select transformer turns ratio. =1 to select the transmit transformer with ratio 1.25:1 =0 to select the transmit transformer with ratio 1:1 (default) works as link_established after reset. weakly pull down. mode1 i,d 19 24 test mode select bit 1. weakly pull down. mode0 i,d 1 6 test mode select bit 0. weakly pull down. test2 o 68 88 used as the test mode output monitor pin nc0 74 94 no connection nc1 75 95 no connection nc2 - 1 nc3 - 2 nc4 - 3 nc5 - 4 nc6 - 5 nc7 - 26 nc8 - 27 nc9 - 28 nc10 - 29 nc11 - 30 nc12 - 51 nc13 - 52 nc14 - 53 nc15 - 54
myson technology mtd981a mtd981a revision 1. 2 0 2 / 19/ 200 1 6 nc16 - 55 nc17 - 76 nc18 - 77 nc19 - 78 nc20 - 79 nc21 - 80 cvdd io 36 46 power pin for core. cgnd io 35 45 power pin for core.
myson technology mtd981a mtd981a revision 1. 2 0 2 / 19/ 200 1 7 functional descriptions 1. media independent interface (mii) the mtd981a implements an ieee 802.3u clause 22 compliant mii interface described as follows. the interface signals can be grouped into transmit, receive, and status. the transmit data signals comprise txd[3:0], txen, txer, and txclk. txd[3:0] are the nibble size data path, txen signals the presence of data on txd[3:0], txer indicates substitution of data with the halt symbol, and txclk carries the transmit clock that synchronizes all the transmit signals. the receive data signals also include seven signals, rxd[3:0], rxdv, rxer, and rxclk. rxd[3:0] are the nibble size data path, rxdv signals the presence of data on rxd[3:0], rxer indicates the validity of data, and rxclk carries the receive clock. depending on the operation mode, rxclk signal is generated by the clock recovery module of either the 100base-x or 10base-t receiver. two status signals, col and crs, are generated in the mtd981a to indicate collison status and carrier sense status to the mac. 2. serial management interface (smi) the mtd981a implements a serial management interface (smi) used both to obtain status from and to configure the phy. this mechanism corresponds to the mii spec for 100base-x (clause 22). the smi interface consists of two signals, mdc and mdio. mdc is a clock input to the phy and is used to latch data and instructions for the phy. the clock rate can run up to 2.5mhz. mdio is bi-directional and is used to write instruction to, write data to, or read data from phy. each data bit is latched either in or out on the rising edge of mdc. mdc/mdio are a common signal pair to up to 32 phys. therefore, each phy needs its unique address. the mtd981a uses 5 bits as phy address. the address is latched into internal register during reset from the pin setting. the smi interface supports registers 0 through 6. additional ? vendor- specific ? registers are implemented. all the registers are described in the register section. the access method of these registers is described as follows. typical mii read operation typical mii write operation figure 1. mii read/write operation 0 1 1 0 0 1 1 0 0 0 0 0 0 z 1 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 start opcode phyaddr regaddr ta register data idle z z z mdc midio (sta) mdio (phy) z z idle z 0 1 0 1 0 1 1 0 0 0 0 0 start opcode phyaddr regaddr idle 0 1 0 0 0 0 0 0 0 0 0 0 ta register data 0 0 0 0 0 0 0 0 z mdc midio (sta) z z idle
myson technology mtd981a mtd981a revision 1. 2 0 2 / 19/ 200 1 8 before any transaction, the station must send 32 continuous logic "1" on mdio to establish synchronization. figure 1 shows the read and write operation. the start code is "01" followed by an op code, either "01" for read or "10" for write. for read operation, the device address must match the address of the target phy device. for write operation, the address may be all zero or match a specific phy address. turnaround cycle is an idle cycle consists of two bit times between the register address field and data field in order to avoid conflict. for reading, no device drive mdio in the first bit time, phy drive "0" in the second bit time. for writing, station drive "10" during the idle cycle. 3. 10base-t when configured to run in 10base-t mode, either through hardware configuration, software, or auto- negotiation, the mtd981a will support all the functions specified in ieee 802.3 standard for 10base-t (clause 14). 3.1 transmit function in 10base-t mode, the transmit function uses parallel-to-serial logic to convert the 4-bit transmit data into a serial data stream. this serial data stream is manchester-encoded and then output through the waveshaping driver. filtering is performed in silicon to reduce emi emission. txop/txon can be connected directly to a standard transformer. external filtering modules are not needed 3.2 receive function in 10base-t mode, the signals at rxip/rxin first pass a smart squelch circuit. a manchester decoder and a serial-to-parallel converter then follow to generate the 4-bit nibble in mii interface. the squelch level of the smart squelch circuit drops to half its threshold value after unsquelch to allow reception of minimum amplitude signals to mitigate carrier fade in the event of worst case signal attenuation. 3.3 link monitor in 10base-t mode, link pulse detection circuit will constantly monitor the rxip/rxin pins for the presence of valid link pulses. in the absence of valid link pulses, the link led will deassert. 4. 100base-tx when configured to run in 100base-t mode, either through hardware configuration, software, or auto- negotiation, the mtd981a will support all the functions specified in ieee 802.3 standard for 10base-tx. 4.1 transmit function in 100base-tx mode, the transmit function converts synchronous 4-bit data nibbles from the mii to a 125- mbps differential serial data stream in mlt-3 format. the entire operation is synchronous to a 25-mhz clock and a 125-mhz clock. both clocks are generated by an on-chip pll clock synthesizer that is locked to an external 25-mhz clock source. there are three functional blocks in the transmit function: 4b/5b encoder, scrambler, and mlt-3 output driver. the 4b/5b encoder, defined in ieee 802.3 clause 24, converts 4-bit raw data to 5-bit code-group. it also inserts the stream boundary delimiters (/j/k/ and /t/r/) at the beginning and end of the data stream as appropriate. the 4b/5b encoded data has repetitive patterns which result in peaks in the rf spectrum. the peaks in the radiated signal are reduced significantly by scrambling the transmitted signal. the scrambler, defined by the tp-pmd stream cipher function, encodes a plain text nrz bit stream using a key stream periodic sequence of 2047 bits generated by the recursive linear function: x[n] = x[n-11] + x[n-9] (modulo 2) the scrambler reduces peak emission by randomly spreading the signal energy over the transmit frequency range, thus eliminating peaks at a single frequency. the scrambled nrz data stream is then converted to mlt-3 encoded data and then output to the utp-5 cable. the mlt-3 is a tri-level signal. the presence of a transition has a logical value of 1 and the lack of a transition has a logical value of 0. the benefit of mlt-3 is that it reduces the the maximum frequency from 62.5 mhz to 31.25 mhz.
myson technology mtd981a mtd981a revision 1. 2 0 2 / 19/ 200 1 9 4.2 receive function in 100base-tx mode, the receive function includes a receiver with adaptive equalization and baseline wander compensation, data and clock recovery at 125mhz, descrambling, and 5b to 4b decoding. an energy detect circuit is also added to determine whether there is any signal energy on the media. 4.3 link monitor in 100base-tx mode, when no signal or invalid signal is detected on the receiver pair, the link monitor will enter the ? link fail ? state where only the scrambled idle code will be transmitted. when a valid signal is detected for a minimum period of time, the link monitor will then enter the ? link pass ? state when transmit and receive functions are entered. 5. 100base-fx when configured to run in 100base-fx mode, either through hardware configuration or software configuration, the mtd981a will support all the features and parameters of the industry standards. 5.1 transmit function in 100base-fx mode, the 4b/5b encoded data stream bypass the scrambler. the output is nrzi pecl signals. the pecl level signals are used to drive the transmitter of the fiber module. 5.2 receive function in 100base-fx mode, the signal is received through the pecl receiver, and directly passed to the clock recovery circuit for clock/data extraction. the descrambler is bypassed. the data still need 5b/4b decoding. 5.3 link monitor in 100base-fx mode, the external fiber module performs the signal energy detection and communicates this information directly to the sdp pin of mtd981a. 6. auto-negotiation mtd981a implements auto-negotiation logic conforming to the 802.3u specification. the basic operation is based on using fast link pulse (flp) to communicate information between link partners. the auto-negotiation takes three phases to complete: advertising, detection and selection. the auto-negotiation mode can be optionally selected using external pin selection sel[0:2]. mtd981a also implements parallel detect function to allow compatibility with legacy network devices.
myson technology mtd981a mtd981a revision 1. 2 0 2 / 19/ 200 1 10 register descriptions register 0. control register bit name r/w def description 15 rst rw,s c 0 reset 1 = reset. 0 = normal operation. 14 lpbk rw 0 loopback select. 1 = loopback 0 = normal operation. 13 speed rw 1 speed select. 1 = 100mbps selected. 0 = 10mbps selected. 12 anen rw 1 autonegotiation enable. 1 = enabled. 0 = disabled. 11 pwdn rw 0 power down enable. 1 = power down. 0 = normal operation. 10 iso rw 1 mii isolation. 1 = isolation. 0 = normal operation. 9 restart _ an rw,s c 0 restart autonegotiation. 1 = restart. 0 = normal operation. 8 duplex rw 0 duplex mode select. 1 = full duplex. 0 = half duplex. 7 coltst rw 0 collision test enable. 1 = enable. 0 = disable. 6:0 - - - reserve register 1. status register bit name r/w def description 15 t4 r 0 not capable of t4 operation. 14 txfd r 1 capable of 100-tx full duplex operation. 13 txhd r 1 capable of 100-tx half duplex operation. 12 tpfd r 1 capable of 10-tp full duplex operation. 11 tphd r 1 capable of 10-tp half duplex operation. 10:7 - - - reserved. 6 sprem r 1 accepting mii frames with preamble suppressed. 5 anc r 0 1 = a uto-negotiation complete. 0 = auto-negotiation not complete. 4 rf r,lh 0 1 = remote fault detected. 0 = no remote fault. 3 an r 1 1 = capable of auto-negotiation operation. 2 link r/ll 0 1 = link established. 0 = link not established. 1 jab r/lh 0 1 = jabber detected. 0 = jabber not detected. 0 ext r 1 1 = extended registers exist.
myson technology mtd981a mtd981a revision 1. 2 0 2 / 19/ 200 1 11 register 2. oui register bit name r/w def description 15:0 oui_l r 0302 h oui[3:18] = 0302h register 3. oui_h register bit name r/w def description 15:10 oui_h r 1101 _ 00 oui[19:24] = 1101_00 9:4 partno r 0 part number. 3: 0 rev r 0 revision number. register 4. advertisement register bit name r/w def description 15 np r 0 next page. 0 = no next page. 14 ack r 0 acknowledge. 1 = received link code word acknowledged. 0 = received link code word not acknowledged. 13 rfdet r 0 remote fault detected. 1 = remote fault detected. 0 = no remote fault. 12:10 - rw 000 reserved. ( reserved for pause function ) 9 t4 r 0 1 = capable of t4 operation. 0 = not capable of t4 operation. 8 txfd rw 1 1 = capable of 100-tx full duplex operation. 0 = not capable of 100-tx full duplex operation. 7 txhd rw 1 1 = capable of 100-tx half duplex operation. 0 = not capable of 100-tx half duplex operation. 6 tpfd rw 1 1 = capable of 10-tp full duplex operation. 0 = not capable of 10-tp full duplex operation. 5 tphd rw 1 1 = capable of 10-tp half duplex operation. 0 = not capable of 10-tp half duplex operation. 4:0 select r 1 selector field = 5 ? b00001 means ieee802.3 selected. register 5. link partner ability register bit name r/w def description 15 np r 0 next page. 0 = no next page. 14 ack r 0 acknowledge. 1 = received link code word acknowledged. 0 = received link code word not acknowledged. 13 rfdet r 0 remote fault detected. 1 = remote fault detected. 0 = no remote fault. 12:10 - r - reserved. 9 t4 r 0 1 = capable of t4 operation. 0 = not capable of t4 operation. 8 txfd r 0 1 = capable of 100-tx full duplex operation. 0 = not capable of 100-tx full duplex operation. 7 txhd r 0 1 = capable of 100-tx half duplex operation.
myson technology mtd981a mtd981a revision 1. 2 0 2 / 19/ 200 1 12 0 = not capable of 100-tx half duplex operation. 6 tpfd r 0 1 = capable of 10-tp full duplex operation. 0 = not capable of 10-tp full duplex operation. 5 tphd r 0 1 = capable of 10-tp half duplex operation. 0 = not capable of 10-tp half duplex operation. 5 tphd r 0 1 = capable of 10-tp half duplex operation. 0 = not capable of 10-tp half duplex operation. 4:0 select r 1 selector field = 5 ? b00001 means ieee802.3 selected. register 16. proprietary control register bit name r/w def description 15 rep rw 1 = repeater mode. - full duplex disabled. - sqe function disabled. - crs response to receive activity only. 14 int_sel rw 0 1 = set the interrupt pin to be active high. 0 = set the interrupt pin to be active low. 13:12 stable_time_ sel[1:0] rw 00 stablize timer sel 00 = 700us 01 = 1ms 10 = 5ms 11 = 45ms 11 sqe_dis rw 0 1 = disable sqe function. 0 = enable sqe function. 10 flp_rx_ idle_en rw 1 flp_idle enable (arbitration state machine) 1 single_link_ready = ( flp_idle) & ( ( ( link_status_nlp == 1'b0) & ( link_status_x == ready)) | ( ( link_status_nlp == 1'b1) & ( link_status_x != ready)) ); 0 single_link_ready = ( ( ( link_status_nlp == 1'b0) & ( link_status_x == ready)) | ( ( link_status_nlp == 1'b1) & ( link_status_x != ready)) ); 9 fddi_ load_en rw 1 fddi load enable ( descrambler lock time) 1 load = (~locked) & ( quiet | halt | master | idle); 0 load = (~locked) & ( idle); 8 edpsm rw 0 1 = energy detect power saving mode 0 = no power down 7 fef_en rw 0 1 = far-end-fault enabled. 0 = far-end-fault disabled. 6 xfsel rw 0 1 = select transmit transformer ratio to be 1.25:1. 0 = select transmit transformer ratio to be 1:1. 5 pol_dis rw 0 1 = disable auto polarity detection/correction function. 0 = enable auto polarity detection/correction function. 4 nlp_dis rw 0 1 = force link up without checking nlp. 0 = normal operation. 3 - - - reserved. 2 bp_jab rw 0 1 = bypass jabber function. 0 = enable jabber function. 1 scram_en rw 1 1 = enable scrambler / discrambler 0 = disable scrambler / discrambler 0 fx_sel rw 0 1 = fx mode selected, scram_en will be set to 0. 0 = disable fx mode. scram_en can be programmed after fx mode disabled.
myson technology mtd981a mtd981a revision 1. 2 0 2 / 19/ 200 1 13 register 17. interrupt register bit name r/w def description 15:13 - - - reserved. 12 pdfm rw 0 1 = enable parallel detection fault interrupt. 0 = disable parallel detection fault interrupt. 11 - - - reserved. 10 lfm rw 0 1 = enable link fail interrupt. 0 = disable link fail interrupt. 9 - - - reserved. 8 ancm rw 0 1 = enable autonegotiation complete interrupt. 0 = disable autonegotiation complete interrupt. 7:5 - - - reserved. 4 pdfint w1c 0 1 = parallel detection fault interrupt. this bit is write 1 cleared. 3 - - - reserved. 2 lfint w1c 0 1 = link fail interrupt. this bit is write 1 cleared. 1 - - - reserved. 0 ancint w 1c 0 1 = autonegotiation complete interrupt. this bit is write 1 cleared. register 18. proprietary status register bit name r/w def description 15:12 - - - reserved. 11 duplex r 0 1 = link status is full dup lex. 0 = link status is half duplex or link fail . 10 speed r 0 1 = link speed is 100base-tx. 0 = link speed is 10base-tx. 9:5 - - - reserved. 4:0 phyad r 00000 phy address. register 19. test register bit name r/w def description 15 :14 tstmd [3:2 ] rw 00 125mhz clock source 00 = use internal ( cgm) 125mhz clk 11 = use external 125mhz clk 13 :12 tstmd[1:0 ] rw 00 mlt3shmx control signal. 00 = clk0 clkd0 nrz0 (normal mode) 01 = clk0 clkd0 (high) (test mode with nrz high and clk from cgm) 10 = f25m f25m (high) (test mode with nrz high and clk from ckin) 11 = f25m f25m (high) (test mode with nrz high and clk from ckin) 11:8 reserve d rw 0 reserved 7 no_pwrdn rw 0 1 = force no power down. 0 = accept power down setting. 6 manual_ct rl_pwrdn rw 0 1 = enable manual control power down. 0 = bypass manual control power down. 5: 4 reserve d rw 0 reserved 3 tstmd_ descrm rw 0 1 = accelerate descrambler lock time. 0 = normal descrambler lock time.
myson technology mtd981a mtd981a revision 1. 2 0 2 / 19/ 200 1 14 2 lb_dig rw 1 1 = enable digital loopback. 0 = dis able digital loopback. 1 :0 reserve d reserved
myson technology mtd981a mtd981a revision 1. 2 0 2 / 19/ 200 1 15 electrical characteristics 1. absolute maximum ratings at: ta= 0 to 70 o c, vss=0v name symbol range unit maximum supply voltage vdd -0.3 to +5.0 v maximum input voltage vin -0.3 to vdd+0.3 v maximum output voltage vout -0.3 to vdd+0.3 v maximum storage temperature tstg -25 to +125 o c 2. operating range name symbol min. max. unit supply voltage vdd 3.0 3.6 v operating temperature topg 0 +70 o c
myson technology mtd981a mtd981a revision 1. 2 0 2 / 19/ 200 1 16 package dimension 100-pin pqfp 0.913 +/-0.008 0.787 +/-0.004 0.012 +/-0.004 0.026 0.677 +/-0.008 0.551 +/-0.004 0.107 +/-0.006 0.014 +/-0.004 0.031 +/-0.006 0.063 0~7 0 0.006 +/-0.002
myson technology mtd981a mtd981a revision 1. 2 0 2 / 19/ 200 1 17 80-pin lqfp 0.551 bsc. 0.472 bsc. 0 . 4 7 2 b s c . 0 . 5 5 1 b s c . 0. 0079~0. 0157 0.0256 0.063 max. 0.002~0.006 0.055 +/-0.002 0.00. 9 ref . 12 o +/-1 o
myson technology mtd981a mtd981a revision 1. 2 0 2 / 19/ 200 1 18 document change history revision chapter detail 1.1 document change history add this new chapter product name of 80- pin lqfp mtd981a -> mtd981ag pin description rbias_ret rename as nc0 pin diagram rbias_ret -> nc0 pin description of pa4 ? pa0 rename as phyad4-0 (consistent with pin diagram) phy id -> phy address pin description of tpop/tpon rename as txop/txon (consistent with pin diagram) pin description of tpip/tpin rename as rxip/rxin (consistent with pin diagram) pin description of rmiisel my3045 -> mtd981a 50m -> 50mhz pin description of anen autonegotiation -> auto-negotiation pin description of iso isolation select -> isolate pin description of isodef isolation select -> isolate default pin description of test2 i ->o; vcp -> test mode output monitor pin pin description of ledcol_ add scram_sel description pin description of ledlnk_ remove scram_sel description 1.2 pin diagram gndeq -> nc21 pin description add nc21 description mtd981a(preliminary) -> mtd981a revision number and date

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