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| technical data 1 aug 2012, ver.0 5 cmos lis of real time watch with serial interface features ? count of seconds, minutes, hours, week days, date, months and years with consideration of leap years ( until 2100); ? 400 khz, double wire serial interface ; ? programmed orthogonal output sign al ; ? function programming of alarm, timer and interruption ; ? automatic determination of the supply voltage drop ; ? consumption current of less, than 450 na with supply of 2 v with the operating oscillator ; ? operating temperature range : - 40 ? C ? 85 ? . sop - 8 m sop - 8 = - 40 ... + 85 ? for all packages ordering information device operating temper a ture range package shipping IN1363dt = - 40 ... + 85 ? sop - 8 tape & reel IN1363d sop - 8 tube IN1363 m dt m sop - 8 tape & reel IN1363 m d msop - 8 tube description microcircuit IN1363 is essentially the complete binary - decimal digital watch with calendar, alarm, timer and possesses low power consumption. addresses and data are transferred in series via the do uble wire bi - directional bus. the microcircuit is intended for count of real time in hours, minutes and seconds, count of week days, date, month and year. the last day of the month is automatically adjusted for the months with fewer, than 31 days, includin g correction for the leap year. the watch functions in the 24 hour mode. the microcircuit IN1363 has the built - in power control circuit , which determines the power level < 1 v and forms the bit, signaling, that information about the real time may not be cor rect. IN1363
IN1363 2 aug 2012 , ver.0 5 pins description pin number symbol description 01 osci pin for connection of the quartz resonator 0 2 osco pin for connection of the quartz resonator 0 3 int interruption output 0 4 v ss common pin 05 sda input / output of data 06 scl synchrosig nal input 07 clkout frequency divider output 08 v dd supply source pin block diagram IN1363 3 aug 2012 , ver.0 5 a solute maximum rating limit and limit permissible operating modes of the microcircuit IN1363 are listed in the table characteristics symbol limit permissibl e limit unit min max min max supply voltage v dd 1.0 5.5 C tot - - - 300 mwt input voltage scl , sda , osci v i 0 5.5 C o 0 5.5 C io - - C * stresses beyo nd those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute - maximum - rated conditions for extended periods may affect device reliability . application IN1363 4 aug 2012 , ver.0 5 electrical characteristics ( = C 40...+ 85 ? , v cc = 4,5 C 5,5 v) characteristics symbol test condition min max note unit supply voltage v dd i 2 c bus C scl = 400 khz 1.8 5.5 v in the non - active mode 1.0 5.5 1,2 input leakage current i li v in =v dd ; v in =v ss - 1 u lo v out =v dd ; v out =v ss - 1 u dd 1 clkout C scl =400 khz - 800 u C scl = 1 00 khz - 200 clkout C scl =0 khz , v dd =5 v - 0.55 1,2 clkout C scl =0 khz , v dd =2 v - 0.45 1,2 low level input voltage v il v ss 0.3v dd v high level input voltage v ih 0.7v dd v dd v low level output current at pin clkout i ol1 v ol = 0.4 v , v dd =5 v 1 - m oh1 v oh = 4. 6 v , v dd =5 v 1 - m ol2 v ol = 0.4 v , v dd =5 v 1 - m ol3 vol = 0.4 v, vdd =5 v 3 - m low 1 1 v note 1 ta =(25 5) o c 2 parameters of the quartz oscillator: f osc =32.768 khz , r s 40 l =8 IN1363 5 aug 2012 , ver.0 5 dynamic characteristics ( = C 40...+ 85 ? , v cc = 4,5 C 5,5 v are listed in the table ) characteristics symbol test condition min max unit cycle frequency scl f scl C buf C C hd:sta 1) C C low C C high C C su:sta C C hd:dat 2) C C su:dat C C r C C f C C su:sto C C c b C C i/o C lx C 1) after this time interval the first cycle signal is formed ; 2) the device should internally ensure the hold time, at least, 300 nsec for the signal sda ( relative to v ihmin of the signal scl ) in order to overlap the indeterminacy area of the signal scl drop front maximum value t hd:dat should be definite in that case, if the device does not increase duration of the low condition (t low ) of the signal scl IN1363 6 aug 2012 , ver.0 5 timing diagramm operation descriptio n IN1363 operates as the ?slave? device on the serial bus. for access to it expedient to set the co n dition start and transfer after the register address the device identification code. the next registers can be address in series till the condition stop is preset. with v cc below 1,8 v, access granting to the device by the serial interface is not guaranteed. the current time is counted with the supply voltage 1 5,5 v. when the supply level becomes lower, than 1v, the bit vl=1 is formed, signaling, that the information about the current time may be incorrect. description of signa ls v dd C positive supply . v dd C input from +1 ti ll +5 v. with supply < 1,8 v access to the interface circuit is not guaranteed. int C interrupt output. interruption condition is formed with coincidence of the current time with the alarm settings, or with attainment of the condition ?0? of the timer cou ntdown. interruption, formed from the alarm, forms the continuous signal, and from the timer can be both continuous and pulse one. scl ( serial clock input ) C scl is used for synchronization of the data transfer by the serial interface. sda ( serial data i/o ) C sda is input/output for the double wire serial interface. output sda is the open drain, for which the external load resistor is required to be connected. clkout (former output of the orthogonal signal) C for output activation the bit fe is preset t o 1. clkout generates the orthogonal signal of four different frequencies (1 hz, 32 hz, 1 khz, 32 khz). output clkout is essentially the open drain, for which the external load resistor is required to be connected. osci, osco C connection of the standar d quartz resonator for the frequency 32,768 khz. capac i tance load of the internal oscillator for the quartz resonator is equal to 12pf. IN1363 can operate from the external oscillator with the frequency 32,768 khz. with this configuration the output osci i s connected to the signal external oscillator, and osco is left unconnected. IN1363 7 aug 2012 , ver.0 5 watch and calendar acquisition of information on time and date is performed by means of reading the appropriate re g ister bytes . presetting and time and calendar initialization is performed by means of the appropriate bytes. information, contained in the time, calendar and alarm registers, is essentially the binary - decimal code. bit 7 of register 2 is essentially the indication bit of the supply level decrease. < 1 v ( vl ). when t his bit = 1 , this signifies, that the supply voltage was below the norm, and the information on the current time may be unreliable . when switching power supply on, all register bits are preset to "0", with the exception of bits fe, vl, td1, td0, testc and ae, which are preset to "1". when applying the signal start on the double wire bus, the current time transfer occurs from the counters to the auxiliary set of registers. the data on time are read out from these auxiliary registers, while the watch c ontinue to operate. this eliminates the necessity in the repeated reading in case of u p dating the basic registers in the access process. registers rtc IN1363 address data registers / range d7 d6 d5 d4 d3 d2 d1 d0 00 h test1 0 stop 0 testc 0 0 0 contr ol 1 01h 0 0 0 ti/tp af tf aie tie control 2 02h vl tens of seconds units of seconds seconds 00 C 59 03h tens of minut e s units of minutes minutes 00 C 59 04h tens of hours units of hours hours 00 C 23 05 h tens of date units of date dates 01 C 31 06 h day of week day of week 0 C 6 07 h 10 . units of month century / month 0 - 1/01 - 12 08 h tens of years units of years year 00 C 99 09 h ae tens of minutes units of minutes minute alarm 00 C 59 0 ah ae tens of hours units of hours hour alarm 00 C 23 0 bh ae tens of date units of date date alarm 01 C 31 0 ch ae day of week weekday alarm 0 C 6 0dh fe fd1 fd0 control of clkout 0eh te td1 td0 control of timer 0fh value of timer timer IN1363 8 aug 2012 , ver.0 5 control registers control register 1 a ddress 0 0 h : control / status 1 register bits bit 7 6 5 4 3 2 1 0 symbol test1 0 stop 0 testc 0 0 0 test1 (activation of test mode) C this bit, preset to logic 1, activates the test mode, with logic 0 normal function ing of the circuit. stop C this bit , preset to logic 1 in the test mode perform the zero setting of all dividers , with logic 0 C normal functioning of the circuit . testc ( activation of the test mode ) C this bit, preset to logic 1, activates the tes t mode, with logic 0 normal functioning of the circuit . w hen the control register1 is programmed, the osc generates . control register 2 a ddress 0 1 h : control / status 2 register bits bit 7 6 5 4 3 2 1 0 symbol 0 0 0 ti/tp af tf aie tie ti / tp ( f ormation of the pulse interruption signal at output int ) C this bit, preset to logic 0, with appearance of the timer flag tf at output int forms the constant interruption signal of the low level. the bit, preset to logic 1 at output int, forms the inte rruption pulse signal ( signal frequencies are listed in the table ). timer input frequency ( hz ) period int ( sec ). [1] n =1 [2] n > 1 4096 1/8192 1/4096 64 1/128 1/64 1 1/64 1/64 1/60 1/64 1/64 [1] tf and int become active simultaneously . [2] n C valu e, loaded to the timer register . timer is stopped with n = 0. af ( alarm flag ) - bit , in logic 1 informs about interruption by actuation of the alarm, by means of software the bit af can be reset only . tf ( timer flag ) - bit , in logic 1 informs about interruption by actuation of the timer , by the software means the bit tf can be reset only . aie ( activation of alarm ) - bit , preset to logic 1, activates operation of the alarm . tie ( activation of timer ) - bit , preset to logic 1, activates operation of the alarm . af tf read 0 a larm flag inactive 0 timer flag inactive 1 a larm flag inactive 1 t imer flag active write 0 a larm flag inactive 0 timer flag is cleared 1 a larm flag inactive 1 t imere flag remains unchanged IN1363 9 aug 2012 , ver.0 5 control register clkout. a d dress 0 d h : clkout frequency register bits bit 7 6 5 4 3 2 1 0 symbol fe fd1 fd0 fe ( output activation clkout ) - this bit, preset to logic 1, activates output clkout . frequency of the output orthogonal signal is determined by the bits fd 0 an d fd 1. the source clock for the timer is also selected by the timer control register. other timer properties,e.g interrupt generation are controlled via the control./ststus 2 register. for accurate read back of the countdown value, the i2c - bus clock scl must be operating at a frequency of at least twice the selected timer clock. fd1 fd0 frequency clkout 0 0 32,768 khz 0 1 8,192 khz 1 0 4,096 khz 1 1 1 hz timer control register the timer register is an 8 C bit binary countdown timer . it is enab led and disabled via the timer control register bit te . th e sourc e cloc k fo r th e time r i s als o selecte d b y thetime r contro l register . othe r time r properties , e.g . interru p t generation , ar e controlled via the control/statu s2 register. for accurate read back of the countdown value, the i2c bus clock scl must be operating at a frequency of at least twice the selected timer clock. a ddress 0 e h : timer control register bits bit 7 6 5 4 3 2 1 0 symbol te td1 td0 t e ( timer activation ) - this bit, preset to logic 1, activates the frequency application to the timer i n put from the oscillator . the signal frequency is determined by bits t d0 and t d1. d1 d0 timer input frequency 0 0 4096 hz 0 1 64 hz 1 0 1 hz 1 1 1 / 60 hz a ddress 0 f h : timer countdown value register bits bit 7 6 5 4 3 2 1 0 symbol t imer countdown value - this register holds the loaded countdown value n n coun tdown perio d = ------------------------------ source clock frequency IN1363 10 aug 2012 , ver.0 5 seconds, minutes and hours register a ddress 02h : seconds / vl register bits bit 7 6 5 4 3 2 1 0 symbol vl seconds vl = 0 : reliable clock/calendar information is guaranteed vl = 1 : reliable clock/calendar information is no longer guaranteed. IN1363 11 aug 2012 , ver.0 5 days, weekdays,months/century and years register a ddress 0 5 h : da tes register bits bit 7 6 5 4 3 2 1 0 symbol - - days < days > these bits represent the current day value coded in bcd format; value=01to 31 a ddress 0 6 h : weekdays register b its bit 7 6 5 4 3 2 1 0 symbol - - - - - w eek day < week days > these bits represent the current week day value 0 to 6 a ddress 0 7 h : century / months registers bits bit 7 6 5 4 3 2 1 0 symbol c - - months < c > century bit. c = 0 ; indicates the century is 20xx. c = 1 : indicate s th e centur y i s 19xx . xx indicate s th e valu e hel d i n the y ears register; this bit is toggled when the years register overflow from 99 to 00. < months > these bits represent the current month val ue coded in bcd format value 0 to12 b4 b3 b2 b1 b0 january 0 0 0 0 1 f ebruary 0 0 0 1 0 march 0 0 0 1 1 april 0 0 1 0 0 may 0 0 1 0 1 june 0 0 1 1 0 july 0 0 1 1 1 august 0 1 0 0 0 september 0 1 0 0 1 october 1 0 0 0 0 november 1 0 0 0 1 dec ember 1 0 0 1 0 a ddress 0 8 h : years register bits bit 7 6 5 4 3 2 1 0 symbol years < years > th is register represent the current year value coded in bcd format :00 to 99 IN1363 12 aug 2012 , ver.0 5 alarm r egister s a ddress 0 9 h : minute alarm register bits bit 7 6 5 4 3 2 1 0 symbol ae m inute alarm a e - a e= 0; minute alarm is enabled. a e= 1; minute alarm is disabled . < minute alarm > t hese bits represents the m inute alarm information coded in bcd format; valu e= 0 0 t o 59 . a ddress 0 a h : hour alarm register bit s bit 7 6 5 4 3 2 1 0 symbol ae - hour alarm a e - a e= 0; hour alarm is enabled. a e= 1; hour alarm is disabled . < hour alarm > these bits represents the hour alarm information coded in bcd format; valu e= 0 0 t o 23. a ddress 0 b h : day alarm register bits bit 7 6 5 4 3 2 1 0 symbol ae - day alarm a e - a e= 0; day alarm is enabled. a e= 1; day alarm is disabled . < day alarm > these bits represents the day alarm information coded in bcd format; valu e= 0 1 t o 31 a ddress 0 c h : weekday alarm regist er bits bit 7 6 5 4 3 2 1 0 symbol ae - - - - weekday alarm a e - a e= 0; weekday alarm is enabled. a e= 1; weekday alarm is disabled . < weekday alarm > these bits represents the weekday alarm information coded in bcd format; valu e= 0 t o 6 IN1363 13 aug 2012 , ver.0 5 2 - wire serial data bus in 1363 supports the bi - directional double wire bus and the data transfer protocol. the bus can be controlled by the master device , which generates the cycle signal ( scl ), controls access to the bus , generates the conditi ons start and stop . typical bus configuration with the double wire is indicated in the figure . data transfer can be started only when the bus is not busy. in the process of the data transfer, the data line should remain stable, while the cycle signal l ine is in the high condition. alterations of the data line conditions at that moment, when the cycle line is in the high condition, will be regarded as the control si g nals. in compliance with this the following conditions are determined: bus is not busy: both lines of data and cycle signal are in the high condition. data transfer start: alteration of the data line condition during transition from high to low, while the cycle line is in the high condition, is determined as the status start. data transfer stop: alteration of the data line condition during transition from low to high, while the cycle line is in the high condition, is determined as status stop. valid data: condition of the data line corresponds to the valid data, when after the condition s tart the data line is stable at the time of the high status of the cycle signal. the data on the line should be a l tered at the time of the low condition of the cycle signal. one cycle pulse per one data bit. each data transfer starts with arrival of the s tatus start and ceases with arrival of the status stop. number of data bytes, transferred between the statuses start and stop, is not limited and is dete r mined by the ?master? device. information is transferred byte by byte, and each reception is confirmed by the ninth bit. reception confirmation: each receiving device, when being addressed, generates the reception co n firmation bit after reception of each byte. the ?master? device should generate the additional cycle pulses, which are set in compliance wit h the confirmation bits. if the reception confirmation signal is in the high condition, then upon arrival of the confirmation cycle signal, confirming reception, the device should switch the sda line to the low condition. of course, the presetting time an d the hold time should be taken into consideration. the ?master? device should signal about termination of the data transfer to the ?slave? device, stopping generation of the confirmation bit, while receiving from the ?slave? cycle pulse of the reception confirmation. in this case, the ?slave? cycle pulse should switch the data line to the low condition for the ?master? cycle pulse to generate the cond i tion stop. IN1363 14 aug 2012 , ver.0 5 data transfer by the serial double wire bus depending on the status of the bit , two types of transfer are possible: 1. data are transferred from the ?master? transmit t er to the ?slave? receiver. the first byte, transferred by the ?master? one, is the address of the ?slave? one. then follows sequence of t he data bytes. the ?slave? one returns the reception confirmation bits after each received byte. order of the data transfer: the first one is the most senior digit (msb). 2. data are transferred from the ?slave? transmit t er to the ?master? receiver. the first byte (a d dress of ?slave?) is transferred to the ?master? one. then the ?master? returns the confirmation bit. this follows after the ?slave? one of the data sequence. the ?master? one returns the reception confirmation bit after each received byte, w ith exception of the last byte. after reception of the last byte the reception confirmation bit does not return. the ?master? device generates all cycle pulse and the conditions start and stop. transmission completes with emergence of the condition stop o r the repeated emergence of the condition start. as the repeated condition start is the beginning of the next serial transmission, then the bus is not vacated. data transfer order: the first one is the most senior digit (msb). w r / IN1363 15 aug 2012 , ver.0 5 ic IN1363 can work i n 2 nex t mode mode of the ?slave? re ceiver (writing mode of IN1363) serial data and cycles are received via sda and scl appropriately. after transfer of each byte the confirming bit is transferred. conditions start and stop are understood as the start and e nd of the serial transmission. address recognition is pe r formed by the hardware means after reception of the address of the ?slave? one and the direction bit. the address byte is the first byte, received after emergence of the condition start, generated by the ?master? one. address byte contains seven address bits IN1363, equal to 1010001, accompanied by the direction bit ( ), which is equal to 0 for writing. after reception and decoding the address IN1363 pr o vides confirmation on t he line sda. after confirmation by IN1363 of the ?slave? address and the write bit, the ?master? one transmits the register address of IN1363. thus, the register indicator will be set in IN1363. then the ?master? one will start to transfer each data byte with the subsequent confirmation r e ception of each byte receipt. upon completion of writing the ?master? one will form the condition stop, for termination of the data transfer. data writing C mode of the ?slave? receiver w r / IN1363 16 aug 2012 , ver.0 5 mode of the ?slave? tran smitter (read - out mode fro m IN1363) the first byte is accepted and is processed as in the mode of the ?slave? receiver. but in this mode the direction bit will indicate, that the transmission direction is altered. the serial data are transferred by in136 3 by means of sda, the cycle pulses C by means of scl. the statuses of start and stop are recognized as the start and end of transmission in series. the address byte is the first byte, received after emergence of the status start, generated by the ?slave? one. the address byte contains the seven address bits ds1363, equal to 1010001, accompanied with the direction bit ( ), which is equal to 1 for reading. after reception and decoding the address byte IN1363 accepts confirmation from the line sda. then IN1363 starts to transmit the data from the address, to which the register indicator indicates. if the register indicator is not written prior to initialization of the writing mode, then the first read address will be the last addres s, stored in the register indicator. IN1363 should transmit the bit of ?non - confirmation?, in order to complete reading. master reads after setting word address (write word address ; read data ) master reads slave immediately after first byte ( read mode ) data reading C mode of ? slave ? transmitter w r / s s l a v e _ a d d r e s s 0 a w o r d _ a d d r e s s a s s l a v e _ a d d r e s s 1 a d a t a a 1 p d a t a r / w r / w a c k n o w l e d g e m e n t f r o m s l a v e a c k n o w l e d g e m e n t f r o m s l a v e a c k n o w l e d g e m e n t f r o m s l a v e a c k n o w l e d g e m e n t f r o m m a s t e r a u t o i n c r e m e n t m e m o r y w o r d a d d r e s s a t t h i s m o m e n t m a s t e r - t r a n s m i t t e r b e c o m e s m a s t e r r e c e i v e r a n d i n 1 3 6 3 s l a v e - r e c e i v e r b e c o m e s s l a v e - t r a n s m i t t e r n b y t e a u t o i n c r e m e n t m e m o r y w o r d a d d r e s s l a s t b y t e n o a c k n o w l e d g e m e n t f r o m m a s t e r s s l a v e _ a d d r e s s d a t a d a t a a 1 p a c k n o w l e d g e m e n t f r o m s l a v e a c k n o w l e d g e m e n t f r o m m a s t e r n o a c k n o w l e d g e m e n t f r o m m a s t e r n b y t e l a s t b y t e r / w a u t o i n c r e m e n t w o r d a d d r e s s a u t o i n c r e m e n t w o r d a d d r e s s s : s t a r t a : a c k n o w l e d g e d r e c e i v i n g p : s t o p a : r e c e i v i n g i s n o t a c k n o w l e d g e d IN1363 17 aug 2012 , ver.0 5 package dimension sop 8 (ms - 012aa) IN1363 18 aug 2012 , ver.0 5 m sop - 8 IN1363 19 aug 2012 , ver.0 5 test fixture for IN1363 & in1 307 application note ik semicon IN1363 20 aug 2012 , ver.0 5 1. t est fixture overview in order to supply convenient method for rtc test , ik - semicon prepared test fixture. its controlled by silabs mcu c8051f410 , user can rtc test by using this fixture. 1.1. installing the har dware IN1363/in1307 is an ic compatible real time clock (rtc). as an application example, it demonstrates how to setup the rtc . this application note explain how to set the register value into a date and time value that can be put in the following form [yy]:[ mm] :[ dd ]:[hh]:[ mm] :[ss]. 1.2. major components f ig 1. test board schematic IN1363 21 aug 2012 , ver.0 5 fig 2 top view of test fixture fig 3 layout of test fixture . socket rs232c socket and pcb should be aligned in the same direction. adapter (main power ? 2400ma polarity + polarity - initial switch programming writing connector s i l a b s c 8 0 5 1 f 4 1 0 r s 2 3 2 c m a x 3 2 2 3 e l e d i n 1 3 0 7 i n 1 3 6 3 i n 1 3 0 7 s o c k e t i n 1 3 0 7 s o c k e t 3 2 . 7 6 8 k h z 3 2 . 7 6 8 k h z t p 1 t p 2 t p 3 t p 4 t p 5 t p 6 t p 7 t p 8 t p 1 1 t p 1 2 t p 1 3 t p 1 4 t p 1 5 t p 1 6 t p 1 0 t p 9 a b c e f f h i j k d i n 1 3 6 3 s o c k e t i n 1 3 6 3 s o c k e t IN1363 22 aug 2012 , ver.0 5 1.3. basic specification a. 12v dc - jack : power termi nal this power terminal normally is connected to the 12v power supply. b. init switch this switch initialize time to 23 july 2012, current time to 14:03:02(IN1363) . c. led this led blinking every 1 seconds. if there is a power on the test fixture. d. test point in/output pin of the mcu is connected. i f need the user, use as the test pin. e. debugger connector this test program exchanges with pc(personal computer) through this debugger connector. f. rs232c female connector user can see the test time through this c onnector. g. 32.768khz connection of the standard quartz resonator for the frequency 32.768khz. IN1363 can operate from external oscillator with the frequency 32.768khz note : to oscillation the 32.768khz , reset to the bit test1 h. in1307_bat if you tes t the in1307, c onnect battery on the in1307_bat. i. IN1363_bat if you test the IN1363, c onnect battery on the IN1363_bat n ote: although the power eliminate , the real time clock is working if the battery is connected on the in1307/IN1363_bat j. IN1363_socket to test of IN1363 rtc, it should select IN1363_socket. k. in1307_socket to test of in1307 rtc, it should select in1307_socket. n ote: to avoid any confusion by program selector, only one ic should be selected by socket. IN1363 23 aug 2012 , ver.0 5 2. r eal t ime c lock p rogram 2.1. f low chart fig 3. f low chart for IN1363 p o w e r o n : i n 1 3 6 3 i n 1 3 6 3 i n i t i a l i z e w r i t e d a t a * b i t t e s t 1 = 0 s w p r e s s d t e : 9 6 0 0 b p s r t c d i s p l a y r e a d d a t a : a d d r e s s 0 x 0 0 y e s ( r e a d d a t a & 0 x 8 0 ) = = 0 n o r e a d d a t a : a d d r e s s f r o m 0 x 0 2 t o 0 x 8 n o y e s i n 1 3 6 3 i n i t i a l i z e w r i t e d a t a t e s t 1 b i t = 0 ; a d d r e s s , d a t a 0 x 0 2 , 0 x 0 2 a d d r e s s , d a t a 0 x 0 3 , 0 x 0 3 a d d r e s s , d a t a 0 x 0 4 , 0 x 1 4 a d d r e s s , d a t a 0 x 0 5 , 0 x 2 3 a d d r e s s , d a t a 0 x 0 7 , 0 x 0 7 a d d r e s s , d a t a 0 x 0 8 , 0 x 1 2 1 2 [ y y ] : 0 7 [ m m ] : 2 3 [ d d ] : 1 4 [ h h ] : 0 3 [ m m ] : 0 2 [ s s ] d t e : c o n t i n u e s t a r t a t 1 3 6 3 a c k r e c e i v e d y e s d t e : i n i t i a l i z e b y m e m o r y n o d a t a y e s d t e : i n i t i a l i z e b y s w p r e s s y e s i n 1 3 6 3 i n i t i a l i z e w r i t e d a t a d t e : i 2 c e r r o r n o a c k n o a c k r e c e i v e d n o d t e : r t c n o a c k i n r e a d y e s IN1363 24 aug 2012 , ver.0 5 fig 4. f low chart for in1307 p o w e r o n : i n 1 3 0 7 i n 1 3 0 7 i n i t i a l i z e w r i t e d a t a * b i t c h = 0 s w p r e s s d t e : 9 6 0 0 b p s r t c d i s p l a y r e a d d a t a : a d d r e s s 0 x 0 0 y e s ( r e a d d a t a & 0 x 8 0 ) = = 0 n o r e a d d a t a : a d d r e s s f r o m 0 x 0 0 t o 0 x 0 6 n o y e s d t e : c o n t i n u e s t a r t a t 1 3 0 7 a c k r e c e i v e d y e s d t e : i n i t i a l i z e b y m e m o r y n o d a t a y e s d t e : i n i t i a l i z e b y s w p r e s s y e s i n 1 3 0 7 i n i t i a l i z e w r i t e d a t a d t e : i 2 c e r r o r n o a c k n o a c k r e c e i v e d n o d t e : r t c n o a c k i n r e a d y e s i n 1 3 0 7 i n i t i a l i z e w r i t e d a t a c h b i t = 0 ; a d d r e s s , d a t a 0 x 0 0 , 0 x 0 5 a d d r e s s , d a t a 0 x 0 1 , 0 x 1 0 a d d r e s s , d a t a 0 x 0 2 , 0 x 1 3 a d d r e s s , d a t a 0 x 0 3 , 0 x 0 5 a d d r e s s , d a t a 0 x 0 4 , 0 x 1 5 a d d r e s s , d a t a 0 x 0 5 , 0 x 0 6 a d d r e s s , d a t a 0 x 0 6 , 0 x 1 2 a d d r e s s , d a t a 0 x 0 7 , 0 x 0 0 1 2 [ y y ] : 0 6 [ m m ] : 1 5 [ d d ] : 5 [ d a y ] : 1 3 [ h h ] : 1 0 [ m m ] : 5 [ s s ] IN1363 25 aug 2012 , ver.0 5 2.2. register set up for IN1363 2.2.1. initialization register setting up it is necessary to enable the generation (bit test1 = 0) when setting the initial configurations . . register address register name initialize write data contents 0x00h control/status 1 0x00 test1 bit = 0 (normal mode) stop bit = 0 (rtc source clock) testc bit = 0 (normal op) 0x01h control/status 2 0x0 0 aie bit = 0 (alarm int disabled) tie bit = 0 (timer int disabled) 0x0dh clkput control - 0x0eh timer control - 0x0fh timer - 2.2.2 timer register setting up register address register name initialize write data contents 0x02h seconds 0x02 0x 03h minutes 0x03 0x04h hours 0x14 0x05h dates 0x23 0x06h day of week - sunday=0,monday=1,tuesday=2, wednesday=3,..., saturday=6 0x07h century/month 0x07 bit7 c of the months/century register indicates century for year 19xx (bit7=1), and year 20x x (bit7=0). 0x08h year 0x12 0x09h minute alarm - 0x0ah hour alarm - 0x0bh date alarm - 0x0ch weekday alarm for example, we want to set the date for 23 july 2012, current time to 12:03:02, and then we need to call. 1. seconds setup : rtc_write( seconds, 0x02); 2. minutes setup : rtc_write( minutes, 0x03); 3. hours setup : rtc_write( hours, 0x14); 4. dates setup : rtc_write( dates, 0x23); 5. month setup : rtc_write( month, 0x07); 6. year setup : rtc_write( year, 0x12); IN1363 26 aug 2012 , ver.0 5 2.3 register set u p for in1307 2.3.1. initialization register setting up it is necessary to enable the generation (bit ch = 0) when setting the initial configurations.. register address register name initialize write data contents 0x00h.bit8 control/status 1 0x00 ch bit = 0 (normal mode) 2.3.2 timer register setting up register address register name initialize write data contents 0x00h seconds 0x05 0x01h minutes 0x10 0x02h hours 0x13 0x03h day 0x05 range 1 - 7 0x04h date 0x15 0x05h month 0x06 0x06h yea r 0x12 0x07h control for example, we want to set the date for 23 june 2012, current time to 13:10:05, and then we need to call. 1. seconds setup : rtc_write( 0x00 , 0x0 5 ); 2. minutes setup : rtc_write( 0x01, 0x10); 3. hours setup : rtc_write( 0x02, 0 x13); 4. day setup : rtc_write( 0x03, 0x05); 5. dates setup : rtc_write( 0x04, 0x15); 6. month setup : rtc_write( 0x05, 0x06); 7. year setup : rtc_write (0x06 , 0x12); IN1363 27 aug 2012 , ver.0 5 2.4 hyper terminal configuration 1. bits per second : 9600 bps 2. data bit : 8 bit 3. parity bit : none 4. s top bits : 1 bit 5. flow control : none fig 5. e xample test program for IN1363 IN1363 28 aug 2012 , ver.0 5 run the serial terminal and make sure the baud rate is set correctly at 9600bps fig 6. IN1363 rtc data on serial terminal fig 7. in1307 rtc data on s erial terminal IN1363 29 aug 2012 , ver.0 5 3. example source for rtc this documentation shows an example of a main function to setup and read/write data. i f you request example source code, we can provide source codes. 3.1. read current time from IN1363 & in1307 ? slave address of IN1363 = 0xa2 ? slave address of in1307 = 0xd0; 3.2.write set time for IN1363 & in1307 IN1363 30 aug 2012 , ver.0 5 3.3. i2c example source for IN1363 & in1307 #ifdef IN1363 sbit scl = p 1 ^ 7 ; sbit sda = p 1 ^ 6 ; // #endif #ifdef in1307 sbit sda = p0^2; sbit scl = p0^ 1; #endif void i2c_start(void) / / start condition { sda = high; delaytimeloop(); scl = high; delaytimeloop(); sda = low; delaytimeloop(); scl = low; delaytimeloop(); } void i2c_stop(void) // stop condition { scl = high ; delaytimeloop(); sda = high; delaytimeloop(); } /* clock pulse generation. the function returns data or acknowledgment bit */ unsigned char i2c_clock(void)//bit i2c_clock(void) { bit level; // state of sda line scl = 1; d elaytimeloop(); while (!scl); // if a pulse was stretched delaytimeloop(); level = sda; delaytimeloop(); scl = 0; return (level); } /* writing a byte to a slave, with most significant bit first. the function returns acknowledgment bit.*/ unsigne d char i2c_write(unsigned char byte) { unsigned char mask = 0x80; unsigned char aaa; while (mask) { IN1363 31 aug 2012 , ver.0 5 if (byte & mask) sda = 1; else sda = 0; i2c_clock(); mask >>= 1; } aaa = i2c_clock(); return (aaa); } /* reading byte from a slave, wi th most significant bit first. the parameter indicates, whether to acknowledge (1) or not (0) */ unsigned char i2c_read(unsigned char acknowledgment) { uchar mask = 0x80, byte = 0x00; while (mask) { if (i2c_clock()) byte |= mask; mask >>= 1; / * next bit to receive */ } if (acknowledgment) { sda = 0; i2c_clock(); sda = 1; } else { sda = 1; i2c_clock(); } return (byte); } unsigned char rtc_read_7_byte(unsigned char addr) { unsigned char status , i; i2c_start(); if (!i2c_wr ite( 0xa2 )){ //0xa2 is slave address for IN1363, 0xd2 is for in1307 delaytimeloop(); if (!i2c_write(addr)){ i2c_start(); if (!i2c_write( 0xa2 | 0x01)){ in1307 s slave address is 0xd2 for(i=0;i<6;i++){ receive_data[i] = i2c_read(1); } receive_data[6] = i2c_read(0); } else { status = 1; } } else{ status = 1; IN1363 32 aug 2012 , ver.0 5 } } else status = 1; i2c_stop(); return(status); } IN1363 33 aug 2012 , ver.0 5 4. test procedure for rtc 4.1. test procedure for IN1363 1. make sure tha t test fixture is power off. 2. place IN1363 on IN1363_socket of test fixture. 3. connect the battery on IN1363_bat. 4. run the serial terminal and make sure the baud rate is set correctly at 9600bps 5. after turning on the power of test fixture, identify whether gre en led of status indic ator is flickering. if that s flickering every 1s, it indicates IN1363 working . method fo r the program is refer to the chapter 2. 6. data is displayed in serial terminal window like to fig6. refer to fig 6 7. and then test fixture is power off. 8. wait for a period of time ( two hours, 10 minutes, etc .). 9. turn the test fixture on again, and check the time. the amount time as power off is p assed . 4.2. test procedure for in1307 1. make sure that test fixture is power off. 2. place IN1363 on in1307_ socket of test fixture. 3. connect the battery on in1307_bat. 4. run the serial terminal and make sure the baud rate is set correctly at 9600bps 5. after turning on the power of test fixture, identify whether green led of status indic ator is flickering. if that s flickering every 1s, it indicates in1307 working . method fo r the program is refer to the chapter 2. 6. data is displayed in serial terminal window like to fig7. refer to fig 7 7. and then test fixture is power off. 8. wait for a period of time ( two hours, 10 minut es, etc .). 9. turn the test fixture on again, and check the time. the amount time as power off is p assed . |
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