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| automotive power data sheet rev. 1.1, 2015-02-15 6 a h-bridge with spi IFX9201SG
data sheet 2 rev. 1.1, 2015-02-15 IFX9201SG table of contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.3 terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.1 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.2 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.3 output stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.4 protection and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.5 current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.6 short circuit to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.7 short circuit to supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.8 short circuit over load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.9 overtemperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.10 undervoltage shut-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.11 open load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.12 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 general product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2 functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.3 thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table of contents pg-dso-12-17 type package marking IFX9201SG pg-dso-12-17 IFX9201SG data sheet 3 rev. 1.1, 2015-02-15 6 a h-bridge with spi IFX9201SG 1overview features ? r dson of 100 m per switch typ. at tj=25 c ? logic inputs 3.3 v and 5.0 v ttl/cmos-compatible ? low standby current ? chopper current limitation ? short circuit shut down with latch behavior ? overtemperature shut down with latch behavior ? vs undervoltage shutdown ? open load detection in on and off state ? detailed spi diagnosis or simple error flag ? green product (rohs compliant) description the IFX9201SG is a general purpose 6 a h-bridge, designed for the control of dc motors or other inductive loads. the outputs can be pulse width modulated at frequencies up to 20khz. pwm/dir cont rol reduces the number of pwm capable pins needed on the microcontroler side. for load currents above the current limitation threshold (8 a typ.) the h-bridge goes into chopper current limitation mode. it is protected against short circuits and overtem perature and provides extensiv e diagnosis via spi or basic feedback via error flag. open load can be detected when the bridge is disabled or during pwm operation of inductive loads. the robust pg-dso-12-17 pack age provides excellent ther mal capabilites due to the thick copper heat slug. thanks to the protruding edges of the heatslug the package is well suited for automatic optical solder inspection. the IFX9201SG is not qualified and manufactured accordin g to the requirements of infineon technologies with regards to automotive and/or transpor tation applications. for automotive applications please refer to the tle9201sg. data sheet 4 rev. 1.1, 2015-02-15 IFX9201SG pin configuration 2 pin configuration 2.1 pin assignment figure 1 pin assignment IFX9201SG 2.2 pin definitions and functions pin symbol function 1 dir direction input to define direction of the motor current 2 vso supply pin for so output. connect to 5v or 3.3v depending on desired logic level 3 so spi serial output 4 vs supply voltage 5 out1 output 1 6 gnd ground 7 out2 output 2 8 si spi serial input 9 csn spi chip select (low active) 10 sck spi clock input 11 dis disable. disables the outputs (all mosfets off) 12 pwm pulse width modulation input (top view ) dis sck csn si pwm out2 12 11 10 9 8 7 vso so vs out1 dir gnd 1 2 3 4 5 6 heat slug (gnd) IFX9201SG pin configuration data sheet 5 rev. 1.1, 2015-02-15 2.3 terms figure 2 terms IFX9201SG csn pwm so vso dis dir out1 gnd vs out2 v vso i so i pw m i dir i dis i vso v so v pw m v dir v dis v sc k i out1 i out2 v out2 v out1 i vs v vs sck si i si v si i sc k i csn v csn data sheet 6 rev. 1.1, 2015-02-15 IFX9201SG block diagram 3 block diagram figure 3 block diagram csn sck pwm vso dis dir out1 gnd vs out2 control logic gate driver current monitor internal supply charge pump temperature monitor si so IFX9201SG block description data sheet 7 rev. 1.1, 2015-02-15 4 block description 4.1 power supply all internal supply voltages are derived from the pin vs. a charge pump provides the gate voltage for the high side switches. the charge pump does not require an external capacitor. the output buffer of the digital output so is supplied by the pin vso. therefore the outpu t level at so can be easily configured for 3.3 v or 5 v logic by c onnecting vso to the respective voltage. 4.2 sleep mode in order to minimize current consumpt ion during inactive phases the device can be put into sleep mode by pulling the vso pin to gnd. this functionality can also be used to provide a second switch off path for the outputs similar to an enable pin, simply by driving vso directly from a microcontroller output. since vso is supplying also th e output buffer of the so signal it has to be ensured that the microcontroller output can provide sufficient current. alternatively an external mosf et or a driver stage could be used to switch the vso supply voltage. to account for dynamic switching curren ts it might be advisable to buffer vso with a small capacitor (see figure 7 ?application example vso as enable input? on page 24 ). please note that the push pull stage of the so output prov ides a current return path to vso via the bulk diode of the highside mosfet. therefore it has to be ensured that the voltage at so never exceeds the voltage at vso by more than 0.3v. figure 4-1 so output buffer vso so spi_serial_ out sleep _mode v_ vso_sleep + - data sheet 8 rev. 1.1, 2015-02-15 IFX9201SG block description 4.3 output stages the output stages consist of four n-channel mosfets in h- bridge configuration. the ou tputs are protected against short circuits and over temperature. the bridge is controlled using the inputs pwm and dir. th e signal at dir is defining the direction of the driven dc motor whereas the pwm signal sets the duty cycle. the outputs can be set tristate (i.e. high side and low side switches are turned off) by setting dis to high level. figure 4-2 operation modes table 4-1 output truth table dis pwm dir out1 out2 comment 1 x x z z disabled, outputs tristate 0 1 1 h l forward / clockwise 0 1 0 l h reverse / counterclockwise 0 0 1 h z freewheeling in hs (forward) 0 0 0 z h freewheeling in hs (reverse) hs1 on m ls 1 off hs2 off ls2 on dir=1, pwm=1 forward i l hs1 off m ls1 on hs2 on ls 2 off dir=0, pwm=1 reverse i l hs1 on ls 1 off dir=1, pwm=0 freewheeling through hs 2 body diode (forward ) m hs2 off ls 2 off i l dir=0, pwm=0 freewheeling through hs 1 body diode ( rever se ) hs1 off m ls 1 off hs2 on ls 2 off i l IFX9201SG block description data sheet 9 rev. 1.1, 2015-02-15 4.4 protection and diagnostics both output stages of the IFX9201SG ar e equipped with fault diagnostic functions: ? short to supply voltage (scvs) ? short to ground (scg) ? open load (ol) ? over-temperature (ot) 4.5 current limitation to limit the output current a chopper current limitation is integrated. current measurement for current limitation is done in the high side path. figure 4-3 chopper current limitation figure 4-3 shows the behavior of the current limitation for over current detection in hs 1. it applies accordingly also for hs2. when the current in high-side switch of out1 (hs1) exceeds the limit i l longer than the blanking time t b , the low side switch of out2 (ls2) is switched off, independent of the input signal at pwm. this leads to freewheeling through the bulk diode of hs2 and therefore to a decrease of the load current. as soon as the current falls below i l , out2 is switched back to normal ope ration, i.e. the outputs follow the inputs according to the truth table. to avoid high switching frequencies in case of low inductiv e loads the minimum time between two transitions is limited to t trans . i out time i l t trans t b hs1 m ls 1 hs2 ls2 data sheet 10 rev. 1.1, 2015-02-15 IFX9201SG block description 4.6 short circuit to ground figure 4-4 short to ground detection the short circuit to ground detection is activated when the current through one of the high side switches rises over the threshold i sc and remains higher than i sc for at least the filter time t sdf within the blanking time t b . both outputs will be switched off and the fa ilure will be reported in the spi diagnosis register. the outputs can be re-activated by disabling and enabling the bridge via the disable sign al dis, pulling vso to gnd or by a reset command via spi. 4.7 short circuit to supply a short circuit to the supply voltage vs is detected in the same way as a short circuit to ground, only in the low side switch instead of the high side switch. 4.8 short circuit over load short circuit over load will trigge r the short circuit detec tion either of the hi gh side or the low side switch (whichever is faster). 4.9 overtemperature in case of high dc-currents, insufficient cooling or high ambient temperature, the chip temperature may rise above the thermal shut-down temperature t jsd . in that case, all output transistors are turned off. overtemperature shutdown is latching. the outputs can be re-activated as soon as the junction temperature has fallen below the switch-on temperature t jso . i out i l time t b i sc pwm t sdf t < t b out1 current both outputs off current tracking current limitation, freewheeling in hs short dir tristate out2 tristate tristate short circuit detected IFX9201SG block description data sheet 11 rev. 1.1, 2015-02-15 4.10 undervoltage shut-down if the supply voltage at the vs pins falls below the undervoltage detection threshold v uv_off , the outputs are turned off. the undervoltage detection is not latching. that means that as soon as v s rises above v uv_on again, the device is returning to normal operation. 4.11 open load detection 4.11.1 open load detection in off state when the bridge is disabled (dis=high) the open load in off detection becomes acti ve. two diagnostic current sources will then be connected to the outputs, a pull up curr ent source at out1 and a pull down current source at out2. the pull down current so urce is stronger than the pull up curr ent source and therefore will pull down out1 if a load is present. if no load is present out1 will be pulled high by the pull up curr ent source. this is detected by a comparator and reported in the spi diagnosis register. please note that capacitors that might be placed at th e outputs for emc reasons first have to be discharged by the pull down current source at out2 for the open load detection to work properly. also, if current is flowing th rough the load at the time of disabling th e freewheeling current will force the outputs towards supp ly voltage v s . this may lead to an erroneous reporting of open load. therefore the first diagnostic reading after disabling shou ld be discarded and a second reading should be taken after the load is deenergized and the outpu t capacitors are discharged completely. the open load detection can be disabl ed by setting the oldis bit in the ctrl_reg register. this will disconnect the diagnostic current sources and suppress the re porting of open load in the dia_reg register. figure 4-5 open load detection in off state 4.11.2 open load detection in on state the IFX9201SG contains an open load diagnosis during ope ration for inductive loads. it evaluates whether freewheeling occurs in the switching phase. in order to avoid inadvertent triggering of the open load diagnosis a failure counter is implemented. there have to be at least 5 occurances of the internal open load signal (i.e. 5 pwm pulses without freewheeling detected) before open lo ad is reported in the spi diagnosis register. depending on the operation conditions and on external circui try like the output capacitors it is possible that open load is indicated although the load is present. this might be the case for example during a direction change or for small load currents respectively sma ll pwm duty cycles. therefore it is recommended to evaluate the open load diagnosis only in known suitable operating conditions and to ignore it otherwise. the open load diagnosis is not latching. 5v int. + - v ref_ol out1 ol out2 m data sheet 12 rev. 1.1, 2015-02-15 IFX9201SG block description 4.12 serial periphera l interface (spi) for diagnosis purposes the IFX9201SG is equipped with a ?serial peripheral interface? (spi). the spi of several IFX9201SGs can be connected in daisy chain configuration in order to save microcontroller interface pins. the IFX9201SG is configured as a ?slave? device. this means that the c as the master is providing the chip select (csn) and clock signal (sck). a data transfer on the spi bus is initiaded with a falling ed ge on csn and is terminated by a rising edge on csn. the data on the serial input pin si is sampled with the falling edge of sck, the seri al data output at so is determined by the rising clock edge. the data is transferred ?msb first?. the word length of the spi is 8 bit. please note that t here is no check for the number of clocks within a spi frame. any low pulse at csn will be regarded as one frame. 4.12.1 error flag between the falling edge of csn and the first rising edge of sck an additional er ror flag signal is set asynchronously at the so pin. the error flag signal set to high whenever the output stag es are shut down (tristate) due to a failure or due to disabling of the output stages. additionally the ef signal is or?ed with the si input signal. by connecting the so of one device to the si of the next device the ef signal can be routed through similar to a spi daisy chain configuration. this flag can be used for simple error feedback with out spi communication by con necting sck and csn to gnd permanently (see figure 5 ?application example h-bridge with error flag? on page 22 ). figure 4-6 spi timing definiti on (drawing not to scale) 10 2 3 4 5 6 7 10 2 3 4 5 6 7 ef z z csn sck si so command n si: data will be accepted on the falling edge of sck -signal so: state will change on the rising edge of sck-signal answer to command n-1 10 9 2 1 3 8 5 6 7 ef 4 IFX9201SG block description data sheet 13 rev. 1.1, 2015-02-15 4.12.2 spi register description the IFX9201SG provides detailed diagnosis and the opti on to control the outputs via spi. following commands are available (x=don?t care, d=data): the first spi response provided after power up is the device revision number (rd_ rev). for any unspecified commands the device will respond with the cont ent of the diagnosis register (rd_dia). the registers are addressed wordwise. table 4-2 spi command set command input byte description rd_dia 000x xxxx read diagnosis register res_dia 100x xxxx reset diagnosis register rd_rev 001x xxxx read device revision number rd_ctrl 011x xxxx read control register wr_ctrl 111d dddd write control - sets and returns control register values wr_ctrl_rd_dia 110d dddd write control and read diagnosis- sets control register values and returns diagnosis register values data sheet 14 rev. 1.1, 2015-02-15 IFX9201SG block description 4.12.2.1 control register control register ctrl_reg offset reset value controlregister 01 h 00 h field bits type description cmd 7:5 rw command 011: rd_ctrl 110: wr_ctrl_rd_dia 111: wr_ctrl oldis 4 rw open load disconnect 1: open load current source disconnected. sin 3 rw spi control 0: control outputs via pwm/dir inputs 1: control outputs via spi note: can only be set if dis=0 and pwm=0 and dir=0. any change of the dis, pwm or dir signals will reset this bit and revert to standard control via pwm/dir sen 2 rw 1: enable outputs in case of spi control (sin=1) 0: disable outputs in ca se of spi control (sin=1) sdir 1 rw dir signal in case of spi control (sin=1) spwm 0 rw pwm signal in case of spi control (sin=1) 7 0 75 rw cmd 4 4 rw oldis 3 3 rw sin 2 2 rw sen 1 1 rw sdir 0 0 rw spwm IFX9201SG block description data sheet 15 rev. 1.1, 2015-02-15 4.12.2.2 diagnosis register diagnosis register diagnosis truth table the short circuit and vs undervoltage diagnosis is coded in the dia bits according to the following truth table. together with transmission valid ation bit tv (always 0) it is ensured that there is always at least one 1->0 change at so during a valid transmission. therefore a ?s tuck at? failure of the so pin can be detected. dia_reg offset reset value diagnosis register 00 h df h field bits type description en 7 r 1= outputs enabled by low signal on pin dis 0 = outputs disabled by high signal on pin dis ot 6 r 0 = overtemperature shutdown tv 5 r always 0 - used for transmission validation cl 4 r 0 = current limitation active dia4 3 r diagnosis bit 4 dia3 2 r diagnosis bit 3 dia2 1 r diagnosis bit 2 dia1 0 r diagnosis bit 1 table 4-3 encoding of diagnosis bits (sorted by hex value, only listed combinations are valid) type dia4 dia3 dia2 dia1 hex comment no failure 1 1 1 1 0xf - short to gnd at out1 (scg1) 1 1 1 0 0xe latched short to vs at out1 (scvs1) 1 1 0 1 0xd latched open load (ol) 1 1 0 0 0xc not latched short to gnd at out2 (scg2) 1 0 1 1 0xb latched short to gnd at out1 and out2 (scg1, scg2) 1 0 1 0 0xa latched short to vs at out1 and short to gn d at out2 (scvs1, scg2) 1 0 0 1 0x9 latched short to supply at out2 (scvs2) 0 1 1 1 0x7 latched short to gnd at out1 and short to vs at out2 (scg1, scvs2) 0 1 1 0 0x6 latched short to vs at out1 and out2 (scvs1, scvs2) 0 1 0 1 0x5 latched vs undervoltage (vs_uv) 0 0 1 1 0x3 not latched 7 0 7 7 r en 6 6 r ot 5 5 r tv 4 4 r cl 3 3 r dia4 2 2 r dia3 1 1 r dia2 0 0 r dia1 data sheet 16 rev. 1.1, 2015-02-15 IFX9201SG block description reset behavior of diagnosis register the diagnosis register is reset by the following events a change of the dir signal will lead to a reset of current limitation (cl) or open load in on (o l) error messages. the open load in on failure will also be reset automatically if th e open load condition no longer persits, i.e. freewheeling is detected for five or more consecutive pulses. 4.12.2.3 revision register the revision register contains the device revision corresponding to the mask set. revision register table 4-4 diagnosis reset types name type comment por power on reset reset due to power up, undervoltage or sleep mode enr enable reset reset due to disabling/enabling of the outputs by dis pin or bit sen in ctrl_reg spir spi reset reset by sending the res_dia command via spi rev_reg offset reset value revision register 01 h 00 h field bits type description 07r fixed to 0 06r fixed to 0 15r fixed to 1 04r fixed to 0 rev 3:0 r device revision corresponding to mask set 7 0 7 7 r 0 6 6 r 0 5 5 r 1 4 4 r 0 30 r rev IFX9201SG general product characteristics data sheet 17 rev. 1.1, 2015-02-15 5 general product characteristics 5.1 absolute maximum ratings notes 1. stresses above the ones listed here may cause perma nent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. integrated protection func tions are designed to prevent ic destructi on under fault conditions described in the data sheet. fault conditions are considered as ?outside? normal operating range. pr otection functi ons are not designed for continuous repetitive operation. table 1 absolute maximum ratings 1) t j = -40 c to 125 c; (unless specified otherwise) 1) not subject to production test, specified by design. parameter symbol values unit note / test condition number min. typ. max. junction temperature t j -40?150c ? p_5.1.1 storage temperature t s -55?150c ? p_5.1.2 supply voltage v vs -0.3 ? 40 v ? p_5.1.4 supply for logic output v vso -0.3 ? 5.5 v ? p_5.1.5 voltage at logic inputs v in -0.3 ? 5.5 v ? p_5.1.6 voltage at logic output so v so -0.3 ? v vso +0.3 v both conditions must be observed p_5.1.7 -0.3 ? 5.5 esd susceptibility esd susceptibility to gnd acc. hbm v esd -2 ? 2 kv hbm 2) 2) esd susceptibility hbm accordi ng to eia/jesd22-a114-b (1.5k ? , 100pf) p_5.1.8 esd susceptibility to gnd acc. cdm v esd -500 ? 500 v cdm 3) 3) esd susceptibility, charged devi ce model ?cdm? eia/jesd22-c101 p_5.1.9 esd susceptibility to gnd acc. cdm, corner pins v esd -750 ? 750 v cdm 3) , corner pins p_5.1.10 IFX9201SG general product characteristics data sheet 18 rev. 1.1, 2015-02-15 5.2 functional range note: within the functional or operating range, the ic operat es as described in the circuit description. the electrical characteristics are specif ied within the conditions given in th e electrical char acteristics table. 5.3 thermal resistance note: this thermal data was generated in accordance wit h jedec jesd51 standards. fo r more information, go to www.jedec.org . table 2 functional range 1) 1) not subject to production test, specified by design. parameter symbol values unit note / test condition number min. typ. max. supply voltage range v s v uv_off ?36v? p_5.2.1 v s supply voltage slew rate d v s /d t -10 ? 10 v/s ? p_5.2.2 so buffer supply voltage v so 2.9 ? 5.5 v ? p_5.2.3 junction temperature t j -40 ? 125 c ? p_5.2.4 table 3 thermal resistance 1) 1) not subject to production test, specified by design. parameter symbol values unit note / test condition number min. typ. max. junction to case r thjc ??2k/w? p_5.3.1 junction to ambient r thja ?30?k/w 2) 2) specified r thja value is according to jedec jesd51-2,-5,-7 at natural convection on fr4 2s2p board; the product (chip+package) was simulated on a 76.2 114.3 1.5 mm boar d with 2 inner copper layers (2 70 m cu, 2 35 m cu). where applicable a thermal via array under the exposed pad contacted the first inner copper layer. p_5.3.2 IFX9201SG electrical characteristics data sheet 19 rev. 1.1, 2015-02-15 6 electrical characteristics table 4 electrical characteristics v vs = 8 v to 36 v; v vso = 5.0 v; t j = -40 c to 125 c; (unless specified otherwise) parameter symbol values unit note / test condition number min. typ. max. supply supply current i vs ?513ma f pwm = 2 khz; i out = 0 a; v vs =13.5v; p_6.0.1 supply current sleep mode i vs ?1930a v vs = 13.5 v ; v vso = 0 v ; v outx = 0 v; t j = 25 c p_6.0.2 vso sleep mode threshold v vso_sleep 0.5 ? 2.0 v ? p_6.0.4 vso input current, csn high i vso ??100a i so =0 a ; v csn > 2 v p_6.0.5 vso input current, csn low i vso ??1.0ma i so =0 a ; v csn = 0 v p_6.0.6 vs undervoltage undervoltage at vs v uv off 3.5 4.2 5.0 v switch off threshold p_6.0.7 undervoltage at vs v uv on 3.6 4.4 5.2 v switch on threshold p_6.0.8 undervoltage at vs v uv hy 100 200 500 mv hysteresis p_6.0.9 vs undervoltage detection filter time 1) t uv ?1? s? p_6.0.10 inputs pwm, dir, sck, si low level v input_l ??0.8v? p_6.0.11 high level v input_h 2.0 ? ? v ? p_6.0.12 hysteresis v input_hys 0.1 0.3 ? v ? p_6.0.13 pull down current i in_pd 93885a v in = 5.5 v p_6.0.14 input capacity 1) c in ? ? 15 pf v bias = 2 v; v test = 20 mvpp; f = 1 mhz p_6.0.15 inputs dis, csn low level v input_l ??0.8v? p_6.0.16 high level v input_h 2.0 ? ? v ? p_6.0.17 hysteresis v input_hys 0.1 0.3 ? v ? p_6.0.18 pull up current i in_pu 93885a v in = 0 v p_6.0.19 input capacity 1) c in ? ? 15 pf v bias = 2 v; v test = 20 mvpp; f = 1 mhz p_6.0.20 data sheet 20 rev. 1.1, 2015-02-15 IFX9201SG electrical characteristics output so low level v so_l 0.0 ? 0.4 v i so = -1 ma p_6.0.21 high level v so_h v vso - 0.75 ? v vso v i so = 1 ma ; 2.9 v < v vso < 5.5 v p_6.0.22 tristage leakage current i so -5 ? 5 a 0v < v so < v vso ; v vso = 5.5 v p_6.0.23 output capacity 1) c so ? ? 19 pf v bias = 2 v; v test = 20 mvpp; f = 1 mhz p_6.0.24 power outputs out1, out2 on resistance low side r outl ?100? m ? i out =2a; t j = 25 c p_6.0.25 ??200m ? i out =2a; t j = 125 c on resistance high side r outh ?100? m ? i out =2a; t j = 25 c p_6.0.26 ??200m ? i out =2a; t j = 125 c leakage current i out1(off) i out2(off) -25 ? 25 a v vs =13.5v; outputs off; oldis high p_6.0.27 -100 ? 25 a v vs =13.5v; sleep mode free-wheel diode forward voltage u d ?0.91.0v i d = 2 a p_6.0.28 output switching times 2) voltage slew rate hs dv out /dt 0.20 ? 1.62 v/s v vs = 13.5 v; r load =6.8 ? p_6.0.29 voltage slew rate ls dv out /dt 1.15 ? 8.1 v/s p_6.0.31 pwm frequency 1) f pwm 0?20khz? p_6.0.33 output delay times 2) output on-delay hs t d_on(hs) ??80s v vs =13.5v; r load =6.8 ? p_6.0.34 output off-delay hs t d_off(hs) ??80s p_6.0.35 output on-delay ls t d_on(ls) ??10s p_6.0.36 output off-delay ls t d_off(ls) ??10s p_6.0.37 disable delay time t d_dis ??80s p_6.0.38 enable delay time t d_en ??80s p_6.0.39 disable/enable filter time 1) t f_en 0.4 ? 3 s p_6.0.40 wake up delay time 1) t wu ? ? 1 ms vso high --> out high p_6.0.41 chopper current limitation current limit i l 6.0 8.0 10.0 a v vs =13.5v p_6.0.42 blanking time 1) t b 5813s? p_6.0.43 minimum transition time 1) t trans ?95? s? p_6.0.44 table 4 electrical characteristics v vs = 8 v to 36 v; v vso = 5.0 v; t j = -40 c to 125 c; (unless specified otherwise) parameter symbol values unit note / test condition number min. typ. max. IFX9201SG electrical characteristics data sheet 21 rev. 1.1, 2015-02-15 short circuit detection short circuit detection threshold high side switch i sc_h 8.0 11.5 14.5 a v vs =13.5v p_6.0.45 short circuit detection threshold low side switch i sc_l 8.0 11.5 14.5 a p_6.0.46 current tracking high side i sc_h - i l 2.0 4.0 5.2 a p_6.0.47 current tracking low side i sc_l - i l 1.8 3.5 5.2 a p_6.0.48 short circuit de tection filter time 1) t sdf ?2? s? p_6.0.49 open load detection in off state pull up current at out1 i out1_ol 60 140 200 a v vs =13.5v; v out1 = 0v p_6.0.50 pull down current at out2 i out2_ol 200 350 500 a v vs = v out2 = 13.5 v p_6.0.51 ratio of current sources ratio_i ol 1.8 2.5 3.5 ? ? p_6.0.52 open load detection in off filter time 1) t f_ol 40 ? ? s ? p_6.0.53 spi timing (see figure 4-6 ) 1) cycle-time (1) t cyc 490 ? ? ns referred to master p_6.0.54 enable lead time (2) t lead 50 ? ? ns referred to master p_6.0.55 enable lag time (3) t lag 150 ? ? ns referred to master p_6.0.56 data valid (4) 3) t v ? ? ? ? 150 230 ns cl = 200 pf cl = 350 pf referred to IFX9201SG p_6.0.57 data setup time (5) t su 40 ? ? ns referred to master p_6.0.58 data hold time (6) t h 40 ? ? ns referred to master p_6.0.59 disable time (7) t dis ? ? 100 ns referred to IFX9201SG p_6.0.60 transfer delay (8) t d 2 ? ? s referred to master p_6.0.61 disable lead time (9) t dld 250 ? ? ns referred to master p_6.0.62 disable lag time (10) t dlg 250 ? ? ns referred to master p_6.0.63 thermal shutdown thermal shutdown junction temperature 1) t jsd 150 175 ? c ? p_6.0.64 thermal switch-on junction temperature 1) t jso 125 ? ? c ? p_6.0.65 1) not subject to production test, specified by design. 2) output switching times are measured between 20% and 80% of the output swing 3) v so timing thresholds are 20% / 80% of v vso for 4.5v< v vso <5.5v and 30% / 70% of v vso for 2.9v< v vso <4.5v table 4 electrical characteristics v vs = 8 v to 36 v; v vso = 5.0 v; t j = -40 c to 125 c; (unless specified otherwise) parameter symbol values unit note / test condition number min. typ. max. data sheet 22 rev. 1.1, 2015-02-15 IFX9201SG application information 7 application information note: the following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functi onality, condition or quality of the device. the function of the described circuits must be verified in the real application figure 4 application example h-bridge with spi interface figure 5 application example h-bridge with error flag dis vso pwm dir out1 gnd vs out2 m supply voltage <33 nf <33 nf 100 nf 100 uf vs< 40 v so csn 3. 3 or 5v digital supply c sck si dis vso pwm dir out1 gnd vs out2 m supply voltage <33 nf <33 nf 100 nf 100 uf vs< 40 v so csn 3. 3 or 5v digital supply c sck si IFX9201SG application information data sheet 23 rev. 1.1, 2015-02-15 figure 6 spi daisy chain konfiguration (other signals omitted for clarity) c dis vso pwm dir out1 gnd vs out2 m <33 nf <33 nf so csn sck si dis vso pwm dir out1 gnd vs out2 m <33 nf <33 nf so csn sck si data sheet 24 rev. 1.1, 2015-02-15 IFX9201SG application information figure 7 application example vso as enable input figure 8 examples for reverse polarity protection the IFX9201SG is not protected against reverse polarity. ex ternal measures have to be taken to ensure the right polarity of the supply voltage. dis vso (en) pwm dir out1 gnd vs out2 m supply voltage <33 nf <33 nf 100nf 100uf vs< 40v so csn 3.3 or 5v digital supply c sck si 1nf 100 nf 100 f main relay power switch v s supply vs < 4 0v reverse polarity protection via main relay 100 nf 100 f v s supply vs < 40v reverse polarity protection using p -fet 10 v 10 k IFX9201SG package outlines data sheet 25 rev. 1.1, 2015-02-15 8 package outlines figure 9 pg-dso-12-17 green product (rohs compliant) to meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. green products are rohs-compliant (i.e pb-free finish on leads and suitable for pb-free soldering according to ipc/jedec j-std-020). for further info rmation on alternative pa ckages, please visit our website: http://www.infineon.com/packages . dimensions in mm data sheet 26 rev. 1.1, 2015-02-15 IFX9201SG revision history 9 revision history revision date changes 0.1 2014-04-16 initial product proposal 0.2 2014-07-08 target data sheet 0.3 2014-08-19 p_5.2.1: supply volt age range max. changed to 36v table 4: voltage range for electr ical characteristics changed to v vs = 8v to 36v 1.0 2015-01-30 data sheet 1.1 2015-02-15 device description updated in overview page (page 3) disclaimer updated edition 2015-02-15 published by infineon technologies ag 81726 munich, germany ? 2015 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infine on technologies hereby disclaims any and all warranties and liabilities of any kind, including witho ut limitation, warranties of non-infrin gement of intellectua l property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. the infineon technologies component described in this data sheet may be used in life-support devices or systems and/or automotive, aviation and aero space applications or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life- support, automotive, aviation and aerospac e device or system or to affect the safety or effectiveness of that device or system. life support devices or syste ms are intended to be implanted in th e human body or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. |
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