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( d oc n o . hx 83 1 2 - a - a n ) HX8312-A 240rgb x 320 dot, 262,144-color tft controller driver with internal ram preliminary version 02 october, 2005 free datasheet http://www..net/
-p.1- himax confidential july 2005 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. 1. intr oduction................................................................................................................ .................................. 4 2. feat ures.................................................................................................................... .................................... 4 3. block diagram............................................................................................................... ............................... 5 4. pad a ssignment .............................................................................................................. ............................ 6 pad coordinate ................................................................................................................. ....................... 6 bump arr angement ............................................................................................................... .................. 12 alignment mark ................................................................................................................. ...................... 12 bump size ...................................................................................................................... ......................... 13 pad coordinate ................................................................................................................. ...................... 14 5. system connecti on block di agram............................................................................................. ............ 15 6. layout r ecommenda tion....................................................................................................... ................... 16 7. fpc circui t exam ple ......................................................................................................... ........................ 17 8. pin d escripti on ............................................................................................................. ............................. 19 9. chip access configuration................................................................................................... .................... 23 9.1 interfac e circuit.......................................................................................................... ....................... 23 9.1.1 system inte rface circuit ................................................................................................. ....... 24 9.2 display ram address mapping ................................................................................................ ........ 35 9.2.1 display ram addre ss access mapping ................................................................................ 35 9.2.2 display ram addre ss update dire ction ............................................................................... 36 9.2.3 display ram address mapping for source outp ut chan nel ................................................ 37 10. initial code for reference ................................................................................................. ...................... 39 11. reversi on hist ory .......................................................................................................... .......................... 46 HX8312-A 240rgb x 320 dot, 262,144-color tft controller driver with internal ram list of contents october, 200 5 free datasheet http://www..net/
-p.2- himax confidential july 2005 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. figure 3. 1 chip block diagram.......................................................................................5 figure 5. 1 system conn ection block diagram ............................................................................. 15 figure 6. 1 layout reco mmendation of hx8312a ........................................................................ 16 figure 9. 1 18 / 16-bit bus width parallel bu s interface timing (for i80 series mpu) ................... 25 figure 9. 2 8-bit bus width parallel bus in terface timing (for i80 series mpu) ............................ 26 figure 9. 3 18 / 16-bit bus width parallel bu s interface timing (for m68 series mpu) ................. 27 figure 9. 4 8-bit bus width parallel bus in terface timing (for m68 series mpu) .......................... 28 figure 9. 5 16?bit serial bus interf ace timing (scleg 1=scleg2=0)......................................... 29 figure 9. 6 18?bit serial bus interf ace timing (scleg 1=scleg2=0)......................................... 30 figure 9. 7 address updat e direction settings .............................................................................. 36 HX8312-A 240rgb x 320 dot, 262,144 color tft controller driver wi th internal ram list of figures july, 200 5 free datasheet http://www..net/
-p.3- himax confidential july 2005 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. table 9. 1 in terface type ...................................................................................................... .......... 23 table 9. 2 mp u selection....................................................................................................... ......... 24 table 9. 3 input bus format select ion of system inte rface circ uit ................................................... 24 table 9. 4 display ram address and display panel position (x size = 240, ad x = 0) ................ 35 table 9. 5 x address and y addr ess update direct ion setti ng...................................................... 36 table 9. 6 x size of panel displa y setting ..................................................................................... 37 table 9. 7 display ram x address and out put source channel ( x size = 240 ) ........................ 37 table 9. 8 display ram x address and out put source channel ( x size = 208 ) ........................ 37 table 9. 9 display ram x address and out put source channel ( x size = 180 ) ........................ 38 hx8312a 240rgb x 320 dot, 262,144 color tft controller driver wi th internal ram list of tables july, 200 5 free datasheet http://www..net/
-p.4- himax confidential july 2005 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. 1. introduction this application note describes the himax?s HX8312-A mobile driver application that include hardware and software design. the HX8312-A is designed to provide a single-chip solution that combined a gate driv er, a source driver, power supply circuit and internal graphics ram for 262,144 colors to drive a tft panel with 240rgb*320 dots at maximum. 2. features z single chip solution to drive a tft panel z 240rgb x 320-dot graphics display lcd c ontroller/driver and 262,144 tft colors z support interface: y system interface (i80 / m68) parallel bus system interface serial bus system interface y rgb interface y vsync interface z internal graphics ram capacity: 1,328,400 bytes z the 262,144 colors can be displayed at the same time with gamma correction z the vertical scroll display function in line units z internal operation circuit of liquid crystal display: y source channel: 720 y gate line: 320 z to write data in a window-ram addre ss area by using a window address area access function z low-power consumption architecture supports: y vci = 2.5 to 3.3 v (internal reference voltage) y vcc = 2.2 to 3.3 v (corre sponding low-vo ltage operation) y iovcc = 1.65 to 3.3 v (i nterface i/o operation) y vlcd=4.5~5.5v y power-saving functions ? 8-color mode ? standby mode ? off mode z n-line inversion ac liquid-crystal drive z partial liquid crystal drive to disp lay two screens at arbitrary positions z internal oscillator and hardwar e / software reset function hx8312a 240rgb x 320 dot, 262,144 color tft controller driver wi th internal ram preliminary version 01 july, 200 5 free datasheet http://www..net/
-p.5- himax confidential october 2005 HX8312-A 240rgbx320 dots, 262,144 color tft controller driver a pplication note preliminary v02 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. 3. block diagram 18 18 dotclk ncs rs nwr(rnw) nrd(e) system_if vsync_if -18-bit -16-bit -8-bit -18-bit serial -16-bit serial 18 lcd driving power circuit timing generator rcosc vci g1~g320 grayscale voltage generator vgs gamma adjustment source driver m/ac circuit latch circuit v0~63 display data ram (240*320*18) bit 1,328,400 bytes osc2 osc1 db17~0 vsync read data latch write data latch 18 18 18 address counter (ac) 16 register address control register bws2-0 psx c86 rgb_ncpu dtx2-1 scleg1-0 vseg hseg dckeg v18 8 16 power regulator vcc sdi scl hsync vgh/vgl s720~s1 ga te dri ver rgb_if -18-bit -16-bit -6-bit vgh vgl addvdh ddvdh vdh vcl vr2-1 vs c11a/c11b cx11a/cx11b c21a/c21b c22a/c22b c23a/c23b c12a/c12b rvcc vddd vcomr vcomh vcoml vmon ds1 dds vcc vcom test1 test2 nreset vssd vssa testa2 testa1 testa3 sdo vcc iovcc enable figure 3. 1 chip block diagram free datasheet http://www..net/
-p.6- himax confidential october 2005 HX8312-A 240rgbx320 dots, 262,144 color tft controller driver a pplication note preliminary v02 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. 4. pad assignment pad coordinate no. pad name x y no. pad name x y no. pad name x y no. pad name x y 1 dummy1 -11928 -547.5 62 dummy16 -10285 -701 .5 123 iovccdum7 -5100 -701.5 184 scl 85 -701.5 2 dummy2 -11904 -702.5 63 vcom1 -10200 -701.5 124 bws2 -5015 -701.5 185 scl 170 -701.5 3 dummy3 -11880 -547.5 64 vcom 1 -10115 -701.5 125 iognddum7 -4930 -7 01.5 186 ncs 255 -701.5 4 dummy4 -11856 -702.5 65 ds1 -10030 -701.5 126 rgbncpu -4845 -701.5 187 ncs 340 -701.5 5 dummy5 -11832 -547.5 66 vgh -9945 -701.5 127 iovccdum8 -4760 -701.5 1 88 cstb 425 -701.5 6 dummy6 -11808 -702.5 67 vgh -9860 -701.5 128 nreset -4675 -701.5 189 cstb 510 -701.5 7 dummy7 -11784 -547.5 68 vgh -9775 -701.5 129 nreset -4590 -701.5 190 test1 595 -701.5 8 dummy8 -11760 -702.5 69 vgh -9690 -701.5 130 vsync -4505 -701.5 191 iognddum8 680 -701.5 9 dummy9 -11736 -547.5 70 c23a -9605 -701.5 131 vsync -4420 -701.5 192 test2 765 -701.5 10 dummy10 -11712 -702.5 71 c23a -9520 -701.5 132 hsync -4335 -7 01.5 193 iognddum 9 850 -701.5 11 dummy11 -11688 -547.5 72 c 23b -9435 -701.5 133 hxync -4250 -701.5 194 vddd 935 -701.5 12 dummy12 -11664 -702.5 73 c23b -9350 -701.5 134 dotclk -4165 -701.5 195 vddd 1020 -701.5 13 through1 -11640 -547.5 74 c22a -9265 -701.5 135 dotclk -4080 -701.5 196 vddd 1105 -701.5 14 through2 -11616 -702.5 75 c22a -9180 -701.5 136 enable -3995 -701.5 197 vddd 1190 -701.5 15 g278 -11592 -547.5 76 c22b -9095 -701.5 137 enable -3910 -701.5 198 rvcc 1275 -701.5 16 g279 -11568 -702.5 77 c22b -9010 -701.5 138 db17 -3825 -701.5 199 rvcc 1360 -701.5 17 g280 -11544 -547.5 78 c21a -8925 -701.5 139 db17 -3740 -701.5 200 rvcc 1445 -701.5 18 g281 -11520 -702.5 79 c21a -8840 -701.5 140 db16 -3655 -701.5 201 rvcc 1530 -701.5 19 g282 -11496 -547.5 80 c21b -8755 -701.5 141 db16 -3570 -701.5 202 v18 1615 -701.5 20 g283 -11472 -702.5 81 c21b -8670 -701.5 142 db15 -3485 -701.5 203 v18 1700 -701.5 21 g284 -11448 -547.5 82 c12a -8585 -701.5 143 db15 -3400 -701.5 204 v18 1785 -701.5 22 g285 -11424 -702.5 83 c12a -8500 -701.5 144 db14 -3315 -701.5 205 v18 1870 -701.5 23 g286 -11400 -547.5 84 c12a -8415 -701.5 145 db14 -3230 -701.5 206 dummyr1 1955 -701.5 24 g287 -11376 -702.5 85 c12a -8330 -701.5 146 db13 -3145 -701.5 207 dummyr2 2040 -701.5 25 g288 -11352 -547.5 86 c12b -8245 -701.5 147 db13 -3060 -701.5 208 osc1 2125 -701.5 26 g289 -11328 -702.5 87 c12b -8160 -701.5 148 db12 -2975 -701.5 209 osc1 2210 -701.5 27 g290 -11304 -547.5 88 c12b -8075 -701.5 149 db12 -2890 -701.5 210 osc2 2295 -701.5 28 g291 -11280 -702.5 89 c12b -7990 -701.5 150 db11 -2805 -701.5 211 osc2 2380 -701.5 29 g292 -11256 -547.5 90 vr2 -7905 -701.5 151 db11 -2720 -701.5 212 vssd 2465 -701.5 30 g293 -11232 -702.5 91 vr2 -7820 -701.5 152 db10 -2635 -701.5 213 vssd 2550 -701.5 31 g294 -11208 -547.5 92 vr2 -7735 -701.5 153 db10 -2550 -701.5 214 vssd 2635 -701.5 32 g295 -11184 -702.5 93 vr2 -7650 -701.5 154 db9 -2465 -701.5 215 vssd 2720 -701.5 33 g296 -11160 -547.5 94 vgl -7565 -701.5 155 db9 -2380 -701.5 216 vssd2 2805 -701.5 34 g297 -11136 -702.5 95 vgl -7480 -701.5 156 db8 -2295 -701.5 217 vssd2 2890 -701.5 35 g298 -11112 -547.5 96 vgl -7395 -701.5 157 db8 -2210 -701.5 218 vssd2 2975 -701.5 36 g299 -11088 -702.5 97 vgl -7310 -701.5 158 db7 -2125 -701.5 219 vssd2 3060 -701.5 37 g300 -11064 -547.5 98 vgl -7225 -701.5 159 db7 -2040 -701.5 220 vssa 3145 -701.5 38 g301 -11040 -702.5 9 9 iovccdum1 -7140 -701.5 160 db6 - 1955 -701.5 221 vssa 3230 -701.5 39 g302 -11016 -547.5 100 dds -7055 -701.5 161 db6 -1870 -701.5 222 vssa 3315 -701.5 40 g303 -10992 -702.5 101 iognddum1 -6970 -701.5 162 db5 - 1785 -701.5 223 vssa 3400 -701.5 41 g304 -10968 -547.5 102 scleg1 -6885 -701.5 163 db5 -1700 -701.5 224 vssa 3485 -701.5 42 g305 -10944 -702.5 103 iovccdum2 -6800 -701.5 164 db4 - 1615 -701.5 225 vssa 3570 -701.5 43 g306 -10920 -547.5 104 scleg0 -6715 -701.5 165 db4 -1530 -701.5 226 iovcc 3655 -701.5 44 g307 -10896 -702.5 105 iognddum2 -6630 -701.5 166 db3 - 1445 -701.5 227 iovcc 3740 -701.5 45 g308 -10872 -547.5 106 hseg -6545 -701.5 167 db3 -1360 -701.5 228 iovcc 3825 -701.5 46 g309 -10848 -702.5 107 iovccdum3 -6460 -701.5 168 db2 - 1275 -701.5 229 iovcc 3910 -701.5 47 g310 -10824 -547.5 108 vseg -6375 -701.5 169 db2 -1190 -701.5 230 vci 3995 -701.5 48 g311 -10800 -702.5 109 iog nddum3 -6290 -701.5 170 db1 -110 5 -701.5 231 vci 4080 -701.5 49 g312 -10776 -547.5 110 dckeg -6205 -701.5 171 db1 -1020 -701.5 232 vci 4165 -701.5 50 g313 -10752 -702.5 111 iovccdum4 -6120 -701.5 172 db0 -935 -701.5 233 vci 4250 -701.5 51 g314 -10728 -547.5 112 psx -6035 -701.5 173 db0 -850 -701.5 234 vci 4335 -701.5 52 g315 -10704 -702.5 113 iognddum4 -5950 -701.5 174 nrd(e) -7 65 -701.5 235 vci 4420 -701.5 53 g316 -10680 -547.5 114 c86 -5865 -701.5 175 nrd(e) -680 -701.5 236 vcc 4505 -701.5 54 g317 -10656 -702.5 115 iovccdum5 -5780 -701.5 176 nwr(rnw) -595 -701.5 237 vcc 4590 -701.5 55 g318 -10632 -547.5 116 dtx1 -5695 -701.5 177 nwr(rnw) -510 -701.5 238 vcc 4675 -701.5 56 g319 -10608 -702.5 117 iognddum5 -5610 -701.5 178 rs -425 -701.5 239 vcc 4760 -701.5 57 g320 -10584 -547.5 118 dtx2 -5525 -701.5 179 rs -340 -701.5 240 vgs 4845 -701.5 58 g321 -10560 -702.5 119 iovccdum6 -5440 -701.5 180 sdo -255 -701.5 241 vgs 4930 -701.5 59 dummy13 -10536 -547.5 120 bws0 -5355 -701.5 181 sdo -170 -701.5 242 vcomr 5015 -701.5 60 dummy14 -10512 -702.5 121 iognddum 6 -5270 -701.5 182 sdi -85 -7 01.5 243 vcomr 5100 -701.5 61 vmon -10488 -547.5 122 bws1 -5185 -701.5 183 sdi 0 -701.5 244 vs 5185 -701.5 free datasheet http://www..net/
-p.7- himax confidential october 2005 HX8312-A 240rgbx320 dots, 262,144 color tft controller driver a pplication note preliminary v02 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. no. pad name x y no. pad name x y no. pad name x y no. pad name x y 245 vs 5270 -701.5 314 g8 10704 -702.5 383 g57 11328 547.5 452 g126 9672 702.5 246 vs 5355 -701.5 315 g9 10728 -547.5 384 g58 11304 702.5 453 g127 9648 547.5 247 vs 5440 -701.5 316 g10 10752 -702.5 385 g59 11280 547.5 454 g128 9624 702.5 248 vcoml 5525 -701.5 317 g11 10776 -547.5 386 g60 11256 702.5 455 g129 9600 547.5 249 vcoml 5610 -701.5 318 g12 10800 -702.5 387 g61 11232 547.5 456 g130 9576 702.5 250 vcoml 5695 -701.5 319 g13 10824 -547.5 388 g62 11208 702.5 457 g131 9552 547.5 251 vcoml 5780 -701.5 320 g14 10848 -702.5 389 g63 11184 547.5 458 g132 9528 702.5 252 vcomh 5865 -701.5 321 g15 10872 -547.5 390 g64 11160 702.5 459 g133 9504 547.5 253 vcomh 5950 -701.5 322 g16 10896 -702.5 391 g65 11136 547.5 460 g134 9480 702.5 254 vcomh 6035 -701.5 323 g17 10920 -547.5 392 g66 11112 702.5 461 g135 9456 547.5 255 vcomh 6120 -701.5 324 g18 10944 -702.5 393 g67 11088 547.5 462 g136 9432 702.5 256 vcl 6205 -701.5 325 g19 10968 -547.5 394 g68 11064 702.5 463 g137 9408 547.5 257 vcl 6290 -701.5 326 g20 10992 -702.5 395 g69 11040 547.5 464 g138 9384 702.5 258 vcl 6375 -701.5 327 g21 11016 -547.5 396 g70 11016 702.5 465 g139 9360 547.5 259 vcl 6460 -701.5 328 g22 11040 -702.5 397 g71 10992 547.5 466 g140 9336 702.5 260 testa1 6545 -701.5 329 g23 11064 -547.5 398 g72 10968 702.5 467 g141 9312 547.5 261 testa1 6630 -701.5 330 g24 11088 -702.5 399 g73 10944 547.5 468 g142 9288 702.5 262 vr1 6715 -701.5 331 g25 11112 -547.5 400 g74 10920 702.5 469 g143 9264 547.5 263 vr1 6800 -701.5 332 g26 11136 -702.5 401 g75 10896 547.5 470 g144 9240 702.5 264 vr1 6885 -701.5 333 g27 11160 -547.5 402 g76 10872 702.5 471 g145 9216 547.5 265 vr1 6970 -701.5 334 g28 11184 -702.5 403 g77 10848 547.5 472 g146 9192 702.5 266 addvdh 7055 -701.5 335 g29 11208 -547.5 404 g78 10824 702.5 473 g148 9168 547.5 267 addvdh 7140 -701.5 336 g30 11232 -702.5 405 g79 10800 547.5 474 g148 9144 702.5 268 addvdh 7225 -701.5 337 g31 11256 -547.5 406 g80 10776 702.5 475 g149 9120 547.5 269 addvdh 7310 -701.5 338 g32 11280 -702.5 407 g81 10752 547.5 476 g150 9096 702.5 270 ddvdh 7395 -701.5 339 g33 11304 -547.5 408 g82 10728 702.5 477 g151 9072 547.5 271 ddvdh 7480 -701.5 340 g34 11328 -702.5 409 g83 10704 547.5 478 g152 9048 702.5 272 ddvdh 7565 -701.5 341 g35 11352 -547.5 410 g84 10680 702.5 479 g153 9024 547.5 273 ddvdh 7650 -701.5 342 g36 11376 -702.5 411 g85 10656 547.5 480 g154 9000 702.5 274 cx11b 7735 -701.5 343 g37 11400 -547.5 412 g86 10632 702.5 481 g155 8976 547.5 275 cx11b 7820 -701.5 344 g38 11424 -702.5 413 g87 10608 547.5 482 g156 8952 702.5 276 cx11b 7905 -701.5 345 g39 11448 -547.5 414 g88 10584 702.5 483 g157 8928 547.5 277 cx11b 7990 -701.5 346 g40 11472 -702.5 415 g89 10560 547.5 484 g158 8904 702.5 278 cx11b 8075 -701.5 347 g41 11496 -547.5 416 g90 10536 702.5 485 g159 8880 547.5 279 cx11b 8160 -701.5 348 g42 11520 -702.5 417 g91 10512 547.5 486 g160 8856 702.5 280 cx11a 8245 -701.5 349 g43 11544 -547.5 418 g92 10488 702.5 487 g161 8832 547.5 281 cx11a 8330 -701.5 350 g44 11568 -702.5 419 g93 10464 547.5 488 dummy37 8808 702.5 282 cx11a 8415 -701.5 351 g45 11592 -547.5 420 g94 10440 702.5 489 dummy38 8784 547.5 283 cx11a 8500 -701.5 352 through3 11616 -702.5 421 g95 10416 547.5 490 vcom3 8760 702.5 284 cx11a 8585 -701.5 353 through4 11640 -547.5 422 g96 10392 702.5 491 vcom3 8736 547.5 285 cx11a 8670 -701.5 354 dummy22 11664 -702.5 423 g97 10368 547.5 492 dummy39 8712 702.5 286 c11b 8755 -701.5 355 dummy23 11688 -547.5 424 g98 10344 702.5 493 dummy40 8688 547.5 287 c11b 8840 -701.5 356 dummy24 11712 -702.5 425 g99 10320 547.5 494 dummy41 8664 702.5 288 c11b 8925 -701.5 357 dummy25 11736 -547.5 426 g100 10296 702.5 495 s720 8640 547.5 289 c11b 9010 -701.5 358 dummy26 11760 -702.5 427 g101 10272 547.5 496 s719 8616 702.5 290 c11b 9095 -701.5 359 dummy27 11784 -547.5 428 g102 10248 702.5 497 s718 8592 547.5 291 c11b 9180 -701.5 360 dummy28 11808 -702.5 429 g103 10224 547.5 498 s717 8568 702.5 292 c11a 9265 -701.5 361 dummy29 11832 -547.5 430 g104 10200 702.5 499 s716 8544 547.5 293 c11a 9350 -701.5 362 dummy30 11856 -702.5 431 g105 10176 547.5 500 s715 8520 702.5 294 c11a 9435 -701.5 363 dummy31 11880 -547.5 432 g106 10152 702.5 501 s714 8496 547.5 295 c11a 9520 -701.5 364 dummy32 11904 -702.5 433 g107 10128 547.5 502 s713 8472 702.5 296 c11a 9605 -701.5 365 dummy33 11928 -547.5 434 g108 10104 702.5 503 s712 8448 547.5 297 c11a 9690 -701.5 366 dummy34 11736 702.5 435 g109 10080 547.5 504 s711 8424 702.5 298 testa2 9775 -701.5 367 vgldmy 11712 547.5 436 g110 10056 702.5 505 s710 8400 547.5 299 dummy18 9860 -701.5 368 dummy35 11688 702.5 437 g111 10032 547.5 506 s709 8376 702.5 300 vcom2 9945 -701.5 369 dummy36 11664 547.5 438 g112 10008 702.5 507 s708 8352 547.5 301 vcom2 10030 -701.5 370 through5 11640 702.5 439 g113 9984 547.5 508 s707 8328 702.5 302 vcom2 10115 -701.5 371 through6 11616 547.5 440 g114 9960 702.5 509 s706 8304 547.5 303 vcom2 10200 -701.5 372 g46 11592 702.5 441 g115 9936 547.5 510 s705 8280 702.5 304 testa4 10285 -701.5 373 g47 11568 547.5 442 g116 9912 702.5 511 s704 8256 547.5 305 dummy20 10488 -547.5 374 g48 11544 702.5 443 g117 9888 547.5 512 s703 8232 702.5 306 dummy21 10512 -702.5 375 g49 11520 547.5 444 g118 9864 702.5 513 s702 8208 547.5 307 g1 10536 -547.5 376 g50 11496 702.5 445 g119 9840 547.5 514 s701 8184 702.5 308 g2 10560 -702.5 377 g51 11472 547.5 446 g120 9816 702.5 515 s700 8160 547.5 309 g3 10584 -547.5 378 g52 11448 702.5 447 g121 9792 547.5 516 s699 8136 702.5 310 g4 10608 -702.5 379 g53 11424 547.5 448 g122 9768 702.5 517 s698 8112 547.5 311 g5 10632 -547.5 380 g54 11400 702.5 449 g123 9744 547.5 518 s697 8088 702.5 312 g6 10656 -702.5 381 g55 11376 547.5 450 g124 9720 702.5 519 s696 8064 547.5 313 g7 10680 -547.5 382 g56 11352 702.5 451 g125 9696 547.5 520 s695 8040 702.5 free datasheet http://www..net/
-p.8- himax confidential october 2005 HX8312-A 240rgbx320 dots, 262,144 color tft controller driver a pplication note preliminary v02 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. no. pad name x y no. pad name x y no. pad name x y no. pad name x y 521 s694 8016 547.5 586 s629 6456 702.5 651 s564 4896 547.5 716 s499 3336 702.5 522 s693 7992 702.5 587 s628 6432 547.5 652 s563 4872 702.5 717 s498 3312 547.5 523 s692 7968 547.5 588 s627 6408 702.5 653 s562 4848 547.5 718 s497 3288 702.5 524 s691 7944 702.5 589 s626 6384 547.5 654 s561 4824 702.5 719 s496 3264 547.5 525 s690 7920 547.5 590 s625 6360 702.5 655 s560 4800 547.5 720 s495 3240 702.5 526 s689 7896 702.5 591 s624 6336 547.5 656 s559 4776 702.5 721 s494 3216 547.5 527 s688 7872 547.5 592 s623 6312 702.5 657 s558 4752 547.5 722 s493 3192 702.5 528 s687 7848 702.5 593 s622 6288 547.5 658 s557 4728 702.5 723 s492 3168 547.5 529 s686 7824 547.5 594 s621 6264 702.5 659 s556 4704 547.5 724 s491 3144 702.5 530 s685 7800 702.5 595 s620 6240 547.5 660 s555 4680 702.5 725 s490 3120 547.5 531 s684 7776 547.5 596 s619 6216 702.5 661 s554 4656 547.5 726 s489 3096 702.5 532 s683 7752 702.5 597 s618 6192 547.5 662 s553 4632 702.5 727 s488 3072 547.5 533 s682 7728 547.5 598 s617 6168 702.5 663 s552 4608 547.5 728 s487 3048 702.5 534 s681 7704 702.5 599 s616 6144 547.5 664 s551 4584 702.5 729 s486 3024 547.5 535 s680 7680 547.5 600 s615 6120 702.5 665 s550 4560 547.5 730 s485 3000 702.5 536 s679 7656 702.5 601 s614 6096 547.5 666 s549 4536 702.5 731 s484 2976 547.5 537 s678 7632 547.5 602 s613 6072 702.5 667 s548 4512 547.5 732 s483 2952 702.5 538 s677 7608 702.5 603 s612 6048 547.5 668 s547 4488 702.5 733 s482 2928 547.5 539 s676 7584 547.5 604 s611 6024 702.5 669 s546 4464 547.5 734 s481 2904 702.5 540 s675 7560 702.5 605 s610 6000 547.5 670 s545 4440 702.5 735 s480 2880 547.5 541 s674 7536 547.5 606 s609 5976 702.5 671 s544 4416 547.5 736 s479 2856 702.5 542 s673 7512 702.5 607 s608 5952 547.5 672 s543 4392 702.5 737 s478 2832 547.5 543 s672 7488 547.5 608 s607 5928 702.5 673 s542 4368 547.5 738 s477 2808 702.5 544 s671 7464 702.5 609 s606 5904 547.5 674 s541 4344 702.5 739 s476 2784 547.5 545 s670 7440 547.5 610 s605 5880 702.5 675 s540 4320 547.5 740 s475 2760 702.5 546 s669 7416 702.5 611 s604 5856 547.5 676 s539 4296 702.5 741 s474 2736 547.5 547 s668 7392 547.5 612 s603 5832 702.5 677 s538 4272 547.5 742 s473 2712 702.5 548 s667 7368 702.5 613 s602 5808 547.5 678 s537 4248 702.5 743 s472 2688 547.5 549 s666 7344 547.5 614 s601 5784 702.5 679 s536 4224 547.5 744 s471 2664 702.5 550 s665 7320 702.5 615 s600 5760 547.5 680 s535 4200 702.5 745 s470 2640 547.5 551 s664 7296 547.5 616 s599 5736 702.5 681 s534 4176 547.5 746 s469 2616 702.5 552 s663 7272 702.5 617 s598 5712 547.5 682 s533 4152 702.5 747 s468 2592 547.5 553 s662 7248 547.5 618 s597 5688 702.5 683 s532 4128 547.5 748 s467 2568 702.5 554 s661 7224 702.5 619 s596 5664 547.5 684 s531 4104 702.5 749 s466 2544 547.5 555 s660 7200 547.5 620 s595 5640 702.5 685 s530 4080 547.5 750 s465 2520 702.5 556 s659 7176 702.5 621 s594 5616 547.5 686 s529 4056 702.5 751 s464 2496 547.5 557 s658 7152 547.5 622 s593 5592 702.5 687 s528 4032 547.5 752 s463 2472 702.5 558 s657 7128 702.5 623 s592 5568 547.5 688 s527 4008 702.5 753 s462 2448 547.5 559 s656 7104 547.5 624 s591 5544 702.5 689 s526 3984 547.5 754 s461 2424 702.5 560 s655 7080 702.5 625 s590 5520 547.5 690 s525 3960 702.5 755 s460 2400 547.5 561 s654 7056 547.5 626 s589 5496 702.5 691 s524 3936 547.5 756 s459 2376 702.5 562 s653 7032 702.5 627 s588 5472 547.5 692 s523 3912 702.5 757 s458 2352 547.5 563 s652 7008 547.5 628 s587 5448 702.5 693 s522 3888 547.5 758 s457 2328 702.5 564 s651 6984 702.5 629 s586 5424 547.5 694 s521 3864 702.5 759 s456 2304 547.5 565 s650 6960 547.5 630 s585 5400 702.5 695 s520 3840 547.5 760 s455 2280 702.5 566 s649 6936 702.5 631 s584 5376 547.5 696 s519 3816 702.5 761 s454 2256 547.5 567 s648 6912 547.5 632 s583 5352 702.5 697 s518 3792 547.5 762 s453 2232 702.5 568 s647 6888 702.5 633 s582 5328 547.5 698 s517 3768 702.5 763 s452 2208 547.5 569 s646 6864 547.5 634 s581 5304 702.5 699 s516 3744 547.5 764 s451 2184 702.5 570 s645 6840 702.5 635 s580 5280 547.5 700 s515 3720 702.5 765 s450 2160 547.5 571 s644 6816 547.5 636 s579 5256 702.5 701 s514 3696 547.5 766 s449 2136 702.5 572 s643 6792 702.5 637 s578 5232 547.5 702 s513 3672 702.5 767 s448 2112 547.5 573 s642 6768 547.5 638 s577 5208 702.5 703 s512 3648 547.5 768 s447 2088 702.5 574 s641 6744 702.5 639 s576 5184 547.5 704 s511 3624 702.5 769 s446 2064 547.5 575 s640 6720 547.5 640 s575 5160 702.5 705 s510 3600 547.5 770 s445 2040 702.5 576 s639 6696 702.5 641 s574 5136 547.5 706 s509 3576 702.5 771 s444 2016 547.5 577 s638 6672 547.5 642 s573 5112 702.5 707 s508 3552 547.5 772 s443 1992 702.5 578 s637 6648 702.5 643 s572 5088 547.5 708 s507 3528 702.5 773 s442 1968 547.5 579 s636 6624 547.5 644 s571 5064 702.5 709 s506 3504 547.5 774 s441 1944 702.5 580 s635 6600 702.5 645 s570 5040 547.5 710 s505 3480 702.5 775 s440 1920 547.5 581 s634 6576 547.5 646 s569 5016 702.5 711 s504 3456 547.5 776 s439 1896 702.5 582 s633 6552 702.5 647 s568 4992 547.5 712 s503 3432 702.5 777 s438 1872 547.5 583 s632 6528 547.5 648 s567 4968 702.5 713 s502 3408 547.5 778 s437 1848 702.5 584 s631 6504 702.5 649 s566 4944 547.5 714 s501 3384 702.5 779 s436 1824 547.5 585 s630 6480 547.5 650 s565 4920 702.5 715 s500 3360 547.5 780 s435 1800 702.5 free datasheet http://www..net/
-p.9- himax confidential october 2005 HX8312-A 240rgbx320 dots, 262,144 color tft controller driver a pplication note preliminary v02 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. no. pad name x y no. pad name x y no. pad name x y no. pad name x y 781 s434 1776 547.5 846 s369 216 702.5 911 s305 -1344 547.5 976 s240 -2904 702.5 782 s433 1752 702.5 847 s368 192 547.5 912 s304 -1368 702.5 977 s239 -2928 547.5 783 s432 1728 547.5 848 s367 168 702.5 913 s303 -1392 547.5 978 s238 -2952 702.5 784 s431 1704 702.5 849 s366 144 547.5 914 s302 -1416 702.5 979 s237 -2976 547.5 785 s430 1680 547.5 850 s365 120 702.5 915 s301 -1440 547.5 980 s236 -3000 702.5 786 s429 1656 702.5 851 s364 96 547.5 916 s300 -1464 702.5 981 s235 -3024 547.5 787 s428 1632 547.5 852 s363 72 702.5 917 s299 -1488 547.5 982 s234 -3048 702.5 788 s427 1608 702.5 853 s362 48 547.5 918 s298 -1512 702.5 983 s233 -3072 547.5 789 s426 1584 547.5 854 s361 24 702.5 919 s297 -1536 547.5 984 s232 -3096 702.5 790 s425 1560 702.5 855 dummy42 0 547.5 920 s296 -1560 702.5 985 s231 -3120 547.5 791 s424 1536 547.5 856 s360 -24 702.5 921 s295 -1584 547.5 986 s230 -3144 702.5 792 s423 1512 702.5 857 s359 -48 547.5 922 s294 -1608 702.5 987 s229 -3168 547.5 793 s422 1488 547.5 858 s358 -72 702.5 923 s293 -1632 547.5 988 s228 -3192 702.5 794 s421 1464 702.5 859 s357 -96 547.5 924 s292 -1656 702.5 989 s227 -3216 547.5 795 s420 1440 547.5 860 s356 -120 702.5 925 s291 -1680 547.5 990 s226 -3240 702.5 796 s419 1416 702.5 861 s355 -144 547.5 926 s290 -1704 702.5 991 s225 -3264 547.5 797 s418 1392 547.5 862 s354 -168 702.5 927 s289 -1728 547.5 992 s224 -3288 702.5 798 s417 1368 702.5 863 s353 -192 547.5 928 s288 -1752 702.5 993 s223 -3312 547.5 799 s416 1344 547.5 864 s352 -216 702.5 929 s287 -1776 547.5 994 s222 -3336 702.5 800 s415 1320 702.5 865 s351 -240 547.5 930 s286 -1800 702.5 995 s221 -3360 547.5 801 s414 1296 547.5 866 s350 -264 702.5 931 s285 -1824 547.5 996 s220 -3384 702.5 802 s413 1272 702.5 867 s349 -288 547.5 932 s284 -1848 702.5 997 s219 -3408 547.5 803 s412 1248 547.5 868 s348 -312 702.5 933 s283 -1872 547.5 998 s218 -3432 702.5 804 s411 1224 702.5 869 s347 -336 547.5 934 s282 -1896 702.5 999 s217 -3456 547.5 805 s410 1200 547.5 870 s346 -360 702.5 935 s281 -1920 547.5 1000 s216 -3480 702.5 806 s409 1176 702.5 871 s345 -384 547.5 936 s280 -1944 702.5 1001 s215 -3504 547.5 807 s408 1152 547.5 872 s344 -408 702.5 937 s279 -1968 547.5 1002 s214 -3528 702.5 808 s407 1128 702.5 873 s343 -432 547.5 938 s278 -1992 702.5 1003 s213 -3552 547.5 809 s406 1104 547.5 874 s342 -456 702.5 939 s277 -2016 547.5 1004 s212 -3576 702.5 810 s405 1080 702.5 875 s341 -480 547.5 940 s276 -2040 702.5 1005 s211 -3600 547.5 811 s404 1056 547.5 876 s340 -504 702.5 941 s275 -2064 547.5 1006 s210 -3624 702.5 812 s403 1032 702.5 877 s339 -528 547.5 942 s274 -2088 702.5 1007 s209 -3648 547.5 813 s402 1008 547.5 878 s338 -552 702.5 943 s273 -2112 547.5 1008 s208 -3672 702.5 814 s401 984 702.5 879 s337 -576 547.5 944 s272 -2136 702.5 1009 s207 -3696 547.5 815 s400 960 547.5 880 s336 -600 702.5 945 s271 -2160 547.5 1010 s206 -3720 702.5 816 s399 936 702.5 881 s335 -624 547.5 946 s270 -2184 702.5 1011 s205 -3744 547.5 817 s398 912 547.5 882 s334 -648 702.5 947 s269 -2208 547.5 1012 s204 -3768 702.5 818 s397 888 702.5 883 s333 -672 547.5 948 s268 -2232 702.5 1013 s203 -3792 547.5 819 s396 864 547.5 884 s332 -696 702.5 949 s267 -2256 547.5 1014 s202 -3816 702.5 820 s395 840 702.5 885 s331 -720 547.5 950 s266 -2280 702.5 1015 s201 -3840 547.5 821 s394 816 547.5 886 s330 -744 702.5 951 s265 -2304 547.5 1016 s200 -3864 702.5 822 s393 792 702.5 887 s329 -768 547.5 952 s264 -2328 702.5 1017 s199 -3888 547.5 823 s392 768 547.5 888 s328 -792 702.5 953 s263 -2352 547.5 1018 s198 -3912 702.5 824 s391 744 702.5 889 s327 -816 547.5 954 s262 -2376 702.5 1019 s197 -3936 547.5 825 s390 720 547.5 890 s326 -840 702.5 955 s261 -2400 547.5 1020 s196 -3960 702.5 826 s389 696 702.5 891 s325 -864 547.5 956 s260 -2424 702.5 1021 s195 -3984 547.5 827 s388 672 547.5 892 s224 -888 702.5 957 s259 -2448 547.5 1022 s194 -4008 702.5 828 s387 648 702.5 893 s223 -912 547.5 958 s258 -2472 702.5 1023 s193 -4032 547.5 829 s386 624 547.5 894 s322 -936 702.5 959 s257 -2496 547.5 1024 s192 -4056 702.5 830 s385 600 702.5 895 s321 -960 547.5 960 s256 -2520 702.5 1025 s191 -4080 547.5 831 s384 576 547.5 896 s320 -984 702.5 961 s255 -2544 547.5 1026 s190 -4104 702.5 832 s383 552 702.5 897 s319 -1008 547.5 962 s254 -2568 702.5 1027 s189 -4128 547.5 833 s382 528 547.5 898 s318 -1032 702.5 963 s253 -2592 547.5 1028 s188 -4152 702.5 834 s381 504 702.5 899 s317 -1056 547.5 964 s252 -2616 702.5 1029 s187 -4176 547.5 835 s380 480 547.5 900 s316 -1080 702.5 965 s251 -2640 547.5 1030 s186 -4200 702.5 836 s379 456 702.5 901 s315 -1104 547.5 966 s250 -2664 702.5 1031 s185 -4224 547.5 837 s378 432 547.5 902 s314 -1128 702.5 967 s249 -2688 547.5 1032 s184 -4248 702.5 838 s377 408 702.5 903 s313 -1152 547.5 968 s248 -2712 702.5 1033 s183 -4272 547.5 839 s376 384 547.5 904 s312 -1176 702.5 969 s247 -2736 547.5 1034 s182 -4296 702.5 840 s375 360 702.5 905 s311 -1200 547.5 970 s246 -2760 702.5 1035 s181 -4320 547.5 841 s374 336 547.5 906 s310 -1224 702.5 971 s245 -2784 547.5 1036 s180 -4344 702.5 842 s373 312 702.5 907 s309 -1248 547.5 972 s244 -2808 702.5 1037 s179 -4368 547.5 843 s372 288 547.5 908 s308 -1272 702.5 973 s243 -2832 547.5 1038 s178 -4392 702.5 844 s371 264 702.5 909 s307 -1296 547.5 974 s242 -2856 702.5 1039 s177 -4416 547.5 845 s370 240 547.5 910 s306 -1320 702.5 975 s241 -2880 547.5 1040 s176 -4440 702.5 free datasheet http://www..net/
-p.10- himax confidential october 2005 HX8312-A 240rgbx320 dots, 262,144 color tft controller driver a pplication note preliminary v02 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. no. pad name x y no. pad name x y no. pad name x y no. pad name x y 1041 s175 -4464 547.5 1106 s110 -6024 702.5 1171 s45 -7584 547.5 1236 g175 -9144 702.5 1042 s174 -4488 702.5 1107 s109 -6048 547.5 1172 s44 -7608 702.5 1237 g176 -9168 547.5 1043 s173 -4512 547.5 1108 s108 -6072 702.5 1173 s43 -7632 547.5 1238 g177 -9192 702.5 1044 s172 -4536 702.5 1109 s107 -6096 547.5 1174 s42 -7656 702.5 1239 g178 -9216 547.5 1045 s171 -4560 547.5 1110 s106 -6120 702.5 1175 s41 -7680 547.5 1240 g179 -9240 702.5 1046 s170 -4584 702.5 1111 s105 -6144 547.5 1176 s40 -7704 702.5 1241 g180 -9264 547.5 1047 s169 -4608 547.5 1112 s104 -6168 702.5 1177 s39 -7728 547.5 1242 g181 -9288 702.5 1048 s168 -4632 702.5 1113 s103 -6192 547.5 1178 s38 -7752 702.5 1243 g182 -9312 547.5 1049 s167 -4656 547.5 1114 s102 -6216 702.5 1179 s37 -7776 547.5 1244 g183 -9336 702.5 1050 s166 -4680 702.5 1115 s101 -6240 547.5 1180 s36 -7800 702.5 1245 g184 -9360 547.5 1051 s165 -4704 547.5 1116 s100 -6264 702.5 1181 s35 -7824 547.5 1246 g185 -9384 702.5 1052 s164 -4728 702.5 1117 s99 -6288 547.5 1182 s34 -7848 702.5 1247 g186 -9408 547.5 1053 s163 -4752 547.5 1118 s98 -6312 702.5 1183 s33 -7872 547.5 1248 g187 -9432 702.5 1054 s162 -4776 702.5 1119 s97 -6336 547.5 1184 s32 -7896 702.5 1249 g188 -9456 547.5 1055 s161 -4800 547.5 1120 s96 -6360 702.5 1185 s31 -7920 547.5 1250 g189 -9480 702.5 1056 s160 -4824 702.5 1121 s95 -6384 547.5 1186 s30 -7944 702.5 1251 g190 -9504 547.5 1057 s159 -4848 547.5 1122 s94 -6408 702.5 1187 s29 -7968 547.5 1252 g191 -9528 702.5 1058 s158 -4872 702.5 1123 s93 -6432 547.5 1188 s28 -7992 702.5 1253 g192 -9552 547.5 1059 s157 -4896 547.5 1124 s92 -6456 702.5 1189 s27 -8016 547.5 1254 g193 -9576 702.5 1060 s156 -4920 702.5 1125 s91 -6480 547.5 1190 s26 -8040 702.5 1255 g194 -9600 547.5 1061 s155 -4944 547.5 1126 s90 -6504 702.5 1191 s25 -8064 547.5 1256 g195 -9624 702.5 1062 s154 -4968 702.5 1127 s89 -6528 547.5 1192 s24 -8088 702.5 1257 g196 -9648 547.5 1063 s153 -4992 547.5 1128 s88 -6552 702.5 1193 s23 -8112 547.5 1258 g197 -9672 702.5 1064 s152 -5016 702.5 1129 s87 -6576 547.5 1194 s22 -8136 702.5 1259 g198 -9696 547.5 1065 s151 -5040 547.5 1130 s86 -6600 702.5 1195 s21 -8160 547.5 1260 g199 -9720 702.5 1066 s150 -5064 702.5 1131 s85 -6624 547.5 1196 s20 -8184 702.5 1261 g200 -9744 547.5 1067 s149 -5088 547.5 1132 s84 -6648 702.5 1197 s19 -8208 547.5 1262 g201 -9768 702.5 1068 s148 -5112 702.5 1133 s83 -6672 547.5 1198 s18 -8232 702.5 1263 g202 -9792 547.5 1069 s147 -5136 547.5 1134 s82 -6696 702.5 1199 s17 -8256 547.5 1264 g203 -9816 702.5 1070 s146 -5160 702.5 1135 s81 -6720 547.5 1200 s16 -8280 702.5 1265 g204 -9840 547.5 1071 s145 -5184 547.5 1136 s80 -6744 702.5 1201 s15 -8304 547.5 1266 g205 -9864 702.5 1072 s144 -5208 702.5 1137 s79 -6768 547.5 1202 s14 -8328 702.5 1267 g206 -9888 547.5 1073 s143 -5232 547.5 1138 s78 -6792 702.5 1203 s13 -8352 547.5 1268 g207 -9912 702.5 1074 s142 -5256 702.5 1139 s77 -6816 547.5 1204 s12 -8376 702.5 1269 g208 -9936 547.5 1075 s141 -5280 547.5 1140 s76 -6840 702.5 1205 s11 -8400 547.5 1270 g209 -9960 702.5 1076 s140 -5304 702.5 1141 s75 -6864 547.5 1206 s10 -8424 702.5 1271 g210 -9984 547.5 1077 s139 -5328 547.5 1142 s74 -6888 702.5 1207 s9 -8448 547.5 1272 g211 -10008 702.5 1078 s138 -5352 702.5 1143 s73 -6912 547.5 1208 s8 -8472 702.5 1273 g212 -10032 547.5 1079 s137 -5376 547.5 1144 s72 -6936 702.5 1209 s7 -8496 547.5 1274 g213 -10056 702.5 1080 s136 -5400 702.5 1145 s71 -6960 547.5 1210 s6 -8520 702.5 1275 g214 -10080 547.5 1081 s135 -5424 547.5 1146 s70 -6984 702.5 1211 s5 -8544 547.5 1276 g215 -10104 702.5 1082 s134 -5448 702.5 1147 s69 -7008 547.5 1212 s4 -8568 702.5 1277 g216 -10128 547.5 1083 s133 -5472 547.5 1148 s68 -7032 702.5 1213 s3 -8592 547.5 1278 g217 -10152 702.5 1084 s132 -5496 702.5 1149 s67 -7056 547.5 1214 s2 -8616 702.5 1279 g218 -10176 547.5 1085 s131 -5520 547.5 1150 s66 -7080 702.5 1215 s1 -8640 547.5 1280 g219 -10200 702.5 1086 s130 -5544 702.5 1151 s65 -7104 547.5 1216 dummy43 -8664 702.5 1281 g220 -10224 547.5 1087 s129 -5568 547.5 1152 s64 -7128 702.5 1217 dummy44 -8688 547.5 1282 g221 -10248 702.5 1088 s128 -5592 702.5 1153 s63 -7152 547.5 1218 dummy45 -8712 702.5 1283 g222 -10272 547.5 1089 s127 -5616 547.5 1154 s62 -7176 702.5 1219 vcom4 -8736 547.5 1284 g223 -10296 702.5 1090 s126 -5640 702.5 1155 s61 -7200 547.5 1220 vcom4 -8760 702.5 1285 g224 -10320 547.5 1091 s125 -5664 547.5 1156 s60 -7224 702.5 1221 dummy46 -8784 547.5 1286 g225 -10344 702.5 1092 s124 -5688 702.5 1157 s59 -7248 547.5 1222 dummy47 -8808 702.5 1287 g226 -10368 547.5 1093 s123 -5712 547.5 1158 s58 -7272 702.5 1223 g162 -8832 547.5 1288 g227 -10392 702.5 1094 s122 -5736 702.5 1159 s57 -7296 547.5 1224 g163 -8856 702.5 1289 g228 -10416 547.5 1095 s121 -5760 547.5 1160 s56 -7320 702.5 1225 g164 -8880 547.5 1290 g229 -10440 702.5 1096 s120 -5784 702.5 1161 s55 -7344 547.5 1226 g165 -8904 702.5 1291 g230 -10464 547.5 1097 s119 -5808 547.5 1162 s54 -7368 702.5 1227 g166 -8928 547.5 1292 g231 -10488 702.5 1098 s118 -5832 702.5 1163 s53 -7392 547.5 1228 g167 -8952 702.5 1293 g232 -10512 547.5 1099 s117 -5856 547.5 1164 s52 -7416 702.5 1229 g168 -8976 547.5 1294 g233 -10536 702.5 1100 s116 -5880 702.5 1165 s51 -7440 547.5 1230 g169 -9000 702.5 1295 g234 -10560 547.5 1101 s115 -5904 547.5 1166 s50 -7464 702.5 1231 g170 -9024 547.5 1296 g235 -10584 702.5 1102 s114 -5928 702.5 1167 s49 -7488 547.5 1232 g171 -9048 702.5 1297 g236 -10608 547.5 1103 s113 -5952 547.5 1168 s48 -7512 702.5 1233 g172 -9072 547.5 1298 g237 -10632 702.5 1104 s112 -5976 702.5 1169 s47 -7536 547.5 1234 g173 -9096 702.5 1299 g238 -10656 547.5 1105 s111 -6000 547.5 1170 s46 -7560 702.5 1235 g174 -9120 547.5 1300 g239 -10680 702.5 free datasheet http://www..net/
-p.11- himax confidential october 2005 HX8312-A 240rgbx320 dots, 262,144 color tft controller driver a pplication note preliminary v02 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. no. pad name x y 1301 g240 -10704 547.5 1302 g241 -10728 702.5 1303 g242 -10752 547.5 1304 g243 -10776 702.5 1305 g244 -10800 547.5 1306 g245 -10824 702.5 1307 g246 -10848 547.5 1308 g247 -10872 702.5 1309 g248 -10896 547.5 1310 g249 -10920 702.5 1311 g250 -10944 547.5 1312 g251 -10968 702.5 1313 g252 -10992 547.5 1314 g253 -11016 702.5 1315 g254 -11040 547.5 1316 g255 -11064 702.5 1317 g256 -11088 547.5 1318 g257 -11112 702.5 1319 g258 -11136 547.5 1320 g259 -11160 702.5 1321 g260 -11184 547.5 1322 g261 -11208 702.5 1323 g262 -11232 547.5 1324 g263 -11256 702.5 1325 g264 -11280 547.5 1326 g265 -11304 702.5 1327 g266 -11328 547.5 1328 g267 -11352 702.5 1329 g268 -11376 547.5 1330 g269 -11400 702.5 1331 g270 -11424 547.5 1332 g271 -11448 702.5 1333 g272 -11472 547.5 1334 g273 -11496 702.5 1335 g274 -11520 547.5 1336 g275 -11544 702.5 1337 g276 -11568 547.5 1338 g277 -11592 702.5 1339 through7 -11616 547.5 1340 through8 -11640 702.5 1341 dummy48 -11664 547.5 1342 dummy49 -11688 702.5 1343 vgldmy -11712 547.5 1344 dummy50 -11736 702.5 alignment mark x y (1-a) -11855 -394.5 (1-b) 11855 -394.5 (2-a) -11802 715.5 (2-b) 11802 715.5 free datasheet http://www..net/
-p.12- himax confidential october 2005 HX8312-A 240rgbx320 dots, 262,144 color tft controller driver a pplication note preliminary v02 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. bump arrangement 24.030mm source output: 720 + ds: 1 + gate output: 232+ dummy : 18 + through: 4 + vcom: 4 = 979 pads 450um 450um 1.670um g277 output pad dummy with internal line i/o pad dummy with internal line dummy : 12 450um 164.5um gate : 45 dummy : 2 dummy : 12 450um gate : 44 dummy : 3 164.5um i/o, input or dummy : 243 vcom1 ds1 vdd1 c1p vcom2 23.710mm g163 g162 vcom4 s2 s360 s361 s363 s719 vcom3 g160 g46 g47 g161 vcom3 s720 s359 s362 d u mmy s1 s3 vcom4 hx8312a face up (bump view) g278 g320 g321 g279 g44 g2 g1 g3 g45 vgldmy vgldmy testa2 testa4 note: there is no gold bumper on dummy 7,9,11, 23, 25, 27 pins. alignment mark (- 11802,715.5) (11802,715.5 ) (-11855,-394.5) (11855,-394.5) all layer prohibition unit:(um) 25um 50um 25um 25um 50um 25um 25um 20um 25um 25um 50um 25um 15um 15um 20um 10um 10um 20um 40um 30um 40um 30um 40um 40um 30um 40um 30um 40um free datasheet http://www..net/
-p.13- himax confidential october 2005 HX8312-A 240rgbx320 dots, 262,144 color tft controller driver a pplication note preliminary v02 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. bump size input bump size (type a) (pad 62~pad 304) 55um 117um 30um 55um output bump size (type b) (pad 1 ~ pad 61; pad 305 ~ pad 1344) height 15um 48um 26um 22um 22um 115um 22um 115um 40um free datasheet http://www..net/
-p.14- himax confidential october 2005 HX8312-A 240rgbx320 dots, 262,144 color tft controller driver a pplication note preliminary v02 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. pad coordinate 62 63 303 304 1343 1344 1341 1342 368 369 366 367 x(-) x(+) y(-) y(+) + origin 1 3 59 61 2 4 58 60 305 307 363 365 306 362 364 free datasheet http://www..net/
-p.15- himax confidential october 2005 HX8312-A 240rgbx320 dots, 262,144 color tft controller driver a pplication note preliminary v02 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. 5. system connection block diagram 320 db0~17 ncs, nwr(rnw), nrd(e), rs 18 240 pixels x rgb s1 s720 g 320 g0 g 319 g1 tft p anel 4 vcom vssd, vssd2 vsync hsync dot clk enable 4 vci vcc, iovcc dc/ dc hx8312a power supply circuit vcom gate driver circuit source driv er circuit os c resister system reset s719 s0 3 sdi, sdo, scl vssa figure 5. 1 system connection block diagram free datasheet http://www..net/
-p.16- himax confidential october 2005 HX8312-A 240rgbx320 dots, 262,144 color tft controller driver a pplication note preliminary v02 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. 6. layout recommendation display pane l 1uf 30 ohm 1uf 1uf 1uf 1uf dummy1 d ummy 2 dummy12 through1 through2 g278 g279 dummy13 dummy14 vmon dummy16 g321 c 23a c 23a c 23b c 23b c 22a c 22a c 22b c 22b c 21a c 21a c 21b c 21b c 12a c 12b c 12a c 12b vr2 vr2 vgl vgl iovccdum1 dds iognddum1 scleg1 iovccdum2 scleg0 iognddum2 hxeg iovccdum3 vseg iognddum3 dckeg iovccdum4 psx iognddum4 c86 iovccdum5 dtx1 iognddum5 dtx2 bws0 iognddum6 nreset nreset vsync vsync hsync hsync bws1 iovccdum7 bws2 iognddum7 rgbncpu iovccdum8 dotclk dotclk enable enable db17 db17 iognddum8 test2 iognddum9 vddd rvcc vddd iovccdum6 vgh rvcc v18 dummyr2 dummyr1 v18 os c1 os c1 os c2 os c2 vssd ds1 vgh vcom1 vcom1 testa2 dummy18 testa4 s3 s4 s1 s2 dummy44 dummy43 dummy45 vcom4 vcom4 dummy46 g162 dummy47 g163 g165 g164 g273 g272 g275 g274 g277 g276 dummy48 through8 through7 dummy49 vgldmy dummy50 dummy11 g320 si db0 db0 nrd(e) nrd(e) nwr(rnw) rs rs so so scl si scl ncs ncs cstb cstb test1 nwr(rnw) vssd vssa vssa iov c c iov c c vcomr vcc vcc vgs vgs vcomr vci vci vs vs vcoml vcoml vcomh vcomh vcl vcl testa1 testa1 vr1 vr1 addvdh addvd h ddvd h ddvd h c x 11a c x 11a c x 11b c x 11b c 11a c 11a c 11b c 11b vcom2 vcom2 dummy21 dummy20 g2 g1 g45 g44 through4 through3 dummy23 dummy22 dummy33 dummy32 vgldmy dummy34 dummy36 dummy35 through6 through5 g46 g48 g47 g161 g160 dummy38 dummy37 vcom3 vcom3 dummy41 dummy40 dummy39 s720 s719 s718 30 ohm 30 ohm 30 ohm 30 ohm 30 ohm 20 ohm 20 ohm 10 ohm 10 ohm 10 ohm 10 ohm 200 ohm 100 ohm 100 ohm 100 ohm 100 ohm 100 ohm 100 ohm 100 ohm 100 ohm 100 ohm 100 ohm 100 ohm 100 ohm 100 ohm 100 ohm 100 ohm 200 ohm 200 ohm 200 ohm 200 ohm 200 ohm 200 ohm 200 ohm 200 ohm 200 ohm 200 ohm 200 ohm 200 ohm 200 ohm 200 ohm 10 ohm 10 ohm 10 ohm 10 ohm 10 ohm 100 ohm 10 ohm 10 ohm 30 ohm 30 ohm 30 ohm 10 ohm 30 ohm 100 ohm 10 ohm 1uf iov c c vcc vci gnd 1uf 1uf 1uf 1uf 1uf 1uf nreset vsync hsync dotclk enable db17-0 nrd(e) nwr(rnw ) rs ncs 1uf 20 ohm 20 ohm 10 ohm 10 ohm 10 ohm open y x hx8312a 30 ohm open open 10 ohm connection inside the chip could be connected in th e panel layout could be connected in th e panel layout 1uf 1uf figure 6. 1 layout recommendation of HX8312-A free datasheet http://www..net/
-p.17- himax confidential october 2005 HX8312-A 240rgbx320 dots, 262,144 color tft controller driver a pplication note preliminary v02 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. 7. fpc circuit example vcc vci rs scleg0 rgbncpu dtx2 db9 enable c86 dummyr2 db0 db4 db15 scleg1 dds ncs sdi dummyr1 bws2 dckeg db5 dotclk vcom vcom db3 db7 db11 nwr(rnw) bws0 vsync bws1 vseg ds1 db10 hsync nreset vcom db8 db16 dtx1 sdo db1 cstb scl hseg vcom db13 db6 db14 db17 psx nrd(e) db2 db12 c12 c13 r1 c18 c7 tp5 tp4 tp2 u1 cmo_220_fpc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 dummy vcom vcom ds1 vgh c23a c23b c22a c22b c21a c21b c12a c12a c12b c12b vr2 vgl vgl dds scleg1 scleg0 hseg vseg dckeg psx c86 dtx1 dtx2 bws0 bws1 bws2 dummy rgbncpu dummy nreset vsync hsync dotclk enable db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 nrd(e) nwr(rnw) rs sdo sdi scl ncs cstb test1 test2 dummy vddd rvcc v18 dummyr1 dummyr2 osc1 osc2 vssd vssd vssa vssa iovcc vci vci vcc vgs vcomr vs vcoml vcomh vcl testa1 vr1 addvdh ddvdh cx11b cx11b cx11a cx11a c11b c11b c11a c11a testa2 vcom vcom testa4 dummy tp1 c17 c2 c8 c10 c9 c1 c5 c15 d1 c4 tp6 c14 c3 c11 tp3 c16 c6 panel hardware setting pin. connect to vcc or gnd in panel layout or in fpc mpu 4. testa1 , testa2 and testa4 is output test pin , and must be left open 3. the input pin must be fixed to vcc or gnd when no use 5. sdo pin is a output pin. sdo pin must be left open when no use 6. vcc and vci need to be separated to prevent interference 1. "tp1~6" are output pin test points 2. dummyr1 and dummyr2 are used for bumping resistance measurement free datasheet http://www..net/
-p.18- himax confidential october 2005 HX8312-A 240rgbx320 dots, 262,144 color tft controller driver a pplication note preliminary v02 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. specification of component connected to HX8312-A capacitor capacitor value / voltage on remarks c1 ( vgh ) 1uf/25v/b ( vgh ) conn ect to capacitor while using vgh c2 (c23a/b ) 1uf/10v/b ( ddvdh ) connect to capacitor according register bt bit setting c3 (c22a/b ) 1uf/10v/b ( ddvdh ) connect to capacitor according register bt bit setting c4 (c21a/b ) 1uf/10v/b ( ddvdh ) connect to capacitor according register bt bit setting c5 (c12a/b ) 1uf/6.3v/b ( vci ) connect to capacitor while using vcl c6 (vr2 ) 1uf/6.3v/b ( vci ) connect to capacitor while using vr2 c7 (vgl) 1uf/25v/b ( vgl ) connect to capacitor while using vgl c8 (v18) 1uf/6.3v/b ( vcc ) c9 (vci) 1uf/6.3v/b ( vcc ) c10 (vcc) 1uf/6.3v/b ( vci ) c11 (vs) 1uf/10v/b ( ddvdh ) connect to capacitor while using vs c12 (vcoml) 1uf/10v/b ( ddvdh ) connect to capacitor while using vcoml c13 (vcomh) 1uf/10v/b ( ddvdh ) connect to capacitor while using vcomh c14 (vcl) 1uf/6.3v/b ( vci ) connect to capacitor while using vcl c15 (vr1 ) 1uf/6.3v/b ( vci ) connect to capacitor while using vr1 c16 (ddvdh ) 1uf/10v/b (ddvdh ) connect to capacitor while using ddvdh c17 (cx11a/b ) 1uf/10v/b (ddvdh ) connect to capacitor while using ddvdh c18 (c11a/b ) 1uf/10v/b (ddvdh ) connect to capacitor while using ddvdh other component spec. remarks d1 ( vgl -gnd) vf < 0.4v / 20ma @ 25 c connect to shottky diode r1 ( vcc ) according to internal oscillator freq uency setting. suggest 100k ohm free datasheet http://www..net/
-p.19- himax confidential october 2005 HX8312-A 240rgbx320 dots, 262,144 color tft controller driver a pplication note preliminary v02 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. 8. pin description input parts signals i/o pin number connected with description bws2 i 1 mpu the bus width selection in rgb interface circuit. 0: 18-bit, 1: 16-bit bws1-0 i 2 mpu the bus width selection in system interface circuit. (see table 2. 1) psx i 1 mpu the parallel and serial bus interface selection in system interface circuit. 0: parallel bus interface, 1: serial bus interface ncs i 1 mpu chip select signal. 0: chip can be accessed; 1: chip cannot be accessed. nreset i 1 mpu reset pin. setting either pin low initializes the lsi. must be reset the chop after power being supplied. nrd (e) i 1 mpu i80 system: serves as a read signal and reads data at the low level. m68 system: 0: read/write disable ; 1: read/write enable fix it to iovcc or vssd level when using serial buss interface. nwr (rnw) i 1 mpu serves as a write signal and writes data at the rising edge. m68 system: 0: write ; 1: read fix it to iovcc or vssd level when using serial bus interface. c86 i 1 mpu mpu selection 0: i80 series mpu; 1: m68 series mpu. fix it to iovcc or vssd level when using serial bus interface. sdi i 1 mpu serial bus interface data input pin. fix it to iovcc or vssd level when using parallel bus interface. scl i 1 mpu serial bus interface clock input pin fix it to iovcc or vssd level when using parallel bus interface. rgb_ncpu i 1 mpu 0: system interface can be accessed. 1: system interface can not be accessed. rs i 1 mpu command/display data selection 0: command, 1: display data connect to iovcc or vssd level when serial bus interface is selected. dtx2-1 i 2 mpu specify the transferring method of on e pixel data in system interface. (see table 2. 3) scleg1-0 i 1 mpu determine the effective edge operation of sclk for sdi data latch and sdo data output. (see table 2. 6) vsync i 1 mpu vertical synchronization signal input pin. must be connected to iovcc if not in use. hsync i 1 mpu horizontal synchronization signal input pin. must be connected to iovcc if not in use. dotclk i 1 mpu dot clock signal input used in the rgb interface circuit. must be connected to iovcc if not in use. enable i 1 mpu enable signal pin used in rgb interface circuit. 0: disable, 1: enable when epl (d1 bit of r157) = 0. 0: enable, 1: disable when epl (d1 bit of r157) = 1. must be connected to iovcc if not in use. vseg i 1 mpu valid vsync polarity selection pin 0: start in the low level, 1: start in the high level hseg i 1 mpu valid hsync polarity selection pin 0: start in the low level, 1: start in the high level. dckeg i 1 mpu valid dotclk polarity selection pin 0: falling edge latch, 1: rising edge latch dds i 1 mpu selection the position of dummy line (321th line). 0: the end of the frame, 1: the beginning of the frame free datasheet http://www..net/
-p.20- himax confidential october 2005 HX8312-A 240rgbx320 dots, 262,144 color tft controller driver a pplication note preliminary v02 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. output parts signals i/o pin number connected with description sdo o 1 mpu serial bus interface data output pin. keep it open while using parallel bus interface cstb o 1 mpu frame synchronization signal output pin. keep it open if not in use. s1~s720 o 720 lcd source driver output pin. output voltages to the liquid crystal. g1~g321 o 321 lcd output signals to panel gate lines. vgh: the level to select the gate lines vgl: the level not to select the gate lines vcom1~4 o 4 lcd vcom output pin. they are short-circuited inside hx8312a. input / output parts signals i/o pin number connected with description db17-0 i/o 18 mpu operates liked an 18-bit bi-directional data bus. fix it to iovcc or vssd level when using serial bus interface. don?t set mpu output as hi-z when mpu has no output. osc2-1 i/o 2 oscillation resistor connect an external resistor for generating internal clock by internal r-c oscillation. or an external clock signal is supplied through osc1 with osc2 open. c11a , c11b cx11a , cx11b i/o 4 step up capacitor connect to the step-up capacitors for step up circuit 1 operation. leave this pin open if the internal step-up circuit is not used. c21a ,c21b c22a ,c22b c23a ,c23b i/o 6 step up capacitor connect to the step-up capacitors for step up circuit 2 operation. leave this pin open if the internal step-up circuit is not used. c12a ,c12b i/o 2 step up capacitor connect to the step-up capacitors for step up circuit 3 operation. leave this pin open if the internal step-up circuit is not used. free datasheet http://www..net/
-p.21- himax confidential october 2005 HX8312-A 240rgbx320 dots, 262,144 color tft controller driver a pplication note preliminary v02 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. power parts signals i/o pin number connected with description vcc i 1 power supply a power supply for the internal logic circuit. vcc = 2.2 ~ 3.3v vci i 1 power supply a power supply for step-up circuit and power supply circuit. vci = 2.5 ~ 3.3v iovcc i 1 power supply power supply fo r i/o circuit. iovcc = 1.65 ~ 3.3v v18 o 1 bypass capacitor and vddd, rvcc 1.8v regulator output. v18, vddd and rvcc must have the same voltage level. connect to vddd and rvcc on the fpc. rvcc i 1 v18 and vddd power supply for ram circuit. vddd i 1 v18 and rvcc power supply for logic circuit. vssd i 1 system ground ground for digital circuit. vssd2 i 1 system ground ground for internal circuit. vssa i 1 system ground ground for analog circuit. vgh o 1 bypass capacitor a positive power supply for the gate line drive circuit. vgl o 1 bypass capacitor schottky diode a negative power supply for the gate line drive circuit. insert a schottky diode in a forward direction to vssa. addvdh i 1 ddvdh power supply pins for vs and comh regulators. connected to ddvdh on fpc ddvdh o 1 addvdh and bypass capacitor output supply pin. connected to advddh on fpc. vdh o 1 bypass capacitor power supply for the source drive unit. vcl o 1 bypass capacitor the voltage of vci x (-1) output vr2-1 o 2 bypass capacitor reference voltage output for the step-up circuit 2. vs o 1 bypass capacitor power supply for the source drive unit. vgldmy o 1 - a negative power supply for the gate line drive circuit. vcomh o 1 bypass capacitor the high level voltage output of vcom ac voltage output. vcoml o 1 bypass capacitor the low level voltage output of vcom ac voltage output. when vcoml is fixed to gnd level ( vcomg=0), capacitor connection is not necessary. vgs i 1 gnd or external r a reference level for the grayscale voltage generating circuit. vcomr i 1 variable resistor adjusting vcomh level with an variable resistor between vdh and vssa. iovccdum 1~8 o 8 - pull-up pin for mode setting. these pins are connected to iovcc inside the chip. iognddum 1~9 o 9 - pull-down pin for mode setting. these pins are connected to vssd inside the chip. free datasheet http://www..net/
-p.22- himax confidential october 2005 HX8312-A 240rgbx320 dots, 262,144 color tft controller driver a pplication note preliminary v02 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. test pins and other signals i/o pin number connected with description test2-1 2 gnd test pin. must connect to gnd. ds1 o 1 - pin for gamma voltage output vmon o 1 - test pin output. must be left open. testa1, 2, 4 o 3 - test pin output. must be left open. through1 - 1 - dummy pads. used to measure the cog contact resistance. through1 and through8 are shor t-circuited within the chip. through8 - 1 - through2 - 1 - dummy pads. used to measure the cog contact resistance. through2 and through7 are shor t-circuited within the chip. through7 - 1 - through3 - 1 - dummy pads. used to measure the cog contact resistance. through3 and through6 are shor t-circuited within the chip. through6 - 1 - through4 - 1 - dummy pads. used to measure the cog contact resistance. through4 and through5 are shor t-circuited within the chip. through5 - 1 - dummyr1 - 1 - dummy pads. used to measure the cog contact resistance. dummyr1 and dummyr2 are short-circuited within the chip. dummyr2 - 1 - dummy1-1 4, 16, 18, 20-50 - 47 - dummy pin. ( there is no gold bumper on dummy 7,9,11, 23, 25 ,27) note : 1. the layout of vssa , vssd , vssd2 need to be separated in panel, and short together in fpc. 2. input pin must be fixed to vcc or vssd when no use. 3. the output pin must be left floating when no use. 4. sdo is a output pin. it must be left floating when no use. 5. test2 , 1 are test pin inputs. it must be conne cted to vssd. and the short connection of test1 , test2 and vssd must be located in fpc , not in panel. 6. ds1 , mon , testa1, 2, 4 are test pin outputs. it must be left floating. free datasheet http://www..net/
-p.23- himax confidential october 2005 HX8312-A 240rgbx320 dots, 262,144 color tft controller driver a pplication note preliminary v02 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. 9. chip access configuration 9.1 interface circuit the hx8312a has a system interface circuit for ram data / command transferring, and a rgb interface circuit for ram data transferring during animated display. the data bus pins (db17-0) is used as input both in system interface circuit and rgb interface circuit. external setting pin interface mode nwrgb (r02h,d0) psx rs vsync, hsync , dena , dotclk command transfer display data transfer 0 0 0 fixed system interface circuit ( parallel bus ) - 0 0 1 fixed - system interface circuit ( parallel bus ) 0 1 0 fixed system interface circuit ( serial bus ) - 0 1 1 fixed - system interface circuit ( serial bus ) 1 0 0 input system interface circuit ( parallel bus ) rgb interface circuit 1 0 1 input - rgb interface circuit 1 1 0 input system interface circuit ( serial bus ) rgb interface circuit 1 1 1 input - rgb interface circuit table 9. 1 interface type note: 1. system interface (parallel and serial bus) circuit is not available when external pin rgb_ncpu = "1". all operation from system interf ace input are not available. 2. please make sure that rgb interface circuit is only used for display data ram access, and can not be used for internal register access. 3. when nwrgb = ?1?, rgb interface circuit is used for display data ram accessed, and system interface circuit is used for internal register accessed. 4. when rgb interface and parallel bus system interf ace is in used, the data bus (db17-0) is used by system interface circuit for internal register acce ss when rs = ?l?, and the data bus (db17-0) is used by rgb interface circuit for display data ram access when rs = ?h?. free datasheet http://www..net/
-p.24- himax confidential october 2005 HX8312-A 240rgbx320 dots, 262,144 color tft controller driver a pplication note preliminary v02 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. 9.1.1 system interface circuit c86 input signal format selection 0 format for i80 series mpu 1 format for m68 series mpu table 9. 2 mpu selection external setting pin interface type psx bws1 bws0 dtx2 dtx1 bus width bit number in a pixel transferring method of ram data transferring method of command mpu1 0 0 0 x x 18-bit parallel 18-bits 18-bit collective mpu2 0 1 0 0 1 9-bit twice mpu3 0 1 0 1 1 18-bits 16-bit + 2-bit mpu4 0 1 0 0 0 16-bit parallel 16-bits 16-bit collective 16-bit collective mpu5 0 1 1 0 1 6-bit 3 times mpu6 0 1 1 1 1 18-bits 8-bit+8-bit+2-bit mpu7 0 1 1 1 0 8-bit parallel 16-bits 8-bit twice 8-bit twice mpu8 1 0 1 x x 18-bit serial 18-bits 18-bit serial 18-bit serial mpu9 1 1 1 x x 16-bit serial 16-bits 16-bit serial 16-bit serial table 9. 3 input bus format selection of system interface circuit free datasheet http://www..net/
-p.25- himax confidential october 2005 HX8312-A 240rgbx320 dots, 262,144 color tft controller driver a pplication note preliminary v02 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. parallel bus system interface ncs rs nwr(rnw) write to the display data ram ( m pu1 , m pu4 ) ncs rs nrd(e) read the display data ram ( mpu1 , mpu4 ) ncs rs nwr(rnw) db17(15)-0 ncs rs nwr(rnw) db17(15)-0 write to the register ( mpu1~ mpu4 ) read the register ( mpu1~mpu4 ) nrd(e) 18-bit parallel 16-bit parallel db15-0 dummy data 1st read data 2nd read data read the display ram data register address and command db15-8: register address db7-0: command data db15-8: register address db7-0: command data db17-8: inv alid data db7-0: command data ouput db15-8: inv alid data db7-0: command data ouput display data write to ram display data write to ram display data write to ram db17(15)-0 register address and command register address and command address = n address = n+1 address = n +2 db17-0 figure 9. 1 18 / 16-bit bus width parallel bus interface timing (for i80 series mpu) free datasheet http://www..net/
-p.26- himax confidential october 2005 HX8312-A 240rgbx320 dots, 262,144 color tft controller driver a pplication note preliminary v02 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. write to the display data ram 18-bit display data (6-bit x 3 transfers / 8-bit + 8-bit + 2-bit transfers) ncs rs db7-2 (db5-0) or db7-0 nwr(rnw) write to the dis pla y da ta ram 16-bit display data (8-bit x 2 transfers) ncs rs db7-0 nwr(rnw) read the display data ram 18-bit display data (6-bit x 3 transfers / 8-bit + 8-bit + 2-bit transfers) ncs rs db7-2 (db5-0) or db7-0 nrd(e) read the display data ram 16-bit display data (8-bit x 2 transfers) ncs rs db7-0 nrd(e) write to the re gis te r ncs rs db7-0 nwr(rnw) read the register ncs rs nrd(e) nwr(rnw) db7-0 register address command command 1st transferred data 2nd transferred data 3rd transferred data 1st transferred data 2nd transferred data 3rd transferred data nth pixel ; address = n (n+ 1)th pixel ; address = n + 1 upper 8-bit data lower 8-bit data upper 8-bit data lower 8-bit data u pper 8-bit data lower 8-bit data nth pixel (n+1)th pixel (n+2)th pixel nth pixel (n+ 1)th pixel nth pixel (n+ 1)th pixel (n+ 2)th pixel dummy data upper 8-bit data u pper 8-bit data u pper 8-bit data lower 8-bit data lower 8-bit data d ummy data 1st read data 2nd read data 3rd read data 1st read data 2nd read data register address db7-2 or db5-0 selection in 6-bit x 3 input mode is decided by msbf ( d0 bit) of r157 figure 9. 2 8-bit bus width parallel bus interface timing (for i80 series mpu) free datasheet http://www..net/
-p.27- himax confidential october 2005 HX8312-A 240rgbx320 dots, 262,144 color tft controller driver a pplication note preliminary v02 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. ncs rs nwr(rnw) write to the display data ram ( mpu1 , mpu4 ) ncs rs nrd(e) read the display data ram( mpu1 , mpu4 ) ncs rs nwr(rnw) db17(15)-0 ncs rs nwr(rnw) db17(15)-0 write to the register( mpu1 ~ mpu4 ) read the register( mpu ~ mpu4 ) 18-bit parallel db17-0 16-bit parallel db15-0 dummy data 1st read data 2nd read data read the display ram data register address and command db15-8: register address db7-0: inv alid data db15-8: register address db7-0: inv alid data db17-8: inv alid data db7-0: command data db15-8: inv alid data db7-0: command data register address and command register address and command nrd(e) nwr(rnw) nrd(e) nrd(e) display data write to ram display data write to ram db17(15)-0 display data write to ram address = n address = n+1 address = n+2 figure 9. 3 18 / 16-bit bus width parallel bus interface timing (for m68 series mpu) free datasheet http://www..net/
-p.28- himax confidential october 2005 HX8312-A 240rgbx320 dots, 262,144 color tft controller driver a pplication note preliminary v02 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. write to the display data ram 18-bit display data (6-bit x 3 transfers / 8-bit + 8-bit + 2-bit transfers) ncs rs db7-2 (db5-0) or db7-0 nwr(rnw) write to the display data ram 16-bit display data (8-bit x 2 transfers) ncs db7-0 read the display data ram 18-bit display data (6-bit x 3 transfers / 8-bit + 8-bit + 2-bit transfers) db7-2 (db5-0) or db7-0 nrd(e) read the display data ram 16-bit display data (8-bit x 2 transfers) db7-0 write to the register ncs rs db7-0 nwr(rnw) read the register ncs rs nrd(e) nwr(rnw) db7-0 register address command comman d 1st transferred data 2nd transferred data 3rd transferred data 1st transferred data 2nd transferred data 3rd transferred data nth pixel ; address = n (n+1)th pixel ; address = n+1 upper 8-bit data lower 8-bit data upper 8-bit data lower 8-bit data upper 8-bit data lower 8-bit data nth pixel ; address = n (n+1)th pixel ; address = n+1 (n+2)th pixel ; address = n+2 nth pixel (n+1)th pixel nth pixel (n+1)th pixel (n+2)th pixel dummy data upper 8-bit data upper 8-bit data upper 8-bit data lower 8-bit data lower 8-bit data dummy data 1st read data 2nd read data 3rd read data 1st read data 2nd read data register address db7-2 or db5-0 used in 6-bit x 3 input mode is decided by msbf ( d0 bit) of r157 nrd(e) rs nwr(rnw) nrd(e) ncs rs nwr(rnw) nrd(e) ncs rs nwr(rnw) nrd(e) figure 9. 4 8-bit bus width parallel bus interface timing (for m68 series mpu) free datasheet http://www..net/
-p.29- himax confidential october 2005 HX8312-A 240rgbx320 dots, 262,144 color tft controller driver a pplication note preliminary v02 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. serial bus system interface write to the display data ram ncs rs nwr(rnw) sdi scl read the display data ram rs nwr(rnw) sdo scl ncs write to the register rs nwr(rnw) sdi scl ncs rs nwr(rnw) sdi scl ncs sdo read the register 1 2 ... 15 16 1 2 ... 15 16 1 2 ... 15 1 6 display data (s15-0) display data write (s15-0) display data write (s15-0) display data read (s15-0) display data read (s15-0) dummy read (only the f irst 16bits) register address (s15-8) command data (s7-0) register address (s15-8) command data (s7-0) 1234567891011121 31415 16 1 23 456 7 8 91 01 112 1 314151 6 1 2 ... 15 16 1 2 ... 15 16 1 2 ... 15 1 6 after sending a command and display data in an 16-bit unit, set ncs as "h", and then send the next command and display data. figure 9. 5 16?bit serial bus interface timing (scleg1=scleg2=0) free datasheet http://www..net/
-p.30- himax confidential october 2005 HX8312-A 240rgbx320 dots, 262,144 color tft controller driver a pplication note preliminary v02 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. write to the display data ram ncs rs nwr(rnw) sdi scl read the display data ram rs nwr(rnw) sdo scl ncs write to the registers rs nwr(rnw) sdi scl ncs rs nwr(rnw) sdi scl ncs sdo read the registers 1 2 ... 1 7 1 81 2 ... 1 71 81 2 ... 1 71 8 display data (s17-0) display data (s17-0) display data(s17-0) display data read (s17-0) display data read (s17-0) dummy read (only the f irst 18bits) register address (s15-8) command data (s7-0) register address (s15-8) command data read (s7-0) 1 2 3 4 56 7 8 9 1 01 1 1 2 1 3 1 4 1 5 1 6 1 2 ... 1 71 812...1 71 8 1 2 ... 1 71 8 1 71 8 don't care 123 456 789 1 01 1 1 2 1 3 1 4 1 5 1 6 1 71 8 don't care invalid after sending a command and display data in an 18-bit unit, set ncs as "h", and then send the next command and display data. figure 9. 6 18?bit serial bus interface timing (scleg1=scleg2=0) free datasheet http://www..net/
-p.31- himax confidential october 2005 HX8312-A 240rgbx320 dots, 262,144 color tft controller driver a pplication note preliminary v02 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. relation between register command data format and input bus (1) mpu1, mpu2, mpu3, mpu4 type register db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 d 15 d 14 d 13 d 12 d 11 d 10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 input data bus transfer order 18-bit data db 2 db 1 db 0 db 5 db 4 db 3 db 17 db 16 (2) mpu5, mpu6, mpu7 type register db 7 db 6 d 15 d 14 d 13 d 12 d 11 d 10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 input data bus transfer order 8-bit data db 2 db 1 db 0 db 5 db 4 db 3 8-bit data db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 2 (3) mpu8 type register d 15 d 14 d 13 d 12 d 11 d 10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 sdi pin transfer order 18-bit data s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 s17 s16 (4) mpu9 type register d 15 d 14 d 13 d 12 d 11 d 10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 sdi pin transfer order 16-bit data s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 free datasheet http://www..net/
-p.32- himax confidential october 2005 HX8312-A 240rgbx320 dots, 262,144 color tft controller driver a pplication note preliminary v02 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. relation between display ram data format and input bus in system interface the display ram data is consist of 18 bits which include r-, g-, b-dot display level information. d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 (1) mpu1 type display ram data 262,144 colors are avaliable db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 d 17 d 16 d 15 d 14 d 13 d 12 d 11 d 10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 input data bus transfer order 18-bit data (2) mpu2 type (9-bit 2) display ram data 262,144 colors are avaliable db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 d 17 d 16 d 15 d 14 d 13 d 12 d 11 d 10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 input data bus transfer order 9-bit data 9-bit data 2 (3) mpu3 type (16-bit + 2-bit) display ram data 262,144 colors are avaliable db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 db 1 db 0 d 17 d 16 d 15 d 14 d 13 d 12 d 11 d 10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 input data bus transfer order 16-bit data 2-bit data 2 free datasheet http://www..net/
-p.33- himax confidential october 2005 HX8312-A 240rgbx320 dots, 262,144 color tft controller driver a pplication note preliminary v02 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. (4) mpu4 type (16-bit 1) display ram data 65,536 colors are avaliable db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 d 17 d 16 d 15 d 14 d 13 d 12 d 11 d 10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 input data bus transfer order 16-bit data (5-1) mpu5 type a (6-bit 3 ) with ( msbf = 0 ; d0 bit of r157 ) display ram data 262,144 colors are avaliable db 5 db 4 db 3 db 2 db 1 db 0 d 17 d 16 d 15 d 14 d 13 d 12 d 11 d 10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 input data bus transfer order 6-bit data db 5 db 4 db 3 db 2 db 1 db 0 db 5 db 4 db 3 db 2 db 1 db 0 6-bit data 6-bit data 2 3 (5-2)mpu5 type b (6-bit 3) with (msbf = 1; d0 bit of r157) display ram data 262,144 colors are avaliable d 17 d 16 d 15 d 14 d 13 d 12 d 11 d 10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 input data bus transfer order 6-bit data 6-bit data 6-bit data 2 3 db 7 db 6 db 5 db 4 db 3 db 2 db 7 db 6 db 5 db 4 db 3 db 2 db 7 db 6 db 5 db 4 db 3 db 2 (6) mpu6 type (8-bit + 8-bit + 2-bit) display ram data 262,144 colors are avaliable d 17 d 16 d 15 d 14 d 13 d 12 d 11 d 10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 input data bus transfer order 8-bit data 8-bit data 6-bit data 2 3 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 db 1 db 0 free datasheet http://www..net/
-p.34- himax confidential october 2005 HX8312-A 240rgbx320 dots, 262,144 color tft controller driver a pplication note preliminary v02 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. (7) mpu7 type (8-bit 2) display ram data 65,536 colors are avaliable d 17 d 16 d 15 d 14 d 13 d 12 d 11 d 10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 input data bus transfer order 8-bit data 8-bit data 2 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 db 2 db 1 db 0 db 7 db 6 db 5 db 4 db 3 (8) mpu8 type (18-bit serial) display data ram 262,144 colors are avaliable d 17 d 16 d 15 d 14 d 13 d 12 d 11 d 10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 sdi pin transfer order 18-bit data s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 s17 s16 (9) mpu9 type (16-bit serial) display ram data 65,536 colors are avaliable d 17 d 16 d 15 d 14 d 13 d 12 d 11 d 10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 sdi pin transfer order 16-bit data s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 free datasheet http://www..net/
-p.35- himax confidential october 2005 HX8312-A 240rgbx320 dots, 262,144 color tft controller driver a pplication note preliminary v02 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. 9.2 display ram address mapping 9.2.1 display ram address access mapping the hx8312a contains a display ram bus address counter (ac) which assigns x (pixel), y(line) address for writing pixel data to display ram. one x address equals to one pixel allocation. the display data will be written at a pixel which address is specified by x address register (r66) and y address register 1, 2 (r67, r68). s/g pins s1 s2 s3 s4 s5 s6 s7 s8 s9 --------- s709 s710 s711 s712 s713 s714 s715 s716 s717 s718 s719 s720 17---------0 17---------0 17---------0 --------- 17---------0 17---------0 17---------0 17---------0 g1 0000h 0001h 0002h --------- 00ech 00edh 00eeh 00efh g2 0100h 0101h 0102h --------- 01ech 01edh 01eeh 01efh g3 0200h 0201h 0202h --------- 02ech 02edh 02eeh 02efh g4 0300h 0301h 0302h --------- 03ech 03edh 03eeh 03efh g5 0400h 0401h 0402h --------- 04ech 04edh 04eeh 04efh g6 0500h 0501h 0502h --------- 05ech 05edh 05eeh 05efh g7 0600h 0601h 0602h --------- 06ech 06edh 06eeh 06efh g8 0700h 0701h 0702h --------- 07ech 07edh 07eeh 07efh g9 0800h 0801h 0802h --------- 08ech 08edh 08eeh 08efh g10 0900h 0901h 0902h --------- 09ech 09edh 09eeh 09efh g11 0a00h 0a01h 0a02h --------- 0aech 0aedh 0aeeh 0aefh g12 0b00h 0b01h 0b02h --------- 0bech 0bedh 0beeh 0befh g13 0c00h 0c01h 0c02h --------- 0cech 0cedh 0ceeh 0cefh g14 0d00h 0d01h 0d01h 0dech 0dedh 0deeh 0defh g15 0e00h 0e01h 0e01h 0eech 0eedh 0eeeh 0eefh ------- ------- ------- ------- --------- ------- ------- ------- ------- g231 13600h 13601 h 13602h --------- 136ech 136edh 136eeh 136efh g232 13700h 13701 h 13702h --------- 137ech 137edh 137eeh 137efh g233 13800h 13801 h 13802h --------- 138ech 138edh 138eeh 138efh g234 13900h 13901 h 13902h --------- 139ech 139edh 139eeh 139efh g235 13a00h 13a01h 13a02h --------- 13aech 13aedh 13aeeh 13aefh g236 13b00h 13b01h 13b02h --------- 13bech 13bedh 13beeh 13befh g237 13c00h 13c01h 13c 02h --------- 13cech 13cedh 13ceeh 13cefh g238 13d00h 13d01h 13d 02h --------- 13dech 13dedh 13deeh 13defh g239 13e00h 13e01h 13e02h --------- 13eech 13eedh 13eeeh 13eefh g240 13f00h 13f01h 13f02h --------- 13fech 13f edh 13feeh 13fefh table 9. 4 display ram address and display panel position (x size = 240, adx = 0) free datasheet http://www..net/
-p.36- himax confidential october 2005 HX8312-A 240rgbx320 dots, 262,144 color tft controller driver a pplication note preliminary v02 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. 9.2.2 display ram addr ess update direction every time when a pixel data is written into or read from the display ram, the x address or y address of ac will be automatically increased by 1 (or decreased by 1), which is decided by the register bits am( d2 bit of r157), adx(d7 bit of r1) and adr(d6 bit of r1) setting. x address direction adx x size = 180 x size = 208 x size = 240 0 x0 ? x179 ? x0 x0 ? x207 ? x0 x0 ? x239 ? x0 1 x179 ? x0 ? x179 x208 ? x0 ? x208 x240 ? x0 ? x240 adr y address direction 0 y0 ? y319 ? y0 1 y319 ? y0 ? y319 table 9. 5 x address and y address update direction setting figure 9. 7 address update direction settings am adr adx description figure am adr adx description figure 0 0 0 1 0 1 0 0 0 1 1 1 1 1 x239 x0 y0 y319 x0 x239 y319 y0 x239 x0 y0 y319 x239 x0 y319 y0 x0 x239 y0 y319 y0 y319 x0 x239 x0 x239 y319 y0 x239 x0 y319 y0 free datasheet http://www..net/
-p.37- himax confidential october 2005 HX8312-A 240rgbx320 dots, 262,144 color tft controller driver a pplication note preliminary v02 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. 9.2.3 display ram address mappi ng for source output channel r13 nso1 nso0 x size for display panel 0 0 240 0 1 208 1 0 180 1 1 inhibited table 9. 6 x size of panel display setting adx = 0 adc = 0 s1 s2 s3 s4 s5 s6 ------- s715 s716 s717 s718 s719 s720 source output adc = 1 s720 s719 s718 s717 s716 s715 ------- s6 s5 s4 s3 s2 s1 x address ?00?h ?01?h ------- ?ee?h ?ef?h bit allocation 17-12 11-6 5-0 17-12 11-6 5-0 ------- 17-12 11-6 5-0 17-12 11-6 5-0 pixel pixel 1 pixel 2 ------- pixel 239 pixel 240 adx = 1 adc = 0 s1 s2 s3 s4 s5 s6 ------- s715 s716 s717 s718 s719 s720 source output adc = 1 s720 s719 s718 s717 s716 s715 ------- s6 s5 s4 s3 s2 s1 x address ?00?h ?01?h ------- ?ee?h ?ef?h bit allocation 17-12 11-6 5-0 17-12 11-6 5-0 ------- 17-12 11-6 5-0 17-12 11-6 5-0 pixel pixel 1 pixel 2 ------- pixel 239 pixel 240 table 9. 7 display ram x address and output source channel ( x size = 240 ) adx = 0 adc = 0 s1 s2 s3 s4 s5 s6 ------- s715 s716 s717 s718 s719 s720 source output adc = 1 s720 s719 s718 s717 s716 s715 ------- s6 s5 s4 s3 s2 s1 x address ?00?h ?01?h ------- ?ce?h ?cf?h bit allocation 17-12 11-6 5-0 17-12 11-6 5-0 ------- 17-12 11-6 5-0 17-12 11-6 5-0 pixel pixel 1 pixel 2 ------- pixel 207 pixel 208 adx = 1 adc = 0 s1 s2 s3 s4 s5 s6 ------- s715 s716 s717 s718 s719 s720 source output adc = 1 s720 s719 s718 s717 s716 s715 ------- s6 s5 s4 s3 s2 s1 x address ?00?h ?01?h ------- ?ce?h ?cf?h bit allocation 17-12 11-6 5-0 17-12 11-6 5-0 ------- 17-12 11-6 5-0 17-12 11-6 5-0 pixel pixel 1 pixel 2 ------- pixel 207 pixel 208 s313 to s408 are invalid table 9. 8 display ram x address and output source channel ( x size = 208 ) free datasheet http://www..net/
-p.38- himax confidential october 2005 HX8312-A 240rgbx320 dots, 262,144 color tft controller driver a pplication note preliminary v02 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. adx = 0 adc = 0 s1 s2 s3 s4 s5 s6 ------- s715 s716 s717 s718 s719 s720 source output adc = 1 s720 s719 s718 s717 s716 s715 ------- s6 s5 s4 s3 s2 s1 x address ?00?h ?01?h ------- ?b2?h ?b3?h bit allocation 17-12 11-6 5-0 17-12 11-6 5-0 ------- 17-12 11-6 5-0 17-12 11-6 5-0 pixel pixel 1 pixel 2 ------- pixel 179 pixel 180 adx = 1 adc = 0 s1 s2 s3 s4 s5 s6 ------- s715 s716 s717 s718 s719 s720 source output adc = 1 s720 s719 s718 s717 s716 s715 ------- s6 s5 s4 s3 s2 s1 x address ?00?h ?01?h ------- ?b2?h ?b3?h bit allocation 17-12 11-6 5-0 17-12 11-6 5-0 ------- 17-12 11-6 5-0 17-12 11-6 5-0 pixel pixel 1 pixel 2 ------- pixel 179 pixel 180 s271 to s450 are invalid table 9. 9 display ram x address and output source channel ( x size = 180 ) free datasheet http://www..net/
-p.39- himax confidential october 2005 HX8312-A 240rgbx320 dots, 262,144 color tft controller driver a pplication note preliminary v02 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. 10. initial code for reference for the cmo s 2.2 glass, 240 x rgb x 320 resolution, vcc = vci = 2.8v input , rosc = 100kohm. the reference setting of chip initial on // this initial for cmo's 2.2" panel, // rosc = 100kohm // external dds pin = 1. // frame rate 65hz // using mpu 16bits /18bits interface, // operation voltage => vcc = vci = 2.8v. void lcd_hx8312a_intial(void) { set_lcd_reg(0x0001,0x0010); // start oscillation set_lcd_reg(0x0000,0x00a0); // standby mode cancel set_lcd_reg(0x0003,0x0001); // software reset operation delayx1ms(10); set_lcd_reg(0x0003,0x0000); // software reset operation cancel set_lcd_reg(0x002b,0x0004); // oscillator frequency adjust setting set_lcd_reg(0x0059,0x0001); // test register setting enable set_lcd_reg(0x0060,0x0022); // test register setting set_lcd_reg(0x0059,0x0000); // test register setting disable note 1 set_lcd_reg(0x0028,0x0018); // dc/dc clock frequency adjust setting set_lcd_reg(0x001a,0x0005); // step up circuit frequency adjust setting set_lcd_reg(0x0025,0x0005); // step up factor in step up circuit 2 setting set_lcd_reg(0x0019,0x0000); // vr1 and vr2 regulator factor setting //############# void power_on_s et(void) ################// set_lcd_reg(0x001c,0x0073); // step up circuit operat ing current setting set_lcd_reg(0x0024,0x0074); // v18 and vcom regulator current setting set_lcd_reg(0x0018,0x00c1); // vr1 and vr2 regulator on delayx1ms(10); set_lcd_reg(0x001e,0x0001); // extra step up circuit1 operation set_lcd_reg(0x0018,0x00c5); // ddvdh turn on set_lcd_reg(0x0018,0x00e5); // vcl turn on delayx1ms(60); set_lcd_reg(0x0018,0x00f5); // vgh and vgl turn on delayx1ms(60); set_lcd_reg(0x001b,0x0009); // vs/vdh turn on and set delayx1ms(10); set_lcd_reg(0x001f,0x0011); // vcom amplitude voltage setting set_lcd_reg(0x0020,0x000e); // vcomh voltage setting set_lcd_reg(0x001e,0x0081); // vcom operation start delayx1ms(10); free datasheet http://www..net/
-p.40- himax confidential october 2005 HX8312-A 240rgbx320 dots, 262,144 color tft controller driver a pplication note preliminary v02 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. //############# void chip_set (void) ################// set_lcd_reg(0x009d,0x0000); set_lcd_reg(0x00c0,0x0000); set_lcd_reg(0x00c1,0x0000); // bgr bit = ?0? note 2 set_lcd_reg(0x000e,0x0000); set_lcd_reg(0x000f,0x0000); set_lcd_reg(0x0010,0x0000); set_lcd_reg(0x0011,0x0000); set_lcd_reg(0x0012,0x0000); set_lcd_reg(0x0013,0x0000); set_lcd_reg(0x0014,0x0000); set_lcd_reg(0x0015,0x0000); set_lcd_reg(0x0016,0x0000); set_lcd_reg(0x0017,0x0000); set_lcd_reg(0x0034,0x0001); set_lcd_reg(0x0035,0x0000); set_lcd_reg(0x004b,0x0000); set_lcd_reg(0x004c,0x0000); set_lcd_reg(0x004e,0x0000); set_lcd_reg(0x004f,0x0000); set_lcd_reg(0x0050,0x0000); set_lcd_reg(0x003c,0x0000); set_lcd_reg(0x003d,0x0000); set_lcd_reg(0x003e,0x0001); set_lcd_reg(0x003f,0x003f); set_lcd_reg(0x0040,0x0002); set_lcd_reg(0x0041,0x0002); set_lcd_reg(0x0042,0x0000); set_lcd_reg(0x0043,0x0000); set_lcd_reg(0x0044,0x0000); set_lcd_reg(0x0045,0x0000); set_lcd_reg(0x0046,0x00ef); set_lcd_reg(0x0047,0x0000); set_lcd_reg(0x0048,0x0000); set_lcd_reg(0x0049,0x0001); set_lcd_reg(0x004a,0x003f); set_lcd_reg(0x001d,0x0008); // gate scan direction setting set_lcd_reg(0x0086,0x0000); set_lcd_reg(0x0087,0x0030); set_lcd_reg(0x0088,0x0002); set_lcd_reg(0x0089,0x0005); set_lcd_reg(0x008d,0x0001); // register set-up m ode for one line clock number set_lcd_reg(0x008b,0x0030) // one line sysclk number in one-line scan set_lcd_reg(0x0033,0x0001); // n line inversion setting set_lcd_reg(0x0037,0x0001); // scanning method setting set_lcd_reg(0x0076,0x0000); free datasheet http://www..net/
-p.41- himax confidential october 2005 HX8312-A 240rgbx320 dots, 262,144 color tft controller driver a pplication note preliminary v02 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. //############# void gamma_s et(void) ################// set_lcd_reg(0x008f,0x0000); set_lcd_reg(0x0090,0x0077); set_lcd_reg(0x0091,0x0007); set_lcd_reg(0x0092,0x0054); set_lcd_reg(0x0093,0x0007); set_lcd_reg(0x0094,0x0000); set_lcd_reg(0x0095,0x0077); set_lcd_reg(0x0096,0x0045); set_lcd_reg(0x0097,0x0000); set_lcd_reg(0x0098,0x0006); set_lcd_reg(0x0099,0x0003); set_lcd_reg(0x009a,0x0000); //############# void display_o n(void) ################// set_lcd_reg(0x003b,0x0001); delayx1ms(40); set_lcd_reg(0x0000,0x0020); } note: 1. change the default setting of internal test register for normal display. 2. change the default setting of the nee-added register in new-version chip for bgr setting. 3. when using initial code as above for cmo 2.2? glass, the gamma curve is as follow blue line : ideal = 2.2 red line : measure data free datasheet http://www..net/
-p.42- himax confidential october 2005 HX8312-A 240rgbx320 dots, 262,144 color tft controller driver a pplication note preliminary v02 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. the reference setting of into standby mode // this initial for cmo's 2.2" panel, // using mpu 16bits /18bits interface, // operation voltage => vcc = vci = 2.8v. void lcd_hx8312a_into_stb(void) { //############# void display_ off_set(void) ################// set_lcd_reg(0x0000,0x00a0); delayx1ms(40); set_lcd_reg(0x003b,0x0000); //############# void power_off_s et(void) ################// set_lcd_reg(0x001e,0x0001); // vcom off set_lcd_reg(0x001b,0x0008); // vs / vdh power off set_lcd_reg(0x001c,0x0000); // step up circuit oper ating current off set_lcd_reg(0x0024,0x0000); // v18 and vcom regulator current off set_lcd_reg(0x0018,0x0000); //############# into stand by mode ################// set_lcd_reg(0x0001,0x0011); // internal oscillator stop set_lcd_reg(0x0000,0x0028); // into stand by mode } note: 1. in standby mode, only register can be updated and the display ram can not be updated. the display ram data can be retained in the stand by mode operation. . free datasheet http://www..net/
-p.43- himax confidential october 2005 HX8312-A 240rgbx320 dots, 262,144 color tft controller driver a pplication note preliminary v02 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. the reference setting of stand by mode cancel void lcd_hx8312a_stb_cancel(void) { //############# stand by mode cancel ################// set_lcd_reg(0x0000,0x00a0); // stand by mode cancel set_lcd_reg(0x0001,0x0010); // internal oscillator start delayx1ms(10); //############# power _on_set ################// set_lcd_reg(0x001c,0x0073); // step up circuit operat ing current setting set_lcd_reg(0x0024,0x0074); // v18 and vcom regulator current setting set_lcd_reg(0x0018,0x00c1); // vr1 and vr2 regulator on delayx1ms(10); set_lcd_reg(0x0018,0x00c5); // ddvdh turn on set_lcd_reg(0x0018,0x00e5); // vcl turn on delayx1ms(60); set_lcd_reg(0x0018,0x00f5); // vgh and vgl turn on delayx1ms(60); set_lcd_reg(0x001b,0x0009); // vs/vdh turn on and set delayx1ms(10); set_lcd_reg(0x001e,0x0081); // vcom operation start delayx1ms(10); //############# void display_o n(void) ################// set_lcd_reg(0x003b,0x0001); delayx1ms(40); set_lcd_reg(0x0000,0x0020); free datasheet http://www..net/
-p.44- himax confidential october 2005 HX8312-A 240rgbx320 dots, 262,144 color tft controller driver a pplication note preliminary v02 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. the reference setting of into off mode // this initial for cmo's 2.2" panel, // using mpu 16bits /18bits interface, // operation voltage => vcc = vci = 2.8v. void lcd_hx8312a_into_off(void) { //############# void display_ off_set(void) ################// set_lcd_reg(0x0000,0x00a0); delayx1ms(40); set_lcd_reg(0x003b,0x0000); //############# void power_off_s et(void) ################// set_lcd_reg(0x001e,0x0001); // vcom off set_lcd_reg(0x001b,0x0008); // vs / vdh power off set_lcd_reg(0x001c,0x0000); // step up circuit oper ating current off set_lcd_reg(0x0024,0x0000); // v18 and vcom regulator current off set_lcd_reg(0x0018,0x0000); //############# into off mode ################// set_lcd_reg(0x0001,0x0011); // internal oscillator stop set_lcd_reg(0x00c0,0x0080); // into off mode } note: 1. in off mode, only offmod bit (d7 bit of r192) can be updated. other register and the display ram can not be updated. the display ram data may not be retained in the off mode operation , and need to rewrite after off mode canceling. free datasheet http://www..net/
-p.45- himax confidential october 2005 HX8312-A 240rgbx320 dots, 262,144 color tft controller driver a pplication note preliminary v02 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. the reference setting of off mode cancel void lcd_hx8312a_off_cancel(void) { //############# off mode canc el ################// set_lcd_reg(0x00c0,0x0000); // off mode cancel set_lcd_reg(0x0001,0x0010); // internal oscillator start delayx1ms(10); //############# power _on_set ################// set_lcd_reg(0x001c,0x0073); // step up circuit operat ing current setting set_lcd_reg(0x0024,0x0074); // v18 and vcom regulator current setting set_lcd_reg(0x0018,0x00c1); // vr1 and vr2 regulator on delayx1ms(10); set_lcd_reg(0x0018,0x00c5); // ddvdh turn on set_lcd_reg(0x0018,0x00e5); // vcl turn on delayx1ms(60); set_lcd_reg(0x0018,0x00f5); // vgh and vgl turn on delayx1ms(60); set_lcd_reg(0x001b,0x0009); // vs/vdh turn on and set delayx1ms(10); set_lcd_reg(0x001e,0x0081); // vcom operation start delayx1ms(10); //############# void display_o n(void) ################// set_lcd_reg(0x003b,0x0001); delayx1ms(40); set_lcd_reg(0x0000,0x0020); free datasheet http://www..net/
-p.46- himax confidential october 2005 HX8312-A 240rgbx320 dots, 262,144 color tft controller driver a pplication note preliminary v02 this information contained herein is the exclusive property of himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of himax. subject to change without notice. 11. reversion history version eff. date description changes 01 2005/07/14 new setup 02 2005/10/04 1. add note 5 in p.22. 2. add note 1, 2 in p.41. 3. a dd and correct the initial code (blue item) in p.39 ~ p.45. 4. correct the ? x address? in table 9.7~9.9 in p.37~p.38 free datasheet http://www..net/

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