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1/11 AN1696 application note april 2003 introduction load sharing is a technique commonly used when powering loads requiring low voltage and high current; for this reason a modular power system is built where two (or more) power supplies or dc-dc converters are par- alleled and supply the load. sharing the output currents is useful to equalize the thermal stress of the different modules providing an advan- tage in terms of electronic components reliab ility (m ean time between failure roughly doubles every 10c de- crease in operating temperature). by luca salati l6615, load share controller for n+1 redundant, hot-swappable application power supply systems are often designed by paralleling converters in order to improve performance or reliability. to ensure uniform distribution of stresses, the total load current should be equally shared among the converters. this application note describes a redundant system (a demo board is available) composed by three par- alleled dc-dc converter modules (synchronous buck topology, managed by st l6910) whose output currents are shared through the new st current sharing controller (l6615). in this application it is shown the innovative use of a mosfet as both or-ing element (replacing or- ing diode) and sensing element (r ds(on )).
AN1696 application note 2/11 in this application, load sharing control is entrusted to st's l6615 [1] that features automatic master-slave cur- rent sharing control [2] [3]: the supply that delivers the highest current (sensed by means of an external resistor) acts as the master and drives a common reference (share bus) to a voltage proportional to its output current; the feedback voltage of the others paralleled power supplies (slaves) is then trimmed by an "adjustment" net- work so that they can support their amount of load current. the slave supplies work as current-controlled current sources. moreover a paralleled supply architecture allows achieving redundancy (a system of paralleled power supplies, each delivering a current lower than its nominal capability); the failure of one of the modules can be tolerated until the capability of the remaining power supplies is enough to provide the required load current. in this way an interruptible power supply will be designed, reducing the failure rate of the output bus. in hot-swappable applications, whenever a section fails, it has to be removed and replaced without turning off the system and causing significant perturbation to both input and output system buses. at insertion, each section exhibits a certain amount of discharged capacitance between the input terminals: if no inrush current limiting protection is implemented, this will cause a large negative drop on the input bus volt- age (the analysis of this issue is beyond the purpose of this document). the same problem occurs on the output side whenever the load is already supplied by other running sections: the discharged output capacitors of the inserted section are a very low impedance that can generate a negative drop on the load bus. this could trigger the uv/oc protection or cause a false value if a logic circuit reads the power supply output voltage at its input. figure 1. system architecture this is way an isolating element is introduced on each of the lines connecting the power output of each section with the load; often an or-ing diode is used for this purpose but the latest trend is to use an or-ing fet to save some points in efficiency. this, combined with the capability of st's l6615 load share controller to perform high side sensing, allows the use of the r ds(on) of this fet as a sensing element as well. system description the system (fig. 2) is composed of: l o a d power supply #1 & current sharing control power supply #2 & current sharing control power supply #n & current sharing control share bus input voltage output voltage l o a d power supply #1 & current sharing control power supply #2 & current sharing control power supply #n & current sharing control share bus input voltage output voltage
3/11 AN1696 application note C three identical sections (daughter boards) able to perform dc-dc conversion starting from +5v dc ; each of them is designed to deliver 3.3v/5a to the load. they must be inserted in the motherboard; C a motherboard whose input terminals will be connected to a +5v dc external source and output ter- minals to the load. this board can accommodate up to three dc-dc converters. on the motherboard there is the circuitry necessary to perform current sharing (l6615) and to isolate a failed section from the load; it is designed to be adaptable to all power supplies (whose rating are compatible with l6615 absolute maximum ratings) having remote sense pins; in fact only changing few components it can be rearranged for new specs. it is so possible to build a system to supply a 10a load at +3.3v in 2+1 redundant configuration. that is, whenever three sections are running, each of them supplies 3.33a, a value lower than its nominal capability. if one of them is switched off, the system is however able to supply the load and each section w ill carry 5a. the dc-dc conversion management is entrusted to the l6910 [4]. it is possible to verify that disabling one section (through the relevant switch on the motherboard) does not cause either overvoltage on the output or overcurrent in other sections. at the same way, enabling one section (with other two already running) does not cause output voltage negative drop or even short to ground and current sharing is established. figure 2. system overview 1.0 daughter board the l6910 controller drives a synchronous step-down stage at 200khz; the internal reference is used for the regulation. the external power mosfet's are included in one so8 package to save space and increase power density. fig. 3 shows the schematic of each daughter board and in table 1 the part list is indicated (for the description of this section see [4]). current sharing (l6615), oring fet and aux. circuitry dc-dc conversion (daughter board) current sharing (l6615) oring fet and aux. circuitry current sharing (l6615) oring fet and aux. circuitry dc-dc conversion (daughter board) r sense dc-dc conversion (daughter board) +5v gnd gnd 10a@+3.3v v sense r sense v sense r sense v sense motherboard sh bus adj adj adj current sharing (l6615), oring fet and aux. circuitry dc-dc conversion (daughter board) current sharing (l6615) oring fet and aux. circuitry current sharing (l6615) oring fet and aux. circuitry dc-dc conversion (daughter board) r sense dc-dc conversion (daughter board) +5v gnd gnd 10a@+3.3v v sense r sense v sense r sense v sense motherboard sh bus adj adj adj
AN1696 application note 4/11 figure 3. daughter board schematic table 1. part list board l6910 resistors r1, r9, r10 10 smd 0805 r7 1k2 smd 0805 r2 1k5 smd 0805 r8 10k smd 0805 r3 2k7 smd 0805, 1% r9 82 smd 0805 r4, r5 2.2 smd 0805 r10 39 smd 0805 r6 3k75 smd 0805, 1% r11 680 smd 0805 capacitors c1, c2 10 m f (tokin) c34y5u1e106zte12 c7, c12 1nf smd0805, ceramic c3, c4, c8, c13 100nf smd0805, ceramic c9, c10 10nf smd0805, ceramic c5 47nf smd0805, ceramic c11 330 m f C 6.3v (poscap) 6tpb330m c6 n.c. smd0805, ceramic inductor l1 10 m h t50-52b core 12t ics u1 l6910 (st) so16 narrow q1 sts8dnf3l l (st) so8 diodes d1, d3, d4 1n4148 sot23 d2 stp130a sma l1 r2 c1Cc2 c7 c11 q1 d2 13 14 10 11 3 1 l6910 vcc out 6 12 5 15 7 9 vcc gnd vref ss ocset ugate phase lgate pgnd pgood vfb comp c5 c3 c8 d1 pgnd c9 c4 r1 c6 8 r3 r8 earef boot ss sgnd +sout r6 r7 c10 r4 r5 r10 r9 4 c12 c13 d3 d4 pump r11 l1 r2 c1Cc2 c7 c11 q1 d2 13 14 10 11 3 1 l6910 vcc out 6 12 5 15 7 9 vcc gnd vref ss ocset ugate phase lgate pgnd pgood vfb comp c5 c3 c8 d1 pgnd c9 c4 r1 c6 8 r3 r8 earef boot ss sgnd +sout r6 r7 c10 r4 r5 r10 r9 4 c12 c13 d3 d4 pump r11
5/11 AN1696 application note besides the standard components necessary to perform dc-dc conversion, a charge pump (d3, d4, c12, c13, r11) has been added to provide a voltage high enough to bring the gate of the or-ing fet (on the motherboard) at least one threshold above v out (v gate >3.3v+v gs(th) ); moreover, increasing v gs voltage allows working with a lower r ds(on) and reducing mosfet conduction losses. this pump, running whenever pwm activity is present, pushes the gate of the or-ing fet up to a voltage equal to: (1) (where v f is the forward drop of the diodes) supplying a current equal to: (2) from the daughter board, besides input/output voltages and ground, other signals exit toward the motherboard: C soft-start: the soft-start voltage is brought out and connected to a switch (that can short soft-start to ground) allowing enable/disable of the relevant section; C +sout and sgnd are the sense terminals for positive and negative load terminals; they are con- nected to the relative power traces through two small resistors to avoid that any kind of open connec- tion (or the sense pins left open) could cause a lost of control. 2.0 motherboard the motherboard accommodates all the auxiliary circuitry necessary to load sharing, to manage start-up and to enable/disable each of the three daughter boards; a led indicates the disabled section. terminals are available to connect input dc voltage and load and three series of connectors allow inserting the daughter boards. in fig. 4 the structure of one section of the motherboard is showed: replying this structure other two times the entire board is obtained; table 2 reports the part list. figure 4. motherboard schematic v gate max () 2v in 2v f C = i ch v in c 12 f sw = 1 7 (-)6 (+)5 8 3( +) 4 2(-) pgnd sgnd +sout ss out vcc pgnd + in -in r1 r14 r7 r5 q1 c4 r15 jp1 r13 u2 1 7 6 5 8 3 4 2 u1 c1 sw 1 c2 c5 c6 r3 r11 r12 c7 r2 led d3 c10 + out - out r10 c3 d1 d2 r4 pump r8 r9 c8 c9 to other sections to other sections common share bus 1 7 (-)6 (+)5 8 3( +) 4 2(-) pgnd sgnd +sout ss out vcc pgnd + in -in r1 r14 r7 r5 q1 c4 r15 jp1 r13 u2 1 7 6 5 8 3 4 2 u1 c1 sw 1 c2 c5 c6 r3 r11 r12 c7 r2 led d3 c10 + out - out r10 c3 d1 d2 r4 pump r8 r9 c8 c9 to other sections to other sections common share bus
AN1696 application note 6/11 table 2. part list board l6615 to measure the current carried by each section, it is possible to open the jumper jp1 (see schematic) and to place a ring for inserting a current probe. 2.1 or-ing fet and current sensing high side current sensing is implemented by reading the voltage drop across the r ds(on) of q1 (during normal operation the fet is maintained on by the charge pump); the voltage at l6615 cga pin of the section #n is proportional to its output current, in particular [1]: (1) the first parameter to consider when selecting the or-ing fet is its r ds(on) because, for a given output cur- rent, it defines both the power dissipation and the drop useful for current sharing. increasing r ds(on) leads to a wide sense signal available but also means higher power dissipation. in the motherboard q1 is a sts8dnf3ll [5] having (for each mos): sts8dnf3ll contains two internal mosfets that are paralleled leading to halve the r ds(on) . the design must be done considering worst case conditions to avoid share bus saturation: only two sections running and maximum value for r ds(on) . considering also the temperature variation, we have: r ds(on)|@tmax = 0.015 w then the maximum drop will be 75mv and (1) leads to v cga(max) = v sh(max) of about 2.8v. it can be useful to calculate the losses associated to the or-ing fet and compare them with the losses in case resistors r1, r10 6k8 r5, r8 1k r13 82 r2 20k r7 330k r14 7k5 r3 2k r9 47k r15 100 r4 3k3 r11, r12 200 capacitors c1, c2, c4 100nf c5 1 m f c8, c9, c10 open c3 4.7 m f c6, c7 10nf ics u1 l6615d (st) so8 u2 lm293 so8 q1 sts8dnf3ll (st) so8 diodes d1, d2, d3 1n4148 sot23 r ds(on) = 0.017 (nom.) @ id=4a, vgs=10v, tcase=25c 0.020 w (max.) v cga # n () i out # n () r ds on () r 14 r 12 --------- =
7/11 AN1696 application note of or-ing diode (as a reference we consider the low drop schottky diode stps10l25d [6]). considering t max and i d = 5a, we have: C or-ing fet (sts8dnf3ll) C or-ing diode (stps10l25d) obviously in the case of the diode, also the sense resistor is needed: assuming the same 75mv drop, the total dissipation will be 1.8w. we can estimate 1.4w saving, leading to about 8.5% efficiency rise. 2.2 current sharing control for each section one l6615 controller is associated with the few external components necessary to its opera- tion. load sharing is achieved through a single wire connection (share bus) between all the paralleled modules, whose voltage is proportional to the highest output current amongst all the active sections. in particular, being unity the (internal) gain between cga and sh pins, on the share bus there w ill be the hi ghest of the values given by (1). in case of very noisy application, two capacitors (c8 and c9) allow filtering the l6615 current sense pins (#2 and #3). the l6615 error amplifier is of transconductance type so a compensation network is required connected be- tween l6615 pin #5 and ground; in this case an rc series network (c5-r15) determines a bandwidth of about 1khz for the sharing loop. the l6615 adj pin (pin#4) is connected to the daughter board: a current proportional to the output currents unbalance is sunk from the feedback path of the relevant section. the value of adjustment resistor (r13, between positive output terminal and adj pin) must be chosen in accor- dance with both the maximum current sink capability of pin adj and the output voltage tolerance. if we consider v out = +3.3v with a tolerance of 5%, the maximum spread between the master output voltage and the slave one could be 330mv: this is the drop that the l6615 must be able to correct imposing a current to flow through the adjustment resistor. its resistance value must be lower than the feedback divider (r6 and r8) to have no impact on the value of regulated voltage. the design of this resistor is a very simple process: it is enough to choose for the maximum adjustment current a value lower than the maximum specified for l6615 (8ma, worst case) and verify that this does not cause the saturation of the l6615 internal bjt (see fig. 5) under steady state condition. in this case: adj. current: i adj(max) = 8ma min adj. resistor: in fact this resistance value is obtained considering the parallel of r13 (motherboard) and r9 (daughter board), each of them equal to 82 w . p diss i d 2 r ds on () 0.375w = = p diss 0.22 i d avg () 0.013 i drms () 2 1.425w = + = r adj min () d v out max () i adj --------------------------------- - 330ma 8ma ------------------- 41.25 w ===
AN1696 application note 8/11 figure 5. adjustment network 2.3 gate driver of or-ing fet the or-ing fet gate is driven by the output of a comparator (one section of an lm293, standard double com- parator) sensing the voltage upstream (source) and downstream (drain) the or-ing fet (see fig. 6). this turns- off the transistor whenever a current tries flowing from the load towards the output stage of a daughter board. whenever one section is enabled with the two others already running (hot plug), its output capacitor is com- pletely discharged: to avoid a negative drop on the load voltage, the gate of the fet is kept low until v c(out) reaches a value very close to v load (this can be set defining the ratio between r5 and r7). the pwm starts charging output capacitor (v c(out ) increases) and, only when: the fet is turned on. moreover the load must be isolated from a failed section; for example in case of a short circuit on the low side power mos of one section, then a current will tend to flow in reverse direction through the corresponding or- ing fet. figure 6. or-ing fet management v out = +3.3v r a adj r 13 + - i adj l6615 motherboard daugtherboard l6910 v fb r 8 r 6 r 7 c 10 v out = +3.3v r a adj r 13 + - i adj l6615 motherboard daugtherboard l6910 v fb r 8 r 6 r 7 c 10 v cout () on C v ref 1 r5 r7 ------- - + ?? ?? v load r8 r8 r9 + ---------------------- ?? ?? 1 r5 r7 ------- - ?? ?? == l o a d - + r8 r9 c2 r7 daughterboard motherboard r5 v c(out) v load v ref v ps+ v gate v ref v c(out) v ps+ v gate d v h yst v pump v c(out)-on v c(out)-off v load sections already running r11 v pump pump charge l o a d l o a d - + r8 r9 c2 r7 daughterboard motherboard r5 v c(out) v load v ref v ps+ v gate v ref v c(out) v ps+ v gate d v h yst v pump v c(out)-on v c(out)-off v load sections already running r11 v pump pump charge
9/11 AN1696 application note for a short time (before overcurrent/undervoltage protections are triggered), the unbroken sections are able to deliver such high current maintaining the load voltage in the right range. this in turn causes v c(out) to be lower than v load and the or-ing fet will be turned off whenever v c(out) = v c(out)-off . it is possible to obtain the value of the current necessary to push v c(out) at v c(out)-off : 3.0 demo-board behaviour the aim of this demo-board is mainly to show the operation of current sharing section, drawing the attention also to the management of the or-ing fet. for this reason no protection have been introduced to prevent in- rush current: it is not possible to actually insert or remove a daughter board during normal operating, neverthe- less it is recommended to simulate a fault by enabling/disabling one section through the switch sw1 (it shorts to gnd the soft-start pin). once all the daughter board are inserted (with the switches on the "on" position), the system is ready to be powered-up. measuring the three output currents and varying the load continuously, it is possible to see the load share ac- curacy (fig. 7); obviously, at light load, the accuracy is not so high because is higher the weight of both the mis- matches between relevant components and the noise is higher. at full load (10a) the maximum error is lower than 2.5%. fig. 8 shows the behaviour of the system whenever a fault condition appears on section 1 when the three sec- tions are operating supplying a total load of 10a (each of them carries about 3.3a); in particular it is simulated a short of the low side fet of the synchronous rectifier section 1. if no or-ing element were implemented, this could cause a short circuit condition on the other two sections (uv and/or overcurrent protection could be activated): here the gate driver circuit opens the or-ing fet preventing current flow from the load to the output of section 1 and the output voltage experiences only a very small drop. the currents of section 2 and 3 grow up to 5a. i rev 1 r ds on () ---------------------- - v load 1 r9 r8 r9 + ---------------------- ?? ?? 1 r5 r7 ------- - + ?? ?? C ?? ?? v pump r5 r7 ------- - + ?? ?? = figure 7. load share accuracy figure 8. fault on one section -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 10 20 30 40 50 60 70 80 90 100 output current [%] load share accuracy [%] i out1 i out2 i out 3
AN1696 application note 10/11 references [1] "l6615 high/low side load share controller" (datasheet) [2] v. j. thouttevelil, c. g. verghese, "analysis and control design of paralleled dc/dc converters with current sharing", ieee transaction on power electronics, vol. 13, n. 4, july 1998, pp. 635-644. [3] j. rajagopalan, k. xing, y. guo, f.c. lee, b. manners, "modeling and dynamic analysis of paralleled dc-dc converters with master-slave current-sharing control", ieee applied power electronics conf. rec. 1996, pp 678-684. [4] "l6910 - adjustable step down controller with synchronous rectification" (datasheet) [5] "sts8dnf3ll, dual n-channel 30v - 0.017 ohm - 8a so-8 low gate charge stripfet ii power mosfet" (datasheet) [6] "stps10l25d, low drop power schottky rectifier" (datasheet) appendix layout figure 9. daughter board layout and connectors configuration pump pump ss ss -sout -sout gnd gnd gnd gnd vcc vcc vcc vcc +sout +sout out out out out gnd gnd gnd gnd j2 j3 j1 pump pump ss ss -sout -sout gnd gnd gnd gnd vcc vcc vcc vcc +sout +sout out out out out gnd gnd gnd gnd j2 j3 j1
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan -malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states. http://www.st.com 11/11 AN1696 application note figure 10. motherboard layout

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