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| geometry process details principal device types cmldm7120 cmpdm7120g gross die per 6 inch wafer 28,000 process CP326X small signal mosfet transistor n-channel enhancement-mode transistor chip die size 33.5 x 25.6 mils die thickness 5.5 mils gate bonding pad area 4.7 x 4.7 mils source bonding pad area 20 x 12 mils top side metalization al-si - 35,000? back side metalization au - 12,000? www.centralsemi.com r1 (22-march 2010)
process CP326X typical electrical characteristics www.centralsemi.com r1 (22-march 2010) |
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