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CS1242 specification copyright reserved shenzhen chipsea technologies co., ltd. 1 -28 www.chipsea.com c c s s 1 1 2 2 4 4 2 2 s s p p e e c c i i f f i i c c a a t t i i o o n n may.2005
CS1242 specification copyright reserved shenzhen chipsea technologies co., ltd. 2 -28 www.chipsea.com c c o o n n t t e e n n t t s s 1 CS1242 description .............. ........................ ........................ ........................ ....................... .. 4 1.1 CS1242 features....... ....................... ........................ ................... ................... ................ ..... 4 1.2 applications ............................................................................................................... ....... 4 1.3 description................................................................................................................ ......... 5 2 CS1242 characteristic description...... ................... ................... ................... ........... 6 2.1 absolute maximum ratings ...................................................................................... 6 2.2 digital characteristics ............................................................................................. 6 2.3 pins and packaging......................................................................................................... .. 7 2.4 electrical characteri stics ............ ........................ ................... ................... ........... 9 2.5 timing characteristics............................................................................................. 11 3 CS1242 function module description . ............... ................... ................... .............. 13 3.1 input multiplexer ........................................................................................................ 13 3.2 analog input buffer ................................................................................................... 13 3.3 programmable gain amplifier (pga) .................................................................. 14 3.4 modulator .................................................................................................................. ..... 14 3.5 calibration................................................................................................................ ...... 14 3.5.1 self calibration ..................................................................................................... 14 3.5.2 system calibration............................................................................................... 14 3.6 external voltage reference ................................................................................ 15 3.7 clock unit................................................................................................................. ........ 15 3.8 digital filter (fir) ....................................................................................................... .15 3.9 serial peripheral interface (spi) ......................................................................... 16 3.9.1 chip select (cs) ......................................................................................................... 16 3.9.2 serial clock (sclk) ................................................................................................ 16 3.9.3 clock polarity (pol) ............................................................................................. 16 3.9.4 data input (sdi) and data output (sdo).......................................................... 16 3.10 data ready (drdy)..... ....................... ........................ ................... ................... .............. 1 6 3.11 synchronization (sync) ............................................................................................ 16 3.12 power-up reset and chip reset ................................................................................. 17 4 CS1242 register descript ion................. ................... ................... ................... .............. 18 4.1 rigister list .............................................................................................................. ....... 18 4.2 detailed register definitions ............................................................................... 19 5 CS1242 command descriptio n .................... ........................ ....................... ................... 23 5.1 CS1242 command list ..... ........................ ........................ ................... ................... ......... 23 5.2 detailed commands description.......................................................................... 24 6 CS1242 package ................................................................................................................ .... 28
CS1242 specification copyright reserved shenzhen chipsea technologies co., ltd. 3 -28 www.chipsea.com diagram lists figure 1 CS1242 principle block diagram ........ ............................................................................. 5 figure 2 pin diagram .................................................................................................................... .. 7 figure 3 timing diagram ...............................................................................................................11 figure 4 schematic of input multiplexer........................................................................................13 figure 5 schematic of using external crystal ...............................................................................15 table lists table 1 limit value.................................................................................................................... ........ 6 table 2 digital characteristics ....................... ................... .......................... ................... ................. ... 6 table 3 pin description ................................................................................................................ ...... 7 table 4 package........................................................................................................................ .......... 8 table 5 electrical characteristics (avdd=5v) ....................... .......................... ............. ................... 9 table 6 electrical characteristics (avdd=3v) ....................... .......................... ............. ..................10 table 7 timing table ................................................................................................................... .....12 table 8 the sample frequency of the modulator............................................................................14 table 9 the relation between external reference voltage and ran .............................................15 table 10 registers list................................................................................................................. ...18 table 11 commands table..............................................................................................................23
CS1242 specification copyright reserved shenzhen chipsea technologies co., ltd. 4 -28 www.chipsea.com 1 CS1242 description the CS1242 is precision, low power dissipation, analog-to-digital (a/d) converter with 24-bit resolution and up to 21-bit enob. the CS1242 has world wide applications in industrial process control, weigh scales, liquid/gas chemical analysis, blood analysis, smart transmitters and portable instrumentation. 1.1 CS1242 features z 24 bits no missing code, 21 bits effective precision analog-to-digital converters z simultaneous 50hz and 60hz rejection (reaching 90db) z 0.0015% inl z pga gains from 1 to 128 z single-cycle setting z programmable adc data output rates z external differential reference of 0.1v to 5v z on-chip calibration z integrated compatible spi bus interface z low power dissipation with 0.6mw minimum z 3 analog single input channels and 2 differential input channels 1.2 applications z industrial process control z weigh scales z liquid/gas chemical analysis z blood analysis z smart transmitters z portable instrumentation
CS1242 specification copyright reserved shenzhen chipsea technologies co., ltd. 5 -28 www.chipsea.com 1.3 description the CS1242 principle block diagram is shown in figure 1. the CS1242 is a 24 bits sigma-delta analog-to-digital converter chip with high accuracy and low power dissipation. the CS1242 works from 2.7v to 5.5v power supplies with 21 bits enob. the input channels are multiplexed, and analog input buffer can be selected to provide very high input impedance or direct input. the programmable gain amplifier (pga) provides sele ctable gains from 1 to 128 with 18 bits enob at the gain of 128. the a/d conversion is performe d with a second-order sigma-delta modulator, and programmable fir filter that provides a simultaneous 50hz and 60hz notch, which effectively improve the interference immunity. the CS1242 provides spi compatible serial interface bus. figure 1 CS1242 principle block diagram pga buf 2 nd - orde r modulato r digital filte r controlle r registe r serial interface clock generate r mux vrefp vrefn sclk mcl k xtal a in 0 a in 1 a in 2 a in 3 sdi sdo
CS1242 specification copyright reserved shenzhen chipsea technologies co., ltd. 6 -28 www.chipsea.com 2 CS1242 characteristic description 2.1 absolute maximum ratings table 1 shows the limit values of the CS1242 table 1 limit value description symbol min max units avdd to agnd avdd -0.3 6 v dvdd to dgnd dvdd -0.3 6 v dgnd to agnd dvgnd -0.3 0.3 v transient input current 100 ma continuous input current 10 ma digital input voltage to dgnd -0.3 dvdd+0.3 v digital output voltage to dgnd -0.3 dvdd+0.3 v max junction temperature 150 o c operating temperature -40 85 o c storage temperature -60 150 o c lead temperature (soldering, 10s) 240 o c 2.2 digital characteristics table 2 shows the digital char acteristics of the CS1242. table 2 digital characteristics parameter min typ max units condition vih 0.8 dvdd dvdd v vil dgnd 0.2 dvdd v voh dvdd-0.4 dvdd+0.4 v ioh=1ma vol dgnd dgnd+0.4 v iol=1ma iih 10 ua vi=dvdd iil -10 ua vi=dgnd fosc 1 5 mhz tosc 200 1000 ns notes the digital interface is cmos logic.
CS1242 specification copyright reserved shenzhen chipsea technologies co., ltd. 7 -28 www.chipsea.com 2.3 pins and packaging the pins of the CS1242 are shown in figure 2, and particular description refers to table3. figure 2 pin diagram table 3 pin description pin number symbol description remark 1 dvdd digital power supply voltage, 2.7~5.25v 2 dgnd digital ground 3 mclk master clock input, 1 10mhz 4 xtal crystal oscillator drive pin 2 5 rst active low, chip reset pin 6 sync active low, sync control signal 7 pd active low, power down control 8 dgnd digital ground 9 refp analog reference voltage input (positive) 10 refn analog reference voltage input (negative) 11 ain0 analog input 0 12 ain1 analog input 1 13 ain2 analog input 2 14 ain3 analog input 3 15 nc no connection 16 agnd analog ground 17 avdd analog power supply voltage, 2.7v~5.25v 18 pol serial clock polarity 19 cs active low, chip select 20 sdi serial data input 21 sdo serial data output 22 sclk serial clock , schmitt trigger 23 drdy active low ,data ready 24 buf active high ,analog input buffer enable CS1242 ssop topview 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 dvdd dgnd mclk xtal rst sync pd dgnd refp refn a in 0 a in 1 a in 2 a in 3 nc a gnd a vdd pol cs sdi sdo sclk drdy buf
CS1242 specification copyright reserved shenzhen chipsea technologies co., ltd. 8 -28 www.chipsea.com the CS1242 uses ssop-24 package, the temperature range of the CS1242 is from -40 to +85 , seeing the table 4. table 4 package name package temperature range CS1242 ssop 24 40 85
CS1242 specification copyright reserved shenzhen chipsea technologies co., ltd. 9 -28 www.chipsea.com 2.4 electrical characteristics table 5 electrical characteristics (avdd=5v) parameter conditions min typ max units buffer off agnd-0.1 avdd+0.1 v analog input range buffer on agnd+0.4 avdd-1.5 v ran=0 vref/pga v full-scale input range (ain+) - (ain-) ran=1 vref/(2 pga) v buffer off 5/pga m ? differential input impedance buffer on 5 g ? f data = 3.75hz 1.65 hz f data = 7.50hz 3.44 hz bandwidth (- 3db) f data = 15.0hz 3.7 hz pga user-selectable gain ranges 1 128 input capacitance 9 pf input leakage current modulator off, t = 25 5 pa analog input burnout current sources 2 2ua resolution no missing codes 24 bits integral nonlinearity 0.0015 % of fs offset error 8 ppm of fs offset error drift 0.02 ppm of fs/ gain error 0.005 % gain error drift 0.5 ppm/ at dc 100 db f cm = 60hz, f data = 15hz 130 db common-mode rejection f cm = 50hz, f data = 15hz 120 db f cm = 60hz, f data = 15hz 100 db notch rejection f sig = 50hz, f data = 15hz 100 db system performa nce power-supply rejection at dc 80 95 db ran = 0 0.1 2.5 2.6 v vref refp refn ran = 1 0 2.5 avdd v ran = 0 0 avdd v refp, refn input range ran = 1 0.1 avdd v at dc 120 db common-mode rejection f vrefcm = 60hz 120 db voltage reference input bias current 1.3 ua power-supply voltage avdd 4.75 5.25 v pd = 0, or sleep 1 na pga = 1, buffer off 120 ua pga = 1, buffer on 160 ua pga = 128, buffer off 400 ua current of analog part pga = 128, buffer on 760 ua normal mode 2 ma sleep mode 200 ua read data continuous mode 2.2 ma current of digital part (dvdd = 5v) pd = 0 0.5 na power- supply power dissipation pga = 1, buffer off 11 15 mw
CS1242 specification copyright reserved shenzhen chipsea technologies co., ltd. 10 -28 www.chipsea.com table 6 electrical characteristics (avdd=3v) parameter condition min typ max units buffer off agnd-0.1 avdd+0.1 v analog input range buffer on agnd+0.3 avdd-1.5 v ran=0 vref/pga v full-scale input range (ain+) - (ain-) ran=1 vref/(2 pga) v buffer off 5/pga m ? differential input impedance buffer on 5 g ? f data = 3.75hz 1.65 hz f data = 7.50hz 3.44 hz bandwidth (- 3db) f data = 15.0hz 14.6 hz pga user-selectable gain ranges 1 128 input capacitance 9 pf input leakage current modulator off, t = 25 5 pa analog input burnout current sources 2 2ua resolution no missing codes 24 bits integral nonlinearity 0.0015 % of fs offset error 15 ppm of fs offset error drift 0.04 ppm of fs/ gain error 0.01 % gain error drift 1.0 ppm/ at dc 100 db f cm = 60hz, f data = 15hz 130 db common-mode rejection f cm = 50hz, f data = 15hz 120 db f cm = 60hz, f data = 15hz 100 db notch rejection f sig = 50hz, f data = 15hz 100 db system performa nce power-supply rejection at dc 75 90 db ran = 0 0.1 1.25 1.30 v vref refp refn ran = 1 0 2.5 2.6 v ran = 0 0 avdd v refp, refn input range ran = 1 0.1 avdd v at dc 120 db common-mode rejection f vrefcm = 60hz 120 db voltage reference input bias current 0.65 ua power-supply voltage avdd 2.7 3.3 v pd = 0, or sleep 1 na pga = 1, buffer off 107 ua pga = 1, buffer on 118 ua pga = 128, buffer off 360 ua current of analog part pga = 128, buffer on 500 ua normal mode 2 ma sleep mode 200 ua read data continuous mode 2.2 ma current of digital part (dvdd = 3v) pd = 0 0.5 na power- supply power dissipation pga = 1, buffer off 6.6 9 mw
CS1242 specification copyright reserved shenzhen chipsea technologies co., ltd. 11 -28 www.chipsea.com 2.5 timing characteristics the timing diagram is shown in figure 3, a nd particular description refers to table7. figure 3 timing diagram t cs sclk (pol = 0) sclk (pol = 1) sdi sdo t t msb lsb msb ( 1) t spw t dso t dsoh t cs 2 t dsot t sdelay t dio lsb (1) note: ( 1 ) bit orde r =0; t 1 t 2 t 3 t 2 t 4 sclk sclk reset waveform cs 1242 reset on the falling edge t 8 t data t 6 t 7 300 * t osc < t 1 < 500* t osc t 2 => 5 * t osc 550 * t osc < t 3 < 750* t osc 1050 * t osc < t 4 < 1250 * t osc t 5 rst , sync , pd sclk s t cs 1 t spw ds dh drdy
CS1242 specification copyright reserved shenzhen chipsea technologies co., ltd. 12 -28 www.chipsea.com table 7 timing table spec description min max units t s sclk period 4 tosc periods t spw sclk pulse width, high and low 200 ns t cs1 cs low to first sclk edge, setup time 0 ns t ds sdi data setup time (with sclk delay) 50 ns t dsh valid sdi data hold time 50 ns t dio delay between last sclk edge for sdi and first sclk edge for sdo when sending the following commands: rdata, rdatac, rreg, wreg 50 tosc periods t dso sclk edge to sdo new output data 50 ns t dsoh sdo data hold time 0 t dsot last sclk edge to sdo goes tri-state 6 10 tosc periods t cs2 cs low time after final sclk edge 0 ns rreg, wreg, sync, sleep, rdata, rdatac, stopc 4 tosc periods gcalself, selfoca, ocalsys, gcalsys 8 drdy periods calself 15 drdy periods t sdelay final sclk edge of one command until first edge sclk of next command: reset (also sclk reset or rst pin gives off reset command) 16 tosc periods t 5 pulse width 4 tosc periods t 6 allowed analog input change for next valid conversion 5000 tosc periods t 7 dor update, dor data is invalid 4 tosc periods rdatac mode 10 tosc periods t 8 first sclk after drdy goes low any other mode 0 tosc periods
CS1242 specification copyright reserved shenzhen chipsea technologies co., ltd. 13 -28 www.chipsea.com 3 CS1242 function module description 3.1 input multiplexer the input multiplexer can provide for any combination of differential inputs, as shown in figure 4. figure 4 schematic of input multiplexer the CS1242 provides up to 2 independent differential input channels or 3 single-ended input channels. when using single-ended input, one of the four pins should be selected as the negative terminal. for example, if adin1 is selected as the positive (negative) differential input channel, any other channel can be selected as the negative (positive) terminal for the differential input channel. the CS1242 can achieve stable output of the digital filter and switch the inputs in single-cycle. to minimize the switching error, mux register should be set immediately on the falling edge of the drdy signal. 3.2 analog input buffer the input impedance of the CS1242 is about 5m ? /pga with the buffer off, but the input impedance is up to about 5g ? with the buffer on. the buffer can be controlled by the buf pin and the register acr. when the buf bit in acr register and buf pin is high, the buffer is on. the buffer will draw additional power dissipation when activated. the power depends on the pga setting. when pga=1, the buffer produces approximately 50ua additional current; when the pga=128, the buffer produces approximately 150ua additional current. the input range should be agnd+0.3v to avdd-1.5v with the buffer on. buffe r bufen a in 0 a in 1 a in 2 a in 3
CS1242 specification copyright reserved shenzhen chipsea technologies co., ltd. 14 -28 www.chipsea.com 3.3 programmable gain amplifier (pga) the programmable gain amplifier (pga) can be set to 1, 2, 4, 8, 16, 32, 64, or 128. using pga can improve the enob of the a/d converter. for example, when pga=1, the full scale input is 5v, the converter can resolve down to 1uv; when pga=128, the full scale input is 39mv, the converter can resolve down to 75nv. 3.4 modulator the modulator of the CS1242 is a single loop, second order sigma-delta system. the sample frequency of the modulator is cont rolled by the speed bit in acr register. the sample frequency is shown in table8: table 8 the sample frequency of the modulator data output rate (hz) frequency (mhz) speed adc sample frequency (khz) dr 00 dr 01 dr 10 rejection frequency (hz) 0 19.200 15 7.5 3.75 50/60 2.4576 1 9.600 7.5 3.75 1.875 25/30 0 38.400 30 15 7.5 100/120 4.9152 1 19.200 15 7.5 3.75 50/60 3.5 calibration the CS1242 provides both self calibration and system calibration which include offset and gain calibration of the a/d converter. during calibration, the drdy signal will be held at high, which indicates the result of the ad converter is invalid. in order to ensure the accuracy of the a/d converter, the calibration should be performed after power- up, a change in temperature, or a change of the pga. at the completion of the calibration, the drdy signa l goes low, indicating the calibration is finished. the first output data of the converter after calibrat ion is invalid because of the delay of the inside circuit, and the second output data is valid. 3.5.1 self calibration self calibration for the CS1242 is handled by the three commands: calself, gcalself, and ocalself. the command calsefl performs both offset and gain calibration. gcalself command performs a gain calibration, and ocalself performs an offset calibration, each calibration is completed in eight tdata cycles. performing seflcal needs fifteen tdata cycles. tdata is the reciprocal of output speed. during self calibration, a/d converter cuts off the external input automatically, and then connect to the inside voltage. during gain calibration, the pga is set to 1 automatically. after the completion of the gain calibration, the pga returns to the previous value set by the users. however, it is unnecessary to change the pga during offset calibration. note: when performing calibration, if the external reference voltage is higher than avdd-1.5v, the buffer must be closed during calibration. 3.5.2 system calibration system calibration corrects the offset and gain errors of the chip and the system. when performing system calibration, appropriate signal must be ap plied to the inputs. the commands of system calibration include ocalsys and gcalsys. the command ocalsys corrects the offset error; the command gcalsys corrects the gain error. each calibration is finished in eight tdata cycles.
CS1242 specification copyright reserved shenzhen chipsea technologies co., ltd. 15 -28 www.chipsea.com the differential input voltage must be zero for of fset calibration. the CS1242 computes the offset error for eliminating the system offset error. the input voltage must be positive full-scale for gain calibration. the CS1242 computes the gain error for eliminating the system gain error. 3.6 external voltage reference the CS1242 requires an external reference voltage which connects to refp and refn pins. acr register decides the specific reference voltage value. the value can?t exceed the supply voltage. the specific voltage value is shown in table9: table 9 the relation between external reference voltage and ran ran (acr.2) power voltage (v) reference voltage (v) remark 0 5 <=2.5 1 5 <=5 0 3.0 <=1.25 1 3.0 <=2.5 3.7 clock unit the clock source for the CS1242 can be provided from external clock, a crystal, or oscillator. if the clock source is external clock, the clock is only c onnected to mclk pin, and the xtal pin is unused. if the source is a crystal, the clock circuit is shown in figure5: (two capacitances of 10~20pf connect to the mclk and xtal pins) figure 5 schematic of using external crystal 3.8 digital filter (fir) the CS1242 has a programmable fir filter which can be set to different data output rates. when the clock is 2.4576mhz, the data output rate can be set to 15hz, 7.5hz, or 3.75hz. under these conditions, the fir filter rejects both 50hz and 60hz interference. using other clock frequency can get other data ou tput rates, and the notch frequencies change simultaneously. for example, when the clock frequency is 3.6864mhz, the register is under the default setting, and the data output rate is: (3.6864mhz/2.4576mhz) 15hz = 22.5hz notch frequency: ( 3.6864mhz/2.4576mhz ) ( 50hz and 60hz ) ( 75hz and 90hz ) c2 c1 mclk xtal
CS1242 specification copyright reserved shenzhen chipsea technologies co., ltd. 16 -28 www.chipsea.com 3.9 serial peripheral interface (spi) the CS1242 can communicate with external controller through the spi bus. the CS1242 only operates in slave mode. the serial interface is a st andard four-wire spi interface, including cs, sclk, sdi, sdo, and an additional clock polarity contro l pin pol. the bus supports both serial clock polarities controlled by pol pin. 3.9.1 chip select (cs) before communicating with the CS1242, the external controller must send the chip select (cs) signal to the chip. during communication, the cs signal must be maintained at low. when the cs signal is high, the entire spi is reset. cs can be hard-wired low, the spi bus can work in the three-wire mode which fits for communicating with external controller. 3.9.2 serial clock (sclk) the serial clock features a schmitt-triggered input, which is used for sampling the sdi and sdo signals. the sclk must be very clean to prevent the sample error. if the sclk doesn?t appear in three drdy cycles, the spi bus is reset on next sclk and starts a new communication cycle. a special waveform can reset the entire chip. se e the reset chapter for more information. 3.9.3 clock polarity (pol) the pol pin controls the polarity of serial clock (sclk). when pol is low, the data is sampled on the falling edge of the sclk. if there is no clock pulse, the sclk should be kept at low. when the pol is high, the data is sampled on the rising edge of the sclk. if there is no clock pulse, the sclk should be kept at high. 3.9.4 data input (sdi) and data output (sdo) the data input pin (sdi) and the data output pi n (sdo) receive and send data. the sdo is high impendence when unused, allowing sdi and sdo to be connected together and driven by a bidirectional bus. under this situation, the command rdatac should not be sent to the CS1242, because stopping the rdatac mode requires the command stopc or reset. under rdatac mode, the bidirectional bus is busy sending data, so the command stopc or reset can not be sent to the CS1242 through the bus to stop the rdatac mode. however, if the data from sdo includes the command stopc or reset, sdi will detect the command, and the rdatac mode will be stopped. 3.10 data ready (drdy) the drdy signal is used for indicating the status of data registers. when the new data in the data output register (dor) is ready, the drdy signal goes low. after a read operation, the drdy signal goes high. when the dor register is ready to update, the drdy goes high, which indicates that the data in dor can?t be read. the status of drdy also can be got from the seventh bit of acr register. 3.11 synchronization (sync) synchronization can be achieved through sync pin or sync command. the digital circuit will be reset on the falling edge of the sync signal when using the sync pin. while the sync is low, the serial interface is inactivated. while the sync is high, the digital circuit releases from the reset status, synchronization occurs on the rising edge of next system clock. when using the command sync to achieve synchronizat ion, the digital filter is reset on the edge of the last sclk pulse, the modulator will be held at reset status until the next edge of sclk is detected. synchronization occurs on the rising edge of the system clock in the first sclk after sync command.
CS1242 specification copyright reserved shenzhen chipsea technologies co., ltd. 17 -28 www.chipsea.com 3.12 power-up reset and chip reset the power-on reset circuit is designed to rese t the CS1242 automatically after power-up. the CS1242 can be reset through three methods when the CS1242 is working: pulling the rst pin down to low, sending reset command, or sending specific waveform on the sclk (the sclk reset waveform, as shown in the timing diagram of the CS1242).
CS1242 specification copyright reserved shenzhen chipsea technologies co., ltd. 18 -28 www.chipsea.com 4 CS1242 register description the CS1242 configures the working mode through a series of control registers, which are used for controlling data format, mux setti ng, data rate, calibration, etc. 4.1 rigister list registers list is shown in table 10: table 10 registers list address register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00h setup id3 id2 id1 id0 reserved pga2 pga1 pga0 01h mux ps3 ps2 ps1 ps0 ns3 ns2 ns1 ns0 02h acr drdy b u/ speed buf bitor ran dr1 dr0 03h odac reserved chsel iset1 iset0 reserved reserved reserved reserved 04h reserved 05h reserved 06h reserved 07h occ0 occ07 occ06 occ05 occ04 occ03 occ02 occ01 occ00 08h occ1 occ15 occ14 occ13 occ12 occ11 occ10 occ09 occ08 09h occ2 occ23 occ22 occ21 occ20 occ19 occ18 occ17 occ16 0ah gcc0 gcc07 gcc06 gcc05 gcc04 gcc03 gcc02 gcc01 gcc00 0bh gcc1 gcc15 gcc14 gcc13 gcc12 gcc11 gcc10 gcc09 gcc08 0ch gcc2 gcc23 gcc22 gcc21 gcc20 gcc19 gcc18 gcc17 gcc16 0dh dor2 dor23 dor22 dor21 dor20 dor19 dor18 dor17 dor16 0eh dor1 dor15 dor14 dor13 dor12 dor11 dor10 dor09 dor08 0fh dor0 dor07 dor06 dor05 dor04 dor03 dor02 dor01 dor00
CS1242 specification copyright reserved shenzhen chipsea technologies co., ltd. 19 -28 www.chipsea.com 4.2 detailed register definitions setup register (address = 00h, reset value = xxxx0000) pga control msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 id3 id2 id1 id0 reserved pga2 pga1 pga0 setup. 7 4 : code of the chip, factory programmed bits setup. 3 : reserved setup. 2 0 : pga2/pga1/pga0, programmable gain amplifier gain selection 000 = 1 (default) 001 = 2 010 = 4 011 = 8 100 = 16 101 = 32 110 = 64 111 = 128
CS1242 specification copyright reserved shenzhen chipsea technologies co., ltd. 20 -28 www.chipsea.com multiplexer control register (mux) (address = 01h, reset value = 01h) input channel select msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ps3 ps2 ps1 ps0 ns3 ns2 ns1 ns0 setup. 7 4 : ps3 0, positive channel selection 0000 = adin0 (default) 0001 = adin1 0010 = adin2 0011 = adin3 rest = reserved setup. 3 0 : ns3 0, negative channel selection 0000 = adin0 0001 = adin1 (default) 0010 = adin2 0011 = adin3 rest = reserved analog control register (acr) (address = 02h, reset value = x0h) analog control msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 drdy b u/ speed buf bitor ran dr1 dr0 setup.7 : drdy (data ready), read only, bit 7 duplicates the state of the drdy signal. setup.6 : b u/ , data format 0= bipolar (default); fsr output 0x7fffffh, zero = 0x00000h, fsr = 0x800000h; 1 = unipolar; fsr output 0xffffffh, zero = 0x00000h, fsr = 0x000000h; setup.5 : speed, modulator clock speed control 0 = fosc/128 (default) 1 = fosc/256; setup.4 : buf (buffer enable) 0 = buf disabled (default); 1 = buf enabled; setup.3 : bitor, set bit order for output data 0 = most significant bit transmitted first (default); 1 = least significant bit transmitted first; setup.2 : ran, range selection 0 = full-scale input range equal to / v ref (default); 1 = full-scale input range equal to / v ref / 2; setup.1-0 : dr1/dr0, (data rate) 00 = 15hz (default); 01 = 7.5hz; 10 = 3.75hz; 11 = reserved
CS1242 specification copyright reserved shenzhen chipsea technologies co., ltd. 21 -28 www.chipsea.com odac register (address = 03h, reset value = 00h) offset dac set msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 nullity chsel isel1 iset1 nullity nullity nullity nullity iset11-0 : analog bias current select, 00 = the bias current is 10ua (default), 01 or 10 = bias current increase by 25%, 11 = bias current increase by 50%, when using a higher clock frequency, increasing the analog bias current will help improve the performance of the CS1242. chsel : chopper-modulation select 0 = chopper frequency is half the sample frequency of modulator, when pga=1 to 128 is enabled (default); 1 = chopper frequency is equal to the sample frequency of modulator, when pga = 2 to 128 is enabled; chsel is set to 0 in normal state. however, in certain state (the state relates to the application circuit), high frequency noise will couple to the low frequency signal, chsel can be set to 1, and this will cause offset and noise increase. offset calibration coefficient register 0 (occ0) (address = 07h, reset value = 00h) msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 occ07 occ06 occ05 occ04 occ03 occ02 occ01 occ00 offset calibration coefficient is composed of occ0, occ1 and occ2. occ23-00(totally 24 bits, occ23 is msb, occ00 is lsb) is used for calibrating the offset error. offset calibration coefficient register 1 (occ1) (address = 08h, reset value = 00h) msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 occ15 occ14 occ13 occ12 occ11 occ10 occ09 occ08 offset calibration coefficient is composed of occ0, occ1 and occ2. occ23-00(totally 24 bits, occ23 is msb, occ00 is lsb) is used for calibrating the offset error. offset calibration coefficient register 2 (occ2) (address = 09h, reset value = 00h) msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 occ23 occ22 occ21 occ20 occ19 occ18 occ17 occ16 offset calibration coefficient is composed of occ0, occ1 and occ2. occ23-00(totally 24 bits, occ23 is msb, occ00 is lsb) is used for calibrating the offset error. gain calibration coefficient register 0 (gcc0) (address = 0ah, reset value = 59h) msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 gcc07 gcc06 gcc05 gcc04 gcc03 gcc02 gcc01 gcc00 gain calibration coefficient is composed of gcc0, gcc1 and gcc2. gcc23-00(totally 24 bits, gcc23 is msb, gcc00 is lsb) is used for calibrating the gain error.
CS1242 specification copyright reserved shenzhen chipsea technologies co., ltd. 22 -28 www.chipsea.com gain calibration coefficient register 1 (gcc1) (address = 0bh, reset value = 55h) msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 gcc15 gcc14 gcc13 gcc12 gcc11 gcc10 gcc09 gcc08 gain calibration coefficient is composed of gcc0, gcc1 and gcc2. gcc23-00(totally 24 bits, gcc23 is msb, gcc00 is lsb) is used for calibrating the gain error. gain calibration coefficient register 2 (gcc2) (address = 0ch, reset value = 55h) msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 gcc23 gcc22 gcc21 gcc20 gcc19 gcc18 gcc17 gcc16 gain calibration coefficient is composed of gcc0, gcc1 and gcc2. gcc23-00(totally 24 bits, gcc23 is msb, gcc00 is lsb) is used for calibrating the gain error. data output register 2 (dor2) (address = 0dh, reset value = 00h) adc data msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dor 23 dor22 dor 21 dor 20 f dor 19 dor 18 dor 17 dor 16 adc data is composed of dor0, dor1 and dor 2. dor23-00(totally 24 bits, dor23 is msb, dor00 is lsb) data output register 1 (dor1) (address = 0eh, reset value = 00h) adc data msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dor15 dor14 dor13 dor12 dor11 dor10 dor09 dor08 adc data is composed of dor0, dor1 and dor 2. dor23-00(totally 24 bits, dor23 is msb, dor00 is lsb) data output register 0 (dor0) (address = 0fh, reset value = 00h) adc data msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dor07 dor06 dor05 dor04 dor03 dor02 dor01 dor00 adc data is composed of dor0, dor1 and dor 2. dor23-00(totally 24 bits, dor23 is msb, dor00 is lsb)
CS1242 specification copyright reserved shenzhen chipsea technologies co., ltd. 23 -28 www.chipsea.com 5 CS1242 command description the CS1242 has a series of commands, which control the working mode, working speed, calibration, etc. some of the commands are single (such as reset); some need operands (such as wreg, etc). operands: n = amount (0-127) r = register (0-15) x = arbitrary value 5.1 CS1242 command list commands aggregate of the CS1242 is shown in table 11. table 11 commands table commands description operate code operands rdata read data from dor register 0000 0001 ( 01 h ) -- rdatac read data from dor register continuously 0000 0011 ( 03 h ) -- stopc stop read data from dor register continuously 0000 1111 ( 0f h ) -- rreg read value from ?rrrr? register 0001 r r r r ( 1x h ) xxxx_nnnn wreg write value to ?rrrr? register 0101 r r r r ( 5x h ) xxxx_nnnn calself self offset and gain calibration 1111 0000 ( f0 h ) ocalself self offset calibration 1111 0001 ( f1 h ) gcalself self gain calibration 1111 0010 ( f2 h ) ocalsys system offset calibration 1111 0011 ( f3 h ) gcalsys system gain calibration 1111 0100 ( f4 h ) wakeup wake up system from sleep mode 1111 1011 ( fb h ) sync sync drdy 1111 1100 ( fc h ) sleep put in sleep mode 1111 1101 ( fd h ) reset reset to power-up value 1111 1110 ( fe h ) note: the received data format is always msb first; the bitor bit in acr register sets the data out format.
CS1242 specification copyright reserved shenzhen chipsea technologies co., ltd. 24 -28 www.chipsea.com 5.2 detailed commands description rdata read data from data output register (dor) description: read the most recent conversion single data from the data output register (dor). this is a 24-bit value. operands: none byte: 1 encoding: 0000 0001 data transmit sequence: rdatac read data continuous from data output register (dor) description: read data continuous mode enables the c ontinuous output of new data on each drdy signal period, and don?t need to send the command rdata when drdy goes low. this mode can be terminated by either the stopc command or the reset command. after the drdy goes low, it needs more than 10 t osc to execute this command. operands: none byte: 1 encoding: 0000 0011 data transmit sequence: msb mid-byte lsb xxxx xxxx xxxx xxxx 0000 0001 xxxx xxxx ??.. sdi sdo msb mid-byte lsb 0000 0011 uuu uuuu ??.. sdi sdo uuu uuuu uuu uuuu drdy msb mid-byte lsb sdo drdy
CS1242 specification copyright reserved shenzhen chipsea technologies co., ltd. 25 -28 www.chipsea.com stopc stop continuous data output mode description: stop the continuous data output mode. the command is sent after drdy goes low. operands: none byte: 1 encoding: 0000 1111 data transmit sequence: rreg read from register description: output the data from up to 16 registers, the starting register address is decided by operand in command. the number of registers read will be one plus the second byte. if the count exceeds the remaining registers, the addresses will wrap back to the beginning. operands: r, n byte: 2 encoding: 0001 rrrr xxxx nnnn data transmit sequence: read 2 registers, starting with the register 01h (mux) wreg write to register description: write multi-data to registers. the starting register address is decided by operand in command. the number of registers that will be written is one plus the value of the second byte. operands: r, n byte: 2 encoding: 0101 rrrr xxxx nnnn data transmit sequence: write data to two registers, starting with the register 04h (dio) xxx 0000 11111 xxx sdi drdy mux a cr xxxx xxxx xxxx xxxx 0001 0001 ??.. 0000 0001 sdi sdo 0101 0100 xxxx 0001 data for dio data for dir sdi
CS1242 specification copyright reserved shenzhen chipsea technologies co., ltd. 26 -28 www.chipsea.com calself offset and gain self calibration description: perform offset and gain self calibration. the occ register and the gcc register are updated after the operation. operands: none byte: 1 encoding: 1111 0000 data transmit sequence: ocalself offset self calibration description: perform offset self calibration. the occ register is updated after this operation. operands: none byte: 1 encoding: 1111 0011 data transmit sequence: slfgcal gain self calibration description: perform gain self calibration. the gcc register is updated after this operation. operands: none byte: 1 encoding: 1111 0010 data transmit sequence: ocalsys system offset calibration description: perform system offset calibration. for a system offset calibration, the input should be set to 0v, and the CS1242 computes the occ value that will compensate for offset errors. the occ value is updated after this operation. 0v signal must be applied to the analog inputs, and the occ register is updated automatically. operands: none byte: 1 encoding: 1111 0011 data transmit sequence: 1111 0000 sdi 1111 0001 sdi 1111 0010 sdi 1111 0011 sdi
CS1242 specification copyright reserved shenzhen chipsea technologies co., ltd. 27 -28 www.chipsea.com gcalsys system gain calibration description: perform system gain calibration. for a system gain calibration, the input should be set to the full-scale voltage and the CS1242 computes the gcc value that will compensate for gain errors. gcc register value is updated after this operation. full-scale voltage must be applied to the analog inputs, and the gcc register is updated automatically. operands: none byte: 1 encoding: 1111 0100 data transmit sequence: wakeup wake up from the sleep mode description: wake up the CS1242 from the sleep mode operands: none byte: 1 encoding: 1111 1011 data transmit sequence: sync synchronize drdy description: synchronize the data of the CS1242 operands: none byte: 1 encoding: 1111 1100 data transmit sequence: sleep sleep mode description: put the CS1242 into sleep mode. use wakeup command to wake up from sleep mode. operands: none byte: 1 encoding: 1111 1101 data transmit sequence: reset reset to power-up value description: restore the registers to their power-up values. this command will also stop the rdatac command. operands: none byte: 1 encoding: 1111 1110 data transmit sequence: 1111 0100 sdi 11111011 sdi 1111 1100 sdi 1111 1101 sdi 1111 1110 sdi
CS1242 specification copyright reserved shenzhen chipsea technologies co., ltd. 28 -28 www.chipsea.com 6 CS1242 package the CS1242 uses ssop24 packaging, shown in the following figure.

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