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asahi kasei [AK8448] ms1513-e-00 2013/02 1 AK8448 6-channel linear sensor compatible 10 bit 40 msps x 3 analog pre-processor features ? maximum processing speed in cds mode and clamp mode 1ch, 2ch and 3ch mode: 40m samples/sec per channel 4ch and 6ch mode: 20m sample/sec per channel in dc direct-coupled mode 1ch, 2ch and 3ch mode: 15m sample/sec per channel 4ch and 6ch mode: 15m sample/sec per channel ? maximum input level: 1.35vpp (t yp.)@cds mode and dc connection mode 1.19vpp (typ.)@clamp mode ? compatible with both ccd and cis signal polarities ? simultaneously sampling 6-channel cds ci rcuits ( correlated double sampling ) ? offset dacs: adjustable range : 298.7 mv (typ.), independent 6-channel 8 bit dacs ? pga: adjustable gain range : 0 db ~ 18.75 db (typ.) independently adjustable 6- channel 8 bit pgas. ? linearity: dnl = -1lsb (min.), +1l sb (max.) with guaranteed no missing code. ? 5 bit output bus: enables to output 10 bit data in 5 bit x 2 cycles ? 4-wire serial interface ? supply: 3.3v 0.3v ? power dissipation: t.b.d(typ.)@6ch mode, at 20m samples/sec per channel ? package: 64 pin lqfp, pin pitch 0.5 mm, mold size 10 mm x 10 mm ccdin5 refin5 refin4 ccdin4 ccdin3 refin3 refin2 ccdin2 ccdin1 refin1 refin0 ccdin0 cl a mp cds pga dac dac cl a mp cds pga mux adc 10bit 40msps cl a mp cds pga dac dac cl a mp cds pga mux adc 10bit 40msps cl a mp cds pga dac dac cl a mp cds pga mux adc 10bit 40msps output control 10 10 10 5 5 5 adck shd shr timing control sdenb sdin sdout serial i/f control sdclk da04 db04 dc04 darefp darefn reference voltage vrn vcom vrp avss avdd dvdd dvss vclp aiset clpb resetb ce0 ce1
asahi kasei [AK8448] ms1513-e-00 2013/02 2 functional description of each block ? clamp / cds sensor interface circuit it samples the image signal level from the sensor. the AK8448 has 3 sampling modes ? cds m ode, clamp mode and dc direct-coupled mode. there are 5 ,number of channel select modes ? 1, 2, 3, 4 and 6 channels. channel(s) to be used is selected by the number of channel mode. cds circuits, dacs, pgas and adcs of the un-used channels ar e automatically powered-down. ? dac offset addition d/a converter this is a d/a converter to gener ate an offset voltage which is added to the sampled signal level at the sensor interface par t. voltage range of dac is 298.7mv (typ.) and its resolution is 8 bit. an independent offset voltage can be set to each channel by register setting. ? pga ( programmable gain amplifier ) this is a programmable gain amplifier to adjust signal amplitude of each channel. adjustable range is from 0 db to 18.75 db (typ.), and its resolution is 8 bit. an independent gain can be set to eac h channel by register setting. ? mux channel multiplexer this is an analog switch to input in t he time-division-multiplexed fashion the simultaneously-sampled 2 channel signals to an a dc, in 4 channel mode and 6 channel mode. in 4 channel mode and 6 channel m ode, 10 bit adcs process dual channels in time-division- multiplexed method. ? adc a/d converter this is a 10 bit, 40 msps a/d converter to conv ert an image signal level into digital data after offset adjustment and gain adj ustment are made. there ar e 3 adcs and 2 channels are connected to each adc thr ough a channel multiplexer. ? output control adc output data control digital circuit to control the ou tput form of adc data. adc data can be output in either 5 bit-wide or 10 bit-wide by register setting. in case of 5 bit-wide data operation, the upper 5 bi t of the adc data is out put at the rising edge of acdk clock, and the lower 5 bit data ,at the falling edge of adck. in case of 10 bit-wide data operat ion, adc data from two differ ent data channels are output at the rising edge and at the falling edge of adck respectively. it is also possible to output adc data at only the falling edge of adck clock by register setting in 10 bit-wide data operation.
asahi kasei [AK8448] ms1513-e-00 2013/02 3 ? reference voltage referenc e voltage generation circuit circuit to generate internal clamp level vc lp, analog common level vcom, adc reference voltages vrp & vrn and dac refer ence voltages darefp & darefn. ? timing control timing generating circuit digital circuit to generate internal timing pulse s from those input clocks, adck, shr, shd and clpb. adck is a clock which is used for adc operation and for operation of adc output data control part. shr is a timing pulse which is used to sa mple reference level of sensor signal. shd is a timing pulse which is used to sample data level of sensor signal. clpb is a timing pulse to show clamp period. ? serial i/f control serial register interface circuit a 4-wire interface to set val ues at the control registers. control registers also can be read out. by assigning specific address to individual devices by chip enable pins ce0 and ce1, up to 4. AK8448 devices can be connect ed on the same, 4-wires.
asahi kasei [AK8448] ms1513-e-00 2013/02 4 pin assignment 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 top view 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 48 4 7 46 4 5 44 4 3 42 41 40 3 9 38 3 7 36 35 34 33 avss ccdin1 refin1 vclp vcom ccdin2 refin2 refin3 ccdin3 vr p vrn ccdin4 refin4 refin5 ccdin5 avdd sdout nc da4 (d9) da3 (d8) da2 (d7) da1 (d6) da0 (d5) dv dd dvss db4 (d4) db3 (d3) db2 (d2) db1 (d1) db0 (d0) nc dv dd dv ss dc4 dc3 dc2 dc1 dc0 nc dvdd dv ss avss av dd clpb adck shd shr avss av dd ccdin0 refin0 darefn darefp aiset av dd a v ss res etb ce1 ce0 sdclk sdenb sdin av dd avss figure 1 pin layout
asahi kasei [AK8448] ms1513-e-00 2013/02 5 pin function no. name type description 1 avss pwr analog ground 2 shr i reference level sampling pulse input 3 shd i data level sampling pulse input 4 adck i adc sampling clock input 5 clpb i clamp control input low : clamp operation ?on? high : clamp operation ?off? this should be fixed to low during cds mode 6 avdd pwr analog power supply 7 avss pwr analog ground 8 dvss pwr digital ground 9 dvdd pwr digital power supply 10 nc left open or should be connected to vss 11 12 13 14 15 dc0 dc1 dc2 dc3 dc4 o o o o o adc output in a straight binary code( dc0 : lsb side , dc4 : msb side ) in 5 bit-wide output operation in 3-channel and 6 channel modes, data output corresponds to ccdin4 and ccdin5. in 10 bit-wide output operation and in 5 bit-wide output operation in 1 channel, 2 channel and 4 channel modes , these outputs are not used. when these modes are selected, low level is output in normal operation and either low level or high-z output is programmable in power-down mode by register setting. 16 dvss pwr digital ground 17 dvdd pwr digital power supply 18 nc left open or should be connected to avss 19 20 21 22 23 db0 (d0) db1 (d1) db2 (d2) db3 (d3) db4 (d4) o o o o o adc output in a stra ight binary code. signal name with parenthesis means a signal name in 10 bit-wide output operation ( in 5 bit-wide output operation, db0 : lsb side, db4 : msb side and in 10 bit-wide output operation, d0 : lsb ). when in 5 bit-wide output operation in 1 channel mode, these outputs are not used. they become low le vel output in normal operation and either low level or high-z output is programmable by register setting in power-down mode. 24 dvss pwr digital ground 25 dvdd pwr digital power supply
asahi kasei [AK8448] ms1513-e-00 2013/02 6 no. name type description 26 27 28 29 30 da0 (d5) da1 (d6) da2 (d7) da3 (d8) da4 (d9) o o o o o adc output in a stra ight binary code. signal name with parenthesis means a signal name in 10 bit-wide output operation ( in 5 bit-wide output operation, da0 : lsb side, da4 : msb side and in 10 bit-wide output operation, d9 : msb ). 31 nc left open or should be connected to avss. 32 sdout o serial i/f data output, pull up or pull down please. 33 avss pwr analog ground 34 avdd pwr analog power supply 35 sdin i serial i/f data input 36 sdenb i serial i/f data enable 37 sdclk i serial i/f clock 38 39 ce0 ce1 i i chip enable 40 resetb i reset 41 avss pwr analog ground 42 avdd pwr analog power supply 43 aiset i internal bias current connect a 8.2kohm resistor between avss and this pin. 44 nc left open or should be connected to avss. 45 test i for test , connect to avss. 46 refin0 i reference input connect a same value capacitor as ccdin0 input capacitor between avss and this pin. in dc direct-coupl ed mode, an externally-fed signal reference level should be input. 47 ccdin0 i sensor signal input 48 avdd pwr analog power supply 49 avss pwr analog ground 50 ccdin1 i sensor signal input 51 refin1 i reference input connect a same value capacitor as ccdin1 input c apacitor between avss and this pin. in dc direct-coupled mode, an exter nally-fed signal reference level should be input. 52 vclp o clamp level output connect a stabilizing capacitor between avss and this pin.
asahi kasei [AK8448] ms1513-e-00 2013/02 7 no. name type description 53 vcom o internal reference voltage connect a stabilizing capacit or between avss and this pin 54 ccdin2 i sensor signal input 55 refin2 i reference input connect a same value capacitor as ccdin2 input c apacitor between avss and this pin. in dc direct-coupled mode, an exter nally-fed signal reference level should be input. 56 refin3 i reference input connect a same value capacitor as ccdin3 input c apacitor between avss and this pin. in dc direct-coupled mode, an exter nally-fed signal reference level should be input. 57 ccdin3 i sensor signal input 58 vrp o adc reference voltage positive side connect a stabilizing capacitor between avss and this pin. 59 vrn o adc reference voltage negative side connect a stabilizing capacitor between avss and this pin. 60 ccdin4 i sensor signal input 61 refin4 i reference input connect a same value capacitor as ccdin4 input c apacitor between avss and this pin. in dc direct-coupled mode, an exter nally-fed signal reference level should be input. 62 refin5 i reference input connect a same value capacitor as ccdin5 input c apacitor between avss and this pin. in dc direct-coupled mode, an exter nally-fed signal reference level should be input. 63 ccdin5 i sensor signal input 64 avdd pwr analog power supply type description i : input pin o : output pin pwr : power supply pin note ) avdd is a power supply for analog part and digital part. dvdd is a power supply for t he digital output bufferes.
asahi kasei [AK8448] ms1513-e-00 2013/02 8 absolute maximum ratings avss = dvss = 0 v. all voltages are referenced to ground. parameter symbol min. max. unit notes power supplies avdd dvdd ? 0.3 ? 0.3 4.5 4.5 v v input current iin ? 10 10 ma except supply pins analog input voltage vina ? 0.3 avdd+0.3 v digital input voltage (input pins) vinl ? 0.3 avdd+0.3 v digital input voltage (output pins) vonl ? 0.3 dvdd+0.3 v restriction on the over input ambient operating temperature ta 0 70 c storage temperature tstg ? 65 150 c operation under a condition exc eeding above limits may cause per manent damage to the device. normal operation is not guaranteed under the above extreme conditions. recommended operating conditions avss = dvss = 0 v. all voltages are referenced to ground. parameter symbol min. typ. max. unit notes power supplies analog output buffer avdd dvdd 3.0 3.0 3.3 3.3 3.6 3.6 v v refinn ( n = 0 ~ 5 ) input voltage at dc direct-coupled mode vrefin 0 avdd ? 1.3 v positive polarity
asahi kasei [AK8448] ms1513-e-00 2013/02 9 electrical characteristics ? dc characteristics ( avdd = 3.0 ~ 3.6 v, dvdd = 3.0 ~ 3.6 v, ta = 0 ~ 70 c) parameter symbol pin min. max. unit notes high level input voltage vih note 1 0. 7avdd v low level input voltage vil note 1 0. 3avdd v high level output voltage 1 voh1 note 2 0.8dvdd v ioh= ? 1ma low level output voltage 1 vol1 note 2 0.2dvdd v iol= 1ma high level output voltage 2 voh2 note 3 0.8dvdd v ioh= ? 0.25ma low level output voltage 2 vol2 note 3 0.2dvdd v iol= 0.25ma input leakage current ilikg note 1 ? 10 10 a high-z leakage current ioz note 2 ? 10 10 a ( note 1 ) shd, shr, adck, clpb, sdcl k, sdenb, sdin, ce0, ce1,resetb ( note 2 ) da0 ~ da4, db0 ~ db4, dc0 ~ dc4 ( note 3 ) sdout
asahi kasei [AK8448] ms1513-e-00 2013/02 10 ? analog characteristics ( avdd = 3.3 v, dvdd = 3.3 v, ta = 25 c, adck at 40mhz unle ss otherwise specified ) parameter symbol condition min. typ. max. unit reference voltage part clamp voltage vclp positive polarity negative polarity 0.94 2.15 1.04 2.3 1.14 2.45 v common voltage vcom 1.1 1.2 1.3 v adc reference voltage positive negative vrp vrn 1.5 0.7 1.6 0.8 1.7 0.9 v clamp / cds part input range vi at pga gain= 0db cds mode clamp mode dc direct-coupled mode 1.20 1.04 1.20 1.35 1.19 1.35 1.50 1.34 1.50 vpp input capacitance cin ccdin 10 pf input bandwidth ( note 1 ) cbw ccdin~adc at pga gain= 0db 1 pixel cds effect cds noise 0.4vpp 150khz signal 0.8vpp 1mhz -35 db offset adjust dac resolution dres 8 bit range drng input referred value 366.6 mv differential non-linearity dnl guaranteed monotonicity ? 0.26 db adc resolution res 10 bit differential non-linearity dnl ccdin~adc guaranteed no-missing code ? ? ? 3
asahi kasei [AK8448] ms1513-e-00 2013/02 11 ( avdd = 3.3 v, dvdd = 3.3 v, ta = 25 c, adck at 40mhz unle ss otherwise specified ) parameter symbol condition min. typ. max. unit current consumption analog part in normal operation ia 6 channel mode 160 202 ma digital output part id 6 channel mode, a full scale minus 2 db 1 mhz sine-wave input signal, cl = 10 pf 14.5 30 ma at power-down ipd analog part + digital part 0.1 ma characteristics above are when same external components and time-cons tant are used as shown in the recommended , external circuit configuration examples. ( note 1 ) time till the adc output settles within +/ ? 1 lsb of the final value when a full-scale minus 2 db step signal is input. ( note 2 ) defined as a sigma of a dc output code variations. ( note 3 ) it defines that the offset dac setting value in no input signal c ondition exists between offset dac setting value of a0h ( equivalent to an input -referred, ? 50 mv ) and 60h ( equivalent to an input-referred, + 50 mv ) where adc output code changes from 000h to 001h. since a total adjustable range of o ffset adjust dac includes this internal offset adjust range, a practical adjustable range of input signal is reduced by the internal offset amount. ( note 4 ) definition at adck = 40 mhz, a/d conversion rate mode, 6 c hannels, cds mode. pga gain of the channel to be measured is set at its maximum value, all other channels? pga gains are set at minimum values. then measure how much the output code of the target channel to be measured fluctuates when input to the measured c hannel is fixed and a full-scale minus 1 db step signal is input on all other channels. ( note 5 ) definition at adck = 10 mhz, a/d conversion rate mode, all channels? pga gains at minimum values. then measure how much the output code of the target channel to be measured fluctuates when input to the measured c hannel is fixed and a full-scale minus 1 db step signal is input on all other channels.
asahi kasei [AK8448] ms1513-e-00 2013/02 12 ? switching characteristics 1 : in adc conversion rate mode, dc direct-coupled mode z timing diagrams ( 1 ) 5 bit wide, 1 channel, 2 channel, 3 channel modes z timing diagrams ( 3 ) 5 bit wi de, 4 channel, 6 channel modes z timing diagrams ( 5 ) 10 bit wide, 1 channel mode z timing diagrams ( 7 ) 10 bit wide, 2 channel mode z timing diagrams ( 9 ) 10 bit wide, 4 channel mode ( avdd = 3.0 ~ 3.6 v, dvdd = 3.0 ~ 3.6 v, ta = 0 ~ 70 c) no. parameter pin min. typ. max. unit condition 1 adck cycle time ( t ) a dck 33.3 2000 ns 4, 6ch mode 66.6 2000 1, 2, 3 ch mode 2 adck low level width adck 15.0 ns 4, 6 ch mode 31.7 1, 2, 3 ch mode 3 adck high level width adck 15.0 ns 4, 6 ch mode 31.7 1, 2, 3 ch mode 4 adck rise time adck 6 ns 5 adck fall time adck 6 ns 6 shd cycle time shd 2t ns 4, 6 ch mode t 1, 2, 3 ch mode 7 shd pulse width shd 12 ns 8 shd set-up time ( time to adck to rise ) shd 0 ns 9 shd delay time ( time from adck to fall ) shd 14 ns 10 shd aperture delay shd 2.5 ns 11 output data delay time ( time from adck edge ) da4~da0 db4~db0 dc4~dc0 1 9 ns c=10pf 12 pipe line delay da4~da0 db4~db0 dc4~dc0 9 unit: # of adck cycles 2, 3, 4, 6 ch mode and 1 ch 5 bits width mode 8.5 1 ch 10 bits width mode 13 shd = ? h ? inhibit period ( time till the first adck to rise after shd to fall ) shd t+1 ns 4, 6ch mode
asahi kasei [AK8448] ms1513-e-00 2013/02 13 ? switching characteristics 2 : in adc conversion rate mode, cds, clamp modes z timing diagrams ( 2 ) 5 bit wide, 1 channel, 2 channel, 3 channel modes z timing diagrams ( 4 ) 5 bit wi de, 4 channel, 6 channel modes z timing diagrams ( 6 ) 10 bit wide, 1 channel mode z timing diagrams ( 8 ) 10 bit wide, 2 channel mode z timing diagrams ( 10 ) 10 bit wide, 4 channel mode ( avdd = 3.0 ~ 3.6 v, dvdd = 3.0 ~ 3.6 v, ta = 0 ~ 70 c) no. parameter pin min. typ. max. unit condition 1 adck cycle time ( t ) adck 25 2000 ns 2 adck low level width adck 10.9 ns 3 adck high level width adck 10.9 ns 4 shr, shd cycle time shr, shd 2t ns 4, 6ch mode t 1, 2, 3ch mode 5 shr pulse width shr 8 ns 6 shd pulse width shd 8 ns 7 shd set-up time ( time to adck to rise ) shd 0 ns 8 shd delay time ( time from adck to fall ) shd 10 ns 9 shr aperture delay shr 3.0 ns 10 shd aperture delay shd 2.5 ns 11 output data delay time ( time from adck edge ) da4~da0 db4~db0 dc4~dc0 1 9 ns c=10pf 12 pipe line delay da4~da0 db4~db0 dc4~dc0 9 unit: # of adck cycles 2, 3, 4, 6ch mode and 1ch 5 bits width mode 8.5 1ch 10 bits width mode 13 shd = ? h ? inhibit period ( time till the first adck to rise after shd to fall ) shd t+1 ns 4, 6ch mode
asahi kasei [AK8448] ms1513-e-00 2013/02 14 ? switching characteristics 3 : in tota l pixel rate mode, dc direct-coupled mode z timing diagrams ( 11 ) 10 bit wide, 2 channel mode z timing diagrams ( 13 ) 10 bit wide, 3 channel mode z timing diagrams ( 15 ) 10 bit wide, 4 channel mode z timing diagrams ( 17 ) 10 bit wide, 6 channel mode ( avdd = 3.0 ~ 3.6 v, dvdd = 3.0 ~ 3.6 v, ta = 0 ~ 70 c) no. parameter pin min. typ. max. unit condition 1 adck cycle time ( t ) adck 12.5 333 ns 6ch mode 16.6 500 4ch mode 22.2 666 3ch mode 33.3 1000 2ch mode 2 adck low level width adck 4.6 ns 6ch mode 6.7 4ch mode 9.5 3ch mode 15.0 2ch mode 3 adck high level width adck 4.6 ns 6ch mode 6.7 4ch mode 9.5 3ch mode 15.0 2ch mode 4 shd cycle time shd 6t ns 6ch mode 4t 4ch mode 3t 3ch mode 2t 2ch mode 6 shd pulse width shd 12 ns 7 shd set-up time ( time to adck to rise ) shd 0 t/2-2 ns 8 shd delay time ( note 1 ) shd 14 ns 9 shd aperture delay shd 2.5 ns 10 output data delay time ( time from adck edge ) da4~da0 db4~db0 1 9 ns c=10pf 11 pipe line delay da4~da0 db4~db0 30 unit: # of adc k cycle s 3ch,6ch mode 20 2ch,4ch mode 12 shd = ? h ? inhibit period ( time till the first adck to rise after shd to fall ) shd 3t+1 ns 6ch mode 2t+1 4ch mode ( note 1 ) time from the adck edge where a falling edge of the internal a / d clock is generated. in 2 channel, 4 channel modes, it is from adck to rise. in 3 channel, 6 channel modes, it is from adck to fall.
asahi kasei [AK8448] ms1513-e-00 2013/02 15 ? switching characteristics 4 : in to tal pixel rate mode, cds, clamp modes z timing diagrams ( 12 ) 10 bit wide, 2 channel mode z timing diagrams ( 14 ) 10 bit wide, 3 channel mode z timing diagrams ( 16 ) 10 bit wide, 4 channel mode z timing diagrams ( 18 ) 10 bit wide, 6 channel mode ( avdd = 3.0 ~ 3.6 v, dvdd = 3.0 ~ 3.6 v, ta = 0 ~ 70 c) no. parameter pin min. typ. max. unit condition 1 adck cycle time ( t ) adck 12.5 333 ns 6ch mode 12.5 500 4ch mode 12.5 666 3ch mode 12.5 1000 2ch mode 2 adck low level widt h adck 4.6 ns 3 adck high level widt h adck 4.6 ns 4 shr, shd cycle time s hr, shd 6t ns 6ch mode 4t 4ch mode 3t 3ch mode 2t 2ch mode 5 shr pulse width shr 8 ns 6 shd pulse width shd 8 ns 7 shd set-up time ( time to adck to rise ) shd 0 t/2-2 ns 8 shd delay time ( note 1 ) shd 10 ns 11 shr aperture delay shr 3.0 ns 12 shd aperture delay shd 2.5 ns 11 output data delay time ( time from adck edge ) da4~da0 db4~db0 1 9 ns c=10pf 12 pipe line delay da4~da0 db4~db0 30 unit: # of adc k cycle s 3ch,6ch mode 20 2ch,4ch mode 13 shd = ? h ? inhibit period ( time till the first adck to rise after shd to fall ) shd 3t+1 ns 6ch mode 2t+1 4ch mode ( note 1 ) time from the adck edge where a falling edge of the internal a / d clock is generated. in 2 channel, 4 channel modes, it is from adck to rise. in 3 channel, 6 channel modes, it is from adck to fall. timings are specified at the points where specified levels by the dc characteristics are intersected.
asahi kasei [AK8448] ms1513-e-00 2013/02 16 ? timing diagrams (1) : adck frequency = a/d conversion rate mode ( 5 bit-wide output ) z 1 channel, 2 channel, 3 channel modes ( dc direct-coupled, pos itive polarity ) please refer to switching characteristics 1 table. ccdin0 ccdin2 ccdin4 adck shr shd da40 9 adck cycles (pipeline delay) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 m l m l m l m l m l m l m l m l m l m l m l m l ml m l m l 01 2 3 m l m l m l m l m l m l m l m l m l m l m l m l ml m l m l 01 2 3 m l m l m l m l m l m l m l m l m l m l m l m l ml m l m l 01 2 3 db40 dc40 cc d in 0 cc d in 2 cc d in 4 m: msb 5bit l: lsb 5bit timing diagrams in 1 channel , 2 channel, 3 channel modes da 4 0 db4 0 dc4 0 shr shd adck n 8 10 6 1 (t) 3 2 13 9 msb lsb msb lsb lsb 12 13 n+1 n 10 n 9 ccdi n 0 ccdi n2 ccdi n4 4 5 0. 5*avdd 0.5* dvdd 0. 5*avdd 0. 5*dvdd detailed timing diagrams in 1 ch annel, 2 channel, 3 channel modes
asahi kasei [AK8448] ms1513-e-00 2013/02 17 ? timing diagrams (2) : adck frequency = a/d conversion rate mode ( 5 bit-wide output ) z 1 channel, 2 channel, 3 channel modes ( cds mode & clamp m odes, negative polarity ) please refer to switching characteristics 2 table. ccdin0 ccdin2 ccdin4 a dck shr shd da4~0 9 adck cycles (pipeline delay) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 m l m lm l m l m lmlmlmlmlmlml m l m l m l m l 01 2 3 m l m lm l m l m lmlmlmlmlmlml m l m l m l m l 01 2 3 m l m lm l m l m lmlmlmlmlmlml m l m l m l m l 01 2 3 cc din0 cc din2 cc din4 db4~0 dc4~0 m: msb 5bit l: lsb 5bit timing diagrams in 1 channel, 2 channel, 3 channel modes da4~0 db4~0 dc4~0 ccdin0 ccdin2 ccdin4 shr shd msb 12 10 8 9 2 3 1 (t) 6 6 13 13 lsb lsb lsb lsb lsb msb msb msb msb 7 11 a dck n n 10 n 11 n 12 n 9 n 8 n-1 n-2 n+1 45 0.5*avdd 0.5*dvdd detailed timing diagrams in 1 cha nnel, 2 channel, 3 channel modes
asahi kasei [AK8448] ms1513-e-00 2013/02 18 ? timing diagrams (3) : adck frequency = a/ d conversion rate ( 5 bit-wide output ) z 4 channel, 6 channel modes ( dc direct -coupled mode, posit ive polarity ) please refer to switching characteristics 1 table. ccdinn (n=0~5) a dck shr shd da4~0 9 adck cycles (pipeline delay) 0 1 2 3 4 5 6 7 m l m lm l m l m lmlmlmlmlmlml m l m l m l m l 0 even 0 od d even= ccdin0 odd= ccdin1 1 eve n 1 odd m l m lm l m l m lmlmlmlmlmlml m l m l m l m l 0 even 0 od d even= ccdin2 odd= ccdin3 1 eve n 1 odd m l m lm l m l m lmlmlmlmlmlml m l m l m l m l 0 even 0 od d even= ccdin4 odd= ccdin5 1 eve n 1 odd db4~0 dc4~0 2 eve n 2 eve n 2 eve n m: msb 5bit l: lsb 5bit timing diagrams in 4 channel, 6 channel modes da4~0 db4~0 dc4~0 shr shd adck 8 10 6 1 (t) 3 2 13 9 msb lsb msb l sb lsb 12 13 n n ? ? 5 even ccdi n n (n=0~5) 0.5*a vdd 0. 5 *dvdd 4 5 detailed timing diagrams in 4 channel, 6 channel modes
asahi kasei [AK8448] ms1513-e-00 2013/02 19 ? timing diagrams (4) : adck frequency = a/d conversion rate mode ( 5 bit-wide output ) z 4 channel, 6 channel modes ( cds mode & clamp mode, negative polarity ) please refer to switching characteristics 2 table. ccdinn (n=0~5) a dck shr shd 0 1 2 3 4 5 6 7 da4~0 9 adck cycles (pipeline delay) m l m lm l m l m lmlmlmlmlmlml m l m l m l m l 0 even 0 od d even= ccdin0 odd= ccdin1 1 eve n 1 odd m l m lm l m l m lmlmlmlmlmlml m l m l m l m l 0 even 0 od d even= ccdin2 odd= ccdin3 1 eve n 1 odd m l m l m l m l m lmlmlmlmlmlml m l m l m l m l 0 even 0 od d even= ccdin4 odd= ccdin5 1 eve n 1 odd db4~0 dc4~0 2 eve n 2 eve n 2 eve n m: msb 5bit l: lsb 5bit timing diagrams in 4 channel, 6 channel modes da4~0 db4~0 dc4~0 ccdinn (n=0~5) shr shd msb 12 10 8 9 2 4 1 (t) 6 6 13 13 lsb lsb lsb lsb lsb msb msb msb msb 7 11 a dck n n-1 n+1 n-6 odd n-5 even n-5 odd n-6 even n-4 even n-7 odd 5 0.5*dvdd 0.5*avdd detailed timing diagrams in 4 channel, 6 channel modes
asahi kasei [AK8448] ms1513-e-00 2013/02 20 ? timing diagrams(5): adck frequency = a/d c onversion rate mode ( 10 bit-wide output ) z 1 channel mode ( dc direct-coupl ed mode, positive polarity ) please refer to switching characteristics 1 table. ccdin 0 a dck shr shd da4~0 (d9~5) 8.5 adck cycles (pipeline delay) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 db4~0 (d4~0) dc4~0 012 3 msb msb msb msb msb msb msb msb msb msb msb msb msb msb 012 3 lsb lsb lsb lsb lsb lsb lsb lsb lsb lsb lsb lsb lsb lsb 4 4 timing diagrams in 1 channel mode da4~0 (d9~5) db4~0 (d4~0) ccdin0 shr shd 12 10 8 9 2 3 1 (t) 6 13 a dck n n-1 n+1 n+2 n+3 n-10 n-9 n-8 n-7 n-11 1 (t) 4 5 0.5*avdd 0.5*dvdd detailed timing diagrams in 1 channel mode
asahi kasei [AK8448] ms1513-e-00 2013/02 21 ? timing diagrams(6): adck frequency = a/d c onversion rate mode ( 10 bit-wide output ) z 1 channel mode ( cds mode & cl amp mode, negative polarity ) please refer to switching characteristics 2 table. ccdin0 a dck shr shd da4~0 (d9~5) 8.5 adck cycles (pipeline delay) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 db4~0 (d4~0) dc4~0 012 3 msb msb msb msb msb msb msb msb msb msb msb msb msb msb 012 3 lsb lsb lsb lsb lsb lsb lsb lsb lsb lsb lsb lsb lsb lsb 4 4 timing diagrams in 1 channel mode da4~0 (d9~5) db4~0 (d4~0) ccdin0 shr shd 12 10 8 9 6 6 7 11 a dck n n-1 n+1 n+2 n+3 2 3 1 (t) 13 n-10 n-9 n-8 n-7 n-11 1 (t) 4 5 0.5*dvdd 0.5*avdd detailed timing diagrams in 1 channel mode
asahi kasei [AK8448] ms1513-e-00 2013/02 22 ? timing diagrams(7): adck frequency = a/d c onversion rate mode ( 10 bit-wide output ) z 2 channel mode ( dc direct-coupl ed mode, positive polarity ) please refer to switching characteristics 1 table. ccdin0 ccdin2 a dck shr shd da4~0 (d9~5) 9 adck cycles (pipeline delay) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0 2 0 20 2 0 2 0 202020 2 020202 0 2 0 2 0 2 0 2 012 3 0 2 0 20 2 0 2 0 2020202020202 0 2 0 2 0 2 0 2 012 3 msb lsb db4~0 (d4~0) dc4~0 ccd in0 ccdin2 4 4 timing diagrams in 2 channel mode da4~0 (d9~5) db4~0 (d4~0) ccdin0 ccdin2 shr shd 0 10 8 9 2 3 1 (t) 6 13 13 2 2 2 2 2 0 0 00 a dck n-10 n-11 n-12 n-9 n-8 12 n n-1 n-2 n+1 ccdin0 ccdin2 4 5 0.5*avdd 0.5*dvdd detailed timing diagrams in 2 channel mode
asahi kasei [AK8448] ms1513-e-00 2013/02 23 ? timing diagrams(8): adck frequency = a/d c onversion rate mode ( 10 bit-wide output ) z 2 channel mode ( cds mode & clam p mode, negative polarity ) please refer to switching characteristics 2 table. ccdin0 ccdin2 a dck shr shd da4~0 (d9~5) 9 adck cycles (pipeline delay) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0 2 0 2 0 2 0 2 0 202020 2 020202 0 2 02 0 2 0 2 012 3 0 2 0 20 2 0 2 0 2020202020202 0 2 0 2 0 2 0 2 012 3 msb lsb db4~0 (d4~0) dc4~0 ccd in0 ccdin 2 4 4 timing diagrams in 2 channel mode da4~0 (d9~5) db4~0 (d4~0) ccdin0 ccdin2 shr shd 12 10 8 9 6 6 7 11 a dck n n-1 n-2 n+1 0 2 3 1 (t) 13 13 2 2 2 2 2 0 0 00 n-10 n-11 n-12 n-9 n-8 ccdin0 ccdin2 4 5 0.5*avdd 0.5*dvdd detailed timing diagrams in 2 channel mode
asahi kasei [AK8448] ms1513-e-00 2013/02 24 ? timing diagrams(9): adck frequency = a/d c onversion rate mode ( 10 bit-wide output ) z 4 channel mode ( dc direct-coupl ed mode, positive polarity ) please refer to switching characteristics 1 table. ccdinn (n=0~3) a dck shr shd 0 1 2 3 4 5 6 7 da4~0 (d9~5) 9 adck cycles (pipeline delay) 0 2 1 30 2 1 3 0 21302130213 13 0 2 0 2 1 3 0 0 msb 1 1 0 2 1 30 2 1 3 0 21302130213 13 0 2 0 2 1 3 0 0 1 1 db4~0 (d4~0) dc4~0 lsb 0 2 2 0 2 2 timing diagrams in 4 channel mode da4~0 (d9~5) db4~0 (d4~0) ccdinn (n=0~3) shr shd 0 12 10 8 15 2 3 1 (t) 6 13 13 3 2 3 2 3 1010 a dck n n-1 n+1 n-6 n-5 n-7 n-4 9 4 5 0.5*avdd 0.5*dvdd detailed timing diagrams in 4 channel mode
asahi kasei [AK8448] ms1513-e-00 2013/02 25 ? timing diagrams(10):adck frequency = a/d c onversion rate mode ( 10bit-wide output ) z 4 channel mode ( cds mode & cl amp mode, negative polarity ) please refer to switching characteristics 2 table. ccdinn (n=0~3) a dck shr shd 0 1 2 3 4 5 6 7 da4~0 (d9~5) 9 adck cycles (pipeline delay) 0 2 1 30 2 1 3 0 21302130213 13 0 2 0 2 1 3 0 0 msb 1 1 0 2 1 3 0 2 1 3 0 2 13021302 13 13 0 2 0 2 1 3 0 0 1 1 db4~0 (d4~0) dc4~0 lsb 0 2 2 0 2 2 timing diagrams in 4 channel mode da4~0 (d9~5) db4~0 (d4~0) ccdinn (n=0~3) shr shd 12 10 8 9 6 6 7 9 a dck n n-1 n+1 15 0 2 3 1 (t) 13 13 3 2 3 2 3 1010 n-6 n-5 n-7 n-4 4 5 0.5*avdd 0.5*dvdd detailed timing diagrams in 4 channel mode
asahi kasei [AK8448] ms1513-e-00 2013/02 26 ? timing diagrams(11): adck frequency = tota l pixel rate mode ( 10 bit-wide output ) z 2 channel mode ( dc direct-coupl ed mode, positive polarity ) please refer to switching characteristics 3 table. ccdinn (n=0,2) a dck shr shd 0 1 2 3 4 5 6 7 da4~0 (d9~5) 20 adck cycles (pipeline delay) msb 0 2 db4~0 (d4~0) dc4~0 lsb internal a /d clock 89 10 11 0 1 0 1 0 2 0 2 0 20 20 20 20 20 2 0 2 0 2 2 0 0 2 0 2 0 2 0 20 20 20 20 20 2 0 2 0 2 2 0 ccdin0 ccdin2 timing diagrams in 2 channel mode da4~0 (d9~5) db4~0 (d4~0) ccdin0 ccdin2 shr shd 0 10 8 9 2 3 1 (t) 6 13 2 2 2 2 2 0000 a dck n-11 n-12 n-13 n-10 n-9 12 n n-1 n-2 n+1 internal a/d clock 4 5 0.5*avdd 0.5*dvdd detailed timing diagrams in 2 channel mode
asahi kasei [AK8448] ms1513-e-00 2013/02 27 ? timing diagrams(12): adck frequency = tota l pixel rate mode ( 10 bit-wide output ) z 2 channel mode ( cds mode & cl amp mode, negative polarity ) please refer to switching characteristics 4 table. ccdinn (n=0,2) a dck shr shd 0 1 2 3 4 5 6 7 da4~0 (d9~5) 20 adck cycles (pipeline delay) msb 0 2 db4~0 (d4~0) dc4~0 lsb internal a /d clock 89 10 11 0 1 0 1 0 2 0 2 0 20 20 20 20 20 2 0 2 0 2 2 0 0 2 0 2 0 2 0 20 20 20 20 20 2 0 2 0 2 2 0 ccdin0 ccdin2 timing diagrams in 2 channel mode da4~0 (d9~5) db4~0 (d4~0) ccdin0 ccdin2 shr shd 10 8 9 6 a dck 12 n n-1 n-2 n+1 internal a/d clock n-3 11 7 6 0 2 3 1 (t) 13 2 2 2 2 2 0000 n-11 n-12 n-13 n-10 n-9 4 5 0.5*dvdd 0.5*avdd detailed timing diagrams in 2 channel mode
asahi kasei [AK8448] ms1513-e-00 2013/02 28 ? timing diagrams(13): adck frequency = tota l pixel rate mode ( 10 bit-wide output ) z 3 channel mode ( dc direct-coupl ed mode, positive polarity ) please refer to switching characteristics 3 table. ccdinn (n=0,2,4) a dck sh r shd 0 1 2 3 4 5 6 7 da4~0 (d9~5) 30 adck cycles (pipeline delay) 2 4 0 2 4 02 4 0 2 4 0 2402402402 24 40 02 4 0 msb 2 4 0 2 4 02 4 0 2 4 0 2402402402 24 40 02 4 0 db4~0 (d4~0) dc4~0 lsb internal a /d clock 89 10 11 2 4 0 2 40 0 1 2 4 0 2 4 0 0 1 ccdin0 ccdin2 ccdi n4 timing diagrams in 3 channel mode 10 8 n-1 n n+1 ccdinn shd adck internal a/d clock (n=0,2,4) 9 6 1 (t) n-10 shr da4~0 (d9~5) db4~0 (d4~0) 0 2 4 0 2 4 0 2 4 0 2 n-11 n-12 n-9 13 12 2 3 4 5 0.5*avdd 0.5*dvdd detailed timing diagrams in 3 channel mode
asahi kasei [AK8448] ms1513-e-00 2013/02 29 ? timing diagrams(14): adck frequency = tota l pixel rate mode ( 10 bit-wide output ) z 3 channel mode ( cds mode & cl amp mode, negative polarity ) please refer to switching characteristics 4 table. ccdinn (n=0,2,4) a dck shr shd 0 1 da4~0 ( d9~5 ) 30 adck cycles (pipeline delay) 0 2 4 db4~0 (d4~0) dc4~0 internal a/d clock 0 2 4 2 02 4 02 4 3 0 2 4 0 2 4 4 02 4 024 5 024 024 6 024 024 7 024 024 8 024 024 9 02 4 02 4 10 0 2 4 0 2 4 0 2 4 0 2 4 msb lsb 0 0 11 ccdin0 ccdin2 ccdi n4 timing diagrams in 3 channel mode 8 ccdinn (n=0,2,4) shd a dck internal a /d clock da4~0 (d9~5) db4~0 (d4~0) 9 1 (t) shr 6 12 n 10 n-10 0 2 4 0 2 4 2 4 0 2 n-11 n-9 13 0 n+1 n-1 9 7 6 2 3 4 5 0.5*avdd 0.5*dvdd detailed timing diagrams in 3 channel mode
asahi kasei [AK8448] ms1513-e-00 2013/02 30 ? timing diagrams(15): adck frequency = tota l pixel rate mode ( 10 bit-wide output ) z 4 channel mode ( dc direct-coupl ed mode, positive polarity ) please refer to switching characteristics 3 table. ccdinn (n=0~3) a dck shr shd 0 1 da4~0 (d9~5) 20 adck cycles (pipeline delay) db4~0 (d4~0) dc4~0 internal a /d clock 2 3 4 5 0 msb 0 2 1 3 0 2 1 3 0 2 1 3 0 2 1 3 0 2 1 3 0 2 0 lsb 0 2 1 3 0 2 1 3 0 2 1 3 0 2 1 3 0 2 1 3 0 2 3 3 ccdi n0 ccdin2 ccdin3 ccdi n1 timing diagrams in 4 channel mode n 0 ccdinn shd adck internal a/d clock da4~0 (d9~5) db4~0 (d4~0) n-6 2 1 3 0 n-5 2130 n-4 2 n+1 (n=0~3) 9 1 (t) shr 13 8 10 15 6 10 2 3 4 5 0.5*avdd 0.5*dvdd detailed timing diagrams in 4 channel mode
asahi kasei [AK8448] ms1513-e-00 2013/02 31 ? timing diagrams(16): adck frequency = tota l pixel rate mode ( 10 bit-wide output ) z 4 channel mode ( cds mode & cl amp mode, negative polarity ) please refer to switching characteristics 4 table. ccdinn (n=0~3) a dck shr shd da4~0 (d9~5) 20 adck cycles (pipeline delay) 0 msb db4~0 (d4~0) dc4~0 internal a /d clock 0 2 1 3 0 2 1 3 0 2 1 3 0 2 1 3 0 2 1 3 0 2 0 lsb 0 2 1 3 0 2 1 3 0 2 1 3 0 2 1 3 0 2 1 3 0 2 3 3 1 2345 0 ccdi n0 ccdin2 ccdin3 ccdi n1 timing diagrams in 4 channel mode 0 ccdinn shd a dck internal a /d clock da4~0 (d9~5) db4~0 (d4~0) n-6 2 1 3 0 n-5 2130 n-4 2 (n=0~3) 9 shr 13 8 10 15 6 6 11 7 12 n n+1 1 (t) 2 3 4 5 0.5*avdd detailed timing diagrams in 4 channel mode
asahi kasei [AK8448] ms1513-e-00 2013/02 32 ? timing diagrams(17): adck frequency = tota l pixel rate mode ( 10 bit-wide output ) z 6 channel mode ( dc direct-coupl ed mode, positive polarity ) please refer to switching characteristics 3 table. - ccdinn (n=0~5) a dck sh r shd 0 1 da4~0 (d9~5) 30 adck cycles (pipeline delay) db4~0 (d4~0) dc4~0 internal a /d clock 0 2 4 1 3 5 3 5 2 0 2 4 1 3 5 3 0 2 4 1 3 5 4 0 2 4 1 3 5 5 0 2 5 1 3 5 0 2 4 1 0 2 4 1 3 5 3 5 0 2 4 1 3 5 0 2 4 1 3 5 0 2 4 1 3 5 0 2 4 1 3 5 0 2 4 1 0 0 msb lsb ccdin0 ccdi n2 ccdin3 ccdin4 ccdin1 ccdin5 timing diagrams in 6 channel mode n n+1 0 ccdinn shd adck internal a/d clock da4~0 (d9~5) db4~0 ( d4~0 ) n-6 2 4 1 3 5 0 n-5 241350 n-4 2 4 1 3 5 0 n-3 2 n+2 (n=0~5) 9 1 (t) 2 3 shr 13 8 10 15 6 12 0.5*avdd 0.5*dvdd 4 5 detailed timing diagrams in 6 channel mode
asahi kasei [AK8448] ms1513-e-00 2013/02 33 ? timing diagrams(18): adck frequency = tota l pixel rate mode ( 10 bit-wide output ) z 6 channel mode ( cds mode & cl amp mode, negative polarity ) please refer to switching characteristics 4 table. - ccdinn (n=0~5) a dck shr shd 0 1 da4~0 ( d9~5 ) 30 adck cycles (pipeline delay) db4~0 (d4~0) dc4~0 internal a /d clock 2 3 4 5 0 2 4 1 3 5 3 5 0 2 4 1 3 5 0 2 4 1 3 5 0 2 4 1 3 5 0 2 4 1 3 5 0 2 4 1 0 0 msb lsb ccdin0 ccdi n2 ccdin3 ccdin4 ccdin1 ccdin5 0 2 4 1 3 5 3 5 0 2 4 1 3 5 0 2 4 1 3 5 0 2 4 1 3 5 0 2 4 1 3 5 0 2 4 1 timing diagrams in 6 channel mode detailed timing diagrams in 6 channel mode 9 1 (t) 2 3 0 ccdinn (n=0~5) shr shd a dck internal a /d clock da4~0 (d9~5) db4~0 (d4~0) n-6 13 8 10 15 6 2 4 1 3 5 0 n-5 2 4 1 3 5 0 n-4 2 4 1 3 5 0 n-3 2 6 9 7 12 n n-1 n+1 n+2 4 5 0.5*avdd 0.5*dvdd
asahi kasei [AK8448] ms1513-e-00 2013/02 34 ? switching characteristics : serial i / f ( avdd = 3.0 ~ 3.6 v, dvdd = 3.0 ~ 3.6 v, ta = 0 ~ 70 c) parameter symb ol pin min. typ. max. unit condition clock cycle scyc sdclk 10 mhz clock pulse width ( ? h ? period ) shi sdclk 40 ns clock pulse width ( ? l ? period ) slo sdclk 40 ns set-up time ( time to sdclk ) ssu sdin sdenb 20 ns hold time ( time from sdclk ) sh sdin sdenb 20 ns rise time of sdclk, sdenb sr sdclk sdenb 6 ns 0.3 avdd 0.7 avdd fall time of sdclk, sdenb sf sdclk sdenb 6 ns 0.3 avdd 0.7 avdd sdenb high level pulse width sdw sdenb 40 ns data delay time ( time from sdclk ) sdly sdout 30 ns data hold time ( time from sdenb ) shld sdout 0 ns number of serial data snum sdclk 16 sdenb high-z high-z 16 15 2 1 sdin ssu scyc slo shi sh ssu sh sdw sdclk sdout 16 10 2 1 sdw 8 sdl y 9 shld scyc shi slo ssu sh ssu sh figure 2 write to AK8448 read from AK8448
asahi kasei [AK8448] ms1513-e-00 2013/02 35 control registers address (hex) data initial (hex) d7 d6 d5 d4 d3 d2 d1 d0 0 00 sensor interface mode signal polarity channel number adck freq. power down 1 00 shr shd polarity output as power down te s t pattern output 0 output data width order of channel 0 and 1 order of channel 2 and 3 order of channel 3 and 4 2 3 4 5 6 7 80 80 80 80 80 80 offset data for ccdin0 offset data for ccdin1 offset data for ccdin2 offset data for ccdin3 offset data for ccdin4 offset data for ccdin5 8 9 a b c d 00 00 00 00 00 00 pga gain data for ccdin0 pga gain data for ccdin1 pga gain data for ccdin2 pga gain data for ccdin3 pga gain data for ccdin4 pga gain data for ccdin5 e 08 test f 00 test in this data sheet, r0 indicates a register at address 0, for example. r0, d0 description means, d0 bit of register at address 0. each bit of registers to be described in the fo llowing is set to a condi tion as noted to be default after the reset. ? r0 register ? r0, d7-d6 sensor i/f mode d7 d6 sensor interface mode 0 0 dc direct-coupled ( default ) 0 1 cds 1 0 clamp
asahi kasei [AK8448] ms1513-e-00 2013/02 36 ? r0, d5 signal polarity d5 signal polarity sensor type 0 negative signal swings to low voltage side from the reference level. ccd sensors etc. ( default ) 1 positive signal swings to high volt age side from the reference level. cis sensors etc. ? r0, d4 ~ d2 cannel number d4 d3 d2 cannel number ccdin 0 1 2 3 4 5 0 0 0 1( default ) { - - - - - 0 0 1 2 { - { - - - 0 1 0 3 { - { - { - 0 1 1 4 { { { { - - 1 0 0 6 { { { { { { { : denotes input channel( s ) to be used in the selected # of channel mode. un-used functional blocks, cds, dac, pga and adc are automatically powered-down. no capacitor connection is required on ccdinn & refinn pins for the un-used channels. those, un-used pins s hould be connected to avss. ? r0, d1 adck frequency d1 adck input frequency note 0 a/d conversion rate ( default ) either 5 bit-wide or 10 bit-wide output data is output both at the ri sing edge and the falling edge of adclk. 1 total pixel rate 10 bit-wide out put data is output at the rising edge of adck. in the default mode, adck at the same frequency as adc conver sion rate should be input. adc data is output both at the rising edge and t he falling edge of adck. in total pixel rate mode, adck at the same frequency as a total sum of pixel rate of effective channels should be i nput. adc data is output at the rising edge of adck. ? r0, d0 power-down d0 operation 0 normal operation ( default ) 1 power-down in power-down mode, clock feed to the digital part is stopped while analog part is powered-down. adc data output conditions ( da0 ~ da4, db 0 ~ db4, dc0 ~ dc4 ) at power-down can be selected to be either fixed low or high-z output by d6 bit of register r1.
asahi kasei [AK8448] ms1513-e-00 2013/02 37 ? r1 register ? r1, d7 shr, shd polarity select d7 polarity 0 active high ( default ) 1 active low all diagrams shown in this data sheet ar e when shr and shd polarities are set at default conditions ( active high ). ? r1, d6 output conditions at power-down d6 output conditions 0 fixed to low ( default ) 1 high z r1, d5 test pattern output d5 output 0 normal (default) 1 test pattern output 10-bit increment pattern is outputted at test pattern output. 0,1,2,3, ??? ,1022,1023,0,1,2,3, ??? ? r1, d3 output data width d3 output data width 0 5 bit ( default ) 1 10 bit when the setting of adck frequency is equal to total pixel rate mode ( r0, d1 = 1 ), output data is output in 10 bit-wide mode, regardless of output data width setting.
asahi kasei [AK8448] ms1513-e-00 2013/02 38 ? r1, d2-d0 channel processing order d2 channels 0, 1 processing order 0 ccdin0 ccdin1 ccdin0 ccdin1 ( default ) 1 ccdin1 ccdin0 ccdin1 ccdin0 ? d1 channels 2, 3 processing order 0 ccdin2 ccdin3 ccdin2 ccdin3 ( default ) 1 ccdin3 ccdin2 ccdin3 ccdin2 ? d0 channels 4, 5 processing order 0 ccdin4 ccdin5 ccdin4 ccdin5 ( default ) 1 ccdin5 ccdin4 ccdin5 ccdin4 ? this is to select the processing order of corresponding input channel pair of the selected, single adc. processing order can be individually set at every pair. this register is valid either in 4 channel mode / 5 bit-wide output or 6 channel mode / 5 bit-wide output. all diagrams shown in this data sheet are when the channel processing order is set at default condition.
asahi kasei [AK8448] ms1513-e-00 2013/02 39 ? r2~r7 registers ? d7-d0 offset data mv x x offset ) 128 ( 127 7 . 298 ) ( ? = 0 x 255 default x =128 ? r8~rd registers ? d7-d0 pga gain data setting code and gain ( ideal value ) relation is expressed in the following equation. 255 3 . 33 208 2 ) ( x x gain ? + = where x is register set value ( 0 < = x < = 255 ) at default x = 0 0 2 4 6 8 10 12 14 16 18 20 0 64 128 192 256 code gain[db] 0 0.0 2 0.0 4 0.0 6 0.0 8 0.1 0.1 2 0 64 128 192 256 co de gain st e p[ db] figure 3 pga gain curves ( ideal values ) d7-d0 ( straight binary ) offset voltage at negative mode at positive mode 11111111 ? 298.7mv maximum shift to white level side ( adc code large ) | | maximum shift to black level side ( adc code small ) maximum shift to black level side ( adc code small ) | | maximum shift to white level side ( adc code large ) 11111110 -296.3mv : : 10000001 ? 2.4mv 10000000 ( default ) 0mv 01111111 2.4mv : : 00000001 298.7mv 00000000(inhibition) (298.7mv)
asahi kasei [AK8448] ms1513-e-00 2013/02 40 operations ? sensor i/f mode AK8448 has three sensor interface modes : cds, clamp and dc c onnect. the sensor interface mode is selected by sensor interface mode register r0, d7~d6. z cds mode a mode to process the difference vpix as it s pixel level which is between the reference level vprec of each pixel from the sens or output signal and its data level vdata. reference level of the sensor signal is sa mpled at shr and data level of the sensor signal is sampled at shd respectively. sampling point is at the falling edge of shr and shd respectively. when polarity of shr and shd is inverted by r egister ( r1, d7 = 1 ), the sampling point becomes at the rising edge. v prec v data v pi x shr shd ccdinn clpb low figure 4 cds mode timing outline z clamp mode a mode to process the difference vpix as its pixel level which is between the internally generated clamp level vclamp and data level vdata of the sensor output signal. data level of the sensor signal is sampled at shd. v da ta v pix shr shd ccdinn internal clamp level v clamp clpb figure 5 clamp mode timing outline
asahi kasei [AK8448] ms1513-e-00 2013/02 41 z dc direct-coupled mode a mode to process a difference vpix as its pi xel level which is between a reference level fed on refinn pin externally, and data le vel vdata of the sensor output signal. when no reference level exists in sensor output signal, this mode is used as an example. data level of the sensor signal is sampled at shd. since shr is not used, connect it to either low or high. low( or high) refinn (input) v da ta v pix shr clpb shd ccdinn figure 6 dc direct-coupled mode timing outline
asahi kasei [AK8448] ms1513-e-00 2013/02 42 ? clamp operation in cds mode and clamp mode, cl amping is made in order to adjust the reference dc level of sensor signal to match the in ternal reference level of the AK8448. clamp operation is contro lled by clpb and shr. clamp switch closes during clpb = low and shr = high ( ? low ? when shr, shd polarities are inverted ), and ccdinn ( n = 0 ~ 5 ) pin signal is pulled toward the internal clamp level. refinn ( n = 0 ~ 5 ) is also clamped in the same way. in cds mode, fix clpb to low so that clamping is always enabled. sensor ccdinn cds (sample & hold) clpb .and. shr 0: open 1: close ccdinn clamp level figure 7 clamp circuit outline effective pixel effective pixel optical black ccd shr clpb ccdinn internal clamp level clamp is active pull in reference level to clamp level figure 8 clamp operation timing outline
asahi kasei [AK8448] ms1513-e-00 2013/02 43 ? signal polarity the AK8448 accepts both positive and negative input polarities. either signal polarity is selected by setting si gnal polarity register ( r0,d5 ) to meet sensor types to be used. in general, ccd exhibits negative polarity c haracteristics and cis exhibits positive polarity characteristics. either polarity c an be selected, regardless of sensor i/f mode setting. z negative polarity characteristics reference level data level white (adc code 3ff h black (adc code 000 h z positive polarity characteristics reference level data level black (adc code 000 h white (adc code 3ff h figure 9 signal polarities ? output data control adc output data is output in either 5 bit- wide or 10 bit-wide by setting data width register ( r1, d3 ). when 5 bit-wide data mode is selected, data is output on each of three 5 bit buses ? da4 ~ da0, db4 ~ db0 and dc4 ~ dc0 respec tively which correspond to each adc. when 10 bit-wide data mode is selected, data is output on 10 pins ? da4 ( msb ) ~ da0 and db4 ~ db0 ( lsb ). in 5 bit-wide data mode, the upper 5 bit of data is output at the rising edge of adck, and the lower 5 bit at the falling edge of adck. in 10 bit-wide data mode, two different c hannel data are output at the rising edge and at the falling edge of adck respectively. it is also possible to output data at only the falling edge of adck in 10 bit-wide data mode, by setting adck frequency register ( r0, d1 ). in this operation, it is required to input adck at the frequency of a total sum of pixel rate of all channels ( total pixel rate ). un-us ed buses db4 ~ db0 and dc4 ~ dc0 such as a case in 1 channel mode with 5 bit- wide output, will output low levels.
asahi kasei [AK8448] ms1513-e-00 2013/02 44 ? adck a/d conversion rate mode and total pixel rate mode adck generates adc conversion ti ming and adc data output timing. whether to output data at bot h the rising edge and the falling edge of adck or to output data at only the rising edge can be sele cted by adck frequency mode register. a/d conversion rate mode is a mode where data is output at both the rising edge and the falling edge of adck. in a/d conversion rate mode, input an adck clock of same frequency as adc conversion rate. total pixel rate mode is a mode where data is output at only the adck rising edge. in this mode, input an adck clock of same fr equency as a total sum of effective channels? pixel rates. for example, when to process a 20 mhz / c hannel sensor signal in 3 channel mode, a 20 mhz adck is input in a/d conversion rate mode which is equal to adc conversion rate. maximum conversion rate maximum operating speed of adc data output buffers da0 ~ da4, db0 ~ db4, dc0 ~ dc4 is designed to be 80 mbps. when a total pixel rate mode is selected as adck frequency mode, maximum sampling rate per channel in 3 channel and 6 channel modes is limited by this output buffer speed. for example, maximum conversion rate in 6 channel mode is 80 msps / 6 = 13.3 msps per channel, and not 20 msps.
asahi kasei [AK8448] ms1513-e-00 2013/02 45 number of channels and its adck frequency, a possible data width combination and its maximum conversion rate per channel are listed in the following table. [cds, clamp mode] a/d conversion rate mode total pixel rate mode # of channels 5 bits width 10 bits width maximum conversion rate [sps/ch] 5 bits width 10 bits width maximum conversion rate [sps/ch] 1 { { 40m - { note1 40m 2 { { 40m - { 40m 3 { - 40m - { 26.6m 4 { { 20m - { 20m 6 { - 20m - { 13.3m [dc direct mode] a/d conversion rate mode total pixel rate mode # of channels 5 bits width 10 bits width maximum conversion rate [sps/ch] 5 bits width 10 bits width maximum conversion rate [sps/ch] 1 { { 15m - { note1 15m 2 { { 15m - { 15m 3 { - 15m - { 15m 4 { { 15m - { 15m 6 { - 15m - { 13.3m note1: a/d conversion rate mode and total pixel rate mode have same timing waveforms in 1 channel / 10 bit-wide output operation. pl ease use a/d conversion rate mode at the default state.
asahi kasei [AK8448] ms1513-e-00 2013/02 46 ? shr/shd polarity shr shd ccdinn shr shd a ctive high (default) active low shr/shd polarity can be changed by register r1 register.
asahi kasei [AK8448] ms1513-e-00 2013/02 47 serial i / f write operation into and read operation from control registers are executed via a 4 ? wire serial interface. sdin data while sdenb is at low is taken at the rising edge of sdclk. when the starting bit of sdin data is ? zero ?, writing into register is made and when it is ? one ?, reading from register is made. the second and the third bits ( c1, c0 ) correspond to ce1 and ce0 pin data respectively and only when logical levels are at c1 = ce1 and c0 = ce0, either write in or read out operation is enabled. the fourth bit must be zero. bits from the fifth to the eighth are for register address. msb is the fifth bit and lsb is the eighth bit. bits from ninth to sixteenth are data for regist er. msb ( = d7 ) is the ninth bit and lsb ( = d0 ) is the sixteenth bit. ? reset register values at the power-up are i ndeterminate including registers for test. in order to avoid test registers from di sturbing normal operation, a reset should be made right after the power-up. when resetb pin is set to low, each register is set to its default value while test registers are set to necessary values for normal operation. low duration time of reset b should be 100 ns and longer. return resetb pin to high after the rese t, and necessary value should be written to each register. when reset is not made after power-up, write default values into test registers. ? power-down the AK8448 enters power-down mode when operation mode register r0,d1 is set at ? 1 ?. in power-down mode, supplying operation cl ock to digital part is also stopped while current supply to anal og part is ceased. when returning to normal operation from power-down mode ( r0, d0 = 0 ), a wait time is required so that vcom ( reference voltage ) is stabilized to its normal voltage since vcom is made to 0 v at power-down.
asahi kasei [AK8448] ms1513-e-00 2013/02 48 serial interface ? writing into the AK8448 high z w sdclk sdin sdout sdenb c1 c0 0 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 figure 10 write into register ? reading from the AK8448 c1 high z r sdclk sdin sdout sdenb c0 0 a3 a2 a1 a0 d6 d5 d4 d3 d2 d1 d0 d7 figure 11 read from register
asahi kasei [AK8448] ms1513-e-00 2013/02 49 package outline dimensions package marking ( 1 ) pin # 1 identifier (the chamfered corner indicates pin number 1) ( 2 ) marketing code : AK8448vq ( 3 ) date code : xxxxxxx ( 7 digits ) upper 4 digits : week code lower 3 bits : akm?s control code ak84 4 8 v q xxxxxxx 0.22 0.05 0.50 12.00 0.20 10.00 12.00 0.20 0.145 0.055 1.60 max 1.40 0.05 0.10 0.05 1.00 0.60 0.15 0 ~7 0.10 0.10 m 1 16 17 32 33 48 49 64 unit: mm 10.00 s s
asahi kasei [AK8448] ms1513-e-00 2013/02 50 external circuit examples ? cds mode ccdin1 refin1 v clp v com ccdin2 refin2 refin3 ccdin3 v rp v rn ccdin4 refin4 refin5 ccdin5 nc da4 da3 da2 da1 da0 dvdd dvss db4 db3 db2 db1 db0 nc dvss dc4 dc3 dc2 dc1 dc0 nc dvdd dvss avss avdd clpb a dc k shd shr avss avdd ccdin0 refin0 test nc aiset avdd avss resetb ce1 ce0 sdcl k sdenb sdin avdd avss 3.3v 3.3v 8.2k ? 1% 0.1 f 0.1 f 1 f 1 f 0.1 f 0.1 f 0.1 f 0.1 f 1 f 1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f sdout 0.1 f 0.1 f 0.1 f 0.1 ? 20% above example is for reference. please select optimum capacitor values for a target system. figure 12 cds mode
asahi kasei [AK8448] ms1513-e-00 2013/02 51 ? clamp mode ccdin1 refin1 v clp v com ccdin2 refin2 refin3 ccdin3 v rp v rn ccdin4 refin4 refin5 ccdin5 nc da4 da3 da2 da1 da0 dvdd dvss db4 db3 db2 db1 db0 nc dvss dc4 dc3 dc2 dc1 dc0 nc dvdd dvss avss avdd clpb a dc k shd shr avss avdd ccdin0 refin0 test nc aiset avdd avss resetb ce1 ce0 sdcl k sdenb sdin avdd avss avdd avss 3.3v 3.3v 8.2k ? 1% 0.1 f 1 f 1 f 1 f 1 f 1 f 1 f 1 f 1 f 1 f 1 f 1 f 1 f 1 f 0.1 f 0.1 f 0.1 f sdout 0.1 f 1 f 1 f 0.1 ? 20% above example is for reference. please select optimum capacitor values for a target system. figure 13 clamp mode
asahi kasei [AK8448] ms1513-e-00 2013/02 52 ? dc direct-coupled mode ccdin1 refin1 v clp v com ccdin2 refin2 refin3 ccdin3 v rp v rn ccdin4 refin4 refin5 ccdin5 nc da4 da3 da2 da1 da0 dvdd dvss db4 db3 db2 db1 db0 nc dvss dc4 dc3 dc2 dc1 dc0 nc dvdd dvss avss avdd clpb a dc k shd shr avss avdd ccdin0 refin0 test nc aiset avdd avss resetb ce1 ce0 sdcl k sdenb sdin avdd avss avdd avss 3.3v 3.3v 8.2k ? 1% 0.1 f 0.1 f 1 f 1 f 0.1 f 0.1 f 1 f 1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f sdout 0.1 f 0.1 ? 20% above example is for reference. please select optimum capacitor values for a target system. figure 14 dc direct-coupled mode
asahi kasei [AK8448] ms1513-e-00 2013/02 53 important notice z these products and their s pecifications are subject to change without notice. when you consider any use or application of these products, pl ease make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. z akm assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z any export of these products, or devices or systems containing them, may require an export license or other official approval under the la w and regulations of the country of export pertaining to customs and tariffs, currenc y exchange, or strategic materials. z akm products are neither intended nor aut horized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akm assumes no responsibility for such use, exc ept for the use approved with t he express written consent by representative director of akm. as used here: note1) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectivene ss of the device or system containing it, and which must t herefore meet very high standards of performance and reliability. note2) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medici ne, aerospace, nuclear ener gy, or other fields, in which its failure to function or perform may reasonably be expec ted to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm pr oducts, who distribut es, disposes of, or otherwise places the product wi th a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the abs ence of such notification.

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