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jitter cleaner and clock generator with 14 differential or 29 lvcmos outputs data sheet AD9523 features output frequency : <1 mhz to 1 ghz start - up frequency accuracy : < 100 ppm (determined by vcxo reference accuracy) zero delay operation input - to - output edge timing : < 150 ps 14 outputs : configurable lvpecl, lvds, hstl, and lvcmos 14 dedica ted output dividers with jitter - free adjustable delay adjustable delay : 63 resolution steps of ? period of vco output divider output - to - output skew : < 50 ps duty - cycle correction for odd divider settings automatic synchronization of all outputs on power - up absolute ou tput jitter : < 200 fs at 122.88 mhz integration range : 1 2 k hz to 20 mhz distribution phase noise floor: ?160 dbc/hz digital lock detect nonvolatile eeprom stores configuration settings spi - and i2c - compatible serial control port dual pll a rchitecture pll1 l ow bandwidth for reference input clock clean up with external vcxo p hase detector rate of 300 khz to 75 mhz redundant reference inputs auto and manual reference switchover modes revert ive and nonrevert ive switching loss of reference detection with holdover mode low n oise lvcmos output from vcxo used for rf/if s ynthesizers pll2 p hase detector rate of up to 250 mhz integrated low noise vco applications lte and m ulti c arrier gsm base stations wireless and b roadband i nfrastructure medical instrumentation clockin g high speed adcs, dacs, ddss, ddcs, ducs, mxfes low jitter, low phase noise clock distribution clock generation and translation for sonet, 10ge, 10g fc, and other 10 gbps protocols forward error correction (g.710) high performance wireless transceivers at e and high performance instrumentation functional block dia gram pll1 re f a, re f a out0, out0 out1, out1 out12, out12 out13, out13 refb, refb ref_test sclk/sc l sdio/sd a sdo zd_in, zd_in contro l inter f ace (spi and i 2 c) eeprom pll2 zero del a y AD9523 14-clock distribution osc_in, osc_in 08439-001 figure 1. general description the AD9523 provides a low power , multi - output , clock distribution function with low jitter performance, along with an on - chip pll and vco . the on - chip vco tunes from 3.6 ghz to 4.0 ghz. the AD9523 is defined to support the clock requirements for long term evolution (lte) and m ulticarrier gsm base station designs . it relies on an external vcxo to provide the reference jitter cleanup to a chieve the restrictive low phase noise require - ments necessary for acceptable data converter snr performance . the input receivers, oscillator, and zero delay receiver provide both single - ended and differential operation . when connected to a recovered syste m reference clock and a vcxo, the device generates 14 low noise outputs with a range of 1 mhz to 1 g hz , a nd one ded icated buffered output from the input pll ( pll1 ) . the frequency and phase of one clock output relative to another clock output can be varied by means of a divider phase select f unction that serves as a jitter - free coarse timing adjustment in increments that are equal to half the period of the signal coming out of the vco. an in - package eeprom can be programmed through the serial interface to st ore user - defined register settings for power - up and chip reset. rev. c document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to chang e without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 020 62 - 9106, u.s.a. tel: 781.329.4700 ? 2010 C 2013 analog devices, inc. all rights reserved. technical support www.analog.com
AD9523 data sheet rev. c | page 2 of 60 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 func tional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 3 specifications ..................................................................................... 4 conditions ..................................................................................... 4 supply current .............................................................................. 4 power dissipation ......................................................................... 5 refa, refa , refb, refb , osc_in, osc_in , and zd_in, zd_in input characteristics ...................................................... 5 osc_ctrl output characteristics .......................................... 6 ref_test input characteristics ............................................... 6 pll1 characteristics .................................................................... 6 pll1 output characteristics ...................................................... 6 distribution output characteristics (out0, out0 to out13, out13 ) .......................................................................... 7 timing alignment characteristics ............................................ 8 jitter and noise characteristics .................................................. 8 pll2 characteristics .................................................................... 8 logic input pins pd , eeprom_sel, ref_sel, reset , sync .............................................................................................. 9 status output pins status1, status0 ............................... 9 serial control port spi mode .................................................. 9 serial control port i2c mode ................................................ 10 absolute maximum ratings .......................................................... 12 thermal resistance .................................................................... 12 esd caution ................................................................................ 12 pin configuration and function descriptions ........................... 13 typical performance characteristics ........................................... 16 input/output termination recommendations .......................... 18 terminology .................................................................................... 19 theory of operation ...................................................................... 20 detailed block diagram ............................................................ 20 overview ..................................................................................... 20 component blocks input pll (pll1) .................................. 21 component blocks output pll (pll2) .............................. 22 clock distribution ..................................................................... 24 zero delay operation ................................................................ 26 reset modes ................................................................................ 26 power - down mode .................................................................... 27 serial control port ......................................................................... 28 spi/i2c port selection ................................................................ 28 i2c serial port operation .......................................................... 28 spi serial port operation .......................................................... 31 spi instruction word (16 bits) ................................................. 32 spi msb/lsb first transfers .................................................... 32 eeprom operations ..................................................................... 35 writing to the eeprom ........................................................... 35 reading from the eeprom ..................................................... 35 programming the eeprom buffer segment ......................... 36 power dissipation and thermal considerations ....................... 38 clock speed and driver mo de ................................................. 38 evaluation of operating conditions ........................................ 38 thermally enhanced package mounting guidelines ............ 39 control registers ............................................................................ 40 control register map ................................................................ 40 control register map bit descriptions ................................... 45 outline dimensions ....................................................................... 57 ordering guide .......................................................................... 57
data sheet AD9523 rev. c | page 3 of 60 revision history 2 /1 3 rev. b to rev. c deleted vdd1.8_pll2 ................................................. thro ughout change s to d ata s heet t itle ............................................................. 1 added t j of 115c, table 1 .............................................................. 4 changed vdd3_pll1, su pply voltage for pll1 typical parameter from 22 ma to 37 ma and changed vdd3_pll1, supply voltage for pll1 maximum parameter from 25.2 ma to 43 ma , table 2 ................................................................................... 4 changes to table 3 ............................................................................ 5 added pll1 c haracteristics section and table 7; renumbered sequentially ........................................................................................ 6 changes to table 9 summary statement ........................................ 7 change s to pin 7 description, table 19 ....................................... 1 3 changed pin 69 from vdd1.8_pll2 to nc, table 19 .............. 15 changes to figure 23 ...................................................................... 21 changes to clock distribution synchronization section .......... 25 changes to figure 29 ...................................................................... 26 added reset modes section and lock detect section .............. 26 added power - down mode section .............................................. 27 changes to pin descriptions section and read section ............ 31 added figure 38 ; renumbered sequentially ............................... 33 chang e s to register section definition group section ............ 36 changes to power dissipation and thermal considerations section .............................................................................................. 38 changes to table 31 ........................................................................ 40 changes to bits[1:0] description, table 40 and bit 2 description, table 41 ...................................................................... 46 changes to bits[7:6] description, ta ble 42 .................................. 47 changes to bits[1:0] description, table 43 .................................. 48 changes to bit 4, bits [3:2] descriptions, table 47 ..................... 49 change d bit 6 name from status pll2 feedback clock to status pl l1 feedback clock , table 54....................................................... 52 3/11 rev. a to rev. b added table summary, table 8 ....................................................... 7 changes to eeprom operations section and writing to the eeprom section ............................................................................ 3 4 changes to 0x01a, bits[4:3], table 30 .......................................... 3 9 changes to bits[4:3], table 40 ....................................................... 4 6 changes to table 47, bit 1 .............................................................. 4 8 11/10 rev. 0 to rev. a change to general description ....................................................... 1 changes to table sum mary , table 1 ............................................... 3 change to input high voltage a nd input low voltage parameters and added input threshold voltage parameter , table 4 ................................................................................................. 4 change to junction temperature rating, table 16; changes to thermal resistance section ...................................................... 11 changes to table 18 ........................................................................ 12 added fig ure 14, renumbered sequentially ............................... 16 edits to figure 15, figure 17, and figure 19 ................................ 17 changes to vco calibration section ........................................... 22 changed output mode heading to multimode output drivers ; changes to multimode output drivers section ; added figure 26 .............................................................................. 23 added power dissipation and thermal considerations section ; added table 29, renumbered sequentially .................. 35 changes to table 34, table 35, table 36, and table 38 ............... 43 changes to address 0x192, table 50 ............................................ 48 changes to table 52 ........................................................................ 49 changes to table 54 ........................................................................ 50 7 /10 revision 0 : initial versi on
AD9523 data sheet rev. c | page 4 of 60 specifications f vcxo = 122.88 mhz single ended, refa and refb on differential at 30.72 mhz, f vco = 3932.16 mhz, doubler is off, channel control low power mode off, divider phase =1, unless otherwise noted. typical is given for vdd = 3.3 v 5%, and t a = 25c, unless otherwise noted. minimum and maximum values are given over the full vdd, and t a (?40c to +85c) variation, as listed in table 1. conditions table 1. parameter min typ max unit test conditions/comments supply voltage vdd3_pll1, supply voltage for pll1 3.3 v 3.3 v 5% vdd3_pll2, supply voltage for pll2 3.3 v 3.3 v 5% vdd3_ref, supply voltage clock output drivers reference 3.3 v 3.3 v 5% vdd3_out[x:y], 1 supply voltage clock output drivers 3.3 v 3.3 v 5% vdd1.8_out[x:y], 1 supply voltage clock dividers 1.8 v 1.8 v 5% temperature ambient temperature range, t a ?40 +25 +85 c junction temperature, t j 115 c 1 x and y are the pair of differential outputs that share the sa me power supply. for example, vd d3_out[0:1] is supply voltage cl ock output out0, out0 (pin 68 and pin 67, respectively) and supply voltage clock output out1, out1 (pin 65 and pin 64, respectively). supply current table 2. parameter min typ max unit test conditions/comments supplies other than clock output drivers vdd3_pll1, supply voltage for pll1 37 43 ma decreases by 9 ma typical if refb is turned off vdd3_pll2, supply voltage for pll2 67 77.7 ma vdd3_ref, supply voltage clock output drivers reference lvpecl mode 5 6 ma only one output driver turned on; for each additional output that is turned on, the current increments by 1.2 ma maximum lvds mode 4 4.8 ma only one output driver turned on; for each additional output that is turned on, the current increments by 1.2 ma maximum hstl mode 3 3.6 ma values are independent of the number of outputs turned on cmos mode 3 3.6 ma values are independent of the number of outputs turned on vdd1.8_out[x:y], 1 supply voltage clock dividers 2 3.5 4.2 ma current for each divider: f = 245.76 mhz clock output drivers lvds mode, 7 ma vdd3_out[x:y], 1 supply voltage clock output drivers 16 17.4 ma f = 61.44 mhz lvds mode, 3.5 ma vdd3_out[x:y], 1 supply voltage clock output drivers 5 6.2 ma f = 245.76 mhz lvpecl mode vdd3_out[x:y], 1 supply voltage clock output drivers 17 18.9 ma f = 122.88 mhz hstl mode, 16 ma vdd3_out[x:y], 1 supply voltage clock output drivers 21 24.0 ma f = 122.88 mhz hstl mode, 8 ma vdd3_out[x:y], 1 supply voltage clock output drivers 14 16.3 ma f = 122.88 mhz cmos mode (single-ended) vdd3_out[x:y], 1 supply voltage clock output drivers 2 2.4 ma f = 15.36 mhz, 10 pf load 1 x and y are the pair of differential outputs that share the sa me power supply. for example, vd d3_out[0:1] is supply voltage cl ock output out0, out0 (pin 68 and pin 67, respectively) and supply voltage clock output out1, out1 (pin 65 and pin 64, respectively). 2 the current for pin 63 (vdd1_out[0:3]) is 2 that of the other v dd11.8_out[x:y] pairs.
data sheet AD9523 rev. c | page 5 of 60 power dissipation table 3 . parameter min typ max unit test conditions/comments power dissipation d oes not include power dissipated in termination resistors typical configuration 876 970 mw clock distribution outputs running as follows: seven lvpecl outputs at 122.88 mhz, three lvds outputs (3.5 ma) at 61.44 mhz, three lvds outputs (3.5 ma) at 245.76 mhz, one cmos 10 pf load at 122.88 mhz, and one differential input reference at 30.72 mhz; f vcxo = 122.88 mhz, f vco = 3932.16 mhz; pll2 bw = 530 khz, doubler is off pd , power - down 101 132.2 mw pd pin pulled low, with typical configuration conditions incremental power dissipation low power typical configuration 3 89 4 50 mw absolute total power with clock distribution; one lvpecl output running at 122.88 mhz; one differential input reference at 30.72 mhz; f vcxo = 122.88 mhz, f vco = 3932.16 mhz; doubler is off output distribution, driver on incremental power increase (ou t1) from low power typical lvds 15.3 18.4 mw single 3.5 ma lvds output at 245.76 mhz 47.8 55.4 mw single 7 ma lvds output at 61.44 mhz lvpecl 50.1 54.9 mw single lvpecl output at 122.88 mhz hstl 40.2 46.3 mw single 8 ma hstl output at 122.88 mhz 43.7 50.3 mw single 16 ma hstl output at 122.88 mhz cmos 6.6 7.9 mw single 3.3 v cmos output at 15.36 mhz 9.9 11.9 mw dual complementary 3.3 v cmos output at 122.88 mhz 9.9 11.9 mw dual in - phase 3.3 v cmos output at 122.88 mhz refa, refa , refb, refb , osc_in, osc_in , and zd_in, zd_in input characteristic s table 4 . parameter min typ max unit test conditions/comments differential mode input frequ ency range 400 mhz input slew rate (osc_in) 400 v/s minimum limit imposed for jitter performance common - mode internally generated input voltage 0.6 0.7 0.8 v input common - mode range 1.025 1.475 v for dc - coupled lvds (max imum swing) differentia l input voltage , sensitivity frequency < 250 mhz 100 mv p - p capacitive coupling required; can accommodate single - ended input by ac grounding of unused input; the instantaneous voltage on either pin must not exceed the 1.8 v dc supply rails differential input voltage, sensitivity frequency > 250 mhz 200 mv p - p capacitive coupling required; can accommodate single - ended input by ac grounding of unused input; the instantaneous voltage on either pin must not exceed the 1.8 v dc supply rails differential in put resistance 4.8 k? differential input capacitance 1 pf duty cycle duty cycle bounds are set by pulse width high and pulse width low pulse width low 1 ns pulse width high 1 ns cmos mode single - ended input input frequency range 250 mhz input high voltage 1.62 v input low voltage 0.52 v input threshold voltage 1.0 v when ac coupling to the input receiver, the user must dc bias the input to 1 v; the singl e - ended cmos input is 3.3 v compatible input capacitance 1 pf duty cycle duty cycle bounds are set by pulse width high and pulse width low pulse width low 1.6 ns pulse width high 1.6 ns
AD9523 data sheet rev. c | page 6 of 60 osc_ctrl output char acteristics table 5 . parameter min typ max unit test conditions/comments output voltage high vdd3_pll1 ? 0.15 v r load > 20 k? low 150 mv ref_test input chara cteristics table 6 . parameter min typ max unit test conditions/comments ref_test input input frequency range 250 mhz input high voltage 2.0 v input low voltage 0.8 v pll 1 characteristics table 7 . parameter min typ max unit test conditions/comments pll1 figure of merit (fom) ?226 dbc/hz maximum pfd frequency antibacklash pulse width minimum and low 75 mhz maximum and high 75 mhz pll1 output characte ristics table 8 . parameter 1 min typ max unit test conditions/comments maximum output frequency 250 mhz rise/fall time (20% to 80%) 387 665 ps 15 p f load duty cycle 45 50 55 % f = 250 mhz output voltage high output driver static vdd3_pll1 ? 0.25 v load current = 10 ma vdd3_pll1 ? 0.1 v load current = 1 ma output voltage low output driver static 0.2 v load current = 10 ma 0.1 v load current = 1 ma 1 cmos driver strength = strong (see table 52) .
data sheet AD9523 rev. c | page 7 of 60 distribution output characteristics (out0, out0 to out13, out13 ) duty cycle performance is specified with the invert divider bit set to 1, and the divider phase bits set to 0.5. (for example, for channel 0, 0x190[7] = 1 and 0x192[7:2] = 1.) output voltage reference vdd in table 9 refers to the 3.3 vdd3_out[x:y] supply. table 9. parameter min typ max unit test conditions/comments lvpecl mode maximum output frequency 1 ghz minimum vco/maximum dividers rise time/fall time (20% to 80%) 117 147 ps 100 termination across output pair duty cycle 47 50 52 % f < 500 mhz 43 48 52 % f = 500 mhz to 800 mhz 40 49 54 % f = 800 mhz to 1 ghz differential output voltage magnitude 643 775 924 mv voltage across pins, output driver static common-mode output voltage vdd ? 1.5 vdd ? 1.4 vdd ? 1.25 v output driver static scaled hstl mode, 16 ma maximum output frequency 1 ghz minimum vco/maximum dividers rise time/fall time (20% to 80%) 112 141 ps 100 termination across output pair duty cycle 47 50 52 % f < 500 mhz 44 48 51 % f = 500 mhz to 800 mhz 40 49 54 % f = 800 mhz to 1 ghz differential output voltage magnitude 1.3 1.6 1.7 v voltage across pins, output driver static; nominal supply supply sensitivity 0.6 mv/ mv change in output swing vs. vdd3_out[x:y] (v od /vdd3) common-mode output voltage vdd ? 1.76 vdd ? 1.6 vdd ? 1.42 v lvds mode, 3.5 ma maximum output frequency 1 ghz rise time/fall time (20% to 80%) 138 161 ps 100 termination across output pair duty cycle 48 51 53 % f < 500 mhz 43 49 53 % f = 500 mhz to 800 mhz 41 49 55 % f = 800 mhz to 1 ghz differential output voltage magnitude balanced 247 454 mv voltage across pins; output driver static unbalanced 50 mv absolute difference between voltage magnitude of normal pin and inverted pin common-mode output voltage 1.125 1.375 v output driver static common-mode difference 50 mv voltage difference between output pins; output driver static short-circuit output current 3.5 24 ma output driver static cmos mode maximum output frequency 250 mhz rise time/fall time (20% to 80%) 387 665 ps 15 pf load duty cycle 45 50 55 % f = 250 mhz output voltage high output driver static vdd ? 0.25 v load current = 10 ma vdd ? 0.1 v load current = 1 ma output voltage low output driver static 0.2 v load current = 10 ma 0.1 v load current = 1 ma
AD9523 data sheet rev. c | page 8 of 60 timing alignment cha racteristics table 10. parameter min typ max unit test conditions/comments output timing skew delay off on al l outputs; m aximum deviation between rising edges of outputs; all outputs are on, unless otherwise noted between outputs in same group 1 lvpecl , hstl, and lvds between lvpecl , hstl, and lvds outputs 30 183 ps cmos between cmos outputs 100 300 ps single - ended true phase high -z mode mean delta b etween group s 1 50 adjustable delay 0 63 steps resolution step; for example, 8 0.5/1 ghz resolution step 500 ps ? period of 1 ghz zero del ay between input clock edge on refa or refb to zd_in input clock edge, external zero delay mode 150 500 ps pll1 settings: pfd = 7.68 mhz, i cp = 63.5 a, r zero = 10 k?, antibacklash pulse width is at maximum, bw = 40 hz, refa and zd_in are set to differential mode 1 there are three groups of outputs. they are as follows: th e top outputs group: out0, out1, out2, out3; the right outputs group: out4, out5, out6, out7, out8, out9; and the bottom outputs group: out10, out11, out12, out13. jitter and noise characteristic s table 11. parameter min typ max unit test conditions/comments output absolute rms time jit ter application example based on a typical setup (see table 3 ); f = 122.88 mhz lvpecl mode, hstl mode, lvds mode 125 fs integrated bw = 200 khz to 5 mhz 136 fs integrated bw = 200 khz to 10 mhz 169 fs inte grated bw = 12 khz to 20 mhz 212 fs integrated bw = 10 khz to 61 mhz 223 fs integrated bw = 1 khz to 61 mhz pll2 characteristics table 12. parameter min typ max unit test conditions/comments vco (on chip) frequency range 3600 4000 mhz gain 45 mhz/v pll2 figure of merit (fom) ?226 dbc /hz maximum pfd frequency antibacklash pulse width minimum and low 250 mhz maximum and high 125 mhz
data sheet AD9523 rev. c | page 9 of 60 logic input pin s pd , eeprom_sel, ref_sel , reset , sync table 13. parameter min typ max unit test conditions/ comments v o ltage input high 2 .0 v input low 0.8 v input low current 8 0 250 a the minus sign indicates that, due to the internal pull - up resistor , current is flowing out of the AD9523 capacitance 3 pf reset timing pulse width low 50 ns inactive to start of register programming 100 ns sync timing pulse width low 1.5 ns high speed clock is clk input signal status output pins status1, status0 table 14. parameter min typ max unit test conditions/ comments v o ltage output hig h 2.94 v output low 0.4 v serial co ntrol port spi mode table 15. parameter min typ max unit test conditions/comments cs (input) cs has an internal 40 k? pull - up resistor voltage input logic 1 2.0 v input logic 0 0.8 v current input logic 1 3 0 a input logic 0 ?110 a the minus sign indicates that, due to the internal pull - up resistor, current is flowing out of the AD9523 in put capacitance 2 pf sclk (input) in spi mode sclk has an internal 40 k? pull - down resistor in spi mode but not in i 2 c mode voltage input logic 1 2.0 v input logic 0 0.8 v current input logic 1 240 a input logic 0 1 a input capacitance 2 pf sdio (when input is in bidirectional mode) voltage input logic 1 2.0 v input logic 0 0.8 v
AD9523 data sheet rev. c | page 10 of 60 parameter min typ max unit test conditions/comments current input logic 1 1 a input logic 0 1 a input capacitance 2 pf sdio, sdo (outputs) outp ut logic 1 voltage 2.7 v output logic 0 voltage 0.4 v timing clock rate (sclk, 1/t sclk ) 25 mhz pulse width high, t high 8 ns pulse width low, t low 12 ns sdio to sclk setup, t ds 3.3 ns sclk to sdio hold, t dh 0 ns sclk to v alid sdio and sdo, t dv 14 ns cs to sclk setup , t s 10 ns cs to sclk setup and hold, t s , t c 0 ns cs minimum pulse width high, t pwh 6 ns serial control port i2c mode vdd = vdd3_ref, unle ss otherwise noted. table 16. parameter min typ max unit test conditions/comments sda, scl (when inputting data) input logic 1 voltage 0.7 v dd v input logic 0 voltage 0.3 v dd v input current with an input vol tage between 0.1 v dd and 0.9 v dd ?10 +10 a hysteresis of schmitt trigger inputs 0.015 vdd v pulse width of spikes that must be suppressed by the input filter, t spike 50 ns sda (when outputting data) output logic 0 voltage at 3 ma si nk current 0.4 v output fall time from vih min to vil max with a bus capacitance from 10 pf to 400 pf 20 + 0.1 c b 1 250 ns timing note that all i 2 c timing values are referred to vih min (0.3 vdd) and vil max levels (0.7 vdd) clock rate (scl, f i2 c ) 400 khz bus free time between a stop and start condition , t idle 1.3 s setup time for a repeated start condition , t set; str 0.6 s hold time (repeated) start condition , t hld; str 0.6 s after this period, the first clock pulse is generated setup time for stop condition, t set; stp 0.6 s low period of the scl clock , t low 1.3 s high period of the scl clock , t high 0.6 s scl, sda rise time, t rise 20 + 0.1 c b 1 300 ns
data sheet AD9523 rev. c | page 11 of 60 parameter min typ max unit test conditions/comments scl, sda fall time, t fal l 20 + 0.1 c b 1 300 ns data setup time, t se t; dat 100 ns data hold time, t hld; dat 100 880 ns this is a minor deviation from the original i2c specification of 0 ns minimum 2 capaci tive load for each bus line , c b 1 400 pf 1 c b is the capacitance of one bus line in picofarads (pf). 2 according to the original i 2 c specification, an i 2 c master m ust also provide a minimum hold time of 300 ns for the sda signal to bridge the undefined region of the scl falling edge.
AD9523 data sheet rev. c | page 12 of 60 absolute maximum rat ings table 17. parameter rating v dd3_pll1, vdd3_pll2, vdd3_ref, vdd3_out , ldo_vco to gnd ?0.3 v to +3.6 v ref a , ref a , refin , refb, ref b to gnd ?0.3 v to +3.6 v sclk/scl, sdio/sda, sdo, cs to gnd ?0.3 v to +3.6 v out0, out0 , out1 , out1 , out2 , out 2 , out3, out3 , out4, out4 , out5, out5 , out6, out6 , out7, out7 , out8, out8 , out9 , out9 , out10, out10 , out11, out11 , out12 , out12 , out13 , out13 to gnd ?0.3 v to +3.6 v sync , reset , pd to gnd ?0.3 v to +3.6 v status 0, status1 to gnd ?0.3 v to +3.6 v sp0, sp1, eeprom _sel to gnd ?0.3 v to +3.6 v vdd1.8_out , ldo_pll1, ldo_pll2 to gnd 2 v storage te mperature range ?65c to +150c lead temperature (10 sec) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other c onditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst - case con ditions, that is, a device soldered in a circuit board for surface - mount packages. table 18 . thermal resistance package type airflow velocity (m/sec) ja 1, 2 jc 1, 3 jb 1, 4 jt 1, 2 unit 7 2 - lead lfcsp , 10 mm 10 mm 0 21.3 1.7 12. 6 0.1 c/w 1.0 20.1 0.2 c/w 2.5 18.1 0.3 c/w 1 per jedec 51 - 7, plus jedec 51 - 5 2s2p test board. 2 per jedec jesd51 - 2 (still air) or jedec jesd51 - 6 (moving air). 3 per mil - std 883, method 1012.1. 4 per jedec jesd51 - 8 (still air). for information about powe r dissipation, refer to the power dissipation and thermal considerations section. esd caution
data sheet AD9523 rev. c | page 13 of 60 pin configuration and fu nction descriptions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ldo_pll1 vdd3_pll1 refa refa refb refb lf1_ext_cap osc_ctrl osc_in osc_in lf2_ext_cap ldo_pll2 vdd3_pll2 ldo_vco pd ref_sel 17 sync 18 vdd3_ref 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 reset cs sclk/scl sdio/sda sdo ref_test out13 out13 vdd3_out[12:13] out12 out12 vdd1.8_out[12:13] out11 out11 vdd3_out[10:11] out10 35 out10 36 vdd1.8_out[10:11] 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 vdd1.8_out[4:5] out4 out4 vdd3_out[4:5] out5 out5 vdd1.8_out[6:7] out6 out6 vdd3_out[6:7] out7 out7 vdd1.8_out[8:9] out8 out8 vdd3_out[8:9] out9 out9 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 pll1_out zd_in zd_in nc out0 out0 vdd3_out[0:1] out1 out1 vdd1.8_out[0:3] out2 out2 vdd3_out[2:3] out3 out3 eeprom_sel status0/sp0 status1/sp1 08439-002 pin 1 indicator AD9523 (top view) notes 1. pins labeled nc can be allowed to float, but it is better to connect these pins to gro und. avoid routing high speed signals through these pins be cause noise coupling may result. on existing pcb designs, it i s acceptable to leave pin 69 connected to 1.8v supply. 2. the exposed paddle is the ground connection on the chip. it must be soldered to the analog ground of the pcb to ensure proper functionality and heat dissipation, noise, and mechanica l strength benefits. figure 2. pin configuration table 19. pin function descriptions pin no. mnemonic type 1 description 1 ldo_pll1 p/o 1.8 v internal ldo regulator decoupling pin for pll1. connect a 0.47 f decoupling capacitor from this pin to ground. note that, for best performance, the ldo bypass capacitor must be placed in close proximity to the device. 2 vdd3_pll1 p 3.3 v supply pll1. use the same supply as vcxo. 3 refa i reference clock input a. along with refa , this pin is the differential input for the pll reference. alternatively, this pin can be programmed as a single-ended 3.3 v cmos input. 4 refa i complementary reference clock input a. along with refa, this pin is the differential input for the pll reference. alternatively, this pin can be pr ogrammed as a single-ended 3.3v cmos input. 5 refb i reference clock input b. along with refb , this pin is the differential input for the pll reference. alternatively, this pin can be programmed as a single-ended 3.3 v cmos input. 6 refb i complementary reference clock input b. along with re fb, this pin is the differential input for the pll reference. alternatively, this pin can be prog rammed as a single-ended 3.3 v cmos input. 7 lf1_ext_cap o pll1 external loop filter capacitor. conn ect a loop filter capacitor to this pin and to ground. 8 osc_ctrl o oscillator control voltage. connect this pin to the voltage control pin of the external oscillator. 9 osc_in i pll1 oscillator input. along with osc_in , this pin is the differential input for the pll reference. alternatively, this pin can be programmed as a single-ended 3.3 v cmos input. 10 osc_in i complementary pll1 oscillator input. along with osc_i n, this pin is the differential input for the pll reference. alternatively, this pin can be prog rammed as a single-ended 3.3 v cmos input. 11 lf2_ext_cap o pll2 external loop filter capacitor connection. connect a capacitor to this pin and ldo_vco.
AD9523 data sheet rev. c | page 14 of 60 pin no. mnemonic type 1 description 12 ldo_pll2 p/o ldo decoupling pin for pll2 1.8 v internal regulator. connect a 0.47 f decoupling capacitor from this pin to ground. note that for best performance, the ldo bypass capacitor must be placed in close proximity to the device. 13 vdd3_pll2 p 3.3 v supply for pll2. 14 ldo_vco p/o 2.5 v ldo internal regulator decoupling pin for vco. connect a 0.47 f decoupling capacitor from this pin to ground. note that, for best performance, the ldo bypass capacitor must be placed in close proximity to the device. 15 pd i chip power-down, active low. this pin has an internal 40 k pull-up resistor. 16 ref_sel i reference input select. this pin has an internal 40 k pull-down resistor. 17 sync i manual synchronization. this pin initiates a manual synchronization and has an internal 40 k pull-up resistor. 18 vdd3_ref p 3.3 v supply for output clock drivers reference. 19 reset i digital input, active low. resets internal logic to default states. this pin has an internal 40 k pull-up resistor. 20 cs i serial control port chip select, active low. this pin has an internal 40 k pull-up resistor. 21 sclk/scl i serial control port clock signal for spi mode (sclk) or i 2 c mode (scl). data clock for serial program- ming. this pin has an internal 40 k pull-down resistor in spi mode but is high impedance in i2c mode. 22 sdio/sda i/o serial control port bidirectional serial da ta in/data out for spi mode (sdio) or i2c mode (sda). 23 sdo o serial data output. use this pin to read data in 4-wire mode (high impedance in 3-wire mode). there is no internal pull-up/pull-down resistor on this pin. 24 ref_test i test input to pll1 phase detector. 25 out13 o complementary square wave clocking output 13. this pin can be configured as one side of a differential lvpecl/lvds/hstl output or as a single-ended cmos output. 26 out13 o square wave clocking output 13. this pin can be co nfigured as one side of a differential lvpecl/ lvds/hstl output or as a single-ended cmos output. 27 vdd3_out[12:13] p 3.3 v supply for output 12 and output 13 clock drivers. 28 out12 o complementary square wave clocking output 12. this pin can be configured as one side of a differential lvpecl/lvds/hstl output or as a single-ended cmos output. 29 out12 o square wave clocking output 12. this pin can be co nfigured as one side of a differential lvpecl/ lvds/hstl output or as a single-ended cmos output. 30 vdd1.8_out[12:13] p 1.8 v supply for output 12 and output 13 clock dividers. 31 out11 o complementary square wave clocking output 11. this pin can be configured as one side of a differential lvpecl/lvds/hstl output or as a single-ended cmos output. 32 out11 o square wave clocking output 11. this pin can be co nfigured as one side of a differential lvpecl/ lvds/hstl output or as a single-ended cmos output. 33 vdd3_out[10:11] p 3.3 v supply for output 10 and output 11 clock drivers. 34 out10 o complementary square wave clocking output 10. this pin can be configured as one side of a differential lvpecl/lvds/hstl output or as a single-ended cmos output. 35 out10 o square wave clocking output 10. this pin can be co nfigured as one side of a differential lvpecl/ lvds/hstl output or as a single-ended cmos output. 36 vdd1.8_out[10:11] p 1.8 v supply for output 10 and output 11 clock dividers. 37 out9 o complementary square wave clocking output 9. this pin can be configured as one side of a differential lvpecl/lvds/hstl output or as a single-ended cmos output. 38 out9 o square wave clocking output 9. this pin can be configured as one side of a differential lvpecl/ lvds/hstl output or as a single-ended cmos output. 39 vdd3_out[8:9] p 3.3 v supply for output 8 and output 9 clock drivers. 40 out8 o complementary square wave clocking output 8. this pin can be configured as one side of a differential lvpecl/lvds/hstl output or as a single-ended cmos output. 41 out8 o square wave clocking output 8. this pin can be configured as one side of a differential lvpecl/ lvds/hstl output or as a single-ended cmos output. 42 vdd1.8_out[8:9] p 1.8 v supply for output 8 and output 9 clock dividers. 43 out7 o complementary square wave clocking output 7. this pin can be configured as one side of a differential lvpecl/lvds/hstl output or as a single-ended cmos output. 44 out7 o square wave clocking output 7. this pin can be configured as one side of a differential lvpecl/ lvds/hstl output or as a single-ended cmos output. 45 vdd3_out[6:7] p 3.3 v supply for outp ut 6 and supply output 7 clock drivers.
data sheet AD9523 rev. c | page 15 of 60 pin no. mnemonic type 1 description 46 out6 o complementary square wave clocking output 6. this pin can be configured as one side of a differential lvpecl/lvds/hstl output or as a single-ended cmos output. 47 out6 o square wave clocking output 6. this pin can be configured as one side of a differential lvpecl/ lvds/hstl output or as a single-ended cmos output. 48 vdd1.8_out[6:7] p 1.8 v supply for output 6 and output 7 clock dividers. 49 out5 o complementary square wave clocking output 5. this pin can be configured as one side of a differential lvpecl/lvds/hstl output or as a single-ended cmos output. 50 out5 o square wave clocking output 5. this pin can be configured as one side of a differential lvpecl/ lvds/hstl output or as a single-ended cmos output. 51 vdd3_out[4:5] p 3.3 v supply for output 4 and output 5 clock drivers. 52 out4 o complementary square wave clocking output 4. this pin can be configured as one side of a differential lvpecl/lvds/hstl output or as a single-ended cmos output. 53 out4 o square wave clocking output 4. this pin can be configured as one side of a differential lvpecl/ lvds/hstl output or as a single-ended cmos output. 54 vdd1.8_out[4:5] p 1.8 v supply for output 4 and output 5 clock dividers. 55 status1/sp1 i/o lock detect and other status signals (status1)/i 2 c address (sp1). this pin has an internal 40 k pull- down resistor. 56 status0/sp0 i/o lock detect and other status signals (status0)/i 2 c address (sp0). this pin has an internal 40 k pull- down resistor. 57 eeprom_sel i eeprom select. setting this pin high selects the regi ster values stored in the internal eeprom to be loaded at reset and/or power-up. setting this pin low causes the AD9523 to load the hard-coded default register values at power-up/reset. this pin has an internal 40 k pull-down resistor. 58 out3 o complementary square wave clocking output 3. this pin can be configured as one side of a differential lvpecl/lvds/hstl output or as a single-ended cmos output. 59 out3 o square wave clocking output 3. this pin can be configured as one side of a differential lvpecl/ lvds/hstl output or as a single-ended cmos output. 60 vdd3_out[2:3] p 3.3 v supply for output 2 and output 3 clock drivers. 61 out2 o complementary square wave clocking output 2. this pin can be configured as one side of a differential lvpecl/lvds/hstl output or as a single-ended cmos output. 62 out2 o square wave clocking output 2. this pin can be configured as one side of a differential lvpecl/ lvds/hstl output or as a single-ended cmos output. 63 vdd1.8_out[0:3] p 1.8 v supply for output 0, output 1, output 2, and output 3 clock dividers. 64 out1 o complementary square wave clocking output 1. this pin can be configured as one side of a differential lvpecl/lvds/hstl output or as a single-ended cmos output. 65 out1 o square wave clocking output 1. this pin can be configured as one side of a differential lvpecl/ lvds/hstl output or as a single-ended cmos output. 66 vdd3_out[0:1] p 3.3 v supply for output 0 and output 1 clock drivers. 67 out0 o complementary square wave clocking output 0. this pin can be configured as one side of a differential lvpecl/lvds/hstl output or as a single-ended cmos output. 68 out0 o square wave clocking output 0. this pin can be configured as one side of a differential lvpecl/ lvds/hstl output or as a single-ended cmos output. 69 nc p this pin is not connected internally (see figure 2). 70 zd_in i external zero delay clock input. along with zd_in , this pin is the differential input for the pll reference. alternatively, this pin can be prog rammed as a single-ended 3.3 v cmos input. 71 zd_in i complementary external zero delay clock input. alon g with zd_in, this pin is the differential input for the pll reference. alternatively, this pin can be programmed as a single-ended 3.3 v cmos input. 72 pll1_out o single-ended cmos output from pll1. this pin has settings for weak and strong in register 0x1ba, bit 4 (see table 52). ep ep, gnd gnd exposed paddle. the exposed paddle is the ground co nnection on the chip. it must be soldered to the analog ground of the pcb to ensure proper functionality and heat dissipation, noise, and mechanical strength benefits. 1 p = power, i = input, o = output, i/o = in put/output, p/o = power/output, gnd = ground.
AD9523 data sheet rev. c | page 16 of 60 typical performance characteristics f vcxo = 122.88 mhz, refa differential at 30.72 mhz, f vco = 3686.4 mh z, and doubler is off , unless otherw ise noted . 0 10 20 30 40 50 60 0 200 400 600 800 1000 1200 current (ma) frequenc y (mhz) hst l = 16m a hst l = 8m a 08439-003 figure 3. vdd3_out[ x:y ] current ( typical ) vs. frequency; hs tl mode, 16 ma and 8 ma 0 5 10 15 20 25 30 35 40 45 0 200 400 600 800 1000 1200 current (ma) frequenc y (mhz) l vds = 3.5m a l vds = 7m a 08439-004 figure 4. vdd3_out[ x:y ] current ( typical ) vs. frequency; lvds mode , 7 ma and 3.5 ma 0 5 10 15 20 25 30 35 40 45 0 200 400 600 800 1000 1200 current (ma) frequenc y (mhz) 08439-005 figure 5. vdd3_out[ x:y ] current ( typical ) vs. frequency , lvpecl mode 0 100 200 300 400 500 600 current (ma) frequenc y (mhz) 10pf 20pf 08439-006 0 5 10 15 20 25 30 35 2pf figure 6. vdd3_out[ x:y ] current ( typical ) vs. frequency; cmos mode, 20 pf, 10 pf , and 2 pf load 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 200 400 600 800 1000 1200 differentia l swing (v p-p) frequenc y (mhz) hst l = 8m a hst l = 16m a 08439-007 figure 7. differenti a l voltage swing vs. frequency; hstl mode, 16 ma and 8 ma 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0 200 400 600 800 1000 1200 differentia l swing (v p-p) frequenc y (mhz) 08439-008 figure 8. differential voltage swing vs. frequency , lvpecl mode
data sheet AD9523 rev. c | page 17 of 60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0 200 400 600 800 1000 1200 differentia l swing (v p-p) frequenc y (mhz) l vds = 3.5m a l vds = 7m a 08439-009 figure 9 . differential voltage swing vs. frequency ; lvds mode , 7 ma and 3. 5 ma 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 100 200 300 400 500 600 amplitude (v) frequenc y (mhz) 20pf 2pf 10pf 08439-010 figure 10 . amplitude vs. frequency and capacitive load; cmos mode, 2 pf, 1 0 pf, and 20 pf 08439-013 ch1 200mv 2.5ns/div 40.0gs/s a ch1 104mv 1 figure 11 . output waveform (differential), lvpecl at 122.88 mhz ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 ?170 100 1k 10k 100k 1m 10m 08439-015 phase noise (dbc/hz) frequency (hz) 1: 100hz, ?85.0688dbc/hz 2: 1khz, ?113.3955dbc/hz 3: 8khz, ?125.8719dbc/hz 4: 16khz, ?129.5942dbc/hz 5: 100khz, ?134.5017dbc/hz 6: 1mhz, ?145.2872dbc/hz 7: 10mhz, ?156.2706dbc/hz 8: 40mhz, ?157.4153dbc/hz x: start 12khz stop 80mhz center 40.006mhz span 79.988mhz noise: analysis range x: band marker analysis range y: band marker intg noise: ?75.94595dbc/39.99mhz rms noise: 225.539rad 12.9224mdeg rms jitter: 194.746fsec residual fm: 2.81623khz 1 2 3 4 5 6 7 8 figure 12 . phase n oise, output = 184.32 mhz (vcxo = 122.88 mhz, crystek vcxo cvhd - 950) ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 ?170 100 1k 10k 100k 1m 10m 08439-016 phase noise (dbc/hz) frequency (hz) 1: 100hz, ?89.0260dbc/hz 2: 1khz, ?116.9949dbc/hz 3: 8khz, ?129.5198dbc/hz 4: 16khz, ?133.3916dbc/hz 5: 100khz, ?137.7680dbc/hz 6: 1mhz, ?148.3519dbc/hz 7: 10mhz, ?158.3307dbc/hz 8: 40mhz, 159.1629?dbc/hz x: start 12khz stop 80mhz center 40.006mhz span 79.988mhz noise: analysis range x: band marker analysis range y: band marker intg noise: ?78.8099dbc/39.99mhz rms noise: 162.189rad 9.29276mdeg rms jitter: 210.069fsec residual fm: 2.27638khz 1 2 3 4 5 6 7 8 figure 13 . phase noise , output = 122.88 mhz (vcxo = 12 2.88 mhz, crystek vcxo cvhd - 950 ; doubler is off) ch1 500mv ? 2.5ns/div 40.0gs/s a ch1 80mv 1 08439-049 figure 14 . outpu t waveform (differential), hstl at 16 ma, 122.88 mhz
AD9523 data sheet rev. c | page 18 of 60 input/output termina tion recommendations 100? 0.1f 0.1f downstream device l vds output high impedance input AD9523 08439-142 figure 15 . ac - coupled lvds output driver 100? downstream device l vds output AD9523 high impedance input 08439-143 figure 16 . dc - coupled lvds output driver 100? 0.1f 0.1f downstream device l vpecl- com pa tible output high impedance input 08439-044 AD9523 figure 17 . ac - coupled lvpecl output driver 100? downstream device l vpec l com pa tible output high impedance input AD9523 08439-045 figure 18 . dc - coupled lvpecl output driver 100? 0.1f 0.1f downstream device hst l output high impedance input 08439-046 AD9523 figure 19 . ac - coupled hstl output driver 100? downstream device hst l output high impedance input AD9523 08439-047 figure 20 . dc - coupled hstl ou tput driver 1 resis t or v alue depends upon required termin a tion of source. self-biased re f , vcxo, zero del a y inputs AD9523 08439-048 100? (optional 1 ) 0.1f 0.1f figure 21 . ref, vcxo, and zero delay input differential mode
data sheet AD9523 rev. c | page 19 of 6 0 terminology phase jitter and phase noise an ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0 to 360 for each cycle. actual signals, however, display a certain amount of variation from ideal phase progression over time. this phenomenon is called phase jitter. although many causes can contribute to phase jitter, one major cause is random noise, w hich is characterized statistically as being gaussian (normal) in distribution. this phase jitter leads to a spreading out of the energy of the sine wave in the frequency domain, producing a continuous power spectrum. this power spectrum is usually report ed as a series of values whose units are dbc/hz at a given offset in frequency from the sine wave (carrier). the value is a ratio (expressed in decibels) of the power contained within a 1 hz bandwidth with respect to the power at the carrier frequency. fo r each measurement, the offset from the carrier frequency is also given. it is meaningful to integrate the total power contained within some interval of offset frequencies (for example, 10 khz to 10 mhz). this is called the integrated phase noise over th at frequency offset interval and can be readily related to the time jitter due to the phase noise within that offset frequency interval. phase noise has a detrimental effect on the performance of adcs , dacs, and rf mixers. it lowers the achievable dynamic range of the converters and mixers, although they are affected in somewhat different ways. time jitter phase noise is a frequency domain phenomenon. in the time domain, the same effect is exhibited as time jitter. when observing a sine wave, the time of su ccessive zero crossings varies. in a square wave, the time jitter is a displacement of the edges from their ideal (regular) times of occurrence. in both cases, the variations in timing from the ideal are the time jitter. because these variations are random in nature, the time jitter is specified in seconds root mean square (rms) or 1 sigma ( ) of the gaussian distribution. time jitter that occurs on a sampling clock for a dac or an adc decreases the signal - to - noise ratio (snr) and dynamic range of the converter. a sampling clock with the lowest possible jitter provides the highest performance from a given converter. additive phase noise additive phase noise is t he amount of phase noise that can be attribut ed to the device or subsystem being measured. the phase noise of any external oscillators or clock sources is subtracted. this makes it poss ible to predict the degree to which the device impacts the total system phase noise when used in conjunction with the various oscillators and clock sources, each of which contributes its own phase noise to the total. in many cases, the phase noise of one e lement dominates the system phase noise. when there are multiple contributors to phase noise, the total is the square root of the sum of squares of the individual contributors. additive time jitter additive time jitter is the amount of time jitter that can be attribut ed to the device or subsystem being measured. the time jitter of any external oscillators or clock sources is subtracted. this makes it possible to predict the degree to which the device impacts the total system time jitter when used in conjunc tion with the various oscillators and clock sources, each of which contributes its own time jitter to the total. in many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter.
AD9523 data sheet rev. c | page 20 of 60 theory of operation detailed block diagram charge pump 2 d1 vcxo switch- over control m1 out13 out12 out11 out10 out9 out8 out7 out6 out5 out4 out3 out2 out1 out0 out13 out12 out11 out10 out9 out8 out7 out6 out5 out4 out3 out2 out1 out0 status monitor lock detect/ serial port address control interface (sdi and i 2 c) sclk/scl sdo sdio/sda n2 pll2 ldo_pll2 loop filter to sync loop filter charge pump pll1 lock detect lock detect p f d zd_in zd_in pd reset sync d ? t edge d ? t edge d ? t edge d ? t edge d ? t edge d ? t edge d ? t edge d ? t edge d ? t edge d ? t edge d ? t edge d ? t edge d ? t edge d ? t edge sync signal pll1_out vdd1.8_out[x:y] refa refa refb refb AD9523 ref_sel status0/ sp0 status1/ sp1 eeprom eeprom_sel lf2_ext_cap lf1_ext_cap ref_test osc_ctrl osc_in cs r r n1 ldo_pll1 ldo_vco vdd3_out[x:y] vdd3_pll1 vdd3_pll2 nc vco p f d 08439-020 r figure 22. top level diagram overview the AD9523 is a clock generator that employs integer-n-based phase-locked loops (pll). the device architecture consists of two cascaded pll stages. the first stage, pll1, consists of an integer division pll that uses an external voltage-controlled crystal oscillator (vcxo) from 15 mhz to 250 mhz. pll1 has a narrow-loop bandwidth that provides initial jitter cleanup of the input reference signal. the second stage, pll2, is a frequency multiplying pll that translates the first stage output frequency to a range of 3.6 ghz to 4.0 ghz. pll2 incorporates an integer- based feedback divider that enables integer frequency multipli- cation. programmable integer dividers (1 to 1024) follow pll2, establishing a final output frequency of 1 ghz or less. the AD9523 includes reference signal processing blocks that enable a smooth switching transition between two reference inputs. this circuitry automatically detects the presence of the reference input signals. if only one input is present, the device uses it as the active reference. if both are present, one becomes the active reference and the other becomes the backup reference. if the active reference fails, the circuitry automatically switches to the backup reference (if available), making it the new active reference. a register setting determines what action to take if the failed reference is once again available: either stay on reference b or revert to reference a. if neither reference can be used, the AD9523 supports a holdover mode. a reference select pin (ref_sel, pin 16) is available to manually select which input reference is active (see table 43). the accuracy of the holdover is dependent on the external vcxo frequency stability at half supply voltage. any of the divider settings are programmable via the serial programming port, enabling a wide range of input/output frequency ratios under program control. the dividers also include a programmable delay to adjust timing of the output signals, if required. the output is compatible with lvpecl, lvds, or hstl logic levels (see the input/output termination recommendations section); however, the AD9523 is implemented only in cmos. the loop filters of each pll are integrated and programmable. only a single external capacitor for each of the two pll loop filters is required. the AD9523 operates over the extended industrial temperature range of ?40c to +85c.
data sheet AD9523 rev. c | page 21 of 60 component blocks input pll ( pll1 ) pll1 general description fundamentally, the input pll (ref erred to as pll1) consists of a phase - frequency detector (pfd), charge pump, passive loop filter , and an external vcxo operating in a closed loop. pll1 has the flexibility to o perate with a loop bandwidth of approximately 10 hz to 100 hz . this relatively narrow loop bandwidth gives the AD9523 the ability to suppress jitter that appears on the input references (refa and refb). the output of pll1 then becomes a low jitter phase - locked version o f the reference input system clock . pll1 reference clock inputs the AD9523 features two separate differential reference clock inputs, refa and refb . these inputs can be configured to operate in full differential mode or single - ended cmos mode . in differe ntial mode , these pins are internally self - biased . if refa or refb is driven single - ended, the unused side ( refa , refb ) should be decoupled via a suitable capacitor to a quiet ground. figure 21 shows the equivalent circuit of refa or refb . it is possible to dc - couple to these inputs , but the dc operation point should be set as specified in the specifications tables . to operate either the refa or the refb inputs in 3. 3 v cmos mode, the user must set bit 5 or bit 6, respectively, in register 0x01a (see table 41) . the single - ended inputs can be driven by either a dc - coupled cmos level signal or an ac - coupled sine wave or square wave. the diffe rential reference input receiver is powered down when the differential reference input is not selected , or when the pll is powered down. the single - ended buffers power - down when the pll is powered down, when their respective individual power - down registers are set, or when the differential receiver is selected. the refb r divider uses the same value as the refa r divider unless bit 7, the enable refb r divider independent division control bit in register 0x01c, is programmed as shown in table 43 . pll1 loop filter the pll 1 loop filter requires the connection of an extern al capacitor from lf1_ext_cap (pin 7 ) to ground. the value of the external capacitor depends on the use of an external vcxo, as well as such configura tion parameters as input clock rate and desired bandwidth . normally, a 0.3 f capacitor allows the loop bandwidth to range from 1 0 hz to 100 hz and ensures loop stability over the intended oper ating parameters of the device (see table 44 for r zero values ) . r zero c pole1 r pole2 c pole2 charge pump lf1_ext_cap ldo_pll1 buffer 1k? 0.3f osc_ctrl to vcxo v tune input 08439-022 AD9523 figure 23 . pll1 loop filter table 20. pll1 loop filter programmable values r zero (k ? ) c pole1 (nf) r pole2 (k ? ) c pole2 (nf) lf1_ext_cap 1 (f) 883 1.5 f ixed 165 f ixed 0.337 f ixe d 0.3 677 341 135 10 external 1 external loop filter c apacitor . an external r - c low - pass filter should be used at the osc_ctrl output. the values shown in figure 23 add an additional low - pass pole at ~530 hz. this r - c network filters the noise associated with the osc_ctrl buffer to achieve the best noise performance at the 1 khz offset region. r zero c pole1 r pole2 lf1_ext_cap switch- over control refa refb refa refb ref_sel ref_test divide-by- 1, 2, ...1023 charge pump 7 bits, 0.5a lsb vdd3_pll ldo_pll1 1.8v ldo 3.3v cmos or 1.8v differential osc_ctrl osc_in divide-by- 1, 2, ...1023 divide-by- 1, 2, ...1023 divide-by- 1, 2, ...63 p f d vcxo c pole2 AD9523 08439-021 figure 24 . input pll ( pll1 ) block diagram
AD9523 data sheet rev. c | page 22 of 60 pll1 input dividers each reference input feeds a dedicated reference divider block. the input dividers provide division of the reference frequency in integer steps from 1 to 1023. they provide the bulk of the frequency prescaling that is necessary to reduce the reference frequency to accommodate the bandwidth that is typically desired for pll1. pll1 reference switchover the reference monitor verifies the presence/absence of the prescaled refa and refb signals (that is, after division by the input dividers). the status of the reference monitor guides the activity of the switchover control logic. the AD9523 supports automatic and manual pll reference clock switching between refa (the refa and refa pins) and refb (the refb and refb pins). this feature supports networking and infrastructure applications that require redundant references. there are several configurable modes of reference switchover. the manual switchover is achieved either via a programming register setting or by using the ref_sel pin. the automatic switchover occurs when refa disappears and there is a reference on refb. the reference automatic switchover can be set to work as follows: ? nonrevertive: stay on refb. switch from refa to refb when refa disappears, but do not switch back to refa if it reappears. if refb disappears, then go back to refa. ? revert to refa. switch from refa to refb when refa disappears. return to refa from refb when refa returns. see table 43 for the pll1 miscellaneous control register bit settings. pll1 holdover in the absence of both input references, the device enters holdover mode. holdover is a secondary function that is provided by pll1. because pll1 has an external vcxo available as a frequency source, it continues to operate in the absence of the input reference signals. when the device switches to holdover, the charge pump tristates. the device continues operating in this mode until a reference signal becomes available. then the device exits holdover mode, and pll1 resynchronizes with the active reference. in addition to tristate, the charge pump can be forced to vcc/2 during holdover (see table 43, bit 6 in register 0x01c). component blocksoutput pll (pll2) pll2 general description the output pll (referred to as pll2) consists of an optional input reference doubler, phase-frequency detector (pfd), a partially integrated analog loop filter (see figure 25), an integrated voltage-controlled oscillator (vco), and a feedback divider. the vco produces a nominal 3.8 ghz signal with an output divider that is capable of division ratios of 4 to 11. the pfd of the output pll drives a charge pump that increases, decreases, or holds constant the charge stored on the loop filter capacitors (both internal and external). the stored charge results in a voltage that sets the output frequency of the vco. the feedback loop of the pll causes the vco control voltage to vary in a way that phase locks the pfd input signals. the gain of pll2 is proportional to the current delivered by the charge pump. the loop filter bandwidth is chosen to reduce noise contributions from pll sources that could degrade phase noise requirements. the output pll has a vco with multiple bands spanning a range of 3.6 ghz to 4.0 ghz. however, the actual operating frequency within a particular band depends on the control voltage that appears on the loop filter capacitor. the control voltage causes the vco output frequency to vary linearly within the selected band. this frequency variability allows the control loop of the output pll to synchronize the vco output signal with the reference signal applied to the pfd. typically, the device automatically selects the appropriate band as part of its calibration process (invoked via the vco control register at address 0x0f3). n divider to dist/ resync 2 pll1_out ldo ldo pll_1.8v ldo_pll2 vdd3_pll2 ldo_vco divide by 1, 2, 4, 8, 16 divide by 4, 5, 6, ...11 divide-by-4 prescaler a/b counters charge pump 8 bits, 3.5a lsb pfd r zero r pole2 c pole1 c pole2 lf2_ext_cap 08439-023 AD9523 figure 25. output p ll (pll2) block diagram
data sheet AD9523 rev. c | page 23 of 60 input 2 frequency multiplier the 2 frequency multiplier provides the option to double the frequency at the pll 2 input. this allows the user to take advantage of a higher frequency at the input to the pll (pfd) and, thus, allows for reduced in - band phase noise and greater separation between the frequency generated by the pll and the modulation spur associated with pfd. however, increased reference spur separation results in harmonic spurs introduced by the frequency multiplier that increase as the duty cycle deviates from 50% at the osc_in inputs. as such, beneficial use of the frequency multiplier is application - sp ecific. typically, a vcxo with proper interfacing has a duty cycle that is approximately 50% at the osc_in inputs. note that the maximum output frequency of the 2 frequency multipliers must not exceed the maximum pfd rate that is specified in table 12. pll2 feedback divider pll2 has a feedback divider (n divider) that enables it to provide in teger frequency up - conversion. the pll2 n divider is a com - bin ation of a prescaler (p) and two counters, a and b. the total divider value is n = ( p b ) + a where p = 4. the feedback divider is a dual modulus pre scaler architecture, with a non programmable p that is equal to 4. the value of the b counter can be from 4 to 63, and the value of the a counter can be from 0 to 3. h owever , due to the architecture of the divider, there are constraints, as listed in table 46 . pll2 loop filter the pll 2 loop filter requires the connection of an external c apacitor from lf2_ext_cap (p in 11 ) to ldo_vco (p in 14) , as illustrated in figure 25. the value of the external capacitor depends on the operating mode and the desired phase noise performance . for example, a loop bandwidth of approximately 500 khz produce s the lowest integrated jitter . a lower bandwidth produce s lower phase noise at 1 mhz but increase s the total integrated jitter. table 21. pll2 loop filter programmable values r zero ( ? ) c pole1 (pf) r pole2 ( ? ) c pole2 (pf) lf2_ext_cap 1 (p f) 3250 48 900 fixed at 16 typical at 1000 3000 40 450 2750 32 300 2500 24 225 2250 16 2100 8 2000 0 1850 1 external loop filter capacitor. vco divider the vco divider prov ides frequency division between the internal vco and the clock distribution. the vco divider can be set to divide by 4, 5, 6, 7, 8, 9, 10, or 11. vco calibration the AD9523 on - chip vco must be manually calibrated to ensure proper operation over process and temperature. this is accom - plished by setting the calibrate vco bit (register 0x0f3, bit 1) to 1. (this bit is not self - clearing.) the setting can be performed as part of the initial setup before executing the io_u pdate bit (register 0x234, bit 0 = 1). a readback bit, vco calibration in progress ( register 0x22d, bit 0), indicates when a vco calibration is in progress by returning a logic true (that is, bit 0 = 1). if the eeprom is in use, setting the calibrate vco bit to 1 before saving the register settin gs to the eeprom ensures that the vco calibrates automatically after the eeprom has loaded. after calibration, it is recommended that a sync be initiated (see the clock distribution synchronization section). note that the calibrat e vco bit defaults to 0. this bit must change from 0 to 1 to initiate a calibration sequence. therefore, any subsequent calibrations require the following sequence: 1. register 0x0f3, bit 1 (calibrate vco bit) = 0 2. register 0x234, bit 0 (io_update bit) = 1 3. reg ister 0x0f3, bit 1 (calibrate vco bit) = 1 4. register 0x234, bit 0 (io_update bit) = 1 vco calibration is controlled by a calibration controller that runs off the vcxo input clock . t he calibration requires that pll 2 be set up properly to lock the pll 2 loop a nd that the vcxo clock be present. during power - up or reset, the distribution section is automatically held in sync until the first vco calibration is finished. therefore, no outputs can occur until vco calibration is complete and pll2 is locked. initiate a vco calibration under the following conditions: ? after changing any of the pll2 b counter and a counter settings or after a change in the pll 2 reference clock frequency. this means that a vco calibration should be initiated any time that a pll 2 register or reference clock changes such that a different vco frequency is the result . ? whenever system calibration is desired. the vco is designed to operate properly over extremes of temperature even when it is first calibrated at the opposite extreme. however, a vco calibration can be initiated at any time, if desired.
AD9523 data sheet rev. c | page 24 of 60 clock distribution the clock distribution block provides an integrated solution for generating multiple clock outputs based on frequency dividing the pll2 vco divider output. the distribution output consists of 14 channels (out0 to out13). each of the output channels has a dedicated divider and output driver , as shown in figure 25. the AD9523 also has the capability to route the vcxo output to four of the outputs ( out0 to ou t 3 ). clock dividers the output clock distribution dividers are referred to as d0 to d13, corresponding to output channels out0 through out13, respectively. each div ider is programmable with 10 bits of division depth that is equal to 1 to 1024 . dividers hav e duty cycle correction to always give 50% duty cycle , even for odd divides . output power - down each of the output channels offer s independent control of the power - down functionality via the channel 0 to channel 13 control register s (see table 51) . each output channel has a dedicated power - down bit for powering down the output driver . however, if all 14 outputs are powered down, the entire distribution output enters a deep sleep mode. although e ach channel has a channel power - down control signal, it may sometimes be desirable to power down an output driver while maintaining the dividers synchronization with the other channel dividers. this is accom - plished by placing the output in tri state mode (this works in cmos mode, as well). m ultimode output drivers the user has independent control of the operating mode of each of the fourteen output channels via the channel 0 to channel 13 control register s ( see table 51 ). the operating mode control includes the follo wing : ? logic family and pin functionality ? output drive strength ? output polarity the four least significant bits (lsbs) of each of the 14 channel 0 to channel 13 control registers comprise the driver mode bits. the mode value selects the desired logic family and pin functionality of an output channel , as listed in table 51. this driver design allows a common 100 ? external resistor for all the different driver modes of operation that are illustrated in figure 26. if the output channel is ac - coupled to the circuit to be clocked, changing the mode va ries the voltage swing to determine sensi - tivity to the drive level. for example, in lvds mode , a current of 3.5 ma causes a 350 mv peak voltage. likewise, in lvpecl mode , a current of 8 ma causes a n 800 mv peak voltage at the 100 ? load resistor. using an y termination other than those specified in the input/output termination recommendations section may results in damage or decrease end of life performance in addition to the four mode bits, each of the 14 channel 0 to channel 1 3 control register s includes the following control bits: ? i nvert divider output. enables the user to choose between normal polarity and inverted polarity. normal polarity is the default state. inverted polarity reverses the representation of l ogic 0 and log ic 1 , regardless of the logic family. ? ignore sync. makes the divider ignore the sync signal from any source. ? power - down channel. powers down the entire channel. ? lower power mode. ? driver mode. ? channel divider. ? divider phase. 3.5ma/8ma lvds/lvpecl enabled hstl enabled hstl enabled ? ? p n n p ?/2$' cm vdd3_out[x:y] 1.25v lvds vdd ? 1.3v lvpecl cm common-mode circuit + ? 08439-031 figure 26 . multimode driver clock distribution synchronization a block diagram of the clock distribution synchronization functionality is shown in figure 27. the synchronization sequence begins with the primary synch ronization signal, which ultimately results in delivery of a synchronization strobe to the clock distribution logic. as indicated, the primary synchronization signal originates from one of the f ollowing sources: ? direct s ync hronization s ource vi a the sync d ividers bit (see register 0x232, bit 0 in table 55 ) ? device pin , sync (pin 17) an automatic synchronization of the divider is initiated the first time that pll2 locks after a power - up or reset event. subsequent lock/unlock events do not initiate a resynchronization of the distribution dividers unless they are preceded by a power - down or reset of the part. both sources of the primary synchronization signal are logic ord; therefore, any one of them can synchroniz e the clock distribution output at any time.
data sheet AD9523 rev. c | page 25 of 60 when using the sync dividers bit, the user first sets and then clears the bit. the synchronization event is the clearing operation (that is, the logic 1 to logic 0 transition of the bit). the dividers are all automatically synchronized to each other when pll2 is ready. the dividers support programmable phase offsets from 0 to 63 steps, in half periods of the input clock (for example, the vco divider output clock). the phase offsets are incorporated in the dividers through a preset for the first output clock period of each divider. phase offsets are sup-ported only by programming the initial phase and divide value and then issuing a sync to the distribution (automatically at startup or manually, if desired). when using the sync pin (pin 17), there are 11 vco divider output pipe line delays plus one period of the clock from the rising edge of sync to the clock output. there is at least one extra vco divider period of uncertainty because the sync signal and the vco divider output are asynchronous. in normal operation, the phase offsets are already programmed through the eeprom or the spi/i 2 c port before the AD9523 starts to provide outputs. although the user cannot adjust the phase offsets while the dividers are operating, it is possible to adjust the phase of all the outputs together without powering down pll1 and pll2. this is accomplished by programming the new phase offset, using bits[7:2] in register 0x192 (see table 51) and then issuing a divide sync signal by using the sync pin or the sync dividers bit (register 0x232, bit 0). all outputs that are not programmed to ignore the sync are disabled temporarily while the sync is active. note that, if an output is used for the zero delay path, it also disappears momentarily. however, this is desirable because it ensures that all the synchronized outputs have a deterministic phase relationship with respect to the zero delay output and, therefore, also with respect to the input. fan out vco output divider sync (pin 17) sync sync dividers bit 08439-025 divider driver outx outx out sync phase divide figure 27. clock output sy nchronization block diagram divide = 2, phase = 0 divide = 2, phase = 6 vco divider output clock sync control 6 0.5 periods 0 8439-026 figure 28. clock output sync hronization timing diagram
AD9523 data sheet rev. c | page 26 of 60 zero delay operation zero de lay operation aligns the phase of the output clocks with the phase of the external pll reference input. the o ut 0 output is de signed to be used as the output for zero delay . there are two zero delay modes on the ad952 3 : internal and external (see figure 29 ). note that the external delay mode provides better matching than the internal delay mode because the output drivers are included in the zero delay path. setting the anti backlash pulse width control of pll1 to maxi mum gives the best zero delay matching. internal fb zd_in refa refa AD9523 feedback delay ref delay enb pfd out0 out0 zd_in 08439-027 figure 29 . zero delay function internal zero delay mode the internal zero delay function of the AD9523 is achieved by feeding the output of channel d ivider 0 back to the pll1 n divider . bi t 5 in register 0x01b is used to select inter nal zero delay mode (see table 42 ). i n the internal zero delay mode , the output of channel divider 0 is routed back to the pll1 (n divider) through a m ux . pll1 synchronizes the phase/ed ge of the output of channel divider 0 with the pha se/edge of the reference input. because the channel dividers are synchronized to each other, the outputs of the channel divider are synchronous with the reference input. external zero delay mode the extern al zero delay function of the AD9523 is achieved by feeding out 0 back to the zd_in input and , ultimately , back to the pll 1 n divider. in figure 29 , the change in signal routing for external zero delay is external to the AD9523. b it 5 in register 0x01b is used to select the external zero delay mode. in external zero delay mode, out0 must be route d back to pll 1 ( the n divider) through the zd_in and zd_in pins. pll1 synchronizes the phase/edge of the feedback outpu t clock with the phase/edge of the reference input. because the channel dividers are synchronized to each other, the clock outputs are synchronous with the reference input. both the ref erence path delay and the feedback delay from zd_in are designed to ha ve the same propagation delay from the output drivers and pll components to minimize the phase offset between the clock output and the reference input to achieve zero delay. lock detect pll1 and pll2 lock detectors issue an unlock condition when the freque ncy error is greater than the threshold of the lock detector. when the pll is unlocked, there is a random phase between the reference clock and feedback clock. due to the random phase relationship that exists the unlock condition could take between 2 15 t pfd cycles to 1 t pfd cycles. for a lock condition it will always take 2 16 t pfd to lock, but it could potentially take 2 31 t pfd cycles depending on how big the phase jump is and when it occurs in relation to the lock detect restart . reset modes the a d9523 has a power - on reset (por) and several other ways to apply a reset condition to the chip. power - on reset during chip power - up, a power - on reset pulse is issued when 3.3 v supply reaches ~2.6 v (<2.8 v) and restores the chip either to the setting sto red in eeprom (eeprom pin = 1) or to the on - chip setting (eeprom pin = 0). at power - on, the AD9523 executes a sync operation, which brings the outputs into phase alignment according to the default settings. the output drivers are held in sync for the durat ion of the internally generated power - up sync timer (~70 ms). the outputs begin to toggle after this period. reset via the reset pin reset , a reset (an asynchronous hard reset is executed by briefly pulling reset low), restores the chip either to the setting stored in eeprom (eeprom pin = 1) or to the on - chip setting (eeprom pin = 0). a reset also executes a sync operation, which brings the outputs into phase alignment according to the default settings. when eeprom is inactive (eeprom pin = 0), it takes ~2 s for the outputs to begin toggling after reset is issued. when eeprom is active (eeprom pin = 1), it takes ~40 ms for the outputs to toggle after reset is brought high. reset via the serial port the serial port control register allows for a reset by setting bit 2 and bit 5 in register 0x000. when bit 2 and bit 5 are set, the chip enters a reset mode and restores the chip either to the setting stored in eeprom (eepr om pin = 1) or to the on - chip setting (eeprom pin = 0), except for register 0x000. except for the self - clearing bits, bit 2 and bit 5, register 0x000 retains its previous value prior to reset. during the internal reset, the outputs hold static. bi t 2 and b it 5 are self - clearing. however, the self - clearing opera tion does not complete until an additional serial port sclk cycle completes , and the AD9523 is held in reset until bit 2 and bit 5 self - clear .
data sheet AD9523 rev. c | page 27 of 60 reset to settings in eeprom when eeprom pin = 0 via the s erial port the serial port control register allows the chip to be reset to settings in eeprom when the eeprom pin = 1 via register 0xb02, bit 1 . this bit is self - clearing. this bit does not have any effect when the eeprom pin = 0. it takes ~40 ms for the o utputs to begin toggling after the soft_eeprom register is cleared. power - down mode chip power - down via pd place the AD9523 into a power - down mode by pulling the pd pin low. power - down turns off most of the functions a nd currents inside the AD9523. the chip remains in this power - down state until pd is returned to a logic high state. when taken out of power - down mode, the AD9523 returns to the settings programmed into its registers prior to the power - d own, unless the registers are changed by new programming while the pd pin is held low.
AD9523 data sheet rev. c | page 28 of 60 serial control port the AD9523 serial control port is a flexible, synchronous serial communications port that allows an easy interface with many industry-standard microcontrollers and microprocessors. the AD9523 serial control port is compatible with most synchronous transfer formats, including philips i2c?, motorola? spi, and intel? ssr protocols. the AD9523 i2c implementation deviates from the classic i2c specification in two specifications, and these deviations are documented in table 16 of this data sheet. the serial control port allows read/write access to all registers that configure the AD9523. spi/i2c port selection the AD9523 has two serial interfaces, spi and i2c. users can select either the spi or i2c depending on the states (logic high, logic low) of the two logic level input pins, sp1 and sp0, when power is applied or after a reset (each pin has an internal 40 k pull-down resistor). when both sp1 and sp0 are low, the spi interface is active. otherwise, i 2 c is active with three different i 2 c slave address settings (seven bits wide), as shown in tabl e 22 . the five msbs of the slave address are hardware coded as 11000, and the two lsbs are determined by the logic levels of the sp1 and sp0 pins. table 22. serial port mode selection sp1 sp0 address low low spi low high i 2 c: 1100000 high low i 2 c: 1100001 high high i 2 c: 1100010 i2c serial port operation the AD9523 i2c port is based on the i2c fast mode standard. the AD9523 supports both i2c protocols: standard mode (100 khz) and fast mode (400 khz). the AD9523 i2c port has a 2-wire interface consisting of a serial data line (sda) and a serial clock line (scl). in an i2c bus system, the AD9523 is connected to the serial bus (data bus sda and clock bus scl) as a slave device, meaning that no clock is generated by the AD9523. the AD9523 uses direct 16-bit (two bytes) memory addressing instead of traditional 8-bit (one byte) memory addressing. i 2 c bus characteristics table 23. i 2 c bus definitions abbreviation definition s start sr repeated start p stop a acknowledge a no acknowledge w write r read one pulse on the scl clock line is generated for each data bit that is transferred. the data on the sda line must not change during the high period of the clock. the state of the data line can change only when the clock on the scl line is low. sda scl data line stable; data valid change of data allowed 0 8439-160 figure 30. valid bit transfer a start condition is a transition from high to low on the sda line while scl is high. the start condition is always generated by the master to initialize the data transfer. a stop condition is a transition from low to high on the sda line while scl is high. the stop condition is always generated by the master to end the data transfer. start condition s stop condition p sd a scl 08439-161 figure 31. start and stop conditions a byte on the sda line is always eight bits long. an acknowledge bit must follow every byte. bytes are sent msb first. the acknowledge bit is the ninth bit attached to any 8-bit data byte. an acknowledge bit is always generated by the receiving device (receiver) to inform the transmitter that the byte has been received. it is accomplished by pulling the sda line low during the ninth clock pulse after each 8-bit data byte.
data sheet AD9523 rev. c | page 29 of 60 s d a msb acknowledge from slave-receiver acknowledge from slave-receiver scl s p 1 2 8 9 1 2 8 3 to 7 3 to 7 9 10 08439-162 figure 32. acknowledge bit s d a msb = 0 acknowledge from slave-receiver acknowledge from slave-receiver scl s p 1 2 8 9 1 2 8 3 to 7 3 to 7 9 10 08439-163 figure 33. data transfer process (master write mode, 2-byte transfer used for illustration) s d a acknowledge from master-receiver no acknowledge from slave-receiver scl s p 1 2 8 9 1 2 8 3 to 7 3 to 7 9 10 msb = 1 08439-164 figure 34. data transfer process (master read mode, 2-byte transfer used for illustration) the no acknowledge bit is the ninth bit attached to any 8-bit data byte. a no acknowledge bit is always generated by the receiving device (receiver) to inform the transmitter that the byte has not been received. it is accomplished by leaving the sda line high during the ninth clock pulse after each 8-bit data byte. data transfer process the master initiates data transfer by asserting a start condition. this indicates that a data stream follows. all i2c slave devices connected to the serial bus respond to the start condition. the master then sends an 8-bit address byte over the sda line, consisting of a 7-bit slave address (msb first), plus an r/ w bit. this bit determines the direction of the data transfer, that is, whether data is written to or read from the slave device (0 = write, 1 = read). the peripheral whose address corresponds to the transmitted address responds by sending an acknowledge bit. all other devices on the bus remain idle while the selected device waits for data to be read from or written to it. if the r/ w bit is 0, the master (transmitter) writes to the slave device (receiver). if the r/ w bit is 1, the master (receiver) reads from the slave device (transmitter). the format for these commands is described in the data transfer format section. data is then sent over the serial bus in the format of nine clock pulses, one data byte (eight bits) from either master (write mode) or slave (read mode), followed by an acknowledge bit from the receiving device. the number of bytes that can be transmitted per transfer is unrestricted. in write mode, the first two data bytes immediately after the slave address byte are the internal memory (control registers) address bytes with the high address byte first. this addressing scheme gives a memory address of up to 2 16 ? 1 = 65,535. the data bytes after these two memory address bytes are register data written into the control registers. in read mode, the data bytes after the slave address byte are register data read from the control registers. a single i 2 c transfer can contain multiple data bytes that can be read from or written to control registers whose address is automatically incremented starting from the base memory address. when all data bytes are read or written, stop conditions are established. in write mode, the master (transmitter) asserts a stop condition to end data transfer during the 10th clock pulse following the acknowledge bit for the last data byte from the slave device (receiver). in read mode, the master device (receiver) receives the last data byte from the slave device (transmitter) but does not pull it low during the ninth clock pulse. this is known as a no acknowledge bit. upon receiving the no acknowledge bit, the slave device knows that the data transfer is finished and releases the sda line. the master then takes the data line low during the low period before the 10th clock pulse and high during the 10th clock pulse to assert a stop condition. a repeated start (sr) condition can be used in place of a stop condition. furthermore, a start or stop condition can occur at any time, and partially transferred bytes are discarded. for an i 2 c data write transfer containing multiple data bytes, the peripheral drives a no acknowledge for the data byte that follows a write to register 0x234, thereby ending the i 2 c transfer. for an i 2 c data read transfer containing multiple data bytes, the peripheral drives data bytes of 0x00 for subsequent reads that follow a read from register 0x234.
AD9523 data sheet rev. c | page 30 of 60 data transfer format send byte format. the send byte protocol is used to set up the register address for subsequent commands. s slave address w a ram address high byte a ram address low byte a p write byte format. the write byte protocol is used to write a register address to the ram, starting from the specified ram addr ess. s slave address w a ram address high byte a ram address low byte a ram data 0 a ram data 1 a ram data 2 a p receive byte format. the receive byte protocol is used to read the data byte(s) from the ram, starting from the current address . s slave address r a ram data 0 a ram data 1 a ram data 2 a p read byte format. the combined format of the send byte and the receive byte. s slave address w a ram address high byte a ram address low byte a sr slave address r a ram data 0 a ram data 1 a ram data 2 a p i2c serial port timing sda scl s sr p s t fall t set; dat t low t rise t hld; str t hld; dat t high t fall t set; str t hld; str t spike t set; stp t rise t idle 08439-165 figure 35. i2c serial port timing table 24. i2c timing definitions parameter description f i2c i2c clock frequency t idle bus idle time between stop and start conditions t hld; str hold time for repeated start condition t set; str setup time for repeated start condition t set; stp setup time for stop condition t hld; dat hold time for data t set; dat setup time for data t low duration of scl clock low t high duration of scl clock high t rise scl/sda rise time t fall scl/sda fall time t spike voltage spike pulse width that must be suppressed by the input filter
data sheet AD9523 rev. c | page 31 of 60 spi serial port oper ation pin descriptions sclk (serial clock) is the s erial shift clock. this pin is an input. sclk is used to synchronize serial control port reads and writes. write data bits are registered on the rising edge of this clock, and read data bits are registered on the falling edge. this pin is internally pulled d own by a 4 0 k? resistor to ground. sdio (serial data input/output) is a dual - purpose pin and acts either as an input only (unidirectional mode) or as an input/ output (bidirectional mode). the AD9523 defaults to the bidirectional i/o mode . sdo (serial data out) is used only in the unidirectional i/o mode as a separate output pin for reading back data. cs (chip select bar) is an active low control that gates the read and write cycles. when cs is high, the sdo and sdio pins enter a high impedance state. this pin is internally pulled up by a 4 0 k? resistor to vdd3_ref . AD9523 serial control port cs sclk/scl sdio/sda sdo 08439-034 figure 36 . serial control port spi mode operation in spi mode, single or multiple b yte transfers are supported, as well as msb first or lsb first transfer formats. the AD9523 serial control port can be configured for a single bidirectional i/o pin (sdio only) or for two unid i rectional i/o pins (sdio/ sdo). by default, the AD9523 is in bidirectional mode. short instruction mode (8 - bit instructions) is not supported. on ly l ong (16 - bit) instruction mode is supported. a write or a read operation to the AD9523 is initiated by pulling cs low. the cs stalled high mode is supported in data transfers where three or fewer bytes of data (plus instruction data) are transferred (se e table 25 ). in this mode, the cs pin can temporarily return high on any byte boundary, allowing time for the system controller to process the next byte. cs can go high only on byte boundarie s ; however, it can go high during either phase (instruction or data) of the transfer. during this period, the serial control port state machine enters a wait state until all data is sent. if the system controller decides to abort the transfer before all o f the data is sent, the state machine must be reset either by completing the remaining transfers or by returning cs low for at least one complete sclk cycle (but fewer than eight sclk cycles). raising the cs pin on a non byte boundary terminates the serial transfer and flushes the buffer. in streaming mode (see table 25 ), any number of data bytes can be transferred in a continuous stream. the register address is automatically incremented or dec remented (see the spi msb/lsb first transfers section). cs must be raised at the end of the last byte to be transferred, thereby ending streaming mode. communication cycle instruction plus data there are two parts to a communication cycle with the AD9523. the first part writes a 16 - bit i n struction word into the AD9523, coincident with the first 16 sclk rising edges. the instruction word provides the AD9523 serial control port with information regarding the dat a transfer, which is the second part of the communication c y cle. the instruction word defines whether the upcoming data transfer is a read or a write, the number of bytes in the data tran s fer, and the starting register address for the first byte of the dat a transfer. write if the instruction word is for a write operation, the second part is the transfer of data into the serial control port buffer of the AD9523. data bits are registered on the rising edge of sclk. the length of the transfer (one, two, or th ree bytes or streaming mod e) is indicated by two bits (w1, w0) in the instruction byte. when the transfer is one, two, or three bytes but not streaming, cs can be raised after each sequence of eight bits to stall the bus (except after the last byte, where it ends the cycle) . when the bus is stalled, the serial transfer resumes when cs is lowered. raising the cs pin on a nonbyte boundary resets the serial control port. during a write, streaming mode does not skip over reserved or blank registers, and the user can write 0x00 to the reserved register addresses . because data is written into a serial control port buffer area, and not directly into the actual control registers of the AD9523, an additional opera tion is needed to transfer the serial control port buffer contents to the actual control registers of the AD9523, thereby causing them to become active. the update registers operation consists of setting the self - clearing io_u pdate bit, bit 0 of register 0 x234 (see table 57 ). any number of data bytes can be changed before executing an update registers operation . the update registers simultaneously actuates all register changes that have been written to the buffer since any previous update. read the AD9523 supports only the long instruction mode. if the instruction word is for a read operation, the next n 8 sclk cycles clock out the data from the address specified in the instruction word, where n is 1 to 3 as determined by bits[ w1 :w0 ] . if n = 4, the read operation is in streaming mode, continuing until cs is raised. during a n spi read, serial data on sdio (or sdo in the case of 4 - wire mode) transitions on the sclk falling edge, and is normally sampled on the sclk rising edge. to read the last bit correctly, the spi host must be able to tolerate a zero hold time. in cases where zero hold time is not possible, the user can either use streaming mode and delay the rising edge of cs , or sample the seri al data on the sclk falling edge. however, to sample the data correctly on the sclk falling edge, the user must ensure that the setup time is greater than t dv (time data
AD9523 data sheet rev. c | page 32 of 60 valid). streaming mode does not skip over reserved or blank registers. the default mod e of the AD9523 serial control port is the bidirectional mode. in bidirectional mode, both the sent data and the readback data appear on the sdio pin. it is also possible to set the AD9523 to unidirectional mode. in unidirectional mode, the readback data a ppears on the sdo pin. a readback request reads the data that is in the serial control port buffer area or the data that is in the active registers (see figure 37 ). serial control port buffer registers update registers active registers sclk/scl sdo sdio/sda cs 08439-035 figure 37 . relat ionship between serial control port buffer registers and active registers spi instruction word (16 bits) the msb of the instruction word is r/ w , which indicates whether the instruction is a read or a write. the next two bits ( [ w1:w0 ] ) indic a te the length of the transfer in bytes. the final 13 bits are the address ( [a12:a0] ) at which to begin the read or write operation. for a write, the instru c tion word is followed by the number of bytes o f data indicated by bits[w1:w0] ( see table 25) . table 25 . byte transfer count w1 w0 bytes to transfer 0 0 1 0 1 2 1 0 3 1 1 streaming mode bits[a12:a0] select the address within the register map that is written to or read from during the data transfer portion of the communic a tions cycle. only bits[a 11 :a0] are needed to cover the range of the 0x 23 4 re gisters used by the AD9523. bit a12 must always be 0. for mu l tibyte transfers, this address is the starting byte address. in msb fi rst mode, subsequent bytes decrement the address. spi msb/lsb first tr ansfers the AD9523 instruction word and byte data can be msb first or lsb first. any data written to register 0x000 must be mirrored: bit 7 is mirrored to bit 0, bit 6 to bit 1, bit 5 to bit 2, and bit 4 to bit 3. this makes it irrelevant whether lsb f irst or msb first is in effect. the default for the AD9523 is msb first. when lsb first is set by register 0x000, bit 1 and register 0x000 , bit 6 , it takes effect immediately because it aff ects only the operation of the serial control port and does not require that an update be executed. when msb first mode is active, the instruction and data bytes must be written from msb to lsb. multibyte data transfers in msb first format start with an i n struction byte that includes the register address of the most significant data byte. subsequent data bytes must follow in order from the high address to the low address. in msb first mode, the serial control port internal address generator decrements for each data byte of the multibyte transfer cycle. when lsb first mode is active, the instruction and data bytes must be written from lsb to msb. multibyte data transfers in lsb first format start with an i n struction byte that includes the register address of the least si g nificant data byte , followed by multiple data bytes. in a multibyte transfer cycle, the inte r nal byte address generator of the serial port increments for each byte. the AD9523 serial control port register address decrements from the registe r address just written toward 0x000 for multibyte i/o operations if the msb first mode is active (default). if the lsb first mode is a c tive, the register address of the serial control port increments from the address just written toward 0x 234 for multibyte i/o operations. unused addresses are not skipped for these operations. for multi byte accesses that cross address 0x234 or address 0x000 in msb first mode , the spi internally disable s writes to subsequent registers and return s zero s for reads to subsequent registers . s treaming mode always terminates wh en crossing address boundaries ( as shown in table 26 ). table 26 . streaming mode (no addresses are skipped) write mode address direction stop sequence msb f i rst decrement , 0x001, 0x000, stop table 27 . serial control port, 16 - bit instruction word, msb first msb lsb i15 i14 i13 i12 i11 i10 i9 i8 i7 i6 i5 i4 i3 i2 i1 i0 r/ w w1 w0 a12 = 0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0
data sheet AD9523 rev. c | page 33 of 60 t s don't care don't care w1w0a12a11a10a9a8a7a6a5d4d3d2d1d0 high-imepdance r/w t ds t dh t high t low t sclk t c cs sclk sdio 08439-138 figure 38. serial control port readmsb firs t, 16-bit instruction, one byte of data cs scl k don't care sdio a12 w0w1 r/w a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 don't care don't care don't care 16-bit instruction header register (n) data register (n ? 1) data 0 8439-038 figure 39. serial control port writemsb firs t, 16-bit instruction, two bytes of data cs scl k sdio sdo register (n) data 16-bit instruction header register (n ? 1) data register (n ? 2) data register (n ? 3) data a12 w0w1 r/w a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 don't care don't care don't care don't care d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 08439-039 figure 40. serial control port readmsb firs t, 16-bit instruction, four bytes of data t s don't care don't care w1w0a12a11a10a9a8a7a6a5d4d3d2d1d0 don't care don't care r/w t ds t dh t high t low t clk t c cs sclk sdio 08439-040 figure 41. serial control port writemsb firs t, 16-bit instruction, timing measurements data bit n ? 1 data bit n cs sclk sdio sdo t dv 08439-041 figure 42. timing diagram for serial control port register read cs scl k don't care don't care 16-bit instruction header register (n) data register (n + 1) data sdio don't care don't care a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 d1d0r/w w1 w0 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 0 8439-042 figure 43. serial control port writelsb firs t, 16-bit instruction, two bytes of data
AD9523 data sheet rev. c | page 34 of 60 cs sclk sdio t high t low t clk t s t ds t dh t c bit n bit n + 1 08439-043 figure 44. serial control port timingwrite table 28. serial control port timing parameter description t ds setup time between data and rising edge of sclk t dh hold time between data and rising edge of sclk t clk period of the clock t s setup time between the cs falling edge and sclk rising edge (start of communication cycle) t c setup time between the sclk rising edge and cs rising edge (end of communication cycle) t high minimum period that sclk should be in a logic high state t low minimum period that sclk should be in a logic low state t dv sclk to valid sdio and sdo (see figure 42)
data sheet AD9523 rev. c | page 35 of 60 eeprom operations the AD9523 contains an internal eeprom (nonvolatile memory). the eeprom can be programmed by the user to c reate and store a user - defined register setting file when the power is off. this setting file can be used for power - up and chip reset as a default setting. the eeprom size is 512 bytes. descriptions of the eeprom registers that control eeprom operation can be found in table 58 and table 59. during the data transfer process, the write and read registers are generally not available via the serial port , except for one readback bit: s tatus _eeprom (register 0xb 00 , bit 0 ) . to determine the data transfer state through the serial port in spi mode, users can read the value of the s tatus _eeprom bit (1 = data transfer in process and 0 = data transfer complete ). in i2c mode, the user can address the AD9523 slave port with the external i2c master (send an address byte to the AD9523). if the AD9523 responds with a no acknowledge bit, the data transfer was not received. if the AD9523 responds with an acknowledge bit, the data transfer process is complete . the user can mo nitor the status _eeprom bit or use register 0x232, bit 4 to program the status 0 pin to monitor t he status of the data transfer (see table 55 ). to transfer all 512 bytes to the eeprom , it takes approximately 46 ms. to transfer the contents of the eeprom to the active register , it takes approximately 40 ms. reset , a hard reset (an asynchronous hard reset is executed by briefly pulling reset low), restores the chip either to the sett ing stored in eeprom (the eeprom pin = 1) or to the on - chip setting (the eeprom pin = 0). a hard reset also executes a sync operation, which brings the outputs into phase alignment according to the default settings. when eeprom is inactive (the eeprom pin = 0), it takes ~2 s for the outputs to begin toggling after reset is issued. when eeprom is active (the eeprom pin = 1), it takes ~ 4 0 ms for the outputs to toggle after reset is brought high. writing to the eepro m the eeprom cannot be programmed directly through the serial port interface. to program the eeprom and store a register setting file, follow these steps : 1. program the AD9523 registers to the desired circuit state. if the user wants pll 2 to lock automatically aft er power - up, the calibrate vco bit (bit 1, register 0x0f3) must be set to 1. this allows vco calibration to start automatically after register loading. note that a valid input reference signal must be present during vco calibration. 2. set the io_update bit ( bit 0, register 0x234) to 1. 3. program the eeprom buffer registers, if necessary (see the programming the eeprom buffer segment section). this step is necessary only if users want to use the eeprom to control the def ault setting s of some (but not all) of the AD9523 registers, or if they want to control the register setting update sequence during power - up or chip reset. 4. set the enable eeprom write bit (bit 0, register 0xb02) to 1 to enable the eeprom. 5. set the reg2eepr om bit (bit 0, register 0xb03) to 1. this starts the process of writing data into the eeprom to create the eeprom setting file. this enables the eeprom controller to transfer the current register values, as well as the memory address and instruction bytes from the eeprom buffer segment, into the eeprom. after the write process is completed, the internal controller sets bit reg2eeprom back to 0. bit 0 of the status _e eprom register (register 0xb00) is used to indicate the data transfer status between the eepr om and the control registers (1 = data transfer in process , and 0 = data transfer complete ) . at the beginn ing of the data transfer, the status _eeprom bit is set to 1 by the eeprom controller and cleared to 0 at the end of the data tran sfer. the user can ac cess status _eeprom via the status 0 pin when the status 0 pin is programmed to monitor the status _eeprom bit . alternatively, the user can monitor the s tatus _eeprom bit directly . 6. when the data transfer is complete ( s tatus _eeprom = 0), set the enable eeprom wr ite bit (bit 0 in register 0xb02) to 1. clearing the e nable eeprom write bit to 0 disable s writing to the eeprom. to ensure that the data transfer ha s completed correctly, verify that the eeprom data error bit (bit 0 in register 0xb01) = 0. a value of 1 in this bit indicates a data transfer error. reading from the eep rom the following reset - related events can start the process of restoring the settings stored in the eeprom to the control registers. when the eeprom _sel pin is set high, do any of the followin g to in i tiate a n eeprom read : ? power up the AD9523 . ? perform a h ardware chip reset by pulling the reset pin low and then releasing reset . ? set the self - clearing soft reset bit (bit 5 , register 0x000) to 1. when the eeprom _s el pin is set low, set the self - clearing soft_eeprom bit (bit 1, register 0xb02) to 1. the AD9523 then starts to read the eeprom and lo ads the values into the AD9523 registers . if the eeprom _sel pin is low during reset or power - up, the eeprom is not active , and the AD9523 default values are loaded instead. when using the eeprom to automatically load the AD9523 register values and lock the pll, the calibrate vco bit (bit 1, register 0x0f3) must be set to 1 when the register values are written to the eeprom. this allows vco calibration to start automatically after register loading. a valid input reference signal must be present during vco calibration.
AD9523 data sheet rev. c | page 36 of 60 to ensure that the data transfer ha s completed correctly, verify that the eeprom data error b it (bit 0 in regi ster 0xb01) is set to 0 . a value of 1 in this bit indicates a data transfer error. programming the eepr om buffer segment the eeprom buffer segment is a register space that allows the user to specify which groups of registers are stored to the eeprom during eeprom programming. normally, this segment does not need to be programmed by the user. instead, the default power - up values for the eeprom buffer segment allow the user to store all of the register values from register 0x000 to register 0x23 4 to the eepro m. for example, if the user want s to load only the output driver set - tings from the eeprom without disturbing the pll register settings currently stored in the eeprom , the eeprom buffer segment can be modified to include only the registers that apply to t he output drivers and exclude the registers that apply to the pll configuration. there are two parts to the eeprom buffer segment: register section definition groups and operational codes. each register section definition group contains the starting addres s and number of bytes to be written to the eeprom. if the AD9523 register map were continuous from address 0x000 to address 0x23 4 , only one register section definition group would consist of a starting addres s of 0x000 and a length of 563 bytes. however, this is not the case. the AD9523 register map is noncontiguous, and the eeprom is only 512 bytes long. therefore, the register section definition group tells the eeprom controller how the AD9523 register map is segmented. there are three operational code s: io_update, end - of - data, and pseudo - end - of - data. it is important that the eeprom buffer segment always have either an end - of - data or a pseudo - end - of - data operat ional code and that an io_update operation code appear at least once before the end - of - data op er ational code. register section definition group the register section definition group is used to define a continuous register section for the eeprom profile. it consists of three bytes. the first byte defines how many continuous register bytes are in this group. if the user puts 0x000 in the first byte, it means there is only one byte in this group. if the user puts 0x001, it means there are two bytes in this group. the maximum number of registers in one group is 128. the next two bytes are the high byte a nd low b yte of the memory address (16 bit s ) of the first register in this group. io_u pdate (operational code 0x80) the eeprom controller uses this operational code to generate an io_u pdate signal to update the active control register bank from the buffer register bank during the download process. at a minimum, there should be at least one io_u pdate operational code after the end of the final register section definition group. this is needed so that at least one io_u pdate occurs after all of the AD9523 reg isters are loaded when the eeprom is read. if this operational code is absent during a write to the eeprom, the register values loaded from the eeprom are not transferred to the active register space, and these values do not take effect after they are load ed from the eeprom to the AD9523. end - of - data (operational code 0xff) the eeprom controller uses this operational code to terminate the data transfer process between eeprom and the control register during the upload and download process. the last item app earing in the eeprom buffer segment should be either this operational code or the pseudo - end - of - data operational code. pseudo - end - of - data (operational code 0xfe) the AD9523 eeprom buffer segment has 23 bytes that can contain up to seven register section d efinition groups. if users want to define more than seven register section definition groups, the pseudo - end - of - data operational code can be used. during the upload process, when the eeprom controller receives the pseudo - end - of - data operational code, it ha lts the data transfer process, clears the reg2eeprom bit ( bit 0, register 0xb03) , and enables the AD9523 serial port. users can then program the eeprom buffer segment again and reinitiate the data transfer process by setting the reg2eeprom bit to 1 and the io_update bit ( bit 0, register 0x23 4 ) to 1. the internal i2c master then begins writing to the eeprom , starting from the eeprom address held from the last writing. this sequence enables more discrete instructions to be written to the eeprom than would ot herwise be possible due to the limited size of the eeprom buffer segment. it also permits the user to write to the same register multiple times with a different value each time.
data sheet AD9523 rev. c | page 37 of 60 table 29. example of an eeprom buffer segment reg iste r addr ess (hex) bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) start eeprom buffer segment 0xa00 0 number of bytes of the first group of registers (bits [6:0] ) 0xa01 address of the first group of registers (bits [15:8] ) 0xa02 address of the first group of registers (bits [7:0] ) 0xa03 0 number of bytes of the second group of registers (bits [6:0] ) 0xa04 address of the second group of registers (bits [15:8] ) 0xa05 address of the second group of registers (bits [7:0] ) 0xa06 0 number of bytes of the third group of registers (bits [6:0] ) 0xa07 address of the third group of registers (bits [15:8] ) 0xa08 address of the third group of registers (bits [7:0] ) 0xa09 io_u pdate operational code (0x80) 0xa0a end - of - data operational code (0xff)
AD9523 data sheet rev. c | page 38 of 60 power diss ipation and thermal considerations the AD9523 is a multifunctional, high speed device that targets a wide variety of clock applications. the numerous innovative features contained in the device each consume incremental power. if all outputs are enabled in the maximum frequency and mode that have the highest power , the safe thermal operating conditions of the device may be exceeded. careful analysis and consideration of power dissi pation and thermal management are critical element s in the successful applica tion of the AD9523 device. the AD9523 device is specified to operate within the industrial temperature range of C 40 c to +85 c. this specification is conditional, however, such that the absolute maximum junction temperature is not exceeded (as specified in table 17.) . at high operating tem peratures, extreme care must be taken when operating the device to avoid exceeding the junction temperature and potentially damaging the device. a maximum junction temperature is listed in table 1 wit h the ambient operating range. the ambient range and max imum junction t emperature specifications ensure the per form ance of the device, as guaranteed in the specification s section . many variables contribute to the operating junction temperature within the device, including ? selected driver mode of operation ? output clock speed ? supply voltage ? ambient temperature the combination of these variables determines the junction temp erature within the AD9523 device for a given set of operating conditions. the AD9523 is specified for an ambient temperature ( t a ). to ensure that t a is not exceeded, an airflow source can be used. use the following equation to determine the junction tempe rature on the application pcb: t j = t case + ( jt pd ) where: t j is the junction temperature (c). t case is the case temperature (c) measured by the user at the top center of the package. jt is the value from table 18. pd is the power dissipation of the AD9523. value s of ja are provided for package comparison and pcb design considerations. ja can be used for a first - order approximation of t j by the equation t j = t a + ( ja pd ) where t a is the ambient temperature (c). value s of jc are provided for package compariso n and pcb design considerations when an external heat sink is required. value s of jb are provided for package comparison and pcb design considerations. clock speed and driver mode clock speed directly and linearly influences the total power dissipation o f the device and , therefore , the junction temperature. two operating frequencies are listed under the incremental power dissipation parameter in table 3 . using linear interpretation is a sufficient approximation fo r frequency not listed in the table. when calculating power dissipation for thermal consideration, the amount of power dissipated in the 100 ? resistor should be removed. if using the data in table 2 , this power is already removed. if using the current vs. frequency graphs provided in the typical performance characteristics sec tion, the power into the load must be subtracted, using the following equation: ? 100 2 swing voltage output al differenti evaluation of operat ing conditions the first step in evaluating the operating conditions is to determine the maximum power consumption (pd) internal to the AD9523 . the maximum pd excludes power dissipated in the load resistors of the drivers because such power is external to the device. use the power dissipation specifications listed in table 3 to calculate the total power dissip ated for the desired configuration. the base typical configuration parameter in table 3 lists a power of 4 28 mw, which includes one lvpecl output at 122.88 mhz. if the frequency of operation is not listed in table 3 , see the typical performance characteristics section, current vs. frequency and driver mode to calculate the power dissipation ; then add 20% for maximum current draw . remove the power dissipated in the load resistor to achieve the most accurate power dissipation internal to the AD9523. see table 30 for a summary of the incremental power dissipation from the base power configuration for two different examples. table 30 . temperature gradient examples description mode frequency (mhz) maximum power (mw) example 1 base typical configuration 4 28 output driver 6 lvpecl 122.88 3 30 output driver 6 lvds 245.76 1 10 total power 868 example 2 base typica l configuration 428 output driver 1 3 lvpecl 983.04 2066 total power 2500
data sheet AD9523 rev. c | page 39 of 60 the second step is to multiply the power dissipated by the thermal impedance to determine the maximum power gradient. for this example, a thermal impedance of ja = 20.1 c/ w was used. example 1 ( 868 mw 20.1 c/w ) = 1 7 .4c w ith a n ambient tem pe rature of 85c , the junction temperature is t j = 85c + 1 7 .4 c = 10 2 c this junction temperature is below the maximum allowable. example 2 (2500 mw 20.1c/w) = 50.2c with an ambient tem pe rature of 85c , the junction temperature is t j = 85c + 50 c = 1 35c this junction temperature is above the maximum allowable. to operate in the condition of example 2, t he ambient temperature must be lowered to 65c . thermally enhanced p ackage moun ting guidelines refer to the an - 772 application note , a design and manufacturing guide for the lead frame chip scale package (lfcsp) , for more information about mounting devices with an exposed paddle.
AD9523 data sheet rev. c | page 40 of 60 contro l register s control register map register addresses that are not listed in table 31 are not used, and writing to those registers has no effect. registers that are marked as reserved should never have their values changed. when wr iting to registers with bits that are marked reserved, the user should take care to always write the default value for the reserved bits. table 31. control register map addr (hex) register name (msb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 (lsb) bit 0 default value (hex) serial port configuration 0x 000 spi mode serial port configuration sdo a ctive lsb first/ address increment soft r eset reserved reserved soft r eset lsb f irst / address increment sdo a ctive 0x 00 i 2 c mode ser ial port configuration reserved reserved soft r eset reserved reserved soft r eset reserved reserved 0x 00 0x 004 readback c ontrol reserved reserved reserved reserved reserved reserved reserved read back active registers 0x 00 0x 005 eepr om customer v ersion id eeprom customer version id[7:0] (lsb) 0x 00 0x 006 eeprom customer version id[15:8] (msb) 0x 00 input pll (pll1) 0x 010 pll1 ref a r d ivider control 10 - bit refa r divider[7:0] (lsb) 0x 00 0x 011 reserved 10 - bit refa r divider[9:8] (msb) 0x 00 0x 012 pll1 ref b r d ivider control 10 - bit refb r divider[7:0] (lsb) 0x 00 0x 013 reserved 10 - bit refb r divider[9:8] (msb) 0x 00 0x 014 pll1 reference test d ivider reserved reserved ref_test d ivider 0x 00 0x 015 pll1 r eserved reserved reserved reserved reserved reserved reserved reserved reserved 0x 00 0x 016 pll1 feedback n d ivider control 10 - bit pll1 feedback divider[7:0] (lsb) 0x 00 0x 017 reserved 10- bit pll1 feedback divider[9:8] (msb) 0x 00 0x 018 pll1 charge p ump control pll1 charge pump t ristate pll1 c har ge pump c ontrol 0x 0c 0x 019 reserved reserved reserved enable spi control of antibacklash pulse width antibacklash pulse width control p ll1 charge pump mode 0x 00 0x 01a pll1 i nput r eceiver control ref_test input receiver e nable refb differential receiver e nable r efa differential receiver e nable refb receiver e nable refa receiver e nable i nput refa, refb receiver power - down control enable osc_in single - ended r eceiver mode enable (cmos mode) osc_in diff erential r ece iv er mode enable 0x 00 0x 01b ref_t est, refa, refb, and zd_in control reserved reserved z ero delay mode osc_in signal feedback for pll1 zd_in single - ended receiver mode enable (cmos mode) zd _in diff eren . receiver m ode enable refb single - ended receiver mod e e nable (cmos mode) refa single - ended receiver mode e nable (cmos mode) 0x 00 0x 01c pll1 miscellaneous control enable refb r divider ind epen. division c ontrol osc_ctrl control voltage to vcc/2 when ref clock fai ls reserved reference selec tion mode reserved reserved 0x 00
data sheet AD9523 rev. c | page 41 of 60 addr (hex) register name (msb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 (lsb) bit 0 default value (hex) 0x 01d pll1 loop filter zero resistor control reserved reserved reserved reserved pll1 loop filter , r zero 0x 00 output pll (pll2) 0x 0f0 pll2 charge p ump control pll2 charge pump contro l 0x 00 0x 0f1 pll2 feedback n d ivide r control a counter b counte r 0x 04 0x 0f2 pll 2 c ontrol pll 2 lock d etector power - d own reserved enable freq uency d oubler enable spi control of a nti backlash p ulse width antibacklash pulse width control pll 2 charge pump mode 0x 03 0x 0f3 vco c ontrol reserve d reserve d reserve d force release of distribution sync when pll2 is unlocked treat ref erence as valid force vco to m idp oint freq uency calibrate vco (not auto - clearing) reserved 0x 00 0x 0f4 vco divider control reserve d reserve d reserve d reserve d vco d ivider power - down vco divider 0x00 0x 0f5 pll2 loop filter c ontrol pole 2 resistor (r pole2 ) zero resistor (r zero ) pole 1 capacitor (c pole1 ) 0x 00 0x 0f6 (9 bits) reserve d reserve d reserve d reserve d reserve d reserve d reserved bypass internal r zero resistor 0x 00 0x 0f9 reserved reserve d reserve d reserve d reserve d reserve d reserve d reserve d reserved 0x 00 clock distribution 0x 190 channel 0 control invert divider o utput ignore sync power - down c hannel lower power mode driver mode 0x 00 0x 191 10 - bit channel divider [ 7:0 ] (lsb) 0x 1f 0x 192 divider phase[5:0] 10- bit channel divider[9:8] (msb) 0x 04 0x 193 channel 1 control invert divider o utput ignore sync power - down c hannel lower power mode driver mode 0x 20 0x 194 10 - bit channel divider[ 7:0 ] (lsb) 0x 1f 0x 195 divide r phase[5:0] 10- bit channel divider[9:8] (msb) 0x 04 0x 196 channel 2 control invert divider o utput ignore sync power - down c hannel lower power mode driver mode 0x 00 0x 197 10 - bit channel divider[ 7:0 ] (lsb) 0x 1f 0x 198 divider phase[5:0] 10- bit channel div ider[9:8] (msb) 0x 04 0x 199 channel 3 control invert divider o utput ignore sync power - down c hannel lower power mode driver mode 0x 20 0x 19a 10 - bit channel divider[ 7:0 ] (lsb) 0x 1f 0x 19b divider phase[5:0] 10 - bit channel divider[9:8] (msb) 0x 04 0x 19c cha nnel 4 control invert divider o utput ignore sync power - down c hannel lower power mode driver mode 0x 00 0x 19d 10 - bit channel divider[ 7:0 ] (lsb) 0x 1f 0x 19e divider phase[5:0] 10- bit channel divider[9:8] (msb) 0x 04 0x 19f channel 5 control invert divider o utput ignore sync power - down c hannel lower power mode driver mode 0x 20 0x 1a0 10 - bit channel divider[ 7:0 ] (lsb) 0x 1f 0x 1a1 divider phase[5:0] 10- bit channel divider[9:8] (msb) 0x 04
AD9523 data sheet rev. c | page 42 of 60 addr (hex) register name (msb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 (lsb) bit 0 default value (hex) 0x 1a2 channel 6 control invert divider o utput ignore sync power - down ch annel lower power mode driver mode 0x 00 0x 1a3 10 - bit channel divider[ 7:0 ] (lsb) 0x 1f 0x 1a4 divider phase[5:0] 10 - bit channel divider[9:8] (msb) 0x 04 0x 1a5 channel 7 control invert divider o utput ignore sync power - down c hannel lower power mode driver mode 0x 20 0x 1a6 10 - bit channel divider[ 7:0 ] (lsb) 0x 1f 0x 1a7 divider phase[5:0] 10- bit channel divider[9:8] (msb) 0x 04 0x 1a8 channel 8 control invert divider o utput ignore sync power - down c hannel lower power mode driver mode 0x 00 0x 1a9 10 - bit channe l divider[ 7:0 ] (lsb) 0x 1f 0x 1aa divider phase[5:0] 10- bit channel divider[9:8] (msb) 0x 04 0x 1ab channel 9 control invert divider o utput ignore sync power - down c hannel lower power mode driver mode 0x 20 0x 1ac 10 - bit channel divider[ 7:0 ] (lsb) 0x 1f 0x 1a d divider phase[5:0] 10- bit channel divider[9:8] (msb) 0x 04 0x 1ae channel 10 control invert divider o utput ignore sync power - down c hannel lower power mode driver mode 0x 00 0x 1af 10 - bit channel divider[ 7:0 ] (lsb) 0x 1f 0x 1b0 divider phase[5:0] 10- bit c hannel divider[9:8] (msb) 0x 04 0x 1b1 channel 11 control invert divider o utput ignore sync power - down c hannel lower power mode driver mode 0x 20 0x 1b2 10 - bit channel divider[ 7:0 ] (lsb) 0x 1f 0x 1b3 divider phase[5:0] 10- bit channel divider[9:8] (msb) 0x 04 0x 1b4 channel 12 control invert divider o utput ignore sync power - down c hannel lower power mode driver mode 0x 00 0x 1b5 10 - bit channel divider[ 7:0 ] (lsb) 0x 1f 0x 1b6 divider phase[ 5:0 ] 10- bit channel divider[9:8] (msb) 0x 04 0x 1b7 channel 13 control inv ert divider o utput ignore sync power - down c hannel lower power mode driver mode 0x 20 0x 1b8 10 - bit channel divider[ 7:0 ] (lsb) 0x 1f 0x 1b9 divider phase[5:0] 10- bit channel divider[9:8] (msb) 0x 04 0x 1ba pll 1 output control reserve d reserve d reserve d pll1 output cmos driver strength out pll1 output 0x 00 0x 1bb pll1 output channel control pll1 output driver p ower - down reserve d reserve d reserve d route vcxo clock to ch 3 divider input route vcxo clock to ch 2 divider input route vcxo clock to ch 1 divider in put route vcxo clock to ch 0 divider input 0x 80 readback 0x 22c readback 0 status pll2 reference clock status pll 1 feedback c lock status vcxo status ref_ test s tatus refb status ref a lock d etect pll2 lock d etect pll1 0x 22d readback 1 reserved reserv ed reserved reserved holdover a ctive selected r eference (in auto mode) reserved vco cal ibration in progress 0x 22e readback 2 reserved reserved reserved reserved reserved reserved reserved reserved 0x 22f readback 3 reserved reserved reserved reserved reserved reserved reserved reserved
data sheet AD9523 rev. c | page 43 of 60 addr (hex) register name (msb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 (lsb) bit 0 default value (hex) o ther 0x 230 st atus s ignals reserved reserved status monitor 0 control 0x 00 0x 231 reserved reserved status monitor 1 control 0x 00 0x 232 reserved reserved reserved e nable s tatus _ eeprom on status 0 pin status1 pin divider enable status0 pin divider enable reserved sync dividers (manual control) 0: sync signal inactive 1: d ividers held in sync (same a s sync pin low) 0x 00 0x 233 power - down control reserved reserved reserved reserved reserved pll1 po wer - down pll 2 power - down dist ribution power - down 0x 07 0x 234 update all registers reserved io_u pdate 0x 00 eeprom buffer 0x a00 eeprom buffer segment register 1 to eeprom buffer segment register 3 i nstruction (data )[ 7:0 ] (serial port configuration registe r ) 0x 00 0x a01 h igh byte of register address (serial port configuration register ) 0x 00 0x a02 l ow byte of register address (serial port configuration register ) 0x 00 0x a03 eeprom buffer segment register 4 to eeprom buffer segment register 6 i nstruction ( data )[ 7:0 ] (r eaback control register ) 0x 02 0x a04 h igh byte of register address (r eaback control register ) 0x 00 0x a05 l ow byte of register address (r eaback control register ) 0x 04 0x a06 eeprom buffer segment register 7 to eeprom buffer segment register 9 i nstruction (data )[ 7:0 ] (pll segment) 0x 0e 0x a07 h igh byte of register address (pll segment) 0x 00 0x a08 l ow byte of register address (pll segment) 0x 10 0x a09 eeprom buffer segment register 10 to eeprom buffer segment register 12 instruction (data)[ 7 :0 ] (pecl/cmos o utput segment) 0x 0e 0x a0a h igh byte of register address (pecl/cmos o utput segment) 0x 00 0x a0b l ow byte of register address (pecl/cmos o utput segment) 0x f0 0x a0c eeprom buffer segment register 13 to eeprom buffer segment register 15 ins truction (data)[ 7:0 ] (d ivider s egment) 0x 2b 0x a0d h igh byte of register address (d ivider s egment) 0x 01 0x a0e l ow byte of register address (d ivider s egment) 0x 90 0x a0f eeprom buffer segment register 16 to eeprom buffer segment register 18 i nstruction ( data )[ 7:0 ] (clock input and ref s egment) 0x 01 0x a10 h igh byte of register address (clock input and ref s egment) 0x 01 0x a11 l ow byte of register address (clock input and ref s egment) 0x e0 0x a12 eeprom buffer segment register 19 to eeprom buffer segment register 21 instruction (data)[ 7:0 ] (other s egment) 0x 03 0x a13 h igh byte of register address (other s egment) 0x 02 0x a14 l ow byte of register address (other s egment) 0x 30 0x a15 eeprom buffer segment register 22 i /o u pdate 0x 80
AD9523 data sheet rev. c | page 44 of 60 addr (hex) register name (msb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 (lsb) bit 0 default value (hex) 0x a16 eeprom buffer seg ment register 23 end of d ata 0x ff eeprom c ontrol 0x b00 status_ eeprom (read only) reserved reserved reserved reserved reserved reserved reserved status_ eeprom (read only) 0x 00 0x b01 e eprom error checking readback (read only) reserved reserved reserve d reserved reserved reserved reserved e eprom data e rro r (read only) 0x 00 0x b02 eeprom control 1 reserved reserved reserved reserved reserved reserved soft_eeprom enable eeprom write 0x 00 0x b03 eeprom control 2 reserved reserved reserved reserved reserved reserved reserved reg2eeprom 0x 00
data sheet AD9523 rev. c | page 45 of 60 control register map bit description s serial port configuration (address 0 x000 to address 0 x006 ) table 32 . spi mode serial port configuration address bits bit name description 0x000 7 sdo active selects unidirectional or bidirectional data transfer mode. this bit is ignored in i 2 c mode. 0: sdio pin used for write and read; sdo is high impedance (default). 1: sdo used for read; sdio used for write; unidirectional mode. 6 lsb first/ addr ess incr e ment spi msb or lsb data orientation. this bit is ignored in i 2 c mode. 0: data - oriented msb first; addressing decrements (default). 1: data - oriented lsb first; addressing increments. 5 soft reset soft reset. 1 (self clearing): soft reset; restores defaul t values to internal registers. 4 reserved reserved. [3:0] mirror[7:4] bits[3:0] should always mirror bits[7:4] so that it does not matter whether the part is in msb first or lsb first mode (see register 0x000, bit 6). set bits as follows: bit 0 = bit 7. bit 1 = bit 6. bit 2 = bit 5. bit 3 = bit 4. 0x004 0 read back active registers for buffered registers, serial port re ad back r eads from actual (active) registers instead of from the buffer. 0 (default): reads valu es currently applied to the internal logic of the device. 1: reads buffered values that take effect on the next assertion of the i/o update. table 33. i 2 c mode serial port config uration address bits bit name description 0x000 [7 :6 ] reserved reserved. 5 soft reset soft reset. 1 (self clearing): s oft reset; restores default values to internal registers. 4 reserved reserved. [3:0] mirror[7:4] bits[3:0] should always mirror bits[7:4]. set bits as follows: bit 0 = bit 7. bit 1 = bit 6. bit 2 = bit 5. bit 3 = bit 4. 0x004 0 read back active registers for buffered registers, serial port re ad back r eads from actual (active) registers instead of from the buffer. 0 (default): reads valu es currently applied to the internal logic of the device. 1: reads buffered values that take effect on the next assertion of the i/o update. table 34 . eeprom customer version id address bits bit name description 0 x 005 [7:0] eeprom customer version id (lsb) 16- bit eeprom id, bits[7:0]. this register, along with regi ster 0x006, allows the user to store a unique id to identify which version of the AD9523 register settings is stored in the eeprom. it does not affect AD9523 operation in any way (default: 0x00). 0 x 006 [7:0] eeprom customer version id (msb) 16- bit eeprom id, bits[15:8]. this register, along with register 0x005, allows the user to store a unique id to identify which version of the AD9523 register settings is stored in the eeprom. it does not affect AD9523 operation in any way (default: 0x00).
AD9523 data sheet rev. c | page 46 of 60 input pll (p ll1) (address 0x010 to address 0x01d ) table 35 . pll1 refa r divider control address bits bit name description 0x010 [7:0] refa r divider 10- bit refa r divider, bits[7:0] (lsb) . divide -by - 1 to divide -by - 1023. 00000000, 00000001: di vide -by -1. 0x011 [1:0] 10- bit refa r divider, bits[9:8] (msb) table 36 . pll1 refb r divider control 1 address bits bit name description 0x012 [7:0] refb r divider 10- bit refb r divider , bits[ 7:0 ] (lsb) . divide -by - 1 to divide -by -1 023. 00000000, 00000001: divide -by -1. 0x013 [1:0] 10- bit refb r divider , b its [9:8] (msb) 1 requires re gister 0x01c, bit 7 = 1 for division that is independent of refa division. table 37. pll1 reference test divider address bits bit name description 0x0 14 [7:6] reserved reserved [5:0] ref_ test d ivider 6 - bit r ef e rence t est divider . divide -by - 1 to divide -by - 63. 000000, 000001: divide -by -1. table 38. pll1 reserved address bits bit name description 0x015 [7:0] reserved reserved table 39 . pll1 feedback n divider cont rol address bits bit name description 0x016 [7:0] pll1 feedback n divider control (n_pll1) 10- bit feedback divider , bits[ 7:0 ] (lsb) . divide -by - 1 to divide -by - 1023. 00000000, 00000001: divide -by -1. 0x017 [1:0] 10- bit feedback divider , b its [1:0] (msb) t able 40 . pll1 charge pump control address bits bit name description 0x018 7 pll1 charge pump tristate tristates the pll1 charge pump. [6:0] pll1 charge pump control these bits set the magnitude of the pll 1 charge pump current. gr anularity is ~0 .5 a with a full - scale magnitude of ~63.5 a. 0x019 [7:5] reserved reserved. 4 enable spi control of antibacklash pulse width controls the functionality of register 0x019, bits[3:2]. 0 (default): the device automatically controls the antibacklash perio d. 1: antibacklash period defined by register 0x019, bits[3:2]. [3:2] antibacklash pulse width control controls the pfd antibacklash period. 00 (default): minimum. 01: low. 10: high. 11: maximum. these bits are ineffective unless register 0x019, bit 4 = 1. [1:0] pll1 charge pump mode controls the mode of the pll1 charge pump. 00 ( default ) : tristate . 01: pump up. 10: pump down. 11: normal.
data sheet AD9523 rev. c | page 47 of 60 table 41 . pll1 input receiver control address bits bit name description 0x01a 7 ref_test input receiver enable 1: enabled. 0: disabled (default). 6 refb differential receiver enable 1: differential receiver mode. 0: single - ended receiver mode (also depends on register 0x01b, bit 1) (default). 5 refa differential receiver enable 1: differen tial receiver mode. 0: single - ended receiver mode (also depends on register 0x01b, bit 0) (default). 4 refb receiver enable refb receiver power - down control mode only when bit 2 = 1. 1: e nable refb receiver. 0: power - down (default) . 3 refa receiver ena ble refa receiver power - down control mode only when bit 2 = 1. 1: e nable refa receiver. 0: power - down (default) . 2 input refa and refb receiver power - down control enable enables power - down control of the input receivers, refa and refb. 1: power - down cont rol enabled. 0: both receivers enabled (default). 1 osc_in single - ended receiver mode enable (cmos mode) selects which single - ended input pin is enabled when in the single - ended receiver mode (register 0x01a, bit 0 = 0). 1: negative rec eiver from oscillator input ( osc_in pin) selected. 0: positive receiver from oscillator input (osc_in pin) selected (default). 0 osc_in differential receiver mode enable 1: differential receiver mode. 0: single - ended receiver mode (als o depends on bit 1) (default). table 42 . ref_test, refa, refb, and zd_in control address bits bit name description 0x01b [ 7 :6] reserved 0: r eserved (default) . 5 zero delay m ode selects the zero delay mode used (via the zd_in pi n) when register 0x01b, bit 4 = 0. otherwise, this bit is ignored. 1: internal zero delay mode. the zero delay receiver is powered down. the internal zero delay path from distribution divider channel 0 is used. 0: external zero delay mode. the zd_in receiv er is enabled. 4 osc_in signal f eedback for pll1 controls the input pll feedback path, local feedback f rom the osc_in receiver or zero delay mode. 1: osc_in receiver input used for the input pll feedback (non - zero delay mode). 0: zero delay mode enabled (also depends on register 0x01b, bit 5 to select the zero delay path. 3 zd_in single - ended receiver mode enable (cmos mode) selects which single - ended input pin is enabled when in the single - ended receiver mode (register 0x01b, bit 2 = 0). 1: zd_in pin enabled. 0: zd_in pin enabled. 2 zd _in diff erential receiver mode e nable 1: differential receiver mode. 0: single - ended receiver mode (also depends on register 0x01b, bit 3). 1 refb single - ended rece iver mode enable (cmos mode) selects which single - ended input pin is enabled when in single - ended receiver mode (register 0x01a, bit 6 = 0). 1: refb pin enabled. 0: refb pin enabled. 0 refa single - ended receiver mode e nable (cmos mode) selects which single - ended input pin is enabled when in single - ended receiver mode (register 0x01a, bit 5 = 0). 1: refa pin enabled. 0: refa pin enabled.
AD9523 data sheet rev. c | page 48 of 60 table 43. pll1 miscellaneous control addr ess bits bit name description 0x01c 7 enable refb r divider independent division control 1: refb r divider is controlled by register 0x012 and register 0x013. 0: refb r divider is set to the same setting as the refa r divider (register 0x010 and register 0x011). this requires that, for the loop to stay locked, the refa and refb input frequencies must be the same. 6 osc_ctrl control voltage to vcc/2 when reference clock fails high permits the osc_ctrl cont rol voltage to be forced to mid supply when the fee dback or input clocks fail. low t ristates the charge pump output. 1: osc_ctrl control voltage goes to vcc/2. 0: osc_ctrl control voltage tracks the tristated (high impedance) charge pump (through the buffer). 5 reserved reserved. [4:2] reference select ion mode programs the refa, refb mode selection (default = 000). ref_sel pin bit 4 bit 3 bit 2 description x 1 0 0 0 nonrevertive: stay on refb. x 1 0 0 1 revert to refa. x 1 0 1 0 select refa. x 1 0 1 1 select refb. 0 1 x 1 x 1 ref_sel pin = 0 (low): refa. 1 1 x 1 x 1 ref_sel pin = 1 (high): refb. [ 1 :0] reserved 0: r eserved (default). 1 x = dont care. table 44. pll1 loop filter zero resistor control address bits bit name description 0x01d [7: 4 ] reserved reserved. [3:0] pll1 loop filter, r zero pro grams the value of the zero resistor, r zero . bit 3 bit 2 bit 1 bit 0 r zero value (k?) 0 0 0 0 883 0 0 0 1 677 0 0 1 0 341 0 0 1 1 135 0 1 0 0 10 0 1 0 1 10 0 1 1 0 10 0 1 1 1 10 1 0 0 0 use external resistor
data sheet AD9523 rev. c | page 49 of 60 outpu t pll (pll2) (address 0x0f0 to address 0x0f6 ) table 45 . pll2 charge pump control table 46 . pll2 feedback n divider control table 47. pll2 control address bits bit name description 0x0f2 7 pll2 lock detector power - down controls power - down of the pll2 lock detector. 1: lock detector powered down. 0: lock detector active. 6 reserved default = 0; value must remain 0. 5 enable frequenc y doubler enables doubling of the pll2 reference input frequency. 1: enabled. 0: disabled. 4 enable spi control of antibacklash pulse width controls the functionality of register 0x0f2, bits[3:2]. set the antibacklash pulse width to the minimum setting. by s et ting bit 4 to 1 from the default of 0 , bits[3:2] consequently default to 00. 0 (default): device automatically controls the antibacklash period to high (equivalent to register 0x0f2, bits[3:2] = 10). 1: antibacklash period defined by register 0x0f2, bits[ 3 : 2 ] (r ecommended setting ) . [3:2] antibacklash pulse width control controls the pfd antibacklash period of pll2. 00 (default): minimum (r ecommended setting ) . 01: low. 10: high. 11: maximum. these bits are ineffective unless register 0x0f2, bit 4 = 1 . [1:0] pll2 charge pump mode controls t he mode of the pll2 charge pump. 00: tristate. 01: pump up. 10: pump down. 11 (default): normal. table 48 . vco control address bits bit name description 0x0f3 [7:5] reserved reserved. 4 force release of distribution sync when pll2 is unlocked 0 (default): distribution is held in sync (static) until the output pll locks. then it is automatically released from sync with all dividers synchronized. 1: overrides the pll2 lock detector state; force s release of the distribution from sync. 3 treat reference as valid 0 (default): uses the pll1 vcxo indicator to determine when the reference clock to the pll2 is valid. 1: treats the reference clock as valid even if pll1 does not consider it to be valid. 2 force vco to midpoint frequency selects vco control voltage functionality. 0 (default): normal vco operation. 1: forces vco control voltage to midscale. address bits bit name description 0x0f0 [7:0] pll2 charge pump control these bits set the magnitude of the pll2 charge pump current. granularity is ~3 .5 a with a full - scale magnitude of ~900 a. address bits bit name description 0x0f1 [7:6] a counter a counter word . [5:0] b counter b counter word . feedback divider constraints a counter (bits[7:6]) b counter (bits[5:0]) allowed n division (4 b + a) a = 0 or a = 1 b = 4 16, 17 a = 0 to a = 2 b = 5 20, 21, 22 a = 0 to a = 2 b = 6 24, 25, 26 a = 0 to a = 3 b 7 28, 29 continuous to 255
AD9523 data sheet rev. c | page 50 of 60 address bits bit name description 1 calibrate vco (not autoclearing) 1: initiates vco calibration (this is not an autoclear ing bit). 0: resets the vco calibration. 0 reserved reserved. table 49 . vco divider control address bits bit name description 0x0f4 [7:4] reserved reserved. 3 vco divider power - down 1: powers down the divider. 0: normal operat ion. [2:0] vco divider note that the vco divider connects to all output channels. bit 2 bit 1 bit 0 divider value 0 0 0 divide -by -4 0 0 1 divide -by -5 0 1 0 divide -by -6 0 1 1 divide -by -7 1 0 0 divide -by -8 1 0 1 divide -by -9 1 1 0 divide -by -10 1 1 1 divide - by - 11 table 50 . pll2 loop filter control address bits bit name description 0x0f5 [7:6] pole 2 resistor (r pole2 ) bit 7 bit 6 r pole2 (?) 0 0 900 0 1 450 1 0 300 1 1 225 [5 :3] zero resistor (r zero ) bit 5 bit 4 bit 3 r zero ( ? ) 0 0 0 3250 0 0 1 2750 0 1 0 2250 0 1 1 2100 1 0 0 3000 1 0 1 2500 1 1 0 2000 1 1 1 1850 [2:0] pole 1 capacitor (c pole1 ) bit 2 bit 1 bit 0 c pole1 (pf) 0 0 0 0 0 0 1 8 0 1 0 16 0 1 1 24 1 0 0 24 1 0 1 32 1 1 0 40 1 1 1 48 0x0f6 [7:1] reserved reserved. 0 bypass internal r zero resistor bypasses the internal r zero resistor (r zero = 0 ? ). requires the use of a series external zero resistor . this bit is the msb of the loop filter control r egister (address 0x0f5 and address 0x0f6) .
data sheet AD9523 rev. c | page 51 of 6 0 clock distribution (register 0x190 to register 0x1b9 ) table 51 . channel 0 to channel 13 control (this same map applies to all 14 channels ) address bits bit name description 0x190 7 invert divider o utput inverts the polarity of the dividers output clock. 6 ignore sync 0: obey s chip - level sync signal (default). 1: ignore s chip - level sync signal. 5 power - down channel 1: power s down the entire channel. 0: normal operation. 4 lower power mode (differential modes only) reduces power used in the differential output modes (lvds/lvpecl/hstl). this reduction may result in power savings, but at the expense of performance. note that this bit d oes not affect output swing and current, just the internal driver power. 1: low strength/lower power. 0: normal operation. [3:0] driver mode driver m ode . bit 3 bit 2 bit 1 bit 0 driver mode 0 0 0 0 tristate output 0 0 0 1 lvpecl (8 ma) 0 0 1 0 lvds (3.5 ma) 0 0 1 1 lvds (7 ma) 0 1 0 0 hstl - 0 (16 ma) 0 1 0 1 hstl - 1 (8 ma) 0 1 1 0 cmos (both outputs in phase) + pin: true phase relative to divider output ? pin: true phase relative to divider output 0 1 1 1 cmos (opposite p hases on outputs) + pin: true phase relative to divider output ? pin: complement phase relative to divider output 1 0 0 0 cmos + pin: true phase relative to divide r output ? pin: high -z 1 0 0 1 cmos + pin: high -z ? pin: true phase relative to divid er output 1 0 1 0 cmos + pin: high -z ? pin: high -z 1 0 1 1 cmos (both outputs in phase) + pin: complement phase relative to divider output ? pin: complement phase relative to divider output 1 1 0 0 cmos (both outputs out of phase) + pin: comple ment phase relative to divider output ? pin: true phase relative to divider output 1 1 0 1 cmos + pin: complement phase relative to divider out put ? pin: high -z 1 1 1 0 cmos + pin: high -z ? pin: complement phase relative to divider output 1 1 1 1 tristate output 0x191 [7:0] channel divider, bits[7:0] (lsb) division = channel divider bits[9:0] + 1. for example, [9:0] = 0 is divided by 1, [9:0] = 1 is divided by 2 [9:0] = 1023 is divided by 1024 . 10 - bit channel divider, bits[7:0] (lsb). 0x192 [7:2] divider phase divider initial phase after a sync is asserted relative to the divider input clock (from the vco divider output). lsb = ? of a period of the divider input clock. phase = 0: no phase offset. phase = 1: ? period offset, phase = 63 : 31 period offset . [1:0] channel divider, bits[9:8] (msb) 10- bit channel divider , bits[9 : 8] ( m sb) .
AD9523 data sheet rev. c | page 52 of 60 table 52 . pll1 output control (pll1_out, pin 72 ) address bits bit name description 0x1ba [7:5] reserved reserved 4 pll1 output cmos driver strength cmos driver strength 1: weak 0: strong [3:0] pll1 output divider 0000 : divide -by -1 0 001: divide -by - 2 (default) 0010: divide -by -4 0100: divide -by -8 1000: divide -by -16 no other inputs permitted table 53. pll1 outpu t channel control address bits bit name description 0x1bb 7 pll1 output driver power - down pll1 output driver power - down [6:4] reserved reserved 3 route vcxo clock to channel 3 divider input 1: channel uses vcxo clock . route s vcxo clock to divider inpu t . 0: channel uses vco divider output clock 2 route vcxo clock to channel 2 divider input 1: channel uses vcxo clock . route s vcxo clock to divider input . 0: channel uses vco divider output clock 1 route vcxo clock to channel 1 divider input 1: channel uses vcxo clock . route s vcxo clock to divider input . 0: channel uses vco divider output clock 0 route vcxo clock to channel 0 divider input 1: channel uses vcxo clock . route s vcxo clock to divider input . 0: channel uses vco divider output clock readback (addre ss 0x22c to address 0x22d ) table 54 . readback registers (readback 0 and readback 1) address bits bit name description 0x22c 7 status pll2 reference clock 1: ok 0: off/clocks are missing 6 status pl l 1 feedback clock 1: ok 0 : off/clocks are missing 5 status vcxo 1: ok 0: off/clocks are missing 4 status ref_test 1: ok 0: off/clocks are missing 3 status refb 1: ok 0: off/clocks are missing 2 status refa 1: ok 0: off/clocks are missing 1 lock detect pll2 1: locked 0: u nlocked 0 lock detect pll1 1: locked 0: unlocked 0x22d [7:4] reserved reserved 3 holdover active 1: holdover is active (both references are missing) 0: normal operation 2 selected reference (in auto mode) selected reference (applies only when the d evice automatically selects the reference; for example, not in manual control mode) 1: refb 0: refa 1 reserved reserved 0 vco calibration in progress 1: vco calibration in progress 0: vco calibration not in progress
data sheet AD9523 rev. c | page 53 of 60 other ( add r ess 0x230 to address 0x2 34) table 55. status signals address bits bit name description 0x230 [7:6] reserved reserved [5:0] status monitor 0 control bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 muxout 0 0 0 0 0 0 gnd 0 0 0 0 0 1 pll1 and pll2 locked 0 0 0 0 1 0 pll1 locked 0 0 0 0 1 1 pll2 locked 0 0 0 1 0 0 both references are missing (refa and refb ) 0 0 0 1 0 1 both references are missing and pll2 is locked 0 0 0 1 1 0 r efb selected (applies only to auto select mode) 0 0 0 1 1 1 r efa is ok 0 0 1 0 0 0 refb is ok 0 0 1 0 0 1 ref_test is ok 0 0 1 0 1 0 vcxo is ok 0 0 1 0 1 1 pll1 feedback is ok 0 0 1 1 0 0 pll2 reference clock is ok 0 0 1 1 0 1 reserved 0 0 1 1 1 0 refa and refb are ok 0 0 1 1 1 1 all clocks are ok (except ref_test) 0 1 0 0 0 0 pll1 feedback is divide -by -2 0 1 0 0 0 1 pll1 pfd down divide -by -2 0 1 0 0 1 0 pll1 ref divide -by -2 0 1 0 0 1 1 pll1 pfd up divide -by -2 0 1 0 1 0 0 gnd 0 1 0 1 0 1 gnd 0 1 0 1 1 0 gnd 0 1 0 1 1 1 gnd note that all bit combinations after 010111 are reserved.
AD9523 data sheet rev. c | page 54 of 60 address bits bit name description 0x231 [7:6] reserved reserved [5:0] status monitor 1 control bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 muxout 0 0 0 0 0 0 gnd 0 0 0 0 0 1 pll1 and pll2 locked 0 0 0 0 1 0 pll1 locked 0 0 0 0 1 1 pll2 locked 0 0 0 1 0 0 both references are missing (refa and refb ) 0 0 0 1 0 1 both references are missing and pll2 is locked 0 0 0 1 1 0 refb selected (applies only to auto select mode) 0 0 0 1 1 1 refa is ok 0 0 1 0 0 0 refb is ok 0 0 1 0 0 1 ref_test is ok 0 0 1 0 1 0 vcxo is ok 0 0 1 0 1 1 pll1 feedback is ok 0 0 1 1 0 0 pll2 reference clock is ok 0 0 1 1 0 1 reserved 0 0 1 1 1 0 refa and refb are ok 0 0 1 1 1 1 all clocks are ok (except ref_test) 0 1 0 0 0 0 gnd 0 1 0 0 0 1 gnd 0 1 0 0 1 0 gnd 0 1 0 0 1 1 gnd 0 1 0 1 0 0 pll2 feedback is divide -by -2 0 1 0 1 0 1 pll2 pfd down divide - by - 2 0 1 0 1 1 0 pll2 ref divide -by -2 0 1 0 1 1 1 pll 2 pfd up divide -by -2 note that all bit combinations after 010111 are reserved. 0x232 [7:5] reserved reserved. 4 enable status_eeprom on status0 pin enables the eeprom status on the status0 pin. 1: enable status. 3 status1 pin divider enable enables a divide -by - 4 on the status1 pin , allowing dynamic signals to be viewed at a lower frequency (such as the pfd input clocks). not to be used with dc states on the status pins, which occur when the settings of register 0x231, bits[5:0] are in the ran ge of 000000 to 001111. 1: enabled. 0: disabled. 2 status0 pin divider enable enables a divide -by - 4 on the status 0 pin, allowing dynamic signals to be viewed at a lower frequency (such as the pfd input clocks). not to be used with dc states on the status pins, which occur whe n the settings of register 0x230 , bits[5:0] are in the range of 000000 to 001111. 1: enable. 0: disable. 1 reserved reserved. 0 sync dividers (manual control) set bit to put dividers in sync; clear bit to release. functions like sync pin low. 1: sync. 0: normal.
data sheet AD9523 rev. c | page 55 of 60 table 56 . power - down control address bits bit name description 0x233 [7: 3 ] reserved reserved. 2 pll1 power - down 1: power - down (default). 0: normal operation. 1 pll2 power - dow n 1: power - down (default). 0: normal operation. 0 distribution power - down powers down the distribution. 1: power - down (default). 0: normal operation. table 57 . update all registers address bits bit name description 0x234 [7:1] r eserved reserved. 0 io_u pdate this bit must be set to 1 to transfer the contents of the buffer registers into the active registers, which happens on the next sclk rising edge. this bit is self - clearing; that is, it does not have to be set back to 0. 1 (s elf - clearing): update all active registers to the contents of the buffer registers. eeprom buffer (address 0xa00 to address 0xa16) table 58 . eeprom buffer segment address bits bit name description 0x a00 to 0x a16 [7:0] eeprom buffe r segment register 1 to eeprom buffer segment register 23 the eeprom buffer segment section stores the starting address and number of bytes that are to be stored and read back to and from the eeprom. because the register space is noncontiguous, the eeprom controller needs to know the starting address and number of bytes in the register s pace to store and retrieve from the eeprom. in addition, there are speci al instructions for the eeprom controller: operational codes (that is, io_u pdate and end - of - data) th at are also stored in the eeprom buffer segment. the on - chip default setting of the eeprom buffer segm ent registers is designed such that all registers are transferred to/from the eeprom, and an io_u pdate is issued after the transfer (s ee the programming the eeprom buffer segment section). eeprom control (address 0xb00 to address 0xb03) table 59. status_eeprom addr ess bits bit name description 0x b00 [7:1] reserved reserved. 0 status_eeprom (read only) th is read - only bit indicates the status of the data transferred be tween the eeprom and the buffer register bank during the writing and reading of the eeprom. this signal is a lso available at the status0 pin when register 0x232, bit 4 is set. 0: data transfe r is complete . 1: data transfer is not complete . table 60 . eeprom error checking readback addr ess bits bit name description 0x b01 [7:1] reserved reserved. 0 eeprom data error (read only) this read - only bit indicates an e rror dur ing the data transfer between the eeprom and the buffer. 0: no error; d ata is correct. 1: incorrect data detected.
AD9523 data sheet rev. c | page 56 of 60 table 61 . eeprom control 1 addr ess bits bit name description 0x b02 [7:2] reserved reserved. 1 soft_eeprom when th e eeprom_sel pin is tied low, setting the soft_eeprom bit resets the AD9523 using the settings saved in eeprom. 1: soft reset with eeprom settings (self - clearing). 0 enable eeprom write enables the user to write to the eeprom. 0: eeprom write protection is enabled. user cannot write to eeprom (default). 1: eeprom write protection is disabled. user can write to eeprom. table 62 . eeprom control 2 addr ess bits bit name description 0x b03 [7:1] reserved reserved. 0 reg2eeprom transf ers data from the buffer register to the eeprom (self - clearing). 1: setting this bit initiates the data transfer from the buffer register to the eeprom (writing process); it is reset by the i2c master after the data transfer is done.
data sheet AD9523 rev. c | page 57 of 60 outline dimensions compliant to jedec standards mo-220-vnnd-4 0.20 ref 0.80 max 0.65 typ 1.00 0.85 0.80 0.05 max 0.02 nom 1 18 54 37 19 36 72 55 0.50 0.40 0.30 8.50 ref pin 1 indicator seating plane 12 max 0.60 0.42 0.24 0.60 0.42 0.24 0.30 0.23 0.18 0.50 bsc pin 1 indicator coplanarity 0.08 06-25-2012-c for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. top view exposed pa d bottom view 10.10 10.00 sq 9.90 9.85 9.75 sq 9.65 0.25 min 5.45 5.30 sq 5.15 figure 45. 72-lead lead frame chip scale package [lfcsp_vq] 10 mm 10 mm body, very thin quad (cp-72-6) dimensions shown in millimeters ordering guide model 1 temperature range package description package option AD9523bcpz ?40c to +85c 72-lead lead frame chip scale package [lfcsp_vq] cp-72-6 AD9523bcpz-reel7 ?40c to +85c 72-lead lead frame chip scale package [lfcsp_vq] cp-72-6 AD9523/pcbz evaluation board 1 z = rohs compliant part.
AD9523 data sheet rev. c | page 58 of 60 notes
data sheet AD9523 rev. c | page 59 of 60 notes
AD9523 data sheet rev. c | page 60 of 60 n otes i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ? 2010 C 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d08439 - 0- 2/13(c)

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