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4-channel, 625 ksps, 12-bit parallel adc with a sequencer prelim inary technical data ad7934-6 rev. pr b in fo rmation fur n ished by an al o g d e v i c e s is believed t o be accurate an d r e liable. how e ver, no r e spon sibili ty is assumed by anal og de vices fo r its use, nor for a n y i n fri n geme nt s of p a t e nt s or ot h e r ri g h t s o f th ird parties that m a y res u lt fro m its use . s p ecificatio n s subj ec t to chan ge witho u t n o tice. no licen s e is g r an te d b y implicatio n or ot h e rwi s e u n de r any p a t e nt or p a t e nt ri ght s of a n al og de vi c e s. tra d emark s a n d registered tra d ema r ks are the proper ty of th eir respectiv e co mpan ies. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . the ad7934-6 has a n acc u ra t e o n -c hi p 2.5 v r e f e r e n c e tha t can b e us e d as t h e refer e n c e s o ur ce fo r t h e a n alog to dig i t a l co n v ersio n . a l te r n a t i vely , t h is p i n can b e o v er dr i v en to p r o v id e an e x te r n a l re f e re nc e. fea t ures specified for v dd of 2.35 v to 5.25 v low power: 6 mw max at 625 ksps with 3v supplies 12 m w max at 625 ksps with 5v supplies this p a r t us es ad van c e d desig n t e c h niq u es t o achiev e v e r y lo w p o w e r d i s s i p at i o n at h i g h t h r o u g hp u t r a t e s . i t a l s o f e at u r e s f l e x ibl e p o we r m a n a ge me n t opt i ons . a n o n - c h i p c o n t ro l r e g i s t er al lo ws t h e us er t o s e t up dif f er en t o p er a t in g co ndi t i o n s in cl u d in g ana l og in p u t ra n g e and co nf igura t ion, o u t p u t co d i ng, p o w e r ma na ge m e n t and cha n n e l s e q u e n ci n g . 4 analog input channels with a sequ encer software configurable ana l og inputs: 4-channe l sin g le ended inpu ts 2-channe l fu l l y di fferentia l i n puts 2-channe l pse u do diff erentia l inputs accurate on-chip 2.5 v refere nce wide input b a ndwidth: 70db s n r at 5 0 khz input fre q uency no pip e line del a ys high speed par a llel interf ace - word/byte modes full sh utdo wn mo de: 1a ma x 28 lead tssop package gener a l description the ad7934-6 is a 12-b i t, hig h sp eed , lo w p o w e r , s u cces s i v e ap p r ox i m at i o n ( s a r ) a d c . i t o p e r at e s f r o m a s i n g l e 2 . 3 5 v t o 5.25 v p o w e r s u p p l y a nd f e a t ur es thr o ug h p u t ra t e s u p t o 625 ks ps. th e ad7 934-6 co n t ain s a lo w n o is e , wide ban d wid t h, dif f er en t i a l t r ack/ h o ld am plif ie r t h a t can han d l e in p u t f r eq uen c ies u p to 3.5mh z . the ad7934-6 fea t ur es 4 a n alog in p u t cha n n e ls wi t h a c h a n n e l s e q u en cer t o al lo w a co n s ec u t i v e s e q u en ce o f cha n n e ls t o be co n v er te d o n . i t ca n ac cep t e i t h er sin g le-e n d e d , f u l l y dif f er en t i al o r p s eudo dif f er en t i al a n alog i n p u t s . f i g u r e 1. f u nc t i on al bl ock d i ag r a m produc t highlight s 1. h i g h thr o ug h p u t wi th l o w p o w e r c o n s um p t io n. 2. f o ur ana l og i n p u ts wi t h a c h annel s e q u e n cer . the con v ersio n p r o c es s an d da t a acq u isi t ion a r e co n t r o l l e d usin g st anda r d co n t r o l in pu ts a l lo win g e a sy i n ter f acin g t o micr o p r o cess o r s a nd dsp s . t h e in p u t sig n a l is s a m p le d on t h e fallin g edg e o f co n v s t a nd t h e con v ersio n is a l s o ini t i a te d a t t h is p o in t. 3. a c c u ra t e on-c hi p 2.5 v r e f e r e n c e . 4. s o f t wa r e c o nf igura b le analog i n p u ts. s i n g le-en d e d , p s eudo dif f er en t i al o r f u l l y dif f er en t i a l a n alog i n p u ts t h a t a r e so ft w a r e se lecta b l e . 5. s i n g le-su p p l y o p era t ion wi t h v dr iv e fu n c t i o n . t h e v dr iv e f u nc t i on a l l o w s t h e p a r a l l el i n te r f a c e to c o nne c t di re c t ly to 1.8 v , 3v o r 5 v p r o c es s o r sys t em s in dep e n d en t o f v dd . 6. n o p i p e lin e d e l a y . 7. a c c u ra t e con t r o l o f th e s a m p ling in s t ance via a co n v s t i n put a n d o n c e of f c o n v e r s i on c o n t ro l.
ad7934-6 rev. prb | page 2 of 27 table of contents features .......................................................................................... 1 general description ..................................................................... 1 product highlights ....................................................................... 1 specifications ..................................................................................... 3 ad7934-6C6 specifications ......................................................... 3 timing specifications .................................................................. 5 absolute maximum ratings ....................................................... 7 pin function description ................................................................ 8 pin configuration ............................................................. 8 terminology .................................................................................... 10 typical performance characteristics ad7934-6 ........................ 12 circuit information ........................................................................ 16 converter operation .................................................................. 16 adc transfer function ............................................................. 16 typical connection diagram ................................................... 17 analog input structure .............................................................. 17 the analog inputs ...................................................................... 18 analog input selection .............................................................. 20 reference section ....................................................................... 21 parallel interface ......................................................................... 22 power modes of operation ...................................................... 23 power vs. throughput rate ........................................................ 23 microprocessor interfacing ....................................................... 23 application hints ........................................................................... 26 grounding and layout .............................................................. 26 outline dimensions ....................................................................... 27 ordering guide .......................................................................... 27 revision history revision prb: initial version
preliminary technical data ad7934-6 rev. prb | page 3 of 27 specifications ad7934-6 specifications v dd = v drive =2.35 v to 5.25v, internal/external v ref = 2.5v, f clkin = 10mhz, f sample = 625 ksps; t a = t min to t max , unless otherwise noted. table 1. parameter b version 1 units test conditions/comments dynamic performance f in =50khz sine wave signal to noise + distortion 2 (sinad) 70 db min signal to noise ratio (snr) 2 70 db min total harmonic distortion (thd) 2 C75 db max C80db typ peak harmonic or sp urious noise (sfdr) 2 C75 db max C82db typ intermodulation distortion (imd) 2 fa = 40.1khz, fb = 51.5khz second order terms C85 db typ third order terms C85 db typ aperture delay 2 5 ns typ aperture jitter 2 50 ps typ full power bandwidth 2, 3 20 mhz typ @ 3 db 2.5 mhz typ @ 0.1 db dc accuracy resolution 12 bits integral nonlinearity 2 1 lsb max differential nonlinearity 2 0.95 lsb max guaranteed no missed codes to 12 bits. total unadjusted error tbd lsb max single ended & pseudo differential input straight binary output coding offset error 2 4.5 lsb max offset error match 2 0.5 lsb max gain error 2 2 lsb max gain error match 2 0.6 lsb max fully differential input twos complement output coding positive gain error 2 2 lsb max positive gain error match 2 0.6 lsb max zero code error 2 3 lsb max zero code error match 2 1 lsb max negative gain error 2 1 lsb max negative gain error match 2 0.5 lsb max analog input single ended input range 0 to v ref or 0 to 2 x v ref v depending on range bit in the control register pseudo differential input range: v in+ 0 to v ref or 2 x v ref v depending on range bit in the control register v in- -0.1 to 0.4 v fully differential input range: v in+ and v in- v cm v ref /2 v v cm = common mode voltage = v ref /2 v in+ and v in- v cm v ref v only when v dd = 4.75 v to 5.25 v. v cm = v ref dc leakage current 4 1 a max input capacitance 45/10 pf typ when in track/hold reference input/output v ref input voltage 2.5 5 v 1% specified performance 1 temperature ranges as follows: b versions: C40c to +85c. 2 see terminology section. 3 analog inputs with slew rates exceeding 27v/s (full-scale input sine wave > 3.5mhz) within the acquisition time may cause an incorrect result to be returned by the converter 4 guaranteed by characterization 5 this device is operational with an external reference in the range 0.1 v to 3.5 v in differential mode and 0.1v to v dd in pseudo differential and single ended modes. see the reference section fo r more information.
ad7934-6 prelim inary technical data parameter b erin 1 unit tet cnitin cmment ref inut ltae dd dd 27 dc leakae current 1 a ma ref inut ime ance 1 k ty ref o ut outut ltae 25 1 25c ref o ut t e m c 1 5 m c t y ref nie 1 ty 1h t 1h b a nwith 13 ty 1h t 1mh b a nwith ref outu t im eance 1 ty ref inut caacitance 1525 f ty hen in trackhl logic inputs inut hih lt ae, inh 24 min drie 27 t 525 drie m i n drie 27 inut lw ltae, inl m a drie 27 t 525 2 drie m a drie 27 inut current, i in 1 a ma tyically 1 na, in r drie inut caacitance, c in 4 1 f m a logic outputs outut hih ltae, oh 24 min i sou r ce 2 a drie 27 t 5 25 drie 2 min i sou r ce 2 a drie 27 outut lw ltae, ol 4 ma i sin 2a flatin-state leakae curren t 1 a ma flatin-state outut caacitance 4 1 f ma outut cin coding it in the cntrl rei ter et t straiht natural binary 2 cmle ment coding it in the cntrl rei ter et t 1 conersion r a te cnerin time t 2 13 tcl k t 2 n trackhl acquiitin time 35 n ma full scale ste i n ut thruhut ra te 625 ksps ma poer reuir emen ts dd 235525 minma drie 36 525 minma dd 36 t 5 25 1 6 3 6 m i n m a dd 27 t 3 6 i dd 6 diital ip r drie nrmal mestatic 5 ma ty dd 27 t 52 5 scl n r nrmal me oeratinal 24 ma ma dd 475 t 5 25 2 ma ma dd 27 t 36 au t stanby me 155 ma ty f am l e 1ksps 9 a ma static au t shut wn me 1 ma ty f am l e 1ksps 1 a ma static full shut-dwn me 1 a ma scl on r o pwer dii a tin nrmal me oeratinal 12 m ma dd 5 6 m ma dd 3 aut stany-me static 45 ma dd 5 27 ma dd 3 au t shut wn-me stati c 5 ma dd 5 3 ma dd 3 full shutw n-me 5 3 ma dd 5 3 6 mea ur e wi t h a m i ca l e c i n ut re pr b pae 4 27
prelim inary technical data ad7934-6 timi ng spe c ific a t io ns 1 (v dd = v dr i v e =2 .35 v t o 5.25v , i n t e r n al/e xt er na l v ref = 2.5v , f cl k i n = 10mh z , f sa mpl e = 625ks p s; t a = t min to t max , u n l e s s o t h e r w i s e not e d. ) table 2. limit at t min , t max parameter ad7934-6 units description f clk i n 2 10 khz min 20 mhz max t qu iet 10 ns min minimum time between conver sions (i.e. time fr om when the da ta bus goes into th ree-state until the next falli ng edge of convst ) t 1 10 ns min convst pulsewid t h t 2 20 ns min convst falling edge to clkin falling edge setup time t 3 tbd ns min clkin falling edge to busy rising edge t 4 0 ns min cs to wr setup time t 5 0 n s m a x cs to wr hold time t 6 2 5 n s m i n wr pulse width t 7 10 ns min data setup time before wr t 8 5 ns min data hold after wr t 9 1 / 2 t clk i n ns min new d a ta valid befo re falling edge of busy t 10 0 ns min cs to rd setup time t 11 0 ns max cs to rd hold time t 12 55 ns min rd pulse width t 13 3 50 ns max data access time after rd t 14 4 5 ns min bus relin q uish time after rd 40 ns max bus relin q uish time after rd t 15 15 ns min hben to rd setup time t 16 5 ns min hben to rd hold time t 17 10 ns min minimum time between reads/writes t 18 0 ns min hben to wr setup time t 19 5 ns max hben to wr hold time t 20 t b d n s min clkin falling edge to busy rising edge 1 gua r a n t eed by ch a r a c t e ri za t i on . al l i n put si gn a ls a r e spec i f i e d wi t h t r = t f = 5 n s (10% t o 90% of v dd ) and timed f r om a vol t age le vel of 1.6 vol t s . al l timin g specifications given above are with a 25pf load capacita nce. se e , , a n d . f i g u r e 2 f i g u r e 3 f i g u r e 4 f i g u r e 5 2 mark/space ratio for cl kin is 40/60 to 60/40. 3 the time re quire d f o r the o u tput to cro s s tbd. 4 t 14 i s deri ve d from t h e m e a s ure d t i m e t a ken by t h e da t a o u t p ut s t o ch a n ge 0. 5 v. th e m e a s ur ed n u m b er i s t h e n ext r a p ola t ed ba ck t o remo v e the e f f e cts o f charging o r d i s c harging the 25 pf capacito r. this me ans that the time , t 14 quoted in the timing charac teris t ics is the true bus reli n q u i s h t i m e of t h e pa rt a n d i s i n de pen d en t of t h e bu s loa d i n g. rev. pr b | page 5 of 27
ad7934-6 prelim inary technical data f i ure 2 a d 79 3 4 - 6 p a r a ll el inte r ace ri t e c y c l e ti min r r m e o er at in b 1 f i u r e 3 ad7 9 3 4 - 6 p a r a ll el i n te r ac e - r it e c y cl e t i mi n r byt e m e o er a t i n b f i g u re 4 a d 79 34- 6 p a r a l l e l int e r f a c e - convers i on a n d r e ad c y c l e in w o r d m o de ( w = 1) rev pr page 6 of 27
prelim inary technical data ad7934-6 f i u re 5 a d 79 34- 6 p a r a l l e l int e r a c e - r e a c y c l e ti m i n r b y te m e o e r at i n b absol u te ma imum r a tings t a 25c un le t h e r w i e n te tale 3 p a r a m e t e r r a t i n dd t ag nddgnd 3 t 7 drie t agnddgnd 3 t 7 anal inut ltae t agnd 3 t dd 3 diital inut ltae t dgnd 3 t 7 drie t dd 3 t dd 3 diital outut ltae t agnd 3 t dd 3 ref i n t agn d 3 t dd 3 inut current t any pin ecet sulie 1 1 m a oeratin tem erature rane cmmercial b erin 4c t 5c strae temerature rane 65c t 15c unctin teme r ature 15c a thermal imeance 979c tsso p c thermal imeance 14c tssop lea temerat ure, slerin ar phae 6 ec 215c inare 15 ec 22c e s d 2 k 1 tranient current u t 1 ma wi ll nt caue scr latch u s t r e e a e t h e li t e u n e r a l ut e m a im u m r a t i n ma y c a u e e r m a n en t ama e t t h e e ice thi i a t r e ra t i n nl y a n u n c t i n al era t i n t h e e i ce a t t h e e r a n y t h e r cn i t i n a e t h e li t e i n t h e era t i nal e c t i n t h i e c i ic a t in i n t i m lie e ur e t a lute m a i m u m r a t i n c n it i n r e te n e e r i m a y a e c t e i c e rel i a i l it y esd c a utin esd electrtatic ichare enitie eice ele c trta tic char e a hih a 4 reaily accumulate n the human y an tet eq uiment an can ichare with ut etectin althuh thi ruct eature rrietary esd rtectin circu i try, ermanent ama e may ccur n eice uecte t hih enery electrtatic ichare there re, r er esd recautin a r e recmmene t ai errm a nce eraatin r l unctina l ity re pr b pae 7 27
ad7934-6 prelim inary technical data pin function description pin c o nfig ur a t ion f i gure 6. pin config ur ation table 4. pin con f iguration pin no. pin mnemonic function 1 v dd power supply input. the v dd ran g e for the ad79 34-6 is from +2.35 v to +5.25 v. t h e supply shou ld be d e coupled to agnd with a 0.1f capacitor and a 10f tantalum capacitor. 2 w / b word/byte input. when this input is logic high, data is transferr e d to and from the ad7934-6 in 12-bit words on pins db0 to db1 1 . when this pin is logi c l o w, byte transfer mod e is enab led . data and the channel id is transferred on pins db0 to db7 and pin db 8/hben assumes its hben functi onality. 3-10 db0 to db7 data bits 0 to 7. t h ree state para llel d i gital i/ o pi ns that provid e the conversi on r e sult and also a l low s the contro l register to be pr ogrammed. t h ese pins are contr o lled by cs , rd and wr . the logic high/low voltage levels for these pins are determined by the v drive input. 11 v drive logic power supply input. t h e voltage supp lie d at this pin determines at wh at voltage the par a lle l interface of the ad7934-6 will operate. 12 dgnd digital ground. this is the ground reference point for all digital circuitry on the ad7934-6. the dgnd and ag nd voltages should ideally be at the same potentia l and must not be more than 0. 3 v apart, even on a transient basi s. 13 db8/hben data bit 8/ high byte enable. when w/b is high, this pin acts as data bit 8, a three state i/o pin that is contro lled by cs , rd and wr . when w/b is low, this pin acts as the high byte enable pin. when hben is low, the low byte of data being written to or read from the ad7934-6 is on db0 to db 7. when hben is high, the t op 4 bits of the data being written to or read from the ad7 934-6 are on db0 to db3. when reading from the device, db4 of the high byte will always be zero a n d db5 and db6 will contai n the id of the channel for whic h the convers i on re s u lt correspo n d s (see channel a ddress bits in table 7). when wri t ing to the d evic e , db4 to db7 of the high byte must be all zeros. 14-16 db9 to db11 data bits 9 to 11. three state parallel digital i/ o pins that provid e the conversi on r e sult and also a l low s the contro l register to be pr ogrammed in word mode. t h ese pins are c o ntr o lled by cs , rd and wr . the logic high/low voltage leve ls f o r these pin s ar e determined by the v drive input . 17 busy busy output. lo gic output indic a ting the status of the conversi o n . the bu sy output goes high following the falling edge of convst and stays high for the duration of the con versi o n . once the con version i s comp lete and the result is available in the output re gister, the busy output will go lo w. t h e track/hold returns to track mode j u st prior to the falli ng edge of busy and the acquisitio n time for the part begins when busy goes low. 18 clin master clock in put. t h e clock s o urce for the co nversio n pr oc ess is applied to this pin. con versi on time for the ad7934-6 takes 13.5 clock cycles. the frequency of the mast er clock input therefore determines the conversi on time and achievable throughpu t rate. 19 convst conversion start input. a falling edge on convst is used to initiate a conversion . t h e track/ hold goes fr om track to hold mode on the falling edge of convst and the conversio n proc ess is in itiated at this poi nt. following powerdown, when operating in the auto-shutd own or auto standby mode, a rising edge on convst is used to power up the device. rev. pr b page 8 of 27
prelim inary technical data ad7934-6 pin n pin mnemnic functin 2 r rite inut acti e lw lic in ut ue in cn unctin with cs t write ata t th e cntrl reit er 21 rd rea inut acti e lw lic in ut ue in cn unctin with cs t acce the c ne r in re ult t h e cner in reult i la c e n the ata u ll win the al l in e e rd rea while cs i l w 22 cs chi select acti e lw l ic in ut ue in cn unctin with rd an r t rea cnerin ata r t rite ata t the cntrl reiter 23 agnd anal grun thi i the run reerence int r all anal circuitry n the ad7934-6 all anal inut inal an any eternal reere n c e inal hul e ree rre t t h i agnd ltae the agnd a n dgnd ltae hul ieally e at the ame tent ial an mut nt e mre than 3 aart, een n a tran i ent ai 2 4 ref i n ref o ut reerence inut outut thi in i c nnecte t the internal reerence an i the reerence urce r the ad c the nminal i n ternal reeren c e ltae i 25 an thi ae ar at thi in t h i in can e er rien y an eternal reere n c e the inut ltae ra ne r the eternal reerence i 1 t 35 r iere ntial me an i 1 t dd in i nl e ene an eu i erential me, eenin n dd 25-2 in in 3 anal inut t anal inut 3 f ur anal i n ut channel that are mu ltile e int the n-chi track hl t h e anal in ut can e rr a mme t e ur inle ene inut , tw ul l y iere ntial air r tw eu ierential air y ettin the mode it in the cntrl reit er arri ately ee tale 7 the anal inut channe l t e c nerte can eit h er e electe y writ in t the are it add1 an add in the cntrl reiter rir t the cneri n, r the n-chi equencer ca n e ue the inut rane r all inut channel c a n either e t ref r t 2 ref an the cin can e in a r y r tw cm lement, een in n the tate the range an coding it in the cntrl re iter any une inut chann e l h ul e c nnecte t agnd t ai nie icku rev. pr b page 9 of 27
ad7934-6 rev. prb | page 10 of 27 terminology integral nonlinearity this is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the endpoints of the transfer function are zero scale, a point 1 lsb below the first code transition, and full scale, a point 1 lsb above the last code transition. differential nonlinearity this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. offset error this is the deviation of the first code transition (00 . . .000) to (00 . . . 001) from the ideal, i.e. agnd + 1 lsb offset error match this is the difference in offset error between any two channels. gain error this is the deviation of the last code transition (111 . . .110) to (111 . . . 111) from the ideal (i.e., v ref C 1 lsb) after the offset error has been adjusted out. gain error match this is the difference in gain error between any two channels. zero code error this applies when using the 2s complement output coding option, in particular to the 2 x v ref input range with -v ref to +v ref biased about the v refin point. it is the deviation of the mid scale transition (all 0s to all 1s) from the ideal v in voltage, i.e. v ref C 1 lsb. zero code error match this is the difference in zero code error between any two channels. positive gain error this applies when using the 2s complement output coding option, in particular to the 2 x v ref input range with -v ref to +v ref biased about the v refin point. it is the deviation of the last code transition (011. . .110) to (011 .. . 111) from the ideal (i.e., +v ref C 1 lsb) after the zero code error has been adjusted out. positive gain error match this is the difference in positive gain error between any two channels. negative gain error this applies when using the 2s complement output coding option, in particular to the 2 x v ref input range with C v ref to +v ref biased about the v ref point. it is the deviation of the first code transition (100 . . . 000) to (100 . . . 001) from the ideal (i.e., C v refin + 1 lsb) after the zero code error has been adjusted out. negative gain error match this is the difference in negative gain error between any two channels. channel-to-channel isolation channel-to-channel isolation is a measure of the level of crosstalk between channels. it is measured by applying a fullscale sine wave signal to all 3 nonselected input channels and applying a 50khz signal to the selected channel. the channel to channel isolation is defined as the ratio of the power of the 50khz signal on the selected channel, to the power of the noise signal that appears in the fft of this channel. psrr (power supply rejection ratio) the power supply rejection ratio is defined as the ratio of the power in the adc output at full-scale frequency, f, to the power of a 100mv p-p sine wave applied to the adc v dd supply of frequency fs. the frequency of the input varies from 1khz to 1mhz. psrr (db) = 10log(pf/pfs) pf is the power at frequency f in the adc output; pfs is the power at frequency fs in the adc output. track/hold acquisition time the track/hold amplifier returns into track mode and the end of conversion. track/hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within 1/2 lsb, after the end of conversion. signal to (noise + distortion) ratio (sinad) this is the measured ratio of signal to (noise + distortion) at the output of the a/d converter. the signal is the rms amplitude of the fundamental. noise is the sum of all non-fundamental signals up to half the sampling frequency (fs/2), excluding dc. the ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. the theoretical signal to (noise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by: signal to (noise + distortion) = (6.02 n + 1.76) db thus for a 12-bit converter, this is 74 db.
prelim inary technical data ad7934-6 t t a l ha r m n i c d i t r t i n t o tal ha rm o n i c d i s t o r ti o n (t hd ) i s th e ra ti o o f th e rm s s u m o f ha r m o n ics t o the f u ndam e n t al . f o r th e ad7934 -6, i t is def i n e d as: inte r m o d u l at i o n d i s t or t i on w i t h i n p u ts co nsist i n g o f sine w a ves a t tw o f r e q uen c ies, fa and fb , a n y a c t i v e de v i ce wi th n o nlin ea ri ti e s will cr ea t e d i s t o r ti o n p r o d uc ts a t s u m a nd dif f er ence f r e q uen c ies o f mfa nfb w h er e m, n = 0, 1, 2, 3, et c. i n ter m o d u l a t io n dis t o r tion t e r m s a r e th os e f o r whic h n e i t her m n o r n a r e e q ual t o zer o . f o r exa m p l e , th e seco n d o r der t e r m s in c l ude (fa + fb) a nd (fa C f b ), while t h e thir d o r der t e r m s in c l ude (2fa + fb), (2fa C fb), (fa + 2fb) a nd (f a C 2fb). () v v v v v v db thd + + + + ? = w h er e v 1 is t h e r m s a m pli t ude o f t h e f u ndam e n t a l and v 2 , v 3 , v 4 , v 5 a nd v 6 a r e t h e r m s am pli t udes o f t h e s e c o nd t h r o ug h t h e six t h ha r m o n i c s . the ad7934-6 is t e s t e d usin g t h e ccif s t anda rd w h er e tw o in p u t f r e q uen c i e s n e a r t h e t o p end o f t h e in pu t b a ndwi d t h a r e us ed . i n this cas e , th e s e con d o r der t e r m s a r e us ual l y dis t an ce d in f r e q uen c y f r o m t h e o r ig ina l s i ne wa v e s w h i l e t h e t h ird o r der t e r m s a r e us ual l y a t a f r e q ue n c y clos e t o t h e i n pu t f r e q uen c ies. a s a r e su lt, t h e s e co nd and t h ir d o r der ter m s a r e sp e c if ie d s e p a r a tely . t h e ca lc u l a t ion o f t h e i n ter m o d u l a t io n disto r t i o n is as p e r t h e t h d sp e c if ic a t ion w h er e i t is t h e ra t i o o f t h e r m s s u m o f th e in d i v i d u al d i s t o r ti o n p r od uct s t o th e rm s a m p l i t ud e o f t h e s u m o f t h e f u ndam e n t als exp r es s e d i n db s. p e a k h a rmo n i c o r s p uri o us n o is e p e a k ha r m o n ic o r sp ur io us n o is e is def i ne d as t h e r a t i o o f t h e r m s val u e o f t h e n e xt la rg es t com p on e n t i n t h e ad c o u t p ut s p e c t r um (u p t o fs/2 a nd excl udin g dc) t o t h e r m s val u e o f t h e f u ndam e n t a l . n o r m a l ly , t h e va lue o f t h is sp e c if ica t ion is det e r m i n e d b y t h e la rges t ha r m o n ic in t h e sp e c t r um, b u t fo r ad cs w h er e t h e ha r m o n ic s a r e b u r i e d i n t h e no is e f l o o r , i t wi l l be a n o ise pea k rev. pr b page 11 of 27
ad7934-6 prelim inary technical data typical perf orm ance cha r acte ristics performa nce curve s t a = 25c, unles s o t h e r w is e n o ted f i g u re 7. psr r vers us sup p ly ri p p le f r e q uenc y w i t h out s u p p ly decoup ling f i g u re 8. ch ann e l t o ch anne l is ol at i o n f i g u re 9. a d 79 34- 6 sina d v s a n a l og i n put f r equenc y f o r v a ri ous sup p l y v o l t ag es f i gur e 1 0 . ad79 34 -6 fft @ v dd =5 v f i gur e 1 1 . ad79 34 -6 t y pi c a l dnl @ v dd =5v f i gur e 1 2 . ad79 34 -6 t y pi c a l inl @ v dd =5v f i gur e 1 3 . ad79 34 -6 cha n ge i n inl vs v ref fo r v dd =5v f i g u re 14 . a d7 93 4- 6 ch ang e in dnl v s v ref fo r v dd =5v rev. pr b | page 12 of 27
prelim inary technical data ad7934-6 f i ur e 1 5 ad79 34 -6 cha n e i n enob ref r dd 5 f i ur e 1 6 ad79 34 -6 o e t ref f i ur e 1 7 ad79 34 -6 hi t r a m c e dd 5 wi th t h e interna l reer e nc e f i ur e 1 ad79 34 -6 hi t r a m c e dd 5 wi th an e t e r n al re er e nc e rev. pr b page 13 of 27
ad7934-6 rev. pr b | page 14 of 27 co n t r o l r e g i s t e r the c o n t r o l reg i s t er o n t h e ad7934-6 is a 12 -b i t , wr i t e-onl y r e g i s t er . da t a is wr i t t e n t o this r e g i s t er usin g t h e cs a nd wr pi ns . t h e c o n t r o l reg i st e r is s h o w n b e lo w an d t h e f u n c t i o n s o f t h e b i ts a r e des c r i b e d i n t a b l e 5. a t p o wer u p , t h e def a u l t b i t s e t t in gs i n t h e c o n t r o l reg i st er a r e al l 0s. f i gure 1 9 . c o nt r o l regi st er bi ts . ta ble 5. co nt rol regi s t er bi t f u nct i on des c r i pt i o n bit mnemonic comment 11, 10 pm1, pm0 power manage ment bits. these two bits are used to select the power mo de of o p eration. the user can cho o se between either normal m o de or various po wer down modes of operatio n as sh own in t a b l e 6. 9 c o d i n g this bit selects t h e output coding of the conversion result. if this bit is set to 0, the output cod i ng will be straight (natural) binary. if this bit is set t o 1, the output coding will be twos complement. 8 r e f t h is bit selects whether the internal or a n exter n al referenc e is used to perform the conversi on. if this bit is logic 0, an externa l refer e nce sh ould be appli e d to the v ref pin and if it is 1, the internal reference is se lec t ed (see the reference section). 7 zero this bit is not used so sh ould al ways be set to l o gic 0. 6, 5 add1, add0 these two address bits ar e used to either select which a n al og in put channel is t o be conv erted on in the next conver sion if th e sequencer i s n o t being used, or to se lect the final cha nnel i n a conse c utive seq u ence when the sequencer i s bei n g used as described in table 8. the se lected input channel is d e coded as sho w n in table 7. 4,3 mode1, mode0 the two mode pins select the ty pe of analog input on the four v in pins. the ad7 934-6 can have either 4 single ended inputs, 2 fully differential inputs or 2 pseudo differential inputs. see table 7. 2 seq1 the seq1 bit in the control regi ster is used in conj unction with the seq0 bit to control the seq u encer function. see table 8. 1 seq0 the seq0 bit in the control regi ster is used in conj unction with the seq1 bit to control the seq u encer function. see table 8. 0 range this bit selects t h e analog input range of the ad7934-6. if it is se t to 0 then the a n alog input range will extend from 0v to v ref . i f it is set to 1 the n the analog input range will ex t e nd from 0v to 2x v ref . when this range is selected , av dd must be 4.75 v to 5.25 v. table 6. power mode selection using the pow e r man a gement bits in the con t rol register p m 1 p m 0 m o d e d e s c r i p t i o n 0 0 normal mode when operating in normal mode, all circui try is fully powerered up at all times. 0 1 auto shutdown when operating in auto shutdown mode, the ad7934-6 will ent e r full shutdown mode at the end of each conver sion. in t h is mode, al l circuitry is powered down. 1 0 auto standby when the ad7934-6 enter this mode, all circuit r y is part ially powered down. this mo de is simi lar to auto shutdown but allows the part to power up in 1 sec. 1 1 full shutdown when the ad7934-6 enters this mode, all circuit r y is pow ered down. the inform ation in the control register is retained. table 7. analo g input ty pe s e lection
preliminary technical data ad7934-6 rev. prb | page 15 of 27 channel address mode0=0, mode1=0 mode0=0, mo de1=1 mode0=1, mode1=0 mode0=1, mode1=1 4 single-ended i/p channels 2 fully differential i/p channels 2 pseudo differential i/p channels not used add1 add0 v in+ v in- v in+ v in- v in+ v in- 0 0 vin0 agnd vin0 vin1 vin0 vin1 0 1 vin1 agnd vin1 vin0 vin1 vin0 1 0 vin2 agnd vin2 vin3 vin2 vin3 1 1 vin3 agnd vin3 vin2 vin3 vin2 sequencer operation the configuration of the seq0 and seq1 bits in the control register allow the user use the sequencer function. table 8 outlines the two modes of operation of the sequencer. table 8. sequence selection seq0 seq1 sequence type 0 0 this configuration is selected when the sequence function is not used. the analog input channel selected on each individual conversion is determined by the contents of th e channel address bits add1 and add0 in each prior write operation. this mode of operation reflects the normal operat ion of a multi-channel adc, without the sequencer function being used, where each write to the ad7934-6 selects the next channel for conversion. 0 1 not used 1 0 not used 1 1 this configuration is used in conjun ction with the channel address bits (a dd1 and add0) to program continuous conversions on a consecutive sequence of channels from channel 0 through to a selected final channel as determined by the channel address bits in the control register. when opera ting in differential or pseudo differential mode, the adc will not convert on inverse pairs ( e.g. vin1 and vin0)
ad7934-6 prelim inary technical data rev. pr b | page 16 of 27 circuit i n forma t ion the ad7934-6 is a 4 c h a n n e l , 12-b i t, sin g le su p p l y , s u cces s i v e a p p r o x ima t ion analog t o dig i t a l co n v er t e r . i t c a n be o p er a t e d f r o m a ei t h er a 2.35 v t o 3.6 v o r a 4.75 v t o 5.25 v p o w e r su p p ly and fe a t u r e s t h rou g h p u t r a te s u p to 6 2 5 ks p s . the ad7934-6 p r o v ides the us er wi t h a n on-chi p trac k/h o ld , a n i n te r n a l a c c u r a t e re fe re nc e, an a n a l o g to di g i t a l c o n v e r te r , a n d a p a ra l l el in t e r f ac e h o us e d i n a 28 ? l e ad t sso p p a c k a g e . the ad7934-6 has f o ur a n alog in p u t c h a n ne ls whic h can b e co nf igur ed t o b e 4 sin g le en de d in p u ts, 2 f u l l y dif f er en tial p a irs o r 2 ps eudo dif f er en t i a l p a irs. th er e is an o n -chi p cha n ne l seq u en ce r wh i c h all o w s th e user t o se l e ct a co n s ecu t i v e s e q u e n ce o f channels t h r o ug h w h ich t h e a d c ca n c y cle w i t h ea c h fall i n g ed ge o f co n v s t . the a n alog in p u t ra n g e f o r th e ad7934-6 is 0 to v ref o r 0 t o 2 x v ref dep e n d i n g o n t h e s t a t us o f t h e r a n g e b i t in t h e c o n t r o l r e g i s t er . the o u t p u t c o di n g o f t h e ad c can b e ei t h er bina r y o r t w o s c o m p l e m e n t , d e p e nd i n g on t h e st atu s of t h e c o di ng bit in t h e c o n t r o l reg i s t er . the ad7934-6 p r o v ides f l exi b le p o w e r ma na gem e n t o p t i o n s to al lo w t h e us er t o achie v e t h e b e s t p o w e r p e r f o r ma nce fo r a gi v e n th r o ugh p u t ra t e . th e s e o p ti o n s a r e s e lect ed b y p r o g ra mmin g t h e p o w e r ma nagem e n t b i ts, pm1 a nd pm0, i n t h e c o n t r o l reg i s t er . c o nverter oper a t ion the ad7934-6 is a s u cces si ve a p p r o x ima t ion ad c bas e d a r o u n d tw o c a p a ci ti v e d a cs. f i gur e 20 a n d f i g u r e 21 s h o w sim p lif i e d s c h e ma t i cs o f t h e a d c in a c q u is i t i o n an d c o n v ersio n phas e r e s p e c t i ve l y . the a d c com p r i s e s o f c o n t r o l logi c, a sa r a n d t w o ca pa ci ti v e d a c s . b o th f i gur e s s h o w th e o p era t ion o f t h e ad c in d i f f er en t i al/ p s e udo di f f er en t i al m o de . sin g le e n de d mo de o p er a t io n is simi la r b u t v in - is in t e r n a l ly t i e d to a g nd . i n acq u isi t io n ph as e, sw3 is clo s e d and sw1 and sw2 a r e in p o si tio n a, t h e com p a r a t o r is he ld in a ba lan c e d co ndi t i on and t h e s a m p li n g c a p a ci to r a r r a y s ac q u ir e t h e dif f er en t i al sig n al o n t h e i n p u t . f i g u re 20. a d c ac quis it i o n p h as e w h en t h e ad c s t a r ts a con v ersio n (f igur e 21), sw3 wi l l o p e n a nd s w 1 an d s w 2 wi l l m o ve to p o si t i o n b , c a usin g t h e co m p a r a t o r t o b e co me u n bal a nced . b o th in p u ts a r e dis c o n n e c t e d on ce t h e co n v ersio n b e g i n s . th e c o n t r o l l o g i c a nd t h e cha r ge r e dist r i b u t i on d a cs a r e us e d to add and subt r a c t f i x e d a m ou n t s of ch ar ge f r om t h e s a m p l i ng c a p a c i tor a r ra ys t o b r in g th e com p a r a t o r bac k in t o a b a lan c e d con d i t ion. w h en t h e com p a r a t o r is r e b a lance d , t h e con v ersio n is co m p le t e . the c o n t r o l l o g i c g e n e r a t e s t h e ad c s o u t p u t co de . th e o u t p ut im p e dan c es o f t h e s o ur ces dr i v in g t h e v in + and th e v in C pi ns m u s t b e ma t c h e d o t her w is e t h e tw o in p u ts wi l l ha v e dif f er en t s e tt l i n g t i me s , re su lt i n g i n e r ror s . f i g u re 21. a d c co nvers i on p h as e adc tr ans f er func tion the o u t p u t co din g f o r th e ad79 34-6 is ei t h er s t ra ig h t b i na r y o r t w o s co m p lem e n t , d e p e n d in g o n th e s t a t us o f th e co d i n g b i t in t h e con t r o l r e g i s t er . the desig n e d co de t r a n si t i o n s o c c u r a t s u cces si v e lsb val u es (i .e . 1ls b , 2ls b s, et c.) and t h e ls b size is v ref /4096 . th e ideal tra n sf er c h a r ac t e r i s t ics o f th e ad7934 -6 f o r bo th s t ra ig h t b i na r y a n d twos co m p lem e n t o u t p u t co din g a r e s h own in f i gur e 22 a n d f i g u r e 23 r e s p ec ti ve l y . f i g u re 22. a d 7 9 3 4 - 6 ide a l t r ans f e r ch ar ac te ris t i c w i t h st r a ig ht b i n a r y ou t p u t c o d i n g
prelim inary technical data ad7934-6 rev. pr b | page 17 of 27 anal og input struc t ure f i gur e 25 s h o w s th e e q ui valen t cir c ui t o f th e a n alog in p u t s t r u c t ur e o f th e ad7934-6 in dif f er en tial/p s e udo dif f er en tial m o de. i n sin g le en d e d m o de, v in is in t e r n a l ly t i e d t o a g nd . the fo ur dio d es p r o v ide es d p r o t e c t i o n fo r t h e a n alog in p u t s . c a r e m u s t be ta k e n t o en s u r e tha t t h e a n alog in p u t sig n als nev e r exceed the s u p p l y ra ils b y m o r e tha n 300mv . this wil l c a us e t h es e dio d es to b e come fo r w a r d b i a s e d a nd st ar t co n d uc t i n g in t o t h e subs t r a t e . th es e dio d es ca n cond uc t u p t o 10ma wi t h o u t c a usin g ir r e v e rsi b le dama ge t o t h e p a r t . the c a p a ci t o rs c1, in f i gur e 25 a r e typ i cal l y 4p f a n d can pr i m ar i l y b e att r ibute d to pi n c a p a c i t a nc e. t h e re s i s t or s are l u m p e d com p on e n ts made u p o f t h e o n -r esis t a n c e o f t h e swi t ch es. th e va l u e o f th es e r e sis t o r s is typ i cal l y a b o u t 100. the c a p a ci t o rs, c2, a r e t h e ad c s s a m p li n g c a p a ci t o rs an d ha v e a c a p a ci tance o f 16pf typ i cal l y . f i g u re 23. a d 7 9 3 4 - 6 ide a l t r ans f e r ch ar ac te ris t i c w i t h t w os co mp le ment ou t p u t c o d i n g t y p i c a l c o nnec t i o n di a g r a m f i gur e 24 s h o w s a typ i cal co nn e c tio n dia g ram f o r th e ad7934- 6. th e a g nd and d g nd pin s a r e co nn e c t e d tog e t h er a t t h e de vice fo r g o o d n o is e s u p p r es si o n . th e v refin /v refo ut pi n i s deco u p led t o a g nd wi th a 0.4 7 f ca p a ci t o r t o a v o i d n o is e p i ck u p if t h e i n ter n a l r e fer e n c e is us e d . a l t e r n a t iv e l y , v refin /v refo ut can b e c o n n e c te d to a e x te r n a l re fe re nc e s o u r c e a nd i n t h is ca s e t h e r e fer e n c e p i n sh o u ld b e de c o u p le d wi t h a 0.1f ca p a ci t o r . i n bo th c a s e s t h e analog in p u t ra n g e can ei t h er be 0v t o v ref (r a n g e b i t = 0) or 0v t o 2 x v ref (r a n g e b i t = 1). the a n a l o g in pu t co nf igur a t ion can b e e i t h er 4 sin g le e n de d in p u ts, 2 dif f er en t i al p a irs o r 2 p s eudo dif f er en t i al p a irs (s e e ta b l e 7 ) . t h e v dd p i n is co nn ec ted t o ei t h er a 3 v o r 5v s u p p l y . the v o l t a g e a p plie d t o t h e v dr iv e in p u t co n t r o ls t h e v o l t a g e o f t h e dig i t a l in t e r f ace an d h e r e , i t is co nne c t e d t o t h e s a me 3v su p p ly of t h e m i c r op ro c e ss or to a l l o w a 3 v l o g i c in te r f ac e ( s e e th e di gi t a l i n p u ts secti o n ) . f o r a c a p pl i c a t i o ns , re mov i ng h i g h f r e q u e nc y c o m p o n e n t s f r om t h e a n a l o g in p u t sig n a l is r e co mmende d b y t h e us e o f a n rc lo w-p a s s f i l t er on t h e r e le v a n t analog in p u t pins. i n a p pli c a t io ns w h er e ha r m oni c dis t o r t i o n and sig n al t o n o is e ra t i o a r e cr i t ical, t h e a n a l o g in p u t sh o u l d b e dr i v en f r o m a lo w i m p e dance s o urce. l a rg e s o ur ce i m p e dan c es wi l l si g n if ica n t l y a f fe c t t h e ac p e r f o r ma n c e o f t h e ad c. this ma y ne ces s i t a t e t h e us e o f a n in p u t b u f f er a m plif ier . th e ch o i ce o f t h e o p am p wi l l b e a f u n c t i on o f t h e p a r t ic u l a r a p plica t ion. f i g u re 25. equiv a le nt a n al og input c i rcuit . conve r s i o n p h as e swit c hes o p en t r a c k p h ase s w itch es cl osed w h en n o am pli f ier is us e d t o dr i v e t h e a n alog in p u t, t h e s o ur ce im p e dan c e sh ou ld be limi t e d to lo w val u es. the maxim u m s o ur ce im p e dance w i l l dep e nd o n t h e am o u n t o f t o t a l h a r m on i c d i st or t i on ( t h d ) t h a t c a n b e to l e r a te d. t h e t h d wil l in cr eas e as th e s o ur ce im p e dan c e in cr eas e s a nd p e r f or m a nc e w i l l d e g r a d e. f i g u re 2 6 show s a g r aph of t h e t h d v e r s us a n alog i n p u t si gn al f r eq uen c y f o r d i f f er en t so ur ce im p e d a n c es fo r b o t h v dd = 5 v a nd 3 v . f i g u re 24. t y pic a l conne c t io n d i ag r a m
ad7934-6 prelim inary technical data rev. pr b | page 18 of 27 f i gure 28. sing le en ded mod e connection d i agr a m f i g u re 26. th d v s a n al og input f r eque nc y f o r v a r i ous s o u r c e impedan c es differential m o de f i g u re 2 7 show s a g r a p h of t h d ve r s u s an a l o g i n put f r e q u e nc y f o r va r i o u s s u p p lies, while s a m p lin g a t 625 ks ps wi t h an scl k o f 10 mh z. i n t h is cas e the s o u r ce im p e dan c e is 10?. the ad7934-6 ca n ha v e 2 dif f er en tial analog i n p u t p a irs b y s e t t in g t h e m o d e 0 a nd m o d e 1 b i ts in t h e con t r o l r e g i s t er t o 0 and 1 re sp e c t i ve ly . dif f er en tial sig n als ha v e s o m e be n e f i ts o v er sin g le ende d sig n als in cl u d in g n o is e imm u n i ty b a s e d o n t h e d e vice s co m m o n m o d e re j e c t i o n a n d i m prove m e n t s i n d i s t or t i on p e r f or m a nc e. f i g u re 29 def i n e s t h e f u l l y dif f er en tial a n alog in p u t o f th e ad7934-6 . f i g u re 27. th d v s a n al og input f r eque nc y f o r v a ri ous su p p ly v o lt ag es the anal og inpu t s the ad7934-6 has s o f t wa r e s e l e c t a b le a n alog in p u t co nf igur a t io n s . the us er can cho o s e ei t h er 4 si n g le ende d i n p u ts, 2 f u l l y dif f er en t i al p a irs o r 2 p s eudo dif f er en t i al p a irs. the a n a l og in pu t co nf igura t ion is ch os e n wi t h t h e mo d e 0/mo d e 1 b i ts in t h e in t e r n al c o n t r o l r e g i s t er (s e e t a ble 7). f i g u re 29. d i f f e r e nt ia l input d e f i nit i on the am pli t ude o f t h e dif f er en t i al sig n al is t h e dif f er en ce be tw e e n t h e sig n als a p p l ie d t o th e v in+ and v inC p i n s in eac h dif f er en t i al p a ir (i .e . v in+ C v in- ). v in+ and v in- sho u ld be sim u l t an e o us l y dr i v en b y tw o sig n als e a c h o f a m p l i t ude v ref tha t a r e 180 o u t o f p h as e . th e a m p l i t ude o f t h e dif f er en tial sig n al is t h er efor e Cv ref to + v ref peak-t o-pea k (i .e . 2 x v ref ). this is r e ga r d le ss o f t h e co m m o n m o de (cm). the co m m on m o de is t h e a v e r a g e o f t h e tw o sig n als, i . e . (v in+ + v in- )/2 a nd is t h er efo r e t h e v o l t a g e t h a t t h e two in p u ts a r e cen t er e d on. this re su l t s in t h e sp an of e a ch i n p u t b e i n g c m v re f /2. this v o l t a g e has t o b e s e t u p ext e r n a l l y a n d i t s ra n g e va r i es wi t h v ref . a s t h e val u e o f v ref in cr e a s e s, t h e comm o n m o de ra n g e de cr e a s e s. w h e n dr i v in g t h e i n p u ts wi t h a n a m plif ier , t h e ac t u a l co m m o n m o de ra n g e w i l l b e de t e r m ine d b y t h e a m plif ier s output vo lt ag e s w i n g . s i ngle ende d mo de the ad7934-6 ca n ha v e 4 sin g le ended a n alog in p u t c h a n ne ls b y s e t t in g t h e mo d e 0 a n d mod e 1 b i ts in t h e co n t r o l r e g i s t er b o t h t o 0. i n a pplica t ion s w h ere t h e sig n a l s o u r ce has a hig h im p e d a n c e , i t is r e co mme n d e d to b u f f er t h e a n a l og in p u t b e fo r e a p p l yin g i t t o the ad c. th e a n a l og in p u t ra n g e ca n be ei t h er 0 to v ref o r 0 t o 2 x v ref . i f th e a n alog in p u t si gn al t o be sa m p le d i s b i po la r , th e i n t e rn al r e f e r e n c e o f th e ad c c a n be us ed t o ext e r n al l y b i as u p this sig n al t o ma k e i t o f th e co r r ec t f o r m a t f o r th e ad c. f i gur e 28 s h o w s a typ i cal co nn e c tio n dia g ram when op era t in g t h e ad c in si ng le en d e d m o de.
prelim inary technical data ad7934-6 rev. pr b | page 19 of 27 f i gur e 30 a nd f i gur e 31 s h o w ho w th e co mm on m o de ran g e typ i cal l y va r i es wi t h v ref fo r b o t h a 5 v and a 3 v p o w e r su p p ly . the co mm on mo de m u st b e in t h is ra n g e t o guara n t e e t h e f u n c tio n al i t y o f th e ad7934-6 . u s i n g an o p am p p a i r an o p a m p p a ir ca n be us e d t o dir e c t l y co u p le a dif f er en t i al sig n al t o o n e o f th e a n alog in p u t p a irs o f th e ad7934-6. th e cir c ui t co nf igur a t io n s sh own in f i gur e 32 a nd f i gur e 33 sh o w h o w a d u a l o p am p can b e us e d t o co n v er t a si ng le-e n d e d sig n a l in t o a dif f er en t i a l sig n a l fo r b o t h a b i p o la r an d uni p ol a r in p u t s i g n a l , re sp e c t i v e ly . w h en a con v ersio n t a k e s pl ace , t h e comm o n mo de is r e je c t e d r e su l t in g i n a vi r t ua l l y n o is e f r e e sig n a l o f a m pl i t ud e Cv ref to +v ref co r r es p o n d in g t o t h e dig i tal co des o f 0 t o 4096. the v o l t a g e a p plie d t o p o i n t a s e ts u p t h e co mm on- m o d e vol t a g e. i n b o t h di a g r a m s , i t is c o nn e c te d in s o m e wa y to t h e r e fer e n c e , b u t an y val u e i n t h e co mm o n - m o d e ra n g e can b e i n p u t h e r e t o se t u p th e co mm o n m o d e . a s u i t a b le d u al o p a m p t h a t co u l d b e us e d i n t h is co nf ig ur a t io n to p r o v i d e dif f er en t i a l dr i v e t o the ad7934-6 is th e ad8022. t a k e ca r e w h en ch o o sin g t h e o p a m p; t h e s e le c t i o n dep e nds o n t h e re qu ire d p o we r su p p ly and s y ste m p e r f or manc e obj e c t ive s . the dr i v er cir c ui ts i n f i gur e 32 a nd f i gur e 33 ar e o p t i mi ze d fo r dc co u p lin g a p plica t ion s r e q u ir i n g b e st dist o r t i o n p e r f o r ma n c e. the cir c ui t conf igura t io n s h own in f i gur e 32 co n v er ts a uni p ol a r , sin g le-en d e d sig n al in to a dif f er en tial sig n al . f i gure 30. input co mm on mode rang e versus v ref (v dd =5v a n d v ref ( m ax ) = 3.5v ) the cir c ui t conf igura t io n in f i g u r e 33 is co nf igur e d t o co n v er t a nd le ve l s h if t a sin g le-e n d e d , g r o u n d -r ef er en c e d (b i p ola r ) si gn al t o a d i f f er en t i al si gn al cen t er ed a t t h e v ref l e vel of t h e ad c. f i g u re 31. input co mm on mode rang e versus v ref (v dd =3 v an d v ref (m ax)=2. 2v ) f i gure 3 2 . dua l o p a m p cir c ui t to co nv er t a single-ended uni p ola r si gna l int o a d i f f e r e nt ia l s i g n a l driv in g differen tial in p u ts dif f er en t i a l op e r a t io n r e q u ir es t h a t v in + an d v in - be sim u l t an eo us l y dr i v en wi t h tw o eq ual sig n als tha t a r e 180 o u t o f p h as e . th e comm on m o de m u s t be s e t u p exter n al l y a n d has a ra n g e w h ich is det e r m i n e d b y v ref , t h e p o we r su p p ly and t h e p a r t ic u l a r a m pli f ier us e d t o dr i v e t h e a n alog in pu ts. dif f er en t i al m o de s o f o p era t io n wi t h ei t h er a n ac o r dc i n p u t, p r o v ide t h e b e st t h d p e r f or m a nc e ove r a w i d e f r e q u e nc y r a nge. si nc e not all a p p l i c a t i o n s h a v e a si g n al p r eco n d i ti o n ed f o r d i f f er en ti al o p er a t ion, t h er e is o f ten a ne e d to p e r f o r m sin g le en d e d to dif f er en t i al co n v ersio n . f i gure 3 3 . dua l o p a m p cir c ui t to co nv er t a single -ende d bipolar sign al into a d i f f e r e nt ia l s i g n a l
ad7934-6 prelim inary technical data rev. pr b | page 20 of 27 pseudo differential mode the ad7934-6 ca n ha v e 2 p s eu do dif f er en tial p a irs b y s e t t in g th e m o d e 0 and m o d e 1 b i ts in the co n t r o l r e g i s t er t o 1, 0 re sp e c t i vely . v in + is co nn e c te d to t h e sig n a l s o ur ce w h ich m u st ha ve an am pli t u d e o f v ref t o mak e us e o f t h e f u l l d y na mic ran g e o f t h e p a r t . a d c in p u t is a p pli e d t o t h e v in C pin. th e v o l t a g e a p pl i e d to t h i s i n put prov i d e s a n of f s e t f r om g r ou nd or a p s e u d o gr o u n d f o r th e v in + in p u t. the b e n e f i t o f ps eu do dif f er en t i al in p u ts is tha t they s e p a ra te the a n alog in p u t sig n al g r o u n d f r om t h e ad c s g r o u nd al lo win g d c co mm on m o de v o l t a g es t o b e can c e l le d . f i gur e 34 s h o w s a conn ec t i o n dia g ram f o r p s eudo dif f er en t i al m o de . f i g u re 35. no r m a l m u lt ic hann el o p er at io n f l o w c h a r t using th e s e quenc e r conse c uti v e s e qu enc e ( s eq0 =1, s e q1 = 1) a seq u en ce o f co n s ecu t i v e c h a n n e l s ca n be co n v e r t e d o n b e g i n n i ng w i t h ch an nel 0 a n d e n d i ng w i t h a f i n a l ch an nel s e le c t e d b y wr i t in g t o t h e add 1 a nd add0 b i t s in t h e c o n t r o l r e g i st er . this is do ne b y s e t t in g t h e s e q0 and seq1 b i ts in t h e co n t r o l r e g i s t er bo th t o 1. on ce th e con t r o l r e g i s t er has been w r it te n to to s e t t h i s mo de up , t h e ne x t c o n v e r s i on w i l l b e on c h a n n e l 0, t h en c h a n n e l 1 and s o o n un til t h e cha n n e l s e le c t e d b y t h e addr es s b i ts (ad d 1 a nd ad d0) is r e ache d . th e ad c w i l l t h e n re t u r n to ch an nel 0 a n d st ar t t h e s e qu e n c e ag ai n . t h e wr in p u t m u s t be k e p t hig h t o en sur e tha t t h e c o n t r o l r e g i s t er is n o accide n t a l ly o ver wr i t te n and t h e s e q u e n c e in ter r u p te d . this p a t t er n wil l co n t in ue un ti l s u c h tim e as the ad7934-6 is w r itte n to . f i g u re 3 6 show s t h e f l ow ch ar t of t h e c o ns e c ut ive se q u e n c e m o d e . f i g u re 34. p s eud o d i f f e r e nt ia l m o de conne c t io n d i ag r a m anal og input selec t ion a s sh o w n i n t a b l e 7, t h e us er c a n s e t u p t h e i r analog in p u t co nf igura t io n b y s e t t in g t h e va lues in t h e mode0 a nd mode1 b i ts in t h e c o n t r o l reg i s t er . a s sumin g t h e co nf i g ura t io n has b e e n ch os en, t h er e a r e tw o dif f e r en t w a ys o f s e le c t in g t h e a n alo g in p u t t o b e con v er t e d o n dep e n d in g on t h e s t a t e o f t h e s e q0 an d se q 1 bit s i n t h e c o n t ro l re g i ste r . normal m u lticha nnel o p er at ion (seq0=seq1= 0) a n y on e of f o u r an a l o g i n put ch an n e l s or 2 p a i r s of ch an n e l s m a y b e se lected f o r co n v er si o n i n a n y o r d e r b y set t in g t h e s e q 0 s e q1 b i ts i n t h e c o n t r o l r e g i s t er b o t h t o 0. th e chann e l t o b e co n v er t e d o n is s e le c t e d b y wr i t in g t o t h e addr es s b i ts ad d1 a nd add0 i n t h e c o n t r o l r e g i s t er t o p r og ra m t h e m u l t i p lexer p r io r t o t h e con v ersio n . this mo de o f o p era t ion is o f a n o r m a l m u l t icha nne l a d c w h er e e a ch da t a wr i t e s e le c t s t h e n e xt ch an nel f o r c o n v e r s i on . f i g u re 3 5 show s a f l ow ch ar t of t h i s m o d e o f o p er a t i o n. t h e channel co nf igur a t io n s a r e sh own i n ta b l e 7 . f i gure 36. cons ecu tive s e qu ence m o d e f l o w ch a r t
prelim inary technical data ad7934-6 rev. pr b | page 21 of 27 ther efo r e , w h e n o p era t in g a t v dd = 5 v , t h e val u e o f v ref ca n ra n g e f r o m 100mv t o a maxim u m val u e o f 3.5 v . w h en v dd = 4.75 v , v ref max = 3.17 v . reference sec t ion the ad7934-6 ca n op era t e wi t h ei t h er t h e o n c h i p r e f e r e n c e or an e x te r n a l re f e re nc e. t h e i n te r n a l re f e re nc e i s s e l e c t e d by s e t t i n g t h e ref b i t in t h e in t e r n al c o n t r o l r e g i s t er t o 1. a b l o c k d i ag r a m of t h e i n te r n a l re f e re nc e c i rc u i t r y i s sh ow n i n f i g u re 37. th e in t e r n al r e f e r e n c e cir c ui tr y in c l udes a n o n -c hi p 2.5 v b a n d g a p re f e re nc e, a n d a re f e re nc e bu f f e r . w h e n u s i n g t h e i n te r n a l re f e re n c e t h e v refin /v re f o u t p i n s h o u ld be de co u p le d to a g nd wi th a 0 . 47f ca p a ci t o r . this in t e r n al r e f e r e n c e n o t o n l y p r o v ides t h e r e fer e n c e fo r t h e analog t o dig i t a l co n v ersio n b u t ca n als o b e us e d ext e r n al l y in t h e syst em. i t is re co mm e n de d t h a t t h e r e fer e nce o u t p u t is b u f f er e d usin g a n ex t e r n al p r e c isio n op am p b e f o re app l y i ng it a n y w he re i n t h e s y ste m . e x am pl e 2: v in ma x = v dd + 0. 3 v in ma x = v ref + v ref /2 if v dd = 3.6v the n v in m a x = 3.9 v ther efo r e 3xv re f /2 = 3. 6 v v ref max = 2.6 v a a v = 3 v a v ref a a m mv a maxm m a 2.v . v = 2.35 v v ref max = .6 v . a a a a m a v = v ref . f m m m a ma a . m a max m m a a a v = .3 v a v .3 v . f 3. a r a a m xa m a maxm m a 36 a a a v . a a x a a a v ref v ref 36. x a ref a . a x a v ref v ref a .f a a . a a m x a a . v 3.5v a a a m x a a .v v . 2 . 5 v v = 2. v 5.25 v a v v 2. v . ma a a a f . a a a a a m m m a a . e a 36 a a a a a . a xa m a a a a a a a a m a a f 3 a a a am a x a . m a a a max m m aa a v max a a v .3v m maxm m a . a m a v ref v v . a . exa m a va r r a a va a max 2.53 . r 2 2 . 5 . 5 r 2 2 . . 5 5 xa m a a max m m v ref a a a 3 6 a m a v 5 v a 3 v . e x am v ma x = v . 3 v ma x = v ref v ref 2 v = 5 v v m a x = 5.3 v 3xv re f 2 = 5. 3 v f 3. a v ref a m v ref max = 3.5 v
ad7934-6 preliminary technical data rev. prb | page 22 of 27 digital inputs the digital inputs applied to the ad7934-6 are not limited by the maximum ratings which limit the analog inputs. instead, the digital inputs applied can go to 7v and are not restricted by the av dd +0.3v limit as on the analog inputs. another advantage of the digital inputs not being restricted by the av dd + 0.3 v limit is the fact that power supply sequencing issues are avoided. if any of these inputs are applied before av dd then there is no risk of latch-up as there would be on the analog inputs if a signal greater than 0.3 v was applied prior to av dd. v drive input the ad7934-6 has a v drive feature. v drive controls the voltage at which the parallel interface operates. v drive allows the adc to easily interface to 1.8v, 3 v and 5 v processors. v drive of 1.8 v can only be used if v dd = 2.35 v to 3.6 v. an example is, if the ad7934-6 was operated with an av dd of 5v, and the v drive pin could be powered from a 3v supply, the ad7934-6 has better dynamic performance with an av dd of 5v while still being able to interface to 3v processors. care should be taken to ensure v drive does not exceed av dd by more than 0.3 v. (see absolute maximum ratings section). parallel interface the ad7934-6 has a flexible, parallel interface. this interface is 12-bits wide and is capable of operating in either word (w/ b tied high) or byte (w/ b tied low) mode. the convst signal is used to initiate conversions and when operating in auto shutdown or auto standby mode, it is used to power up the adc. a falling edge on the convst signal is used to initiate conversions and it also puts the adc track and hold into track. once the convst signal goes low, the busy signal goes high for the duration of the conversion. in between conversions, convst must be brought high for a minimum time of t 1 . this must happen after the 14 th rising edge of clkin otherwise the conversion will be aborted and the track and hold will go back into track. at the end of the conversion, busy goes low and can be used to activate an interrupt service routine. the cs and rd lines are then activated in parallel to read the 12-bits of conversion data. when power supplies are first applied to the device, a rising edge on convst puts the track and hold into track. the acquisition time must be allowed before convst is brought low to initiate a conversion. the adc will then go into hold on the falling edge of convst and back into track on the 13 th rising edge of clkin after this. see figure 4. when operating the device in auto shutdown or auto standby mode, where the adc powers down at the end of each conversion, a rising edge on the convst signal is used to power up the device. reading data from the ad7934-6 with the w/ b pin tied logic high, the ad7934-6 interface operates in word mode. in this case, a single read operation from the device accesses the conversion data word on pins db0 to db11. the db8/hben pin assumes its db8 function. with the w/ b pin tied to logic low, the ad7934-6 interface operates in byte mode. in this case, the db8/hben pin assumes its hben function. conversion data from the ad7934-6 must be accessed in two read operations with 8 bits of data provided on db0 to db7 for each of the read operations. the hben pin determines whether the read operation accesses the high byte or the low byte of the 12-bit word. for a low byte read, db0 to db7 provide the 8 lsbs of the 12-bit word. for a high byte read, db0 to db3 provide the 4msbs of the 12-bit word. db4 of the high byte is always zero and db5 and db6 of the high byte provide the channel id. figure 4 shows the read cycle timing diagram for a 12-bit transfer. when operated in word mode, the hben input does not exist and only the first read operation is required to access data from the device. when operated in byte mode, the two read cycles shown in figure 5 are required to access the full data word from the device. the cs and rd signals are gated internally and level triggered active low. in either word mode or byte mode, cs and rd may be tied together as the timing specification t 10 and t 11 is 0ns min. the data is placed onto the data bus a time t 13 after both cs and rd go low. the rd rising edge can be used to latch data out of the device. after a time, t 14 , the data lines will become three- stated. alternatively, cs and rd can be tied permanently low and the conversion data will be valid and placed onto the data bus a time t 9 before the falling edge of busy. writing data to the ad7934-6 with w/ b tied logic high, a single write operation transfers the full data word on db0 to db11 to the control register on the ad7934-6. the db8/hben pin assumes its db8 function. data to be written to the ad7934-6 should be provided on the db0 to db11 inputs with db0 being the lsb of the data word. with w/ b tied logic low, the ad7934-6 requires two write operations to transfer a full 12-bit word. db8/hben assumes its hben function. data to be written to the ad7934-6 should be provided on the db0 to db7 inputs. hben determines whether the byte which is to be written is high byte or low byte data. the low byte of the data word has db0 being the lsb of the full data word. for the high byte write, hben should be high and the data on the db0 input should be data bit 8 of the 12-bit word. figure 2 shows the write cycle timing diagram of the ad7934-6. when operated in word mode, the hben input does not exist and only the one write operation is required to write the word of data to the device. data should be provided on db0 to db11. when operated in byte mode, the two write cycles shown in
prelim inary technical data ad7934-6 rev. pr b | page 23 of 27 f i gur e 3 a r e r e q u ir e d t o wr i t e t h e f u l l da t a w o rd t o t h e a d 793 4- 6. i n f i gur e 3 th e f i r s t w r i t e tra n sf e r s th e lo w e r 8 b i ts o f th e da ta w o r d f r o m db0 to db7 a nd t h e s e co nd wr i t e t r a n sfers t h e u p p e r 4 b i ts o f t h e da ta w o r d . w h en wr i t in g to th e ad7934-6 , th e t o p 4 b i ts in the hig h b y t e mu s t b e 0 s . the cs and wr sig n als a r e ga t e d in t e r n al l y . cs and wr ma y b e ti ed t o g e t h e r a s th e tim i n g s p ecif i c a t i o n f o r t 4 a nd t 5 is 0n s m i n. the da t a is l a t c h e d i n t o t h e de v i ce o n t h e r i sin g e d g e o f wr . t h e d a t a n eeds t o be set u p a tim e t 7 be f o r e t h e wr ri s i n g ed g e a nd h e ld fo r a t i m e t 8 af te r t h e wr risin g ed g e . po wer modes of oper a t ion the ad7934-6 has f o ur dif f er e n t p o w e r m o des o f o p era t io n. th e s e m o des a r e desig n e d t o p r o v ide f l exi b le p o w e r m a n a ge me n t opt i ons . d i f f e r e n t opt i ons c a n b e c h o s e n to o p timize t h e p o w e r d i s s i p a t io n/thr o ugh p u t ra t e ra tio f o r dif f er in g a p plic a t io n s . t h e m o d e o f o p era t io n is s e le c t e d b y t h e p o w e r ma na ge m e n t b i t s , pm1 a nd pm0, in t h e c o n t r o l r e g i ste r , as deta ile d in t a b l e 6. a t p o w e r o n r e s e t, the def a u l t p o w e r u p co ndi t i on is n o r m a l m o de. normal mo de ( p m1 = pm 0 = 0) this m o d e is in t e nde d fo r t h e f a st est t h r o ug h p u t ra t e p e r f o r ma n c e as t h e us er do es no t ha v e t o w o r r y a b o u t an y p o w e r u p tim e s as the ad7934-6 r e ma in s f u l l y p o w e r e d u p a t al l tim e s. a t p o w e r o n r e s e t, this m o de is t h e defa u l t s e t t in g in t h e c o n t ro l re g i ste r . autos h utdo wn ( p m1 = 0; pm 0 = 1) i n this m o de o f o p era t ion, th e ad7934-6 a u t o ma tical l y en t e rs f u l l sh u t down a t t h e e nd o f e a ch con v ersio n w h ich is sh o w n a t p o in t a in f i gure 4. i n sh u t down m o de , al l in t e r n al cir c ui tr y o n t h e d e vice is p o w e r e d do w n . t h e p a r t r e t a in s in fo r m a t io n in t h e c o n t ro l re g i ste r d u r i ng shutd o w n . i t re m a i n s i n shutd o w n mo d e u n t i l t h e ne x t r i s i ng e d g e of co n v s t (s e e p o in t b in f i gur e 4). on this r i sin g edg e , the p a r t wil l beg i n t o p o w e r u p a nd t h e p o w e r u p t i me wi l l de p e nd on w h et h e r t h e us er is o p era t i n g wi t h t h e i n t e r n al o r e x t e r n al r e fer e n c e . w i t h t h e in t e r n al r e f e r e nce , th e p o w e r u p time is typ i cal l y tb d and wi t h a n ext e r n al r e f e r e n c e , t h e p o w e r u p tim e is typ i cal l y tb d . the us er s h o u ld ensur e t h a t t h e p o w e r u p t i me has e l a p s e d b e fo r e ini t i a t i n g a con v ersio n . auto s t a n db y ( p m1 = 1 ; pm 0 = 0) i n this m o de o f o p era t ion, th e ad7934-6 a u t o ma tical l y en t e rs s t a n d b y m o de a t th e en d o f ea ch co n v e r s i o n . w h en th i s m o d e is en t e r e d , al l cir c ui tr y o n th e ad7934-6 is p a r t ial l y p o w e r e d do wn. a r i sin g e d ge o n co n v s t wil l p o w e r u p th e de vice wh i c h will ta k e a t lea s t tb d . f u ll s h utdo wn mo de ( p m1 =1 ; pm0 = 1) w h en this m o de is en t e r e d , al l cir c ui tr y o n th e ad7934-6 is p o w e r e d do w n . the p a r t r e t a in s t h e i n fo r m a t ion in t h e c o n t r o l reg i st er d u r i n g th e f u l l s h u t do wn. th e ad793 4-6 r e ma in s in f u l l sh u t do wn m o d e un t i l t h e p o w e r ma na ge m e n t b i t s (pm1 a nd pm0) i n t h e c o n t r o l reg i s t er a r e cha n g e d . i f a wr i t e t o t h e c o n t r o l r e g i s t er o c c u rs w h i l e t h e p a r t is in f u l l sh u t down m o d e , an d t h e p o w e r m a na ge men t b i t s a r e chan ge d to pm0 = pm1 = 0, i . e . n o r m al m o de , th e p a r t wil l b e g i n to p o w e r u p o n th e co n v s t r i sin g edg e . t o en s u r e t h e p a r t is f u l l y p o w e r e d u p bef o r e a con v ersio n is ini t ia ted , the p o w e r u p time , tb d , s h o u ld b e al lo w e d bef o r e th e co n v s t fa l l in g e d ge , o t h e r w is e , i n val i d da ta w i ll be r e ad . po wer v s . throug hput r a te a b i g ad van t a g e o f p o w e r i n g t h e ad c do w n a f t e r a con v ersio n is t h a t t h e p o w e r co n s um p t ion o f t h e p a r t is sig n if ican t l y r e d u ce d a t lo w e r t h r o ug h p u t ra t e s. w h e n usin g t h e dif f er en t p o w e r m o des, t h e ad7934 -6 is o n l y p o w e r e d u p f o r th e d u ra t i on o f t h e co n v ersio n . the r efo r e , t h e a v erag e p o w e r co n s um p t io n p e r c y cle is sig n if ica n t l y r e d u c e d . f i gur e 39 a nd f i g u re 4 0 show pl ot s of p o we r v s . t h rou g h p ut w h e n op e r at i n g i n a u to sh u t do w n a nd a u to s t andb y m o des. f i gure 39. p o wer vs. throu g hput in au to s h utd o wn mod e f i gure 40. p o wer v s . thro ughput in au to st andby m o de . micr oprocessor interf a c ing a d 79 34- 6 t o a d s p -21xx in ter f a c e f i gur e 41 s h o w s th e ad7934-6 in t e r f ace d t o t h e ads p -21xx s e r i es o f ds p s as a m e m o r y ma p p ed de vic e . a sin g le wa i t s t a t e ma y b e n e ces s ar y t o in t e r f ace th e ad7934 -6 t o th e ads p -21xx dep e n d in g on t h e clo c k s p e e d o f t h e ds p . the wa i t s t a t e can b e p r og ra mm e d v i a t h e d a t a m e mo r y w a i t s t a t e c o n t r o l reg i s t er o f t h e a d s p -21 xx (ple as e s e e t h e ad s p -21xx f a mil y u s ers
ad7934-6 prelim inary technical data rev. pr b | page 24 of 27 m a n u a l fo r det a i l s). th e fol l o w in g in st r u c t io n re ads f r o m t h e ad7934-6: mr = d m (ad c ) w h er e ad c is th e addr es s o f th e ad7934 -6. f i g u re 41. int e r f a c i n g to t h e a d s p - 21x x a d 79 34- 6 t o a d s p -21 0 6 5 i n ter f a c e f i gur e 42 s h o w s a typ i cal in t e r f ace betw een t h e ad7934-6 and th e ads p -2106 5l s h arc p r o c es s o r . this in t e r f ace is a n exa m ple o f o n e o f t h r e e d m a ha n d s h a k e m o de s. th e ms x co n t r o l line is ac t u al l y thr e e m e m o r y s e le c t lin e s. i n t e r n al ad d r 25-24 a r e de co de d in to ms 3-0 , t h es e li n e s a r e t h e n as s e r t e d as c h i p s e lec t s. the dm a r 1 (d ma r e q u es t 1) is us ed in this s e t u p as t h e in t e r r u p t t o sig n al end o f co n v ersion. th e r e s t o f th e in t e rfa c e i s sta n da r d h a n d s haki n g o p era t i o n. f i gure 4 2 . inter f acing t o th e ads p - 2 10 65 l a d 79 34- 6 t o t m s 3 2 0 2 0 , tms 3 2 0 c 2 5 a n d t m s 3 2 0 c 5 x inte r f a c e the p a ral l e l in ter f ace betw een th e ad7934-6 and the t m s32020, t m s320c25 a nd tms320c5x fa mil y o f ds p s a r e s h own in f i gure 43. the memo r y ma p p ed addr es s c h os en f o r th e ad7934-6 sh o u ld be ch os en t o fal l in t h e i/o m e m o r y s p ace o f t h e dsp s . the p a ral l e l in ter f ace o n t h e ad79 34-6 is fas t en o u g h t o in t e r f ace t o the t m s 32020 wi t h n o extra wa i t s t a t es. i f hig h sp ee d g l ue log i c s u c h as 74a s de vices a r e us ed t o dr i v e th e rd a nd t h e wr lines when in t e r f acin g t o the tms 320c25, t h e n ag ai n , no w a i t st a t e s are n e c e ss ar y . h o we ve r , i f sl owe r l o g i c is u s e d , d a t a ac c e ss e s ma y b e sl owe d su f f i c i e n t l y w h e n re ad ing f r o m a nd wr i t ing t o t h e p a r t t o r e q u ir e t h e in s e r t io n o f o n e wai t st a t e. e x t r a wait st a t e s wi l l b e ne c e ss ar y w h e n u s ing t h e t m s320c5x a t th eir fas t es t c l o c k s p e e ds. (p leas e s e e t h e t m s320c5x u s er g u ide f o r det a ils). d a t a is r e ad f r o m t h e a d c usi n g t h e fol l o w ing in st r u c t io n: in d , ad c w h er e d is d a t a m e m o r y addr ess an d t h e ad c is th e ad793 4- 6 addr ess. f i gur e 4 3 . inte r f ac ing t o the tms3 2020 / c 2 5 / c 5 x a d 79 34- 6 to 8 0 c 1 8 6 i n te r f a c e f i gur e 44 s h o w s th e ad7934-6 in t e r f ace d t o the 80c186 micr o p r o ces s o r . the 80c186 d m a co n t r o l l er p r o v ides tw o indep e n d en t hi g h s p e e d d m a cha n n e ls w h er e da t a t r an sfer can o c c u r betw een m e m o r y a nd i/o s p aces. e a c h da ta tran sf er co n s u m es t w o b u s c y cles , o n e c y cle t o fet c h da t a a nd t h e o t h e r t o s t o r e da t a . af t e r th e ad7934 -6 has f i nish e d a con v ersio n , the b u sy l i ne ge ne r a te s a dm a re qu e s t to c h an n e l 1 ( d rq 1 ) . as a r e s u l t o f t h e i n ter r u p t, t h e p r o c es s o r p e r f o r m s a d m a re ad o p era t ion w h ich a l s o r e s e ts t h e in t e r r u p t l a t c h. s u f f i cien t p r io r i ty m u s t b e as sig n ed t o th e d m a c h a n ne l to en s u r e tha t th e d m a r e q u es t will b e se r v i c ed be f o r e th e co m p le ti o n o f t h e ne x t c o n v e r s i on .
prelim inary technical data ad7934-6 re pr b pae 25 27 f i g u re 44. int e r f a c i n g to t h e 80c 18 6
ad7934-6 rev. prb | page 26 of 27 application hints grounding and layout the printed circuit board that houses the ad7934-6 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be easily separated. a minimum etch technique is generally best for ground planes as it gives the best shielding. digital and analog ground planes should be joined in only one place and the connection should be a star ground point established as close to the ground pins on the ad7934-6 as possible. avoid running digital lines under the device as this will couple noise onto the die. the analog ground plane should be allowed to run under the ad7934-6 to avoid noise coupling. the power supply lines to the ad7934-6 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never run near the analog inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this will reduce the effects of feedthrough through the board. a microstrip technique is by far the best but is not always possible with a doublesided board. in this technique the component side of the board is dedicated to ground planes while signals are placed on the solder side. good decoupling is also important. all analog supplies should be decoupled with 10f tantalum capacitors in parallel with 0.1f capacitors to gnd. to achieve the best from these decoupling components, they must be placed as close as possible to the device.
prelim inary technical data ad7934-6 rev. pr b | page 27 of 27 outline dimensions f i g u re 45. 2 8 l e ad t ssop p a ckag e d i mens ions d i mensions sh o w n in inc h es and mm ordering guide model range linearity error (lsb) 1 package option package descri ptions aD7934-6BRU C40c to +85c 1 ru-32 tssop eval-adxxxxcb 2 evaluation bo ar d eval-control brd2 3 controll er boar d 1 linearity error her e re fer s to integral linearity error. 2 th i s ca n be u s ed a s a st a n d- a l on e eva l ua t i on boa r d or i n c o njunctio n wit h th e e v a l uatio n bo ard c o ntro l l e r fo r e v al uatio n /d e m o n stration purpose s . 3 eva l ua t i on boa r d con t r ol ler. th i s boa r d i s a c o m p let e un i t a llowi n g a p c t o c o n t r ol a n d com m u n i ca t e wi t h a ll an a l og d e vi ce s ev al uation boards en di n g i n t h e cb d e si gn a t ors. th e fo ll o w i n g n eeds t o b e o r der e d t o obt a i n a c o m p let e eva l ua t i on ki t : t h e ad c eva l ua t i on boa r d ( eval adxxxxcb ) , t h e eval- c on tr ol br d 2 a n d a 12 v a c t r a n sform er . s e e t h e ad xx xx eva l ua t i on boa r d t e ch n i ca l n o t e f o r m o re det a i l s . 2004 a n al o g de v i ce s , i n c . al l rig h t s r e s e r v e d . t r ad emark s and reg i ste r e d tr ad emar k s ar e t h e p r op e r t y of t h e i r r e sp e c tive c o m p ani e s . p r in t e d in t h e u . s. a .

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