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ordering number : ena1746 bi-cmos ic for home stereo system 1-chip tuner ic incorporating pll lv23401v overview the lv23401v is a am/fm one-chip tuner ic for home stereo system. functions ? am tuner ? fm tuner ? mpx stereo decoder ? fll tuning system features ? all the adjustment work of external parts is unnecessary. ? ccb control with easy command base ? external parts are reduced by low-if frequency (fm=225khz, am=53khz) adoption. ? the high sensitivity recep tion is achieved in low noise mix input circuit. ? all bands of japan-u.s.-euro can be received by the soft program change (76mhz to 108mhz). ? with built-in fll(frequency locked loop) tune function ? soft mute and stereo blend function (seven stages programmed control possible) ? with built-in adjacent channe l obstruction removal function ? with built-in stereo pilot cancellation function ? for en55020-s1 standard (european immunity) ? with built-in power save function specifications of any and all sanyo semiconductor co.,ltd . products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, charac teristics, and functions of the des cribed products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should al ways evaluate and test devices mounted in the customer ' s products or equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equi pment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extrem ely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use. 61610 sy 20100428-s00002 no.a1746-1/24
lv23401v no.a1746-2/24 specifications maximum ratings at ta = 25 c parameter symbol conditions ratings unit maximum supply voltage v cc max analog block supply voltage 10.0 v maximum output voltage v o max digital block supply voltage 4.5 v v in 1 max ce, di, cl *1) vref2+0.35 v maximum input voltage v in 2 max clk in 4.5 v allowable power dissipation pd max ta 70 c *2) 450 mw operating temperature topr -20 to +70 c storage temperature tstg -40 to +125 c *1) vref2 = 22 pin voltage *2) when mounted on the specified printed circuit board (114.3mm 76.1mm 1.6mm), glass epoxy operating condition at ta = 25 c parameter symbol conditions ratings unit recommended supply voltage v cc analog block supply voltage 9.0 v resister 1eh bit 1(levshif)=0 4.5 to 6.5 v operating supply voltage range v cc op resister 1eh bit 1(levshif)=1 8.5 to 9.5 v * stabilize the service voltage so as not to cause the voltage charge by the noise etc. interface block allowable operation range at ta = -20 to +70 c, v ss = 0v ratings parameter symbol conditions min typ max unit v i h1 ce, di, cl 2.3 3.435 v input ?h? level voltage v i h2 clk in 2.3 3.435 v v i l1 ce, di, cl 0 0.5 v input ?l? level voltage v i l2 clk in 0 0.3 v output voltage v o d0 0 4.0 v crystal frequency f in clk in 32.768 khz f devi1 for the standard european immunity -50 +50 ppm crystal frequency deflection f devi2 when standard non-corresponds european immunity -150 +150 ppm crystal vibrator load capacity cl * 4 12.5 pf * the evaluation request to the crystal ma ker is recommended because it changes by th e substrate and the circuit constant used. operating characteristics at ta = 25 c, v cc = 9.0v with the designated circuit. ratings parameter symbol conditions min typ max unit i cc fm no input in fm mode. 15 pin supply current. 25 35 45 ma current drain (at no input) i cc am no input in am mode. 15 pin supply current. 14 24 34 ma power save current drain i standby 15 pin supply current power save : register 1fh_bit0 = 0 0.25 0.7 ma v dd output voltage v dd 22 pin voltage (reference va lue) (2.772) 3.3 (3.435) v v dd drop-out voltage v dd _drop 22 pin voltage. drive mode at 10ma. *drive current maximum = 10ma 0.15 v [fm receive characteristics] : fc = 98mhz, v in = 60db v, fm = 1khz, de-emphasis = 50 s, if = 225khz, bw = 50% mono : 75khz dev. stereo : l+r = 67.5khz dev., pilot = 7.5khz dev. volume level = 3, soft mute = off, soft stereo = off, resister 1eh bit 1(levshif) = 1, 9 pin output, ihf-bpf s/n 50db sensitivity sn50 input level that becomes s/n=50db 17 24 db v s/n 30db sensitivity sn30 input level that becomes s/n=30db 12 18 db v ihf sensitivity ihf input leve l that becomes thd=3% 12 20 db v sn mono 62 70 db signal-to-noise ratio sn-st1 stereo 58 66 db thd1 mono 0.5 1.5 % thd1-st stereo 0.5 2.5 % thd2 mono, 150khz dev. 1.5 5 % total harmonic distortion thd3 mono, v in = 120db v 0.6 2.5 % continued on next page.
lv23401v continued from preceding page. ratings parameter symbol conditions min typ max unit v o 0 mono, v o l = 0 (reference value) (218) (327) (489) mvrms v o 1 mono, v o l = 1 (reference value) (291) (436) (652) mvrms v o 2 mono, v o l = 2 (reference value) (366) (549) (821) mvrms demodulation output v o 3 mono, v o l = 3 (reference value) *in-house management = typ 3.0db 518 775 1160 mvrms mpx output v o _mpx 6 pin output 100 200 300 mvrms channel balance cb 10 pin output / 9 pin output -1 0 +0 db sd operation level sd fs_s = 4 17 25 33 db v stereo operation level st fs_s = 4 17 25 33 db v stereo separation sep both channels of 9 pins and 10 pins are measured. *in-house management value 25db 25 40 db deemp50 fm = 10khz, 15khz lpf off -12.5 -10 -7.5 db de-emphasis deflection deemp75 fm = 10khz, 15khz lpf off -13 db carrier leakage cl stereo s/n, 15khz lpf off 30 40 db pilot margin (pilot lighting sensitivity) st-on l+r = 67.5khz, pilot-mod 0.6 5.5 % am suppression ratio amr 400hz am 30% mod. 40 65 db mute attenuation mute 60 75 db [am receive characteristics] : fc = 1mhz, v in = 94db v, fm = 400hz, 30% mod, if = 53khz, bw = 50% volume level = 3, soft mute = 4, resister 1eh bit 1(levshif) = 1, 9 pin output, 15khz lpf off sn20 input level that becomes s/n=20db 49 65 db v sn20-l fc = 603khz (reference value) (55) (65) db v s/n 20db sensitivity sn20-h fc = 1404khz (reference value) (49) (65) db v signal-to-noise ratio sn 42 50 db thd1 0.6 2.8 % total harmonic distortion thd2 v in = 104db v 0.8 2.8 % v o 0 vol = 0 (reference value) (55) (78) (109) mvrms v o 1 vol = 1 (reference value) (69) (98) (138) mvrms v o 2 vol = 2 (reference value) (87) (123) (173) mvrms detected output v o 3 vol = 3 110 155 218 mvrms channel balance cb 10 pin output / 9 pin output -1 0 +1 db agc1 input level difference that output level becomes -10db. soft mute = 3 (reference value) (52) (62) db agc response agc2 soft mute = 4 47 57 db frequency response hi-cut fm = 4khz -22 -17 -12 db sd operation level sd agc = on, fs = 4 *in-house management =46 to 65db v 46 54 65 db v mute attenuation mute 15khz lpf on 50 65 db package dimensions unit : mm 3191b sanyo : ssop30(275mil) 9.75 5.6 7.6 0.22 0.65 (0.33) 1 15 16 30 0.5 0.15 1.5max 0.1 (1.3) no.a1746-3/24
lv23401v no.a1746-4/24 pin function pin pin name description remark dc_bias 1 am ant am antenna it connects it to 2pin through the matching coil or the bar antenna. 2 am ref am reference voltage it connects it to 1pin through the matching coil or the bar antenna. 2.0v 3 am cap am capacitor bank it c onnects it to gnd through an external inductor of recommendation 240 h. 4 gnd1 am antenna gnd connect to gnd 5 vref1 analog reference voltage it connects it to gnd through the capacitor of 1 f. 6 mpx out detected output lc72725 and connection when rds is used 7 am agc am agc it c onnects it to gnd through the capacitor of 4.7 f 8 gnd2 analog gnd connect to gnd 9 l out l-ch audio output 10 r out r-ch audio output the dc level changes by setting resistor 1eh bit1 (levshif) to adjust the output level according to the v cc potential. 11 v cc low low voltage mode it is short with 15pin when using it with v cc < 6.0v or less. 12 am lcf am low cutting filt er it connects it to gnd th rough the capacitor of 0.047 f 13 sd out sd detecting phase output 14 st out st detecting phase output 15 v cc supply voltage 16 clk in reference clock input the crystal is recommended to be used. it is also possible to input directly clock signals (square wave gnd standard). 17 st adj pilot margin adjustment pin it connects it to gnd through 180k ? 18 ce address/data switching timing 19 cl communication clock 20 di data input 21 do data output it connects it to 22 pin through 10k ? 22 vref2 v dd voltage output 3.3v voltage output pin. it is also possible to supply the current to other ic up to 10ma. 23 gnd3 logic gnd connect to gnd 24 l1 local oscillation circuit it c onnects it to 25 pin through 33nf. 25 vref3 reference voltage for local oscillation circuit it connects it to gnd th rough the capacitor of 100 f 26 l2 local oscillation circuit it c onnects it to 25 pin through 33nf. 27 sd adj sd = on sensitivity adjustment pin it connects it to gnd through 22k ? 28 fll cap fll low pass filter it c onnects it to 25 pin through 0.1 f. 29 gnd4 fm antenna gnd connect to gnd 30 fm ant fm antenna input impedance 75 ? .
lv23401v description of pin functions no. pin name voltage (v) internal equivalent circuit remarks 1 am-ant 2.2v am antenna input pin. the am antenna coil is connected between 2pin. r = 100 2 am-ref 2.2v am standard bias pin. 3 am-cap - am tuning for tune pin. (am capacitor bank) 4 gnd1 0v analog (am_fe) gnd pin. 5 vref1 4.3v analog (tuner area) standard bias pin. vref = 4.3v 6 mpx-out 2.5v fm demodulation output pin. r1 = 100 r2 = 23k r3 = 1k 7 am rf-agc - agc pin for am-rf department gain control. r1 = 2m r2 = 5k r3 = 250 r4 = 1k 8 gnd2 0v analog (tuner) gnd pin. 9 10 l-out r-out 2.5v (it is 3.3v for levshif = 1) l-ch (r-ch) output pin. r = 100 r out = 150 1 2 rr 15 2 2.2v regulator 3 cap-bank 15 5 4.3v regulator 6 r1 r2 r3 7 r1 r2 r3 r4 15 r 10 9 continued on next page. no.a1746-5/24
lv23401v continued from preceding page. no. pin name voltage (v) internal equivalent circuit remarks 11 v cc -low - it is short 11pin with 15pin when using it with v cc < 6.0v . 12 am lcf 2.2v am low-cut filter pin. r1 = 250 r2 = 100k r3 = 100k r4 = 50k r5 = 50k 13 sd-out v dd sd indicator output pin. active low output r = 100k 14 st-out v dd fm stereo indicator output pin. active low output r = 100k 15 v cc v cc analog area supply voltage pin. 8.5 to 9.5v are impressed at resister 1eh bit 1(levshif) = 1, and it is short at ?0? with v cc _low. 16 clk_in 2.1v clock connection pin for internal standard. 32.768khz crystal is connected. r = 100 17 st-adj 3.7v stereo lightin g sensitivity adjustment pin. it connects it to gnd through 180k ? . r = 24k 18 ce ? chip enable pin. pin assumed to be high-level when serial data input (di) and serial data output (do). 19 cl ? data clock input pin clock that takes data and synchronization when serial data input (di) and serial data output (do). 15 11 regulator 12 r1 r5 r4 r2 r3 13 r sd sw 22 14 r st sw 22 16 r crystal oscillator 17 r r 18 19 continued on next page. no.a1746-6/24
lv23401v continued from preceding page. no. pin name voltage (v) internal equivalent circuit remarks 20 di ? serial data input pin. input pin of the serial data transmitted by controller. 21 do ? serial data output pin. serial data output pin to controller. 22 v dd 3.3v logic area standard bias pin. v dd = 3.3v 23 gnd3 0v digital area (control block) gnd pin. 24 26 l1 l2 4.3v osc coil connect pin. 33nh is connected between 25pin. 25 vref2 4.3v osc area standard bias pin. vref2 = 4.3v 27 sd-adj 0.1v sd lighting sensitivity adjustment pin. it connects it to gnd through 22k ? . r = 100 28 fll-cap ? lpf pin for internal fll control. r = 80k 29 gnd4 0v analog (fmrf) gnd pin. 30 fm-ant 0.9v fm antenna input pin. r = 1.5k r in = 75 20 21 24 cap bank cap bank 26 12 25 4.3v regulator 27 comp r 28 29 30 r no.a1746-7/24
lv23401v block diagram lna fll 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 osc cap gnd local oscillator tuning system bpf image det ldo power management state machine ref. osc sd out demodulator stereo decoder de-emphasis stereo blend st out audio amp. divider lna agc det ant cap measurement circuit fm ant 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 gnd4 fll cap sd adj l2 vref3(4.3v) l1 gnd3 vref2(3.3v) do di cl ce st adj clk in am ant am ref am cap gnd1 vref1(4.3v) mpx out am agc gnd2 l out r out v cc _low am_lcf sd out st out v cc lv23401v bpf l2 33nh l1 33nh do di cl ce c9 10pf x1 32.768khz dummy ant mpx out gnd lout rout sd st v cc =9v t1 no.a1746-8/24
lv23401v example of applied circuit 1 fm ant 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 gnd4 fll cap sd adj l2 vref3(4.3v) l1 gnd3 vref2(3.3v) do di cl ce st adj clk in am ant am ref am cap gnd1 vref1(4.3v) mpx out am agc gnd2 l out r out v cc _low am_lcf sd out st out v cc lv23401v bpf l2 33nh l1 33nh do di cl ce c9 10pf x1 32.768khz mpx out gnd lout rout sd st v cc =9v(5v) optional v cc =5v:short v cc =9v:open for am loop antenna for am ferrite antenna am cap am ref am ant gnd lo1 t1 l3 no.a1746-9/24
lv23401v example of applied circuit 2 fm ant 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 gnd4 fll cap sd adj l2 vref3(4.3v) l1 gnd3 vref2(3.3v) do di cl ce st adj clk in am ant am ref am cap gnd1 vref1(4.3v) mpx out am agc gnd2 l out r out v cc _low am_lcf sd out st out v cc lv23401v bpf l2 33nh l1 33nh do di cl ce c9 10pf x1 32.768khz mpx out gnd lout rout sd st v cc =9v optional v cc =5v:short v cc =9v:open for am loop antenna t1 l3 1 rdsid ready 2 rdda 3 vref 4 mpxin 5 v dd a 6 v ss a 7 flout 8 cin 9 test 10 mode 11 v ss d 12 v dd d 13 xin 14 xout 15 rst 16 rdcl lc72725kv c16 560pf c15 330pf c18 15pf x2 4.332mhz c17 15pf no.a1746-10/24
lv23401v no.a1746-11/24 used parts component parameter value tolerance type supplier l1 local osc coil 33nh 5% ll2012-fhl33nj toko l2 local osc coil 33nh 5% ll2012-fhl33nj toko l3 am loop antenna 18.1 h 5% 4910-csl18r1jn1 sagami a90326057 coils t1 am rf matching - - #7003rns-a1109yzs toko c1 ripple filter 0.1 f c2 ripple filter 1 f c3 am rf agc capacitor 4.7 f c4 coupling capacitor 1 f c5 coupling capacitor 1 f c6 am low-cut filter 0.047 f c7 supply bypass capacitor 0.1 f c8 supply bypass capacitor 22 f c9 correction capacitor 10pf c10 supply bypass capacitor 22 f c11 ripple filter 0.1 f c12 osc filter 0.1 f c13 ripple filter 0.1 f c14 ripple filter 10 f c15 coupling capacitor 330pf c16 coupling capacitor 560pf c17 correction capacitor 15pf c18 correction capacitor 15pf r1 reference resistor 180 r2 pulled-up resistor 10k r3 reference resistor 22k r4 reference resistor 33k r5 pulled-up resistor 10k bpf fm ant bpf - - gfmb7 soshin x1 crystal 32.768khz 100ppm vt-200-f(12.5pf) seiko x2 crystal 4.332mhz 100ppm at-49 daishinki lo1 am ferrite antenna 260 h tbd - - * l1 must be used when you receive an eastern european band (65mhz to 75mhz) and l2 must use 39nh. * inquire match (c9, c17, c18) of x1 and the x2 crysta l of the crystal maker together with the substrate used.
lv23401v interface specification 1) lv23401 interface specification lv23401 is controlled by the c 2 b (computer control bus) cereal bus format. c 2 b is a bus to achieve it economically surely format as for the communications between lsi in the system with two or more lsi. because it is single master's system, the processing of a complex arb itration is unnecessary. therefore, the load of hardware is reduced, and th e system configuration that is econ omically abundant becomes possible. moreover, neither a lot of kinds of controller and interface doing nor special hardware is easily needed by serial i/o with software. c 2 b is thought between lsi in the equipment, and the communications between equipment that need a long line are not targeted. 2) c2b data composition di control data (cereal data input) composition in mode b0 0 b1 0 b2 0 b3 0 a0 0 a1 0 a2 1 a3 1 di address d0 d1 d2 d3 d4 d5 d6 d7 r0 r1 r2 r3 r4 r5 r6 r7 data resister lv23401v is controlled by the bus format composed of the sub-address (register) that st ores the data of the device address of 8bit (address) and each 8bit. "c0" is input from lsb to the start as an address when the serial data is input to lv23401v, the device that controls is specified, and the mode as the data input is fixed. it inputs from lsb in order of data (bit setting) register synchronizing with data clock (cl) afte r the address is input and the data input can be concluded. composition of the do control data (serial data output) out mode b0 1 b1 0 b2 0 b3 0 a0 0 a1 0 a2 1 a3 1 di address r00_b0 r00_b1 r00_b2 r00_b3 r00_b4 r00_b5 r00_b6 r00_b7 reg00h data do r01_b0 r01_b1 r01_b2 r01_b3 r01_b4 r01_b5 r01_b6 r01_b7 r02_b0 r02_b1 r02_b2 r02_b3 r02_b4 r02_b5 r03_b6 r03_b7 reg01h data reg02h data "c1" is input from lsb to the start as an address when the serial data is output from lv23401v, the controlled device is specified, and the mode as the data output is fixed. the subsequent data is output from do pin synchronizing with lock (cl) after the address is input lsb from one with small register numb er. the output of data is ended by setting ce pin to low. no.a1746-12/24
lv23401v no.a1746-13/24 3) description of the register of lv23401 register 00h ? chip_id ? chip identify register (read-only) 7 6 5 4 3 2 1 0 id[7:0] bit 7-0 : id[7:0] : 8-bit chip id. lv23400 : 18h note : to abort the command, wr ite any value in this register. register 01h ? chip_rev ? chip revision identify resister (read-only) 7 6 5 4 3 2 1 0 revision[7:0] bit 7-0 : id[7:0] : 8-bit chip revision es1 : 00h note : to abort the command, wr ite any value in this register. register 02h ? radio_stat ? radio station status (read-only) 7 6 5 4 3 2 1 0 im_stat im_fs[1:0] mo_st fs[2:0] tuned bit 7 : im_stat : state of image evasion code 0 = eternal operation (it is possible to write it.) 1 = the image evasion is being processed. (writing is improper.) note : this bit operates only when resister 14h_bit7 (im_evas) is set to "1". the da ta writing processing to lv23401 when this bit is "1" is prohibited. bit 6 - 5 : im_fs : image bureau electric field strength 0 : image bureau none 1 : 0 2 : 0db to 10db compared with the hope bureau. 3 : the level of the image bureau is +10db or more stronger than that of the hope bureau. bit 4 : mo_st : monaural/stereo display 0 = stereo reception (compelling the monaural setting is also the same.) 1 = receiving in stereo mode. bit 3 - 1 : fs[2:0] : field strength 0 : field strength < 10db v 1 : field strength 10 to 20db v 2 : field strength 20 to 30db v ? ? ? 3 : field strength > 70db v bit 0 : tuned : radio-tuning flag 0 = no tuning. 1 = the tuning. note : when the frequency tuning succeeds, this bit is set. this flag is cleared under the following three conditions. 1. pw_rad = 0 2. do the tuning of the frequency. 3. when fll becomes outside the correction range only when the tuned flag is changed from one into 0, the rad_if interrupt flag is set. when the status of tuned changes from 0 into one, the interrupt is not generated. register 04h ? tnpl ? tune position low (read-only) 7 6 5 4 3 2 1 0 tunepos[7:0] bit 7-0 : tunepos[7:0] : current rf frequency (low 8bit)
lv23401v no.a1746-14/24 register 05h ? tnph_stat ? tune position high / status (read-only) 7 6 5 4 3 2 1 0 error[1:0] tunepos[12:8] bit 7 - 6 : error[1:0] : error code error[1:0] remark 0 ok, command end (no error) 1 dac limit error 2 command forced end 3 command busy (executing it) bit 5 ? 0 : tunepos[13:8] : current rf frequency (high 5 bit) register 06h ? count_l ? counter low (read-only) 7 6 5 4 3 2 1 0 count[7:0] bit 7 ? 0 : count[7:0] : counter value (low 8bit) register 07h ? count_h ? counter high (read only) 7 6 5 4 3 2 1 0 count[15:8] bit 7 ? 0 : count[15:8] : counter value (high 8bit) register 08h ? if_osc ? dac for if osc (read/write) 7 6 5 4 3 2 1 0 ifosc[7:0] bit 7 ? 0 : ifosc[7:0] : if oscillator dac register 09h ? ifbw ? dac for if ? filter band width (read/write) 7 6 5 4 3 2 1 0 ifbw[7:0] bit 7 ? 0 : ifbw[7:0] : if band-pass filter band dac register 0bh ? stereo_osc ? dac for stereo decoder osc (read/write) 7 6 5 4 3 2 1 0 sdosc[7:0] bit 7 ? 0 : sdosc[ 7:0] : stereo decoder oscillator dac register 0ch ? rf_osc ? dac for rf osc (read/write) 7 6 5 4 3 2 1 0 rfcap[7:0] bit 7 ? 0 : rfosc[7:0] : rf oscillator dac register 0dh ? rfcap ? rf cap bank (read/write) 7 6 5 4 3 2 1 0 rfcap[7:0] bit 7 ? 0 : rfcap[7:0] : rf oscillator capacitor bank register 0eh ? amcap1 ? am-ant cap bank1 (read/write) 7 6 5 4 3 2 1 0 amcap[7:0] bit 7 ? 0 : amcap[7:0] : am antenna capacitor bank note : the am antenna capacitor bank is composed of 12 bits. high 4 bits are arranged in amctrl resister.
lv23401v no.a1746-15/24 register 0fh ? amctrl ? am station control (read/write) 7 6 5 4 3 2 1 0 amdiv[2:0] am_cal acap11 acap10 acap9 acap8 bit 7 ? 5 : amdiv[2:0] : am clock divider bit 7 : am_cd2 : am clock divider bit 2. bit 6 : am_cd1 : am clock divider bit 1. bit 5 : am_cd0 : am clock divider bit 0. note : amcd[2:0] uses the frequency of fm belt even for the am belt to lower. set the machine of the am dividing frequency to turning off at fm mode. am_cd[2:0] rate of dividi ng frequency rough estimate am-rf frequency (in khz) 0,1 divider off 0 (fm mode) 2 224 338 ? 483 3 160 474 ? 676 4 112 676 ? 966 5 80 947 ? 1353 6 64 1183 ? 1692 7 48 1578 - 2256 bit 4 : na ( 0 fixation) bit 3 ? 0 : amcap[11:8] : am antenna capacitor bank. bit 3 : amcap_bit11 bit 2 : amcap_bit10 bit 1 : amcap_bit9 bit 0 : amcap_bit8 register 10h ? do_ref_clk_cnf ? do output mode and reference clock configuration (read/write) 7 6 5 4 3 2 1 0 ipol do_sel[1:0] ext_clk_cfg[1:0] fs_s[2:0] bit 7 : ipol : indicator (do pin _sd/st mode) polarity 0 = sd/st active low (the same state cha nge as 13pin ? sd pin / 14pin ? st pin ) 1 = sd/st active high (state change opposite to 13pin ? sd pin / 14pin ? st pin ) note : this bit doesn't influence the polarity of the serial data. bit 6 -5 : do_sel : do pin select (do pi n output mode select) do_sel[1:0] do pin 00 serial data output mode 01 st pin mode 10 sd pin mode 11 local position confirmation mode do pin is used by observing the position (upper heterodyne / lower heterodyne) of a state of sd pi n/st pin besides the serial d ata output and local osc. * the state of do pin changes synchronizing with sd pin / st pin when do_sel is set to (01b) or (10b). * the state of do pin changes by the position of local osc when do is set to (11b). lower heterody ne = 0, upper heterodyne = 1 * set do_sel to (00b) when you output the serial data. bit 4 ? 3 : ext_clk_cfg[1:0] : external clock setting ext_clk_cfg[1:0] reference clock 00 off 01 the external clock is supplied. 10 32768hz crystal oscillation 11 unused bit 2 ? 0 : fs_s[2:0] : sd(station de tector) operate level setting (distinguishes at the fs level )
lv23401v no.a1746-16/24 register 11h ? if_sel ? if frequency selection (read/write) 7 6 5 4 3 2 1 0 fll_mod amif[2:0] fmif[3:0] bit 7 : fll_mod : fll operation mode 0 : smoothing filter = off 1 : smoothing filter = on bit 6 -4 : amif[2:0] : if frequency setting when am mode is selected amif[2:0] 0 1 2 3 4 5 6 7 20khz 31khz 42khz 53khz 64khz 75khz 86khz 97khz bit 3 ? 0 : fmif[3:0] : if frequency setting when fm mode is selected (khz) fmif[3:0] se_ am rf_ sel 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 112.5 125 137.5 150 162.5 175 187.5 212.5 225 237.5 250 262.5 275 287.5 312.5 325 0 1 112.5 127.5 142.5 157.5 157.5 172.5 187.5 202.5 217.5 232.5 247.5 262.5 277.5 292.5 307.5 322.5 register 12h ? ref_clk_mod ? slope correction (read/write) 7 6 5 4 3 2 1 0 refmod[7:0] bit 7 ? 0 : refmod[7:0] : reference clock correction note : as for this register, a set value is different according to the crystal connected with 16pin and the input clock. inform of a set value of this register when you adopt the applications other than an example of applied circuit and recommended parts of this specifications.
lv23401v no.a1746-17/24 register 13h ? sm_ctrl ? statemachine control (read/write) 7 6 5 4 3 2 1 0 fll_on clks_se[2:0] nsd_pm nif_pm dm_se[1:0] bit 7 : fll_on : fll control 0 = fll off 1 = fll on bit 6 ? 4 : clks_se : clock course select 0 = no select 1 = the source of the stereo d ecoder oscillator is effective. 2 = the source of the if oscillator is effective. 3 = the source of the am antenna oscillator is effective. 4 = the source of the fm-rf oscillator is effective. 5 = the source of the am-rf oscillator is effective. 6 ? 7 = no select note : bit[6-4] selects the source of the oscillator. select the arbitr ary source that to be adju sted and to be measured. bit 3 : nsd_pm : stereo decoder clock pll mute 0 = sd pll off (adjustment) 1 = sd pll on (operation usually) bit 2 : nif_pm : if pll mute 0 = if pll off (adjustment) 1 = if pll on (operation usually) bit 1 ? 0 : cm_se : command mode select 0 = command no select 1 = measurement mode 2 = adjustment mode 3 = radio tuning (reception frequency adjustment) mode note : this bit is used to se lect the command mode. select the arbitrary command to be executed. the command is executed by set ting target_val_l/h. command execution time : sd calibration = 540ms if calibration = 134ms rf(fm) tuning = 105ms rf(am) tuning = 158ms * stand-by at time to have provided for the above-mentioned before all processing incl uding reading the register value after ha ving executed the command. register 14h ? ref_clk_prs ? reference clock pre-scalar (read/write) 7 6 5 4 3 2 1 0 im_evas reserved wait_sel a<_fine refpre[3:0] bit 7 : im_evas : image evasion function on/off 0 = the image bureau is not evaded. 1 = the image bureau is evaded. (recommendation) bit 6 : reserved : 0 fixation bit 5 : wait_sel : selection after tuning at mu te release standby time 0 = 8ms standby 1 = 4ms standby bit 4 : am_fine : selection at am_ant adjustment standby time 0 = no standby after switch of dac 1 = 2ms standby after switch of dac bit 3 ? 0 : refpre[3:0] : standard clock pre-scalar 0 = 1:1 1 = 1:2 2 = 1:4 ? ? ? 15 = 1:32768
lv23401v no.a1746-18/24 register 15h ? ref_clk_div ? refe rence clock divider (read/write) 7 6 5 4 3 2 1 0 refdiv[7:0] bit 7 ? 0 : re fdiv[7:0] : standard clock divider 0 : rate of dividing frequency = 1 1 : rate of dividing frequency = 2 ? ? ? 255 : rate of divi ding frequency =256 register 16h ? target_val_l ? target value low register (read/write) 7 6 5 4 3 2 1 0 target[7:0] bit 7 ? 0 : target[7:0] : target frequency low 8bit : targeted value of radio tuning and oscillator adjustment : low byte register 17h ? target_val_h ? target value high register (read/write) 7 6 5 4 3 2 1 0 target[15:8] bit 7 ? 0 : target[15:8] : target frequency high 8 bit : targeted value of radio tuning and oscillator adjustment : high byte note : when subordinate position 8bit of the frequency of the target is set when it is on, and high rank of the frequency of th e target 8bit is set to this register afterwards, the comma nd is executed as for the radio power. tunepos and target : - 1khz interval at am - 10khz interval at fm register 18h ? radio_ctrl1 ? radio control 1 (read/write) 7 6 5 4 3 2 1 0 iqc_ctr ifpol osc_lev[1:0 ] deem vol[1:0] en_amhc bit 7 : iqc_ctr : i/q phase conversion 0 = operational mode usually (upper heterodyne) 1 = i/q phase conversion : image measures (lower heterodyne) note : when the local is switched as an image measures, it uses it. bit 6 : if polarity conversion in state machine. 0 = the if frequency is added to a local frequency. (operational usually) 1 = the if frequency is subtracted by a local frequency. (image measures) bit 5 ? 4 : osc_lev[1:0] : rf-osc oscillation level setting 0 = minimum oscillation level 3 = maximum oscillation level * a possible level adjustment and "2" are assumed to be a recommended value at each interval of 3db. bit 3 : deen : de-emphasis time constant switch 0 = 50 s : japan, south korea, china, and europe 1 = 75 s : the united states bit 2 ? 1 : vol[1:0] : volume setting 0 = minimum (vol0) ? ? ? 3 = maximum (vol3) bit 0 : en_amhc : am high cut filter on/off 0 = am hi-cut filter function off 1 = am hi-cut filter function on
lv23401v no.a1746-19/24 register 19h ? radio_ctrl 2 ? radio control 2 (read/write) 7 6 5 4 3 2 1 0 reserved reserved en_amm reserved if_agc_lev rf_agc_lev[1:0] en_rfagc bit 7 : reserved : 0 fixation bit 6 : reserved : 1 fixation bit 5 : en_amm : am mute on/off 0 = am mute function off 1 = am mute function on bit 4 : reserved : 0 fixation bit 3 : if_agc_lev : if-agc level control 0 = agc slow mode 1 = agc first mode bit 2 ? 1 : rf_agc_lev[1:0] : rf-agc level control 0 = agc slow mode 1 = agc normal mode 3 = agc first mode bit 0 : en_rfagc : rf-agc on/off 0 = agc off 1 = agc on (operational usually) register 1ah ? radio_ctrl3 ? radio control 3 (read/write) 7 6 5 4 3 2 1 0 amosc_ga[2:0] amosc_dl[2:0] amagc_sp[1:0] bit 7 ? 5 : amosc_ga[2:0] : am antenna oscillator gain control 0 = minimum level 7 = maximum level bit 4 ? 2 : amosc_dl[2:0] : am oscillator detection level 0 = minimum level 7 = maximum level bit 1 ? 0 : amsgc_sp[1:0] : am oscillator agc speed 0 = slow mode 3 = first mode
lv23401v no.a1746-20/24 register 1ch ? stereo_ctrl1 ? stereo control 1 (read/write) 7 6 5 4 3 2 1 0 crc[1:0] ss_sp2 ss_sp1 na pi can_en fostereo st_m bit 7 ? 6 : crc[1:0] : capture range control 0 = narrowband mode 1 = recommended value 3 = wideband mode bit 5 : ss_ sp2 : stereo sensitivity speed 2 (first mode) 0 : first mode = off 1 : first mode = on - recommended value bit 4 : ss_ sp1 : stereo sensitivity speed 1 (slow mode) 0 : slow mode = off - recommended value 1 : slow mode = on bit 3 : na bit 2 : pican_en : pilot cancel function on/off 0 = off 1 = on bit 1 : fostereo : compulsion stereo 0 = operational usually 1 = compulsion stereo mode bit 0 : st_m : stereo/monaural setting 0 = stereo function on (operational usually) 1 = stereo function off (compulsion monaural) register 1dh ? stereo_ctrl2 ? stereo control 2 (read/write) 7 6 5 4 3 2 1 0 na foamagc reserved na cpaj[1:0] bit 7 ? 5 : na bit 4 : foamagc 0 : compulsion agc = off 1 : compulsion agc = on bit 3 : reserved : 0 fixation bit 2 : na bit 1 ? 0 : cpaj[1:0] : channel separation adjustment 0 = sub career level minimum 7 = sub career level maximum register 1eh ? radio_ctrl4 ? radio control 4 (read/write) 7 6 5 4 3 2 1 0 softst[2:0] softmu[2:0] levshif fo_softt bit 7 ? 5 : softst[2:0] : soft stereo function setting 0 : soft stereo function = off 7 : soft stereo function = lev7 (max) bit 4 ? 2 : softmu [2:0] : soft audio mute function setting 0 : soft mute function = off 7 : soft mute function = lev7 (max) bit 1 : levshif : audio line dc level shift 0 = normal dc level (v cc =5.0v supply) 1 = dc level shift (v cc =9.0v supply) bit 0 : fo_s oftst : compulsion soft stereo function setting 0 : compulsion soft stereo function = on 1 : compulsion soft stereo function = off * set it to "0" when corresponding to european immunity standard.
lv23401v no.a1746-21/24 register 1fh ? radio_xtrl5 ? radio control 5 (read/write) 7 6 5 4 3 2 1 0 rf_sel ifrim nagc_spd se_fm/am amp_ctr mute na pw_rad bit 7 : rf_sel : rf frequency range setting 0 = normal (japan / usa / europe) 1 = eastern europe (65mhz to 74mhz) bit 6 : ifrim : if oscillator limit setting 0 : max = 350khz (fm mode) 1 : max =150khz (am mode) bit 5 : nagc_spd : if agc speed setting 0 = hi speed (fm mode) 1 = normal (am mode) bit 4 : se_fm/am : am/fm mode select 0 = fm mode 1 = am mode bit 3 : amp_ctr : audio amplifier on/off 0 = off 1 = on bit 2 : mute : audio mute function on/off 0 = mute on 1 = mute off bit 1 : am_cal : am calibration (oscillation mode) 0 = am calibration impropriety (operational usually) 1 = am calibration mode (am antenna frequency setting time) note : set this bit to "1 " when you measure the frequency of the am antenna. bit 0 : pw_rad : radio circuit power 0 = power off (power save) 1 = power on * 1 : after the v cc voltage is impressed, pw_rad of register 1fh_bit0 is automatically set to "0" in 50ms. * 2 : when the v cc voltage is dropped once, content of registers other than pw_rad becomes irregular. * 3 : the content of the register change set at the power save becomes effective, and any comm and processing cannot be executed . * 4 : the standby time of 1200ms is necessary, the circuit with stability (pw_rad = 0 1) after the power save returns. * 5 : tune rf again after the power save returns. * 6 : a built-in each oscillator including the rf bureau departure and all other analogue part circuit operation stop at the po wer save. * 7 : the standby time of 200ms is necessary after the switch of the band to am before counting if after adjusting the first rf .
lv23401v 4) c 2 b communication timing specification serial data input (in1/in2) tsu, thd, tel, tes, teh 0.75 s tlc < 0.75 s cl : normally hi ce b0 b1 b2 b3 a0 a1 a2 a3 d0 d1 d2 d3 d4 d5 d6 d7 t eh t lc t el t es t su t hd cl di internal data cl : normally low ce b0 b1 b2 b3 a0 a1 a2 a3 d0 d1 d2 d3 d4 d5 d6 d7 t eh t lc t el t es t su t hd cl di internal data serial data output (out) tsu, thd, tel, tes, teh 0.75 s tdc, tdh < 0.35 s cl : normally hi ce b0 b1 b2 b3 a0 a1 a2 a3 d0 d1 d2 d3 d20 d21 d22 d23 t eh t dh t el t es t su t hd cl di t dh t dh do cl : normally hi ce b0 b1 b2 b3 a0 a1 a2 a3 d0 d1 d2 d20 d21 d22 d23 t eh t dh t el t es t su t hd cl di t dh t dh do (note) do pin is an nch open drain pin, so that the data varying time (tdc and tdh) differs depending on the pull-up resistance and substrate capacity. no.a1746-22/24
lv23401v serial data timing ce t ch cl di do t cl v i h v i l v i h v i l v i h v i l v i h v i l t el t es t eh t dh t dc t dc v i h v i l t su t hd v i h v i l t lc internal data latch old new << when cl stops at the ?l? level >> ce t ch cl di do t cl v i h v i l v i h v i h v i l v i l t el t es t eh t dh t dc v i h v i l t su t hd v i h v i l t lc internal data latch new old << when cl stops at the ?h? level >> parameter symbol pin conditions min typ max unit data setup time tsu di, cl 0.75 s data hold time thd di, cl 0.75 s clock ?l? level time tcl cl 0.75 s clock ?h? level time tch cl 0.75 s ce wait time tel ce, cl 0.75 s ce setup time tes ce, cl 0.75 s ce hold time teh ce, cl 0.75 s data latch change time tlc 0.75 s tdc do, cl data output time tdh do, ce differs depending on the pull-up resistance and substrate capacity 0.35 s no.a1746-23/24
lv23401v sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rate d values (such as maximum ra tings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qual ity high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. it is possible that these probabilistic failures or malfunction could give rise to acci dents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or e vents cannot occur. such measures include but are not limited to protective circuits and error prevention c ircuits for safe design, redundant design, and structural design. upon using the technical information or products descri bed herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable f or any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. information (including circuit diagr ams and circuit parameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equi pment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor c o.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities conc erned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any in formation storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. this catalog provides information as of june, 2010. specifications and information herein are subject to change without notice. no.a1746-24/24 ps

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