? semiconductor components industries, llc, 2013 august, 2013 ? rev. 8 1 publication order number: pzt651t1/d pzt651 npn silicon planar epitaxial transistor this npn silicon epitaxial transistor is designed for use in industrial and consumer applications. the device is housed in the sot ? 223 package which is designed for medium power surface mount applications. sot ? 223 package ensures level mounting, resulting in improved thermal conduction, and allows visual inspection of soldered joints. the formed leads absorb thermal stress during soldering, eliminating the possibility of damage to the die. features ? high current ? the sot ? 223 package can be soldered using wave or reflow ? available in 12 mm tape and reel ? use pzt651t1 to order the 7 inch/1000 unit reel ? use pzt651t3 to order the 13 inch/4000 unit reel ? pnp complement is pzt751t1 ? s prefix for automotive and other applications requiring unique site and control change requirements; aec ? q101 qualified and ppap capable ? these devices are pb ? free, halogen free/bfr free and are rohs compliant* maximum ratings (t c = 25 c unless otherwise noted) rating symbol value unit collector ? emitter voltage v ceo 60 vdc collector ? base voltage v cbo 80 vdc emitter ? base voltage v ebo 5.0 vdc collector current i c 2.0 adc total power dissipation @ t a = 25 c (note 1) derate above 25 c p d 0.8 6.4 w mw/ c storage temperature range t stg ? 65 to 150 c junction temperature t j 150 c thermal characteristics characteristic symbol max unit thermal resistance from junction ? to ? ambient in free air r ja 156 c/w maximum temperature for soldering purposes time in solder bath t l 260 10 c sec stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. 1. device mounted on a fr ? 4 glass epoxy printed circuit board using minimum recommended footprint. *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. marking diagram sot ? 223 case 318e ? 04 style 1 http://onsemi.com a = assembly location y = year ww = work week = pb ? free package sot ? 223 package high current npn silicon transistor surface mount collector 2, 4 base 1 emitter 3 (note: microdot may be in either location) 1 ayw 651 device package shipping ? ordering information pzt651t1g sot ? 223 (pb ? free) 1,000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. SPZT651T1G sot ? 223 (pb ? free) 1,000 / tape & reel 1 2 3 4
pzt651 http://onsemi.com 2 electrical characteristics (t a = 25 c unless otherwise noted) characteristics symbol min max unit off characteristics collector ? emitter breakdown voltage (i c = 10 madc, i b = 0) v (br)ceo 60 ? vdc collector ? emitter breakdown voltage (i c = 100 adc, i e = 0) v (br)cbo 80 ? vdc emitter ? base breakdown voltage (i e = 10 adc, i c = 0) v (br)ebo 5.0 ? vdc base ? emitter cutoff current (v eb = 4.0 vdc) i ebo ? 0.1 adc collector ? base cutoff current (v cb = 80 vdc, i e = 0) i cbo ? 100 nadc on characteristics (note 2) dc current gain (i c = 50 madc, v ce = 2.0 vdc) (i c = 500 madc, v ce = 2.0 vdc) (i c = 1.0 adc, v ce = 2.0 vdc) (i c = 2.0 adc, v ce = 2.0 vdc) h fe 75 75 75 40 ? ? ? ? ? collector ? emitter saturation voltages (i c = 2.0 adc, i b = 200 madc) (i c = 1.0 adc, i b = 100 madc) v ce(sat) ? ? 0.5 0.3 vdc base ? emitter voltages (i c = 1.0 adc, v ce = 2.0 vdc) v be(on) ? 1.0 vdc base ? emitter saturation voltage (i c = 1.0 adc, i b = 100 madc) v be(sat) ? 1.2 vdc current ? gain ? bandwidth (i c = 50 madc, v ce = 5.0 vdc, f = 100 mhz) f t 75 ? mhz 2. pulse test: pulse width 300 s, duty cycle = 2.0%
pzt651 http://onsemi.com 3 figure 1. typical dc current gain i c , collector current (ma) 10 h fe , dc current gain 300 0 v ce = 2.0 v t j = 125 c 25 c -55 c npn i c , collector current (ma) -10 -20 -50 -100 -200 -500 h fe , dc current gain 250 0 pnp 30 60 90 120 150 180 210 240 270 20 50 100 200 500 1.0 a 2.0 a 4.0 a 25 50 75 100 125 200 175 150 225 -1.0 a -2.0 a -4.0 a v ce = -2.0 v t j = 125 c 25 c -55 c i c , collector current (ma) 50 v, voltage (volts) 2.0 0 v be(sat) @ i c /i b = 10 v be(on) @ v ce = 2.0 v v ce(sat) @ i c /i b = 10 figure 2. typical dc current gain figure 3. on voltages 1.8 1.6 1.4 1.2 1.0 0.4 0.8 0.6 0.2 100 200 500 1.0 a 2.0 a 4.0 a npn i c , collector current (ma) v, voltage (volts) 0 figure 4. on voltages -50 -2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.4 -0.8 -0.6 -0.2 -100 -200 -500 -1.0 a -2.0 a -4.0 a v be(sat) @ i c /i b = 10 v ce(sat) @ i c /i b = 10 pnp v be(on) @ v ce = 2.0 v figure 5. collector saturation region i b , base current (ma) 0.05 1.0 0 npn 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 v ce , collector-emitter voltage (volts) 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200 500 t j = 25 c i c = 10 ma i c = 100 ma i c = 500 ma i c = 2.0 a i b , base current (ma) pnp figure 6. collector saturation region v ce , collector-emitter voltage (volts) t j = 25 c i c = -10 ma i c = -100 ma i c = -500 ma i c = -2.0 a -0.05 -1.0 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -0.1 -0.2 -0.5 -1.0 -2.0 -5.0 -10 -20 -50 -100-200 -500
pzt651 http://onsemi.com 4 package dimensions sot ? 223 (to ? 261) case 318e ? 04 issue n a1 b1 d e b e e1 4 123 0.08 (0003) a l1 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: inch. 1.5 0.059 mm inches scale 6:1 3.8 0.15 2.0 0.079 6.3 0.248 2.3 0.091 2.3 0.091 2.0 0.079 soldering footprint* h e dim a min nom max min millimeters 1.50 1.63 1.75 0.060 inches a1 0.02 0.06 0.10 0.001 b 0.60 0.75 0.89 0.024 b1 2.90 3.06 3.20 0.115 c 0.24 0.29 0.35 0.009 d 6.30 6.50 6.70 0.249 e 3.30 3.50 3.70 0.130 e 2.20 2.30 2.40 0.087 0.85 0.94 1.05 0.033 0.064 0.068 0.002 0.004 0.030 0.035 0.121 0.126 0.012 0.014 0.256 0.263 0.138 0.145 0.091 0.094 0.037 0.041 nom max l1 1.50 1.75 2.00 0.060 6.70 7.00 7.30 0.264 0.069 0.078 0.276 0.287 h e ? ? e1 0 1 0 0 1 0 l l 0.20 ??? ??? 0.008 ??? ??? style 1: pin 1. base 2. collector 3. emitter 4. collector *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 pzt651t1/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
|
