MP2004 dual, low noise, high psrr 200ma linear regulator MP2004 rev. 0.92 www.monolithicpower.com 1 4/6/2010 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2010 mps. all rights reserved. the future of analog ic technology description the MP2004 is a dual-channel, low noise, low dropout and high psrr linear regulator. the output voltage of MP2004 ranges from 1.2v to 5v and 1% accuracy by operating from a +2.5v to +6.0v input. the MP2004 can supply up to 200ma of load current at each channel. the MP2004 uses an internal pmos as the pass element, which consumes 114 a supply current (both ldos on) at no load condition. the en1 and en2 pins control each output respectively. when both channels shutdown simultaneously, the chip will be turned off and consume nearly zero operation current which is suitable for battery-power devices. the MP2004 features current limiting and over temperature protection. it is available in a small 6-pin tsot23 package. features ? two ldos in a tsot23-6 package ? up to 200ma output current (per channel ? two enable pins control each output ? 69db psrr (100hz) ? 95 v rms low noise output ? 110mv dropout at 100ma load ? very fast transient responses with small output capacitor ? current limiting and thermal protection applications ? cellular phones ? laptop pcs ? hand-held equipment ? netbook computing ?mps? and ?the future of analog ic technology? are registered trademarks of monolithic power systems, inc. typical application en2 en1 out2 out1 in gnd out2 out1 en1 en2 MP2004 c in c out2 c out1 in
MP2004-dual, low noise, high psrr, 200ma linear regulator MP2004 rev. 0.92 www.monolithicpower.com 2 4/6/2010 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2010 mps. all rights reserved. ordering information* part number v out1 v out2 package temperature top marking MP2004dj-jg-lf-z 2.5v 1.8v 2b MP2004dj-zs-lf-z 5.0v 3.3v 2l MP2004dj-pn-lf-z 3.0v 2.85v 3l MP2004dj-dd-lf-z 1.85v 1.85v 4l MP2004dj-sj-lf-z 3.3v 2.5v 5l MP2004dj-mg-lf-z 2.8v 1.8v tsot23-6 -40c to +85c 6l * other output voltage versions between 1.2v and 5.0v are ava ilable in 100mv increments. contact factory for availability. ordering guide** MP2004dj- -lf-z v out2 v out1 package type j: tsot23-6 ** for rohs compliant packaging, add suffix - lf (e.g. MP2004dj- -lf); for tape and reel, add suffix -z (e.g. MP2004dj- - lf-z). output voltage selector guide*** code v out code v out c 1.2 t 2.65 b 1.3 l 2.7 f 1.5 m 2.8 w 1.6 n 2.85 g 1.8 v 2.9 d 1.85 p 3.0 y 1.9 q 3.1 h 2.0 x 3.15 e 2.1 r 3.2 j 2.5 s 3.3 k 2.6 z 5.0 *** code in bold are standard versions. for other output voltages between 1.2v and 5.0v contact factory for availability. minimum order quantity on non-standard versions is 25,000 units. package reference out1 top view in en1 en2 gnd 123 4 5 6 out2
MP2004-dual, low noise, high psrr, 200ma linear regulator MP2004 rev. 0.92 www.monolithicpower.com 3 4/6/2010 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2010 mps. all rights reserved. absolute maxi mum ratings (1) supply input voltage ................................. 6.5v continuous power dissipation (t a = +25c) (2) ........................................................... 0.45w operation temperature range ... -40c to 85c storage temperature range ..... -65c to 150c lead temperature (soldering, 10sec) .....260c recommended operating conditions (3) supply input voltage.......................2.5v to 6.0v enable input voltage .........................0v to 6.0v junction temperature range . ?40 c to +125 c thermal resistance (4) ja jc tsot23-6 ..............................220 ....110. . c/w notes: 1) exceeding these ratings may cause permanent damage to the device. 2) the maximum allowable power dissipation is a function of the maximum junction temperature t j (max), the junction-to- ambient thermal resistance ja , and the ambient temperature t a . the maximum allowable continuous power dissipation at any ambient temperature is calculated by p d (max)=(t j (max)- t a )/ ja . exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. internal thermal shutdown circuitry protects the device from permanent damage. 3) the device is not guaranteed to function outside its operating conditions. 4) measured on jesd51-7 4-layer board.
MP2004-dual, low noise, high psrr, 200ma linear regulator MP2004 rev. 0.92 www.monolithicpower.com 4 4/6/2010 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2010 mps. all rights reserved. electrical characteristics v in =3.6v, v out1 =2.5v, v out2 =1.8v, c in =c out1 =c out2 =2.2uf, en1=en2=v in , typical value at t a =25 c for each ldo unless otherwise noted. notes: 5) load regulation= 100(%) v v v out(nom) ] out[i ] out[i out(min) out(max) ? 6) dropout voltage is defined as the input to output different ial when the output voltage drops 100mv below its nominal value. 7) line regulation= ) 100(%/v v ] v [v v v out(nom) in(min) in(max) ] out[v ] out[v in(min) in(max) ? ? pin functions pin # name description 1 vout2 channel 2 output voltage 2 gnd common ground 3 en2 channel 2 enable (active high). do not float this pin. 4 en1 channel 1 enable (active high). do not float this pin. 5 vin supply input pin 6 vout1 channel 1 output voltage parameter symbol condition min typ max units output voltage accuracy (load regulation) (5) v out i load = 1ma to 200ma -1 +1 % maximum output current i max continuous 200 ma current limit i lim r load =1 450 ma quiescent current i q no load 114 ua i out1 = 100ma 110 mv dropout voltage (6) v drop i out1 = 200ma 250 mv line regulation (7) ? v line v in =(v out +0.4v or 2.5v) to 6v, i out =1ma -0.05 +0.05 %/v en input high threshold v ih v in = 2.5v to 6.0v 1.6 v en input low threshold v il v in = 2.5v to 6.0v 0.45 v en input bias current i sd en= v in =6.5v 300 na shutdown supply current i gsd en1 = en2 = gnd 0.03 1 ua thermal shutdown temperature t sd 140 c thermal shutdown hysteresis t sd 10 c output voltage noise 10hz to 100khz, c out =2.2 f, i load =1ma 95 v rms output psrr 100hz, c out = 2.2 f, i load = 100ma 69 db
MP2004-dual, low noise, high psrr, 200ma linear regulator MP2004 rev. 0.92 www.monolithicpower.com 5 4/6/2010 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2010 mps. all rights reserved. typical performanc e characteristics v in =3.6v, v out1 =2.5v, v out2 =1.8v, c in =c out1 =c out2 =2.2uf, en1=en2=v in , typical value at t a =25 c for both channel enabled. 0 20 40 60 80 100 120 100 1000 10000 100000 1000000 frequency(hz) channel-to-channel isolation vs. frequency -40 -20 0 20 40 60 85 quiescent current vs. temperature 200 150 100 50 0 dropout voltage vs. temperature -40 -20 0 20 40 60 85 out voltage accuracy vs. temperature 0 10 20 30 40 50 60 70 80 10 100 1000 10000 100000 1000000 frequency(hz) power supply rejection ratio vs. frequency v out 10mv/div v in 1v/div v out 10mv/div i load 50ma/div v out 1v/div v en 5v/div 200 220 240 260 280 300 -40 -20 0 20 40 60 85 i load =200ma -0.25 -0.20 -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0.20 0.25
MP2004-dual, low noise, high psrr, 200ma linear regulator MP2004 rev. 0.92 www.monolithicpower.com 6 4/6/2010 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2010 mps. all rights reserved. block diagram figure1?functional block diagram operation the MP2004 integrates two low noise, low dropout, low quiescent current and high psrr linear regulators. it is intended for use in devices that require very low voltage, low quiescent current power such as wireless lan, battery- powered equipment and hand-held equipment. the MP2004 uses internal pmoss as the pass elements and features internal thermal shutdown and an internal current limit circuit. dropout voltage dropout voltage is the minimum input to output differential voltage required for the regulator to maintain an output voltage within 100mv of its nominal value. because the pmos pass element behaves as a low-value resistor, the dropout voltage of MP2004 is very low. shutdown the MP2004 can be switched on or off by a logic input at the en pin. a high voltage at this pin will turn the device on. when the en pin is low, the regulator output is off. the en pin should be tied to vin to keep the regulator output always on if the application does not require the shutdown feature. do not float the en pin. current limit the MP2004 includes two independent current limit structures which monitor and control each pmos?s gate voltage limiting the guaranteed maximum output current to 200ma. thermal protection thermal protection turns off the pmos when the junction temperature exceeds +140oc, allowing the ic to cool. when the ic?s junction temperature drops by 10oc, the pmos will be turned on again. thermal protection limits total power dissipation in the MP2004. for reliable operation, junction temperature should be limited to 125 oc maximum. load-transient considerations the output response of load-transient consists of a dc shift and transient response. because of the excellent load regulation of MP2004, the dc shift is very small. the output voltage transient depends on the output capacitor?s value and the esr. increasing the capacitance and decreasing the esr will improve the transient response. typical output voltage transient spike of MP2004 for a step change in the load current from 0ma to 80ma is tens mv.
MP2004-dual, low noise, high psrr, 200ma linear regulator MP2004 rev. 0.92 www.monolithicpower.com 7 4/6/2010 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2010 mps. all rights reserved. application information power dissipation the power dissipation for any package depends on the thermal resistance of the case and circuit board, the temperature difference between the junction and ambient air, and the rate of airflow. the power dissipation across the device can be represented by the equation: p = (v in - v out ) i out the allowable power dissipation can be calculated using the following equation: p (max) = (t junction - t ambient ) / ja where (t junction - t ambient ) is the temperature difference between the junction and the surrounding environment, ja is the thermal resistance from the junction to the ambient environment. connect the gnd pin of MP2004 to ground using a large pad or ground plane helps to channel heat away. input capacitor selection using a capacitor whose value is >0.47f on the MP2004 input and the amount of capacitance can be increased without limit. larger values will help to improve line transient response with the drawback of increased size . ceramic capacitors are preferred, but tantalum capacitors may also suffice. output capacitor selection the MP2004 is designed specifically to work with very low esr ceramic output capacitor in space- saving and performance consideration. a ceramic capacitor in the range of 0.47f and 10f, and with esr lower than 1.2 ? is suitable for the MP2004 application circuit. output capacitor of larger values will help to improve load transient response and reduce noise with the drawback of increased size. load current (ma) unstable stable 0.1 1 10 100 0 40 80 120 160 200 figure 2?relationship between esr and ldo stability reverse current path the pmos used in the MP2004 has an inherent diode connected between input and output (see figure3). if v out -v in is more than a diode-drop, this diode gets forward biased and starts to conduct. to avoid misoperation, an external schottky connected in parallel with the internal parasitic diode prevents it from being turned on by limiting the voltage drop across it to about 0.3v (see figure 4). figure 3?inherent diode connected between each regulator input and output figure 4?external schottky diode connected in parallel with the internal parasitic diode
MP2004-dual, low noise, high psrr, 200ma linear regulator MP2004 rev. 0.92 www.monolithicpower.com 8 4/6/2010 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2010 mps. all rights reserved. pcb layout guide pcb layout is very important to achieve good regulation, ripple rejection, transient response and thermal performance. it is highly recommended to duplicate evb layout for optimum performance. if change is necessary, please follow these guidelines and take figure 5 for reference. 1) input and output bypass ceramic capacitors are suggested to be put close to the in pin and out pin respectively. 2) ensure all feedback connections are short and direct. place the feedback resistors and compensation components as close to the chip as possible. 3) connect in, out and especially gnd respectively to a large copper area to cool the chip to improve thermal performance and long-term reliability. in r1 r2 en1 en2 out1 out2 gnd out1 MP2004 c out2 c out1 in en1 en2 c in out2 1 2 34 5 out2 en2 gnd en1 in 6 out1 top layer figure 5?pcb layout
MP2004-dual, low noise, high psrr, 200ma linear regulator notice: the information in this document is subject to change wi thout notice. users should warra nt and guarantee that third party intellectual property rights are not infringed upon w hen integrating mps products into any application. mps will not assume any legal responsibility for any said applications. MP2004 rev. 0.92 www.monolithicpower.com 9 4/6/2010 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2010 mps. all rights reserved. package information tsot23-6 0.30 0.50 seating plane 0.95 bsc 0.84 0.90 1.00 max 0.00 0.10 top view front view side view recommended land pattern 2.80 3.00 1.50 1.70 2.60 3.00 1 3 4 6 0.09 0.20 note: 1) all dimensions are in millimeters. 2) package length does not include mold flash, protrusion or gate burr. 3) package width does not include interlead flash or protrusion. 4) lead coplanarity (bottom of leads after forming) shall be 0.10 millimeters max. 5) drawing conforms to jedec mo-193, variation ab. 6) drawing is not to scale. 7) pin 1 is lower left pin when reading top mark from left to right, (see example top mark) 0.30 0.50 0 o -8 o 0.25 bsc gauge plane 2.60 typ 1.20 typ 0.95 bsc 0.60 typ see detail "a" detail ?a? aaaa pin 1 see note 7 example top mark
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