integrated circuit systems, inc. general description features icsvf2509b 1036c? 07/13/05 block diagram 3.3v phase-lock loop clock driver pin configuration the icsvf2509b is a high performance, low skew, low jitter clock driver. it uses a phase lock loop (pll) technology to align, in both phase and frequency, the clkin signal with the clkout signal. it is specifically designed for use with synchronous sdrams. the icsvf2509b operates at 3.3v vcc and drives up to nine clock loads. one bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of clkin. output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at clkin. each bank of outputs can be enabled or disabled separately via control (oea and oeb) inputs. when the oe inputs are high, the outputs align in phase and frequency with clkin; when the oe inputs are low, the outputs are disabled to the logic low state. the icsvf2509b does not require external rc filter components. the loop filter for the pll is included on-chip, minimizing component count, board space, and cost. the buffer mode shuts off the pll and connects the input directly to the output buffer. this buffer mode, the icsvf2509b can be use as low skew fanout clock buffer device. the icsvf2509b comes in 24 pin 173mil thin shrink small-outline package (tssop) package. meets or exceeds pc133 registered dimm specification1.1 spread spectrum clock compatible distributes one clock input to one bank of ten outputs operating frequency 20mhz to 200mhz external feedback input (fbin) terminal is used to synchrionize the outputs to the clock input no external rc network required operates at 3.3v vcc plastic 24-pin 173mil tssop package 24 pin tssop 4.40 mm. body, 0.65 mm. pitch fbin clkin avcc oea oeb pll clka0 fbout clka1 clka2 clka3 clka4 clkb0 clkb1 clkb2 clkb3 agnd vcc clka0 clka1 clka2 gnd gnd clka3 clka4 vcc oea fbout clkin vcc clkb 0 clkb1 gnd gnd clkb 2 clkb 3 vcc oeb fbin avcc icsvf2509b 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
2 icsvf2509b 1036c?07/13/05 pin descriptions functionality pin number pin name type description 1 agnd pwr analog ground 2, 10, 15 vcc pwr power supply (3.3v) 3 clka0 out buffered clock output, bank a 4 clka1 out buffered clock output, bank a 5 clka2 out buffered clock output, bank a 6, 7, 18, 19 gnd pwr ground 8 clka3 out buffered clock output, bank a 9 clka4 out buffered clock output, bank a 11 oea 1 in output enable (has internal pull_up). when high, normal operation. when low bank a clock outputs are disabled to a lo g ic low state. 12 fbout out feedback output 13 fbin in feedback input 14 oeb 1 in output enable (has internal pull_up). when high, normal operation. when low bank b clock outputs are disabled to a logic low state. 16 clkb3 out buffered clock output. bank b 17 clkb2 out buffered clock output. bank b 20 clkb1 out buffered clock output. bank b 21 clkb0 out buffered clock output. bank b 22 vcc pwr power supply (3.3v) digital supply. 23 avcc in analog power supply (3.3v). when input is ground pll is off and b y passed. 24 clkin in clock input oea oeb avcc clka ( 0:4 ) clkb ( 0:3 ) fbout source 003.3300drivenplln 0 1 3.33 0 driven driven pll n 1 0 3.33 driven 0 driven pll n 1 1 3.33 driven driven driven pll n 00000drivenclkiny 0100drivendrivenclkiny 100driven0drivenclkiny 110 driven driven driven clkin y test mode: when avcc is 0, shuts off the pll and connects the input directly to the output buffers buffer mode inputs outputs pll shutdown note: 1. weak pull-ups on these inputs
3 icsvf2509b 1036c?07/13/05 absolute maximum ratings supply voltage (avcc) . . . . . . . . . . . . . . . . . avcc < (v cc + 0.7 v) supply voltage (vcc) . . . . . . . . . . . . . . . . . . 4.3 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v cc + 0.5 v ambient operating temperature . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - output t a = 0 - 70c; v dd = v ddl = 3.3 v +/-10%; c l = 30 pf; r l = 500 ohms (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh i oh = -8 ma 2.4 2.9 v output low voltage v ol i ol = 8 ma 0.25 0.4 v v oh = 2.4 v 27 v oh = 2.0 v 39 v ol = 0.8 v 26 v ol = 0.55 v 19 rise time 1 t r v ol = 0.8 v, v oh = 2.0 v 0.5 1.1 2.1 ns fall time 1 t f v oh = 2.0 v, v ol = 0.8 v 0.5 1.1 2.7 ns duty cycle 1 d t v t = 1.5 v;c l =30 pf 48 50 52 % cycle to cycle jitter 1 t cy c - t cy c at 66-100 mhz ; loaded outputs 75 ps absolute jitter 1 t jabs 10000 cycles; c l = 30 pf 100 ps skew 1 t sk v t = 1.5 v (window) output to output 100 ps phase error 1 t p e v t = vdd/2; clkin-fbin -75 75 ps delay input-output 1 d r1 v t = 1.5 v; pll_en = 0 3.3 3.7 ns 1 guaranteed by design, not 100% tested in production. ma ma output high current output low current i oh i ol
4 icsvf2509b 1036c?07/13/05 electrical characteristics - input & supply t a = 0 - 70c; supply voltage v dd = 3.3 v +/-10% (unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2v dd + 0.3 v input low voltage v il v ss - 0.3 0.8 v input high current i ih v in = v dd 0.1 100 ua input low current i il v in = 0 v; 19 50 ua operating current i dd 1 c l = 0 pf; f in @ 66mhz 170 ma input capacitance c in 1 logic inputs 4 pf 1 guaranteed by design, not 100% tested in production. symbol parameter test conditions min. max. unit f op operating frequency 20 200 mhz f clk input clock frequency 25 200 mhz input clock frequency duty cycle 40 60 % stabilization time after power up 15 s timing requirements over recommended ranges of supply voltage and operating free-air temperature note: time required for the pll circuit to obtain phase lock of its feedback signal to its reference signal. in order for p hase lock to be obtained , a fixed-fre q uenc y, fixed- p hase reference si g nal must be p resent at clk. until phase lock is obtained, the specifications for parameters given in the switching characteristics table are not applicable .
5 icsvf2509b 1036c?07/13/05 parameter measurement information figure 1. load circuit for outputs notes: 1. c l includes probe and jig capacitance. 2. all input pulses are supplied by generators having the following characteristics: prr 133 mhz, z o = 5 0 ?, t r 1. 2 n s, t f 1. 2 n s. 3. the outputs are measured one at a time with one transition per measurement. 30 pf 500 ? from output under test figure 2. voltage waveforms propagation delay times figure 3. phase error and skew calculations
6 icsvf2509b 1036c?07/13/05 general layout precautions: an ics2509c is used as an example. it is similar to the icsvf2509. the same rules and methods apply. 1) use copper flooded ground on the top signal layer under the clock buffer the area under u1 in figure 1 on the right is an example. every ground pin goes to a ground via. the vias are not visible in figure 1. 2) use power vias for power and ground. vias 20 mil or larger in diameter have lower high frequency impedance. vias for signals may be minimum drill size. 3) make all power and ground traces are as wide as the via pad for lower inductance. 4) vaa for pin 23 has a low pass rc filter to decouple the digital and analog supplies. c9-12 may be replaced with a single low esr (0.8 ohm or less) device with the same total capacitance. r2 may be replaced with a ferrite bead. the bead should have a dc resistance of at least 0.5 ohms. 1 ohm is better. it should have an impedance of at least 300 ohms at 100mhz. 600 ohms at 100mhz is better. 5) notice that ground vias are never shared. 6) all vcc pins have a decoupling capacitor. power is always routed from the plane connection via to the capacitor pad to the vcc pin on the clock buffer. 7) component r1 is located at the clock source. 8) component c1, if used, has the effect of adding delay. 9) component c7 , if used, has the effect of subtracting delay. delaying the fbin clock will cause the output clocks to be earlier. a more effective method is to use the propagation time of a trace between fbout and fbin. component values: c1,c7= as necessary for delay adjust c[6:2]=.01uf c8,c13=0.1uf c[12:9]=4.7uf r1=10 ohm. locate at driver r2=10 ohm. figure 1.
7 icsvf2509b 1036c?07/13/05 ordering information icsvf2509 ygln-t designation for tape and reel packaging rohs compliant (optional) pattern number (2 or 3 digit number for parts with rom code patterns) package type g = tssop revision designator (will not correlate with datasheet revision) device type (consists of 3 to 7 digit numbers) prefix ics, av = standard device example: ics xxxx y g - ppp ln - t 4.40 mm. body, 0.65 mm. pitch tssop (173 mil) (0.0256 inch) index area index area 12 1 2 n d e1 e seating plane seating plane a1 a a2 e -c- - c - b c l aaa c min max min max a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.19 0.30 .007 .012 c 0.09 0.20 .0035 .008 d e e1 4.30 4.50 .169 .177 e l 0.45 0.75 .018 .030 n 0 8 0 8 aaa -- 0.10 -- .004 v ariations min max min max 24 7.70 7.90 .303 .311 10-0035 symbol in millimeters in inches common dimensions common dimensions see variations see variations 6.40 basic 0.252 basic 0.65 basic 0.0256 basic see variations see variations n d mm. d (inch) reference doc.: jedec publication 95, mo-153
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