View IS31IO7326_7225433.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

IS31IO7326 integrated silicon solution, inc. ? www.issi.com rev.a, 12/19/2011 1 debounced 88 key-scan controller january 2012 general description the IS31IO7326 is a 64 key, key-scan controller. it offloads the burden of keyboard scanning from the host processor. the IS31IO7326 supports keypad matrix of up to 88. key press and release events are encoded into a byte format and loaded into a key event register for retrieval by the host processor. the IS31IO7326 integrates a debounce function which rejects false or transient key switch activities. the interrupt output (int _______ ) is used to signify if there are any keypad activities. to minimize power, the IS31IO7326 automatically enters a low power standby mode when there is no keypad, i/o, or host activity. the IS31IO7326 is available in a pb-free 4mm 4mm qfn-24 package. typical application circuit features ? 2.4v to 5.5v operation ? 400khz i 2 c serial interface ? available for multi-key press detect ? low 0.3 a (typ.) standby current ? operate in -40c to +125c ? pb-free 4mm 4mm qfn-24 package applications ? keypad of qwerty type phones ? pdas, games, and other handheld applications pp0 pp1 pp2 pp3 od0 od1 od2 pp4 pp5 pp6 pp7 od4 od5 od6 od7 od3 scl sda int rst ad0 ad1 gnd vcc micro controller 100k 1 f 4.7k 4.7k 4.7k IS31IO7326 13 12 11 10 8 7 6 5 1 2 3 4 14 15 16 17 19 20 22 23 18 24 9 21 v battery v dd v battery 100k 0.1 f figure 1 typical application circuit
IS31IO7326 integrated silicon solution, inc. ? www.issi.com rev.a, 12/19/2011 2 pin configuration package pin configuration (top view) qfn-24 pin description no. pin description 1~4, 14~17 pp0~pp7 output ports. 5~8, 10~13 od0~od7 input ports. 9 gnd ground. 18 ad0 address setting. 19 scl i2c serial clock. 20 sda i2c serial data. 21 vcc power supply voltage. 22 int _______ interrupt output, active low. 23 rst ________ reset input, active low. 24 ad1 address setting. thermal pad connect to gnd. copyright ? ? ? 2011 ? integrated ? silicon ? solution, ? inc. ? all ? rights ? reserved. ? issi ? reserves ? the ? right ? to ? make ? changes ? to ? this ? specification ? and ? its ? products ? at ? any ? time ? without ? notice. ? issi ? assumes ? no ? liability ? arising ? out ? of ? the ? application ? or ? use ? of ? any ? information, ? products ? or ? services ? described ? herein. ? customers ? are ? advised ? to ? obtain ? the ? latest ? version ? of ? this ? device ? specification ? before ? relying ? on ? any ? published ? information ? and ? before ? placing ? orders ? for ? products. ? integrated ? silicon ? solution, ? inc. ? does ? not ? recommend ? the ? use ? of ? any ? of ? its ? products ? in ? life ? support ? applications ? where ? the ? failure ? or ? malfunction ? of ? the ? product ? can ? reasonably ? be ? expected ? to ? cause ? failure ? of ? the ? life ? support ? system ? or ? to ? significantly ? affect ? its ? safety ? or ? effectiveness. ? products ? are ? not ? authorized ? for ? use ? in ? such ? applications ? unless ? integrated ? silicon ? solution, ? inc. ? receives ? written ? assurance ? to ? its ? satisfaction, ? that: ? a.) ? the ? risk ? of ? injury ? or ? damage ? has ? been ? minimized; ? b.) ? the ? user ? assume ? all ? such ? risks; ? and ? c.) ? potential ? liability ? of ? integrated ? silicon ? solution, ? inc ? is ? adequately ? protected ? under ? the ? circumstances
IS31IO7326 integrated silicon solution, inc. ? www.issi.com rev.a, 12/19/2011 3 ordering information industrial range: -40c to +125c order part no. package qty/reel IS31IO7326-qfls4-tr qfn-24, lead-free 2500
IS31IO7326 integrated silicon solution, inc. ? www.issi.com rev.a, 12/19/2011 4 absolute maximum ratings supply voltage, v cc -0.3v ~ +6.0v voltage at any input pin (except pp0-pp7) -0.3v ~ v cc +0.3v scl, sda, ad, rst ________ , int _______ , od0-od3 -0.3v ~ +6.0v pp0?pp3 -0.3v ~ v cc +0.3v pp source output current 100ma pp/od sink current 120ma sda sink current 10ma int _______ sink current 10ma continuous power dissipation (t a = 70c) 24-pin qfn (derate 33.2mw/c over 70c) 2.65w maximum junction temperature, t jmax 150c storage temperature range, t stg -65c ~ +150c operating temperature range, t a ? 40c ~ +125c solder information, vapor phase (60s) infrared (15s) 215c 220c esd hbm 4kv note: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the sp ecifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. electrical characteristics t a = -40c ~ +125c, v cc = 2.4v ~ 5.5v, unless otherwise noted. typical values are at t a = 25c, v cc = 3.3v. ( note 1 ) symbol parameter condition min. typ. max. units v cc supply voltage 2.4 5.5 v v por power-on-reset voltage v cc falling 2.35 v i stb standby current (interface idle) scl,sda and other digital inputs at v cc 0.3 1.9 a i+ supply current (interface running) f scl = 400khz other digital inputs at v cc 6.5 25 a v ih logic ?1? input voltage 1.4 v v il logic ?0? input voltage 0.4 v i ih , i il input leakage current sda, scl, ad0, ad1, rst ________ , od0~od7 at v cc or gnd -0.2 +0.2 a c in input capacitance sda, scl, ad0, ad1, rst ________ , od0~od7, pp0~pp7 (note 2) 10 pf v ol logic ?0? output voltage pp0~pp7 v cc = 2.5v, i sink = 10ma 200 mv v cc = 3.3v, i sink = 15ma 240 v cc = 5.0v, i sink = 20ma 250 v ol int _______ output low-voltage int _______ i sink = 5ma 180 mv t scan time to scan key matrix completely configuration register bit sd = 0 16 ms configuration register bit sd = 1 9
IS31IO7326 integrated silicon solution, inc. ? www.issi.com rev.a, 12/19/2011 5 timing characteristics t a = -40c ~ +125c, v cc = 2.4v ~ 5.5v, unless otherwise noted. typical values are at t a = 25c, v cc = 3.3v. (note 3) symbol parameter condition min. typ. max. units f scl serial-clock frequency 400 khz t buf bus free time between a stop and a start condition 1.3 s t hd, sta hold time (repeated) start condition 0.6 s t su, sta repeated start condition setup time 0.6 s t su, sto stop condition setup time 0.6 s t hd, dat data hold time (note 3) 0.9 s t su, dat data setup time 100 ns t low scl clock low period 1.3 s t high scl clock high period 0.7 s t r rise time of both sda and scl signals, receiving (note 4) 20 + 0.1cb 300 ns t f fall time of both sda and scl signals, receiving (note 4) 20 + 0.1cb 300 ns t f, t x fall time of sda transmitting (note 4) 20 + 0.1cb 250 ns t sp pulse width of spike suppressed (note 5) 50 ns c b capacitive load for each bus line 400 pf t w rst ________ pulse width 500 ns t rst ________ rst ________ rising to start condition setup time 1 s port and interrupt timing characteristics t = -40c ~ +125c, v cc = 2.4v ~ 5.5v, unless otherwise noted. typical values are at t a = 25c, v cc = 3.3v (note 3) symbol parameter condition min. typ. max. untis t pv port output data valid c l 100pf 4 s t psu port input setup time c l 100pf 0 s t ph port input hold time c l 100pf 4 s t iv int _______ input data valid time c l 100pf 4 s t ir int _______ reset delay time from acknowledge c l 100pf 4 s note 1: all parameters are tested at t a = 25c. specifications over temperature are guaranteed by design. note 2: guaranteed by design. note 3: a master device must provide a hold time of at least 300ns for the sda signal (referred to vil of the scl signal) in order to bridge the undefined region of scl?s falling edge. note 4: cb = total capacitance of one bus line in pf. isink 6ma. tr and tf measured between 0.3 v cc and 0.7 v cc . note 5: input filters on the sda and scl inputs suppress noise spikes less than 50ns.
IS31IO7326 integrated silicon solution, inc. ? www.issi.com rev.a, 12/19/2011 6 detailed description i2c interface the IS31IO7326 uses a serial bus, which conforms to the i2c protocol, to control the chip?s functions with two wires: scl and sda. the IS31IO7326 has a 7-bit slave address (a7:a1), followed by the r/w ____ bit, a0. set a0 to ?0? for a write command and set a0 to ?1? for a read command. the bit a2:a1 are selected by the connection of ad1/ad0 pin. the complete slave address is: table 1 slave address: bit a7:a3 a2 a1 a0 default 10110 ad1 ad0 0/1 ad1/ad0 connects to vcc, ad1/ad0=1; ad1/ad0 connects to gnd, ad1/ad0=0; the scl line is uni-directional. the sda line is bi-directional (open-collector) with a pull-up resistor (typically 4.7k ? ). the maximum clock frequency specified by the i2c standard is 400khz. in this discussion, the master is the microcontroller and the slave is the IS31IO7326. the timing diagram for the i2c is shown in figure 3. the sda is latched in on the stable high level of the scl. when there is no interface activity, the sda line should be held high. the ?start? signal is generated by lowering the sda signal while the scl signal is high (figure 4). the start signal will alert all devices attached to the i2c bus to check the incoming address against their own chip address. the 8-bit chip address is sent next, most significant bit first. each address bit must be stable while the scl level is high. after the last bit of the chip address is sent, the master checks for the IS31IO7326?s acknowledge. the master releases the sda line high (through a pull-up resistor). then the master sends an scl pulse. if the IS31IO7326 has received the address correctly, then it holds the sda line low during the scl pulse. if the sda line is not low, then the master should send a ?stop? signal (discussed later) and abort the transfer. following acknowledge of IS31IO7326, the register address byte is sent, most significant bit first. IS31IO7326 must generate another acknowledge indicating that the register address has been received. an 8-bit data byte is sent next, most significant bit first. each data bit should be valid while the scl level is stable high. after the data byte is sent, the IS31IO7326 must generate another acknowledge to indicate that the data was received. the ?stop? signal ends the transfer. to signal ?stop?, the sda signal goes high while the scl signal is high (figure 4). writing to the registers transmit data to the IS31IO7326 by sending the device slave address and setting the lsb to ?0?. the command byte is sent after the address and determines which registers receive the data following the command byte (figure 2). reading port registers to read the device data, the bus master must first send the IS31IO7326 address with the r/w ____ bit set to ?0?, followed by the command byte, which determines which register is accessed. after a restart, the bus master must then send the IS31IO7326 address with the r/w ____ bit set to ?1?. data from the register defined by the command byte is then sent from the IS31IO7326 to the master (figure 6). figure 2 writing to IS31IO7326
IS31IO7326 integrated silicon solution, inc. ? www.issi.com rev.a, 12/19/2011 7 p s start condition restart condition r stop condition start condition t hd,sta t low t su,dat t high t r t f t hd,dat t su,sta t hd,sta t su,sto t buf scl sda figure 3 interface timing figure 4 start and stop conditions figure 5 acknowledge signal figure 6 reading i/o ports of IS31IO7326 int key press/release 16ms (6ms/8ms) key press/release 9ms (3ms/4ms) figure 7 int _______ timing
IS31IO7326 integrated silicon solution, inc. ? www.issi.com rev.a, 12/19/2011 8 register definition table 2 register function address name function default ta bl e 08h configuration register configure the keypad scan function 0001 0000 3 10h key status register contains the information of the key events 0000 0000 4 table 3 08h configuration register bit d7 d6:d5 d4 d3 d2 d1:d0 name reserved aci de sd le lt default 0 00 1 0 0 00 the configuration register is used to configure the keypad scan function. aci auto clear int _______ 00 auto clear int _______ disabled 01 auto clear int _______ in 5ms 10 auto clear int _______ in 10ms de input port filter enable 0 input port filter disable 1 input port filter enable sd key scan debounce time 0 double debounce time (6ms, 8ms) 1 normal debounce time (3ms, 4ms) le long-pressed key detect enable 0 disable 1 enable lt long-pressed key detect delay time 00 20ms 01 40ms 10 1s 11 2s table 4 10h key status register bit d7 d6 d5:d0 name dn ks km default 0 0 000000 the key status register contains the information of the key events that have been debounced (see the table 5 of the key mapping). dn indicate data number 0 one key event to report 1 more than one key to report ks key state 0 key released 1 key pressed km key mapping km denotes which of the 64 keys have been debounced and the keys are numbered as shown in the table 5. when the key status register is read over (dn=0), the register is set to ?0000 0000?, and the int _______ is cleared.
IS31IO7326 integrated silicon solution, inc. ? www.issi.com rev.a, 12/19/2011 9 table 5 key mapping (d5:d0) pp0 pp1 pp2 pp3 pp4 pp5 pp6 pp7 od0 000000 000001 000010 000011 000100 000101 000110 000111 od1 001000 001001 001010 001011 001100 001101 001110 001111 od2 010000 010001 010010 010011 010100 010101 010110 010111 od3 011000 011001 011010 011011 011100 011101 011110 011111 od4 100000 100001 100010 100011 100100 100101 100110 100111 od5 101000 101001 101010 101011 101100 101101 101110 101111 od6 110000 110001 110010 110011 110100 110101 110110 110111 od7 111000 111001 111010 111011 111100 111101 111110 111111 examples 1. if the key pp1-od3 pressed only, and other keys keep released state, the int _______ asserts, the data in key status register would be ?0101 1001?; 2. if the key pp4-od6 released only, and other keys keep released state, the int _______ asserts, the data in key status register would be ?0011 0100?; 3. if the key pp2-od4 and pp3-od7 are pressing, then pp2-od4 released, the int _______ asserts, the first data in key status register would be ?1010 0010?, the second data would be ?0111 1011?. then judge the msb (bit dn) in the second data is ?0?. data has read over, and int _______ goes to high. we must read over the data in key status register when the i n t _______ asserts. when judge the msb (bit dn) in the data is ?0?, stop reading the key status register. if there are some keys connected to the same od port pressing at the same time, IS31IO7326 only can detect the first pressed key and others will ignore.
IS31IO7326 integrated silicon solution, inc. ? www.issi.com rev.a, 12/19/2011 10 application information input and output port structure a 100k ? pull-up resistor will force input port high at v battery . output v+ gnd pp0~pp7 dirver figure 8 output port structure figure 9 input port structure power-on reset the IS31IO7326 contains an integral power-on-reset circuit that ensures all registers are reset to a known state on power-up. when v cc rises above 2.4v, the circuit releases the registers and the i2c interface for normal operation. when v cc drops to less than v por , the IS31IO7326 resets all register contents to the default value. rst ________ i2c reset control the active-low rst ________ input voids any i2c transaction involving the IS31IO7326, forcing the IS31IO7326 into the i2c stop condition. a reset does not affect the interrupt output. standby mode when the serial interface is idle, the IS31IO7326 automatically enters standby mode, drawing minimal supply current. keypad auto scan the IS31IO7326 can support an 88 matrix keypad scan. the 8 input ports (od ports) need a 100k ? pull-up resistor for each column, the 8 output ports (pp ports) for the rows pull low in standby mode. if a change of the state of the keypad is detected, the keypad would be scanned thrice between the debounce delay. when the state changes have been reliably captured, the key event(s) are encoded and written to temporary key status registers. the int _______ asserts when the key event(s) is (are) stored. reading the key status register reports the key events in the order of lowest encoding value to the highest (see table 5). the int _______ will remain low until all of the key events are read, with one exception: when the auto-clear int _______ is enabled, if all of the key event data is not read before the programmed time, the int _______ will return high after the programmed time. however the temporary key status registers will remain unchanged and the key event data may continue to be read until another key event is detected. debounce when the bit sd of the configuration register (08h) is set to ?0? and there is a change of the state of the keypad, the keypad scans first and stores the data in temporary registers, then waits for about 6ms (3ms) and scans again, then waits for another 8ms (4ms) and scans a final time. if the results are the same, the data is latched into the temporary key status registers and the int _______ asserted. otherwise, the scan is halted and the device returns to standby mode. no data is latched into the temporary key status registers and the int _______ is not asserted. long-pressed key detect when the bit le of the configuration register (08h) is set to ?0?, this function is disabled. when le is set to ?1?, this function is enabled. when a key is pressed for a long period of time, the chip automatically scans again after the int _______ is deasserted. when the key is still pressed, the int _______ asserts again and the key event is latched into the temporary key status registers. the scanning continues until all of the keys are released. the delay time between the int _______ deasserting to the next scan beginning is set by the configuration register (08h) bits lt. key event interrupt (int _______ ) once there is key event code latched in the temporary key status registers, the device produces an interrupt signal to the mcu on the int _______ pin. when the int _______ is asserted, any keypad state changes are ignored. the int _______ will remain low until all of the key events are read, with one exception: when the auto-clear int _______ is enabled, if all of the key event data is not read before the programmed time, the int _______ will return high after
IS31IO7326 integrated silicon solution, inc. ? www.issi.com rev.a, 12/19/2011 11 the programmed time. however the temporary key status registers will remain unchanged and the key event data may continue to be read until another key event is detected. after all of the key events have been read, the device returns to standby mode waiting for the next scan. auto-clear int _______ function when the aci bits of the configuration register (08h) are set to ?01? or ?10?, this function is enabled. setting the aci bits to ?00? disables the function. when enabled, the int _______ would be cleared in 5ms or 10ms after it asserts if there is no read of the key status register. the data in the temporary key status registers does not change when the int _______ goes low. the key status register can be read regardless of whether the int _______ is high or not. however, when the int _______ is cleared and there is new key event activity before the old key event data is read, the temporary key status registers are rewritten and the int _______ asserts again. in this case, the previous key event data is lost and only the new key event(s) can be read. the input port filter the bit de of the configuration register (08h) is used to enable the input port filter. when de is set to ?0?, the input port filter is disabled, and the chip responds to any changes at the input port. when de is set to ?1?, the input port filter is enabled and any glitch shorter than 100ns is filtered. if the input pulse width is greater than 100ns, the chip responds (figure 10). figure 10 input port debounce function
IS31IO7326 integrated silicon solution, inc. ? www.issi.com rev.a, 12/19/2011 12 classification reflow profiles profile feature pb-free assembly preheat & soak temperature min (tsmin) temperature max (tsmax) time (tsmin to tsmax) (ts) 150c 200c 60-120 seconds average ramp-up rate (tsmax to tp) 3c/second max. liquidous temperature (tl) time at liquidous (tl) 217c 60-150 seconds peak package body temperature (tp)* max 260c time (tp)** within 5c of the specified classification temperature (tc) max 30 seconds average ramp-down rate (tp to tsmax) 6c/second max. time 25c to peak temperature 8 minutes max. figure 11 classification profile
IS31IO7326 integrated silicon solution, inc. ? www.issi.com rev.a, 12/19/2011 13 tape and reel information
IS31IO7326 integrated silicon solution, inc. ? www.issi.com rev.a, 12/19/2011 14 package information qfn-24 note: all dimensions in millimeters unless otherwise stated.

▲Up To Search▲

Price & Availability of IS31IO7326

	To Download IS31IO7326 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .