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1 of 20 091707 features ? memory maps into any standard byte-wide data bus. ? eliminates cpu ?bit-banging? by internally generating all 1-wire tim ing and control signals. ? generates interrupts to provide for more efficient programming. ? search rom accelerator relieves cpu from any single bit operations on the 1-wire ? bus. ? capable of running off any system clock from 4 mhz to 128 mhz. ? small size: all digital design, only 3470 gates. ? applications include any circuit containing a 1- wire communication bus. ? supports standard and overdrive 1-wire communication speeds ? supports strong pull-up specifications. ? master available in both verilog and vhdl ? supports single bit transmissions. ? provides added support for long line conditions. customer asic description as more 1-wire devices become available, more a nd more users have to de al with the demands of generating 1-wire signals to communicate to them. this usually requires ?bit-banging? a port pin on a microprocessor, and having the microprocessor perfor m the timing functions required for the 1-wire protocol. while 1-wire transmission can be interru pted mid-byte, it cannot be interrupted during the ?low? time of a bit time slot; this means that a cpu will be idled for up to 60 microseconds for each bit sent and at least 480 microseconds when generating a 1- wire reset. the 1-wire master helps users handle communication to 1-wire devices in their system without tying up valuab le cpu cycles. integrated into a user?s asic as a 1-wire port, the verilog or vhdl core uses little chip ar ea (3470 gates plus 2 bond pads). this circuit is designed to be me mory mapped into the user?s system and provides complete control of the 1-wire bus through 8-bit or singl e commands. the host cpu loads comma nds, reads and writes data, and sets interrupt control through six indi vidual registers. all of the timing and control of the 1-wire bus are generated within. the host merely needs to load a command or data and then may go on about its business. when bus activity has generated a response that the cpu needs to receive, the 1-wire master sets a status bit and, if enabled, generates an in terrupt to the cpu. in addition to write and read simplification, the 1-wire master also provides a search rom accelerator function relieving the cpu from having to perform the complex singl e-bit operations on the 1-wire bus. DS1WM synthesizable 1-wire bus maste r www.maxim-ic.com 1-wire tm master 1-wire bus internal data bus interrupt strong pull-up co n t r o l 1-wire is a registered trademark of dalla s semiconductor corp., a wholly owned subsid iary of maxim integrated products, inc.
DS1WM 2 of 20 the operation of the 1-wire bus is described in detail in the book of ibutton ? standards [1]; therefore, the details of that will not be discussed in this docu ment. each slave device, in general, has its own set of commands that are described in detail in that device?s data sheet. the us er is referred to those documents for detail on specific slave implementations. block diagram interrupt register int enable register data bus buffer control logic master reset 1-wire timing and control interrupt control logic dq a0 m r d0-d7 int r a1 a2 ads rd w r en cl k clock divider command register transmit buffer tx shift register rx shift register receive buffer clock div register control register owstpz pin descriptions the following describes the function of all the block i/ o pins. in the following descriptions, 0 represents logic low and 1 repr esents logic high. a0, a1, a2 , register select: address signals connected to these three inputs select a register for the cpu to read from or write to during da ta transfer. a table of registers a nd their addresses is shown below. i button is a registered trademark of dallas semiconductor corp., a wholly owned subsidiary of maxim integrated products, inc.
DS1WM 3 of 20 register addresses a2 a1 a0 register 0 0 0 command register (read/write) 0 0 1 transmit buffer (write), receive buffer (read) 0 1 0 interrupt register (read) 0 1 1 interrupt enable register (read/write) 1 0 0 clock divisor register (read/write) 1 0 1 control register (read/write) ads , address strobe: the positive edge of an active address strobe ( ads ) signal latches the register select (a0, a1, a2) into an inte rnal latch. provided that setup and hold timings are observed, ads may be tied low making the latch transparent. clk , clock input: this is a (preferabl y) 50% duty cycle clock that can range from 4 mh z to 128 mhz. this clock provides the timing for the 1-wire bus. d7-d0 , data bus: this bus comprises eight input/ output lines. the bus provides bi-directional communications between the 1-wire master and the cpu. data, control words, and status information are transferred via this d7-d0 data bus. dq , 1-wire data line: this open-drai n line is the 1-wire bi-directional data bus. 1-wire slave devices are connected to this pin. this pin must be pulled high by an external resistor, nominally 5 k . en , enable: when en is low, the 1-wire master is enabled; this signal acts as the device chip enable. this enables communication between the 1-wire master and the cpu. intr , interrupt: this line goes to its active state when ever any one of the inte rrupt types has an active high condition and is enabled via the interrupt enable register. the intr signal is reset to an inactive state when the interrupt register is read. mr , master reset: when this input is high, it clears all the registers and the cont rol logic of the 1-wire master, and sets intr to its default inactive state, which is high. rd , read: this pin drives the bus du ring a read cycle. when the circuit is enabled, the cpu can read status information or data from the selected register by driving rd low. rd and w r should never be low simultaneously; if they are, w r takes precedence. stpz , strong pull-up enable: this pin drives the gate of the p-channel transi stor which bypasses the weak pull-up resistor in order to provide the sl ave device with a stiff power supply for high current applications. w r , write: this pin drives the bus during a write cycle. when w r is low while the circuit is enabled, the cpu can write control words or data into the selected register. rd and w r should never be low simultaneously; if they are, w r takes precedence. operation ? commands the 1-wire master can generate two special commands on the bus in addition to reading and writing. the first is a 1-wire reset, which must precede any co mmand given on the bus. secondly, the 1-wire master can be placed into search rom accelerator mode to prevent the host from having to perform single bit manipulations of the bus during a search rom operati on (0xf0h). for details on the reset or search
DS1WM 4 of 20 rom command see [1]. in addition to these two func tions, the command register contains two bits to bypass the 1-wire master features an d control the 1-wire bus directly. command register (read/write) default: 08h addr. 00h x x x x ow_in fow sra 1wr msb lsb bit 3 - ow_in: ow input. this bit always reflects the current state of the 1-wire line. bit 2 - fow: force one wire. this bit can be used to bypa ss 1-wire master operati ons and drive the bus directly if needed. sett ing this bit high will drive th e bus low until it is cleared or the 1-wire master reset. while the 1-wire bus is held low no other 1-wire master operations will function. by controlling the length of time this bit is set and the point when the line is sampled, any 1-wire communication can be generated by the host controller. to prevent accide ntal writes to the bus, the en_fow bit in the control register must be set to a 1 before the fow bit will function. this bit is cleared to a 0 on power-up or master reset. bit 1 - sra: search rom accelerator. when this bit is set, the 1-wire master will switch to search rom accelerator mode. (see ?sea rch rom accelerator description? for the rest of the function description.) when this bit is set to 0, the master w ill function in its normal mode. this bit is cleared to 0 on a power-up or master reset. bit 0 - 1wr: 1-wire reset. if this bit is set a reset will be generated on the 1-wire bus. setting this bit automatically clears the sra bit. the 1wr bit will be automatically cleared as soon as the 1-wire reset completes. the 1-wire master will set the presence det ect interrupt flag (pd) when the reset is complete and sufficient time for a presence detect to occur has passed. the result of the presence detect will be placed in the interrupt register bit pdr. if a pr esence detect pulse was received pdr will be cleared, otherwise it will be set. search rom accelerator description the search rom accelerator mode presupposes th at a reset followed by the search rom command (0xf0h) has already been issued on the 1-wire bus. for details on how the search rom is actually done in the 1-wire system, please see [1]. simply put, the al gorithm specifies that the bus master reads two bits (a bit and its complement), then writes a bit to speci fy which devices should remain on the bus for further processing. after the 1-wire master is placed in search rom accelerator mode, the cpu must send 16 bytes to complete a single search rom pass on the 1-wire bus. these bytes are constructed as follows: first byte 7 6 5 4 3 2 1 0 r 3 x 3 r 2 x 2 r 1 x 1 r 0 x 0 16 th byte 7 6 5 4 3 2 1 0 r 63 x 63 r 62 x 62 r 61 x 61 r 60 x 60 in this scheme, the index (values from 0 to 63, ?n?) designates the position of the bit in the rom id of a 1-wire device. the character ?x? marks bits that act as a filler and do not requi re a specific value (don?t care bits). the character ?r? specifies the selected bit value to write at that particular bit in case of a conflict during the execution of the rom search.
DS1WM 5 of 20 for each bit position n (values from 0 to 63) the 1-wi re master will generate three time slots on the 1- wire bus. these are referenced as: b0 for the first time slot (read data) b1 for the second time slot (read data) and b2 for the third time slot (write data). the 1-wire master determines the type of tim e slot b2 (write 1 or write 0) as follows: b2 = r n if conflict (as chosen by the host) = b 0 if no conflict (there is no alternative) = 1 if error (there is no response) the response bytes that will be in the data register for the cpu to read during a complete pass through a search rom function using the search acce lerator consists of 16 bytes as follows: first byte 7 6 5 4 3 2 1 0 r? 3 d 3 r? 2 d 2 r? 1 d 1 r? 0 d 0 et cetera 16 th byte 7 6 5 4 3 2 1 0 r? 63 d 63 r? 62 d 62 r? 61 d 61 r? 60 d 60 as before, the index designates the position of the bit in the rom id of a 1-wire device. the character ?d? marks the discrepancy flag in that particular bit position. the discrepancy flag will be 1 if there is a conflict or no response in that particular bit pos ition and 0 otherwise. the character ?r?? marks the actually chosen path at that particular bit position. the chosen path is identical to b2 for the particular bit position of the rom id. to perform a search rom sequence one starts with all bits r n being 0s. in case of a bus error, all subsequent response bits r? n are 1?s until the search accelerator is deactivated by writing 0 to bit 1 of the command register. thus, if r? 63 and d 63 are both 1, an error has occurred during the search procedure and the last sequence has to be repeated. otherwise r? n (n=0?63) is the rom code of the device that has been found and addressed. when the search rom proces s is complete the sra bit should be cleared in order to release the 1-wire master from search rom accelerator mode. for the next search rom sequence one re-uses the previous set r n (n=0?63) but sets r m to 1 with ?m? being the index number of th e highest discrepancy flag that is 1 and sets all r i to 0 with i > m. this process is repeated until the highest discrepancy occurs in the same bit position for two consecutive passes.
DS1WM 6 of 20 example ? accelerated rom search in this example, the host will use the 1-wire master to identify four different devices on the 1-wire bus. the rom data of the devices is as shown (lsb first): rom1 = 00110101? rom2 = 10101010? rom3 = 11110101? rom4 = 00010001? 1) the host issues a reset pulse by writing 0x01h to the command register. all slave devices respond simultaneously with a presence detect. 2) the host issues a search rom command by writing 0xf0h to the transmit buffer. 3) the host places the 1-wire master in acceler ator mode by writing 0x02 to the command register. 4) the host writes 0x00h to transmit buffer and reads the returning data from the receive buffer. this process is repeated for a total of 16 bytes. the data read will contain rom4 in the r? locations and discrepancy bits set at d0 and d2 as shown (r? locati ons are underlined, most significant discrepancy is bolded ): received data 1 = 10 00 1 0 01 00 00 00 01 ? 5) the host then de-interleaves the data to ar rive at a rom code of 00010001? with the last discrepancy at location d2. 6) the host writes 0x00h to the command register to exit search accelerator mode. the host is now free to send a command or read da ta directly from this device. 7) steps 1-6 are now repeated to find the next device. the 16 bytes of data transmitted this time are identical to rom4 up until the last discrepancy bit (d2 in this case) which is inverted and all data following is set to 0 as shown. the received data will contain rom1 in the r? locations and bits d0 and d2 will be set again: transmitted data 2 = 00 00 01 00 00 00 00 00 ? received data 2 = 10 00 1 1 01 00 01 00 01 ? 8) since the most significant discrepa ncy (d2) did not change , the next most (d0) will be used and the process repeats. further iterati ons contain the data as shown: transmitted data 3 = 01 00 00 00 00 00 00 00 ? received data 3 = 11 1 0 01 00 01 00 01 00 ? transmitted data 4 = 01 01 00 00 00 00 00 00 ? received data 4 = 11 1 1 01 01 00 01 00 01 ? 9) at this point, the most significant discrepancy (d1) did not change so the next most (d0) should be used. however, d0 has now been reached for the s econd time and since there are no less significant discrepancies, the search is complete having found a total of four devices.
DS1WM 7 of 20 operation ? transmitting / receiving data data sent and received from the 1-wire master passes through the transmit/receive buffer location. the 1- wire master is actually double buffered with separa te transmit and receive buffers. writing to this location connects the transmit buffer to the data bus , while reading connects the receive buffer to the data bus. transmit buffer (write) / rece ive buffer (read) default: 00h addr. 01h data7 data6 data5 da ta4 data3 data2 data1 data0 msb lsb writing a byte to send a byte on the 1-wire bus, the user writes the desired data to the transmit buffer. the data is then moved to the transmit shift register where it is sh ifted serially onto the bus lsb first. a new byte of data can then be written to the tr ansmit buffer. as soon as the transmit shift register is empty, the data will be transferred from the transmit buffer and the process repeats. each of these registers has a flag that may be used as an interrupt source. the transm it buffer empty (tbe) flag is set when the transmit buffer is empty and ready to accept a new byte. as soon as a byte is written into the transmit buffer, tbe is cleared. the transmit shift register empty (temt) flag is set when the shift register has no data in it and is ready to accept a new byte. as soon as a byte of data is transferred from the transmit buffer, temt is cleared and tbe is set. remember that prope r 1-wire protocol requires a reset before any bus communication. reading a byte to read data from a slave device, the device must first be ready to transmit data depending on commands already received from the cpu. data is retrieved fr om the bus in a similar fashion to a write operation. the host initiates a read by writing to the transmit buffer . the data that is then shifted into the receive shift register is the wired-and of the written data a nd the data from the slave device. therefore in order to read a byte from a slave device the host must write 0xffh. when the receive shift register is full the data is transferred to the receive buffer where it can be accessed by the host. additional bytes can now be read by sending 0xffh agai n. if the slave device is not ready to transmit, the data received will be identical to that which was transmitted. the receive bu ffer register can also generate interrupts. the receive buffer flag (rbf) is set when data is tran sferred from the receive shift register and cleared when the host reads the register. if rbf is set, no fu rther transmissions should be made on the 1-wire bus or else data may be lost, as the by te in the receive buffer will be over written by the next received byte. see the timing diagrams for details of the byte recep tion operation. generating a 1-wire reset on the bus is covered under command operations . interrupt flags are explained in further detail under interrupt operations. write and read operations are detailed in the timing diagrams.
DS1WM 8 of 20 operation ? flags and interrupts flags from current status, transmit, receive, and 1- wire reset operations are located in the interrupt register. the presence detect fl ag (pd), ow_low, and ow_short are cleared when the interrupt register is read. the other flags are cleared automatically when th e transmit and receive buffers are written to or read from. all of these flags can gene rate an interrupt on the in tr pin if th e corresponding enable bit is set in the interrupt enable register. to clear the intr signal, the in terrupt register must be read. reading the interrupt register always sets the intr pin inactive even if all flags are not cleared. interrupt register (read only) default: 0eh addr. 02h ow_low ow_short rsrf rbf temt tbe pdr pd msb lsb ow_low: one wire low. this flag will be set to 1 when the 1-wire line is low while the master is in idle signaling that a slave device has issued a pres ence pulse on the 1-wire (dq) line. a read to the interrupt register will clear this bit. ow_short: one wire short. this flag will be set to a 1 when the 1-wire line was low before the master was able to send out the beginning of a reset or a time slot. when this flag is 0, it indicates that the 1-wire line was high as expected prior to all resets and time slots. a read to the interrupt register will clear this bit. rsrf: receive shift register full. this flag will be set to 1 when there is a byte of data waiting in the receive shift register. when this bit is 0, it indicates that the receive shift register is either empty or currently receiving data. this bit wi ll be cleared by the hardware when data in the receive shift register is transferred to the receive buffer. a read to the interrupt register will ha ve no effect on this bit. rbf: receive buffer full. this flag will be set to 1 when there is a byte of data waiting to be read in the receive buffer. when this bit is 0, it indicates that the receive buffer has no new data to be read. this bit will be cleared when the byte is read from the r eceive buffer. a read to the interrupt flag register will have no effect on this bit. however, following a read of the interrupt register, while enable receive buffer full interrupt (erbf) is set to 1, if the erbf is not cleared and the valu e is not read from the receive buffer, the interrupt will fire again. temt: transmit shift register empty. this flag will be set to 1 when there is nothing in the transmit shift register and it is ready to receive the next byte of data to be transmitted from the transmit buffer. when this bit is 0, it indicates that the transmit shift register is busy sending out data. this bit is cleared when data is transferred from the transmit buffer to the transmit shift register. a read to the interrupt register will have no effect on this bit. tbe: transmit buffer empty. this flag will be set to 1 when there is nothing in the transmit buffer and it is ready to receive the next byte of data. when it is 0, it indicates th at the transmit buffer is waiting for the transmit shift register to finish sending its current data before updating it. this bit is cleared when data is written to the transmit buffer. a read to the interrupt register will ha ve no effect on this bit. pdr: presence detect result. when a presence detect in terrupt occurs, this bit will reflect the result of the presence detect read ? it will be 0 if a slave was found, or 1 if no part was found. a read to the interrupt register will have no effect on this bit. pd: presence detect. after a 1-wire reset has been issue d, this flag will be set to 1 after the appropriate amount of time for a presence detect pul se to have occurred. this flag w ill be 0 when the master has not issued a 1-wire reset since the previous read of th e interrupt register. this bit is cleared when the interrupt register is read.
DS1WM 9 of 20 operation ? flags and interrupts (continued) the interrupt enable register allows the system programmer to specify the source of interrupts which will cause the intr pin to be active, and to define the active state for the intr pin. when a master reset is received all bits in this register are cleared to 0 disa bling all interrupt sour ces and setting the active state of the intr pin to low. this means the in tr pin will be pulled high since all interrupts are disabled. the intr pin is re set to an inactive state by r eading the interrupt register. interrupt enable register (r ead / write) default: 00h addr. 03h eowl eowsh ersf erbf etmt etbe ias epd msb lsb eowl: enable one wire low interrupt. setting this bit to a 1 enables the one wire low interrupt. if set, intr will be asserted when the ow_low flag is set. clearing this bit disables ow_low as an active interrupt source. eowsh: enable one wire short interrupt. setting this bit to a 1 enables the one wire short interrupt. if set, intr will be asserted wh en the ow_short flag is set. cleari ng this bit disa bles ow_short as an active interrupt source. ersf: enable receive shift register full interrupt. se tting this bit to a 1 enables the receive shift register full interrupt. if set, intr will be asserted wh en the rsrf flag is set. clearing this bit disables rsrf as an active interrupt source. erbf: enable receive buffer full in terrupt. setting this bit to a 1 enables the receive buffer full interrupt. if set, intr will be asserted when the rbf flag is set. clearing this bit disables rbf as an active interrupt source. etmt: enable transmit shift register empty interrupt. setting this bit to a 1 enables the transmit shift register empty interrupt. if set, intr will be assert ed when the temt flag is set. clearing this bit disables temt as an active interrupt source. etbe: enable transmit buffer empty interrupt. settin g this bit to a 1 enables the transmit buffer empty interrupt. if set, intr will be asserted when th e tbe flag is set. clearing this bit disables tbe as an active interrupt source. ias: intr active state. this bit determines the active st ate for the intr pin. if th is bit is a 1, the intr pin is active high; if it is a 0, the intr pin is active low. epd: enable presence detect interrupt. setting this bit to a 1 enables the presence detect interrupt. if set, intr will be asserted when the pd flag is set. cleari ng this bit disables pd as an active interrupt source.
DS1WM 10 of 20 operation ? clock divisor all 1-wire timing patterns are generated using a base clock of 1.0 mhz. the 1-wire master will generate this clock frequency internally given an external re ference on the clk pin. the external clock must have a frequency from 4 to 128 mhz and a 50% duty cycle is preferred. the clock divisor register controls the internal clock divider and provide s the desired reference frequency. th is is done in two stages: first a prescaler divides by 1, 3, 5, or 7, then the re maining circuitry divides by 2, 4, 8, 16, 32, 64, or 128. clock divisor register default: 00h addr. 04h clk_en x x div2 div1 div0 pre1 pre0 msb lsb the clock divisor must be configured before communi cation on the 1-wire bus can take place as well as setting the clk_en bit to a 1. this register is set to 0x00h if a master reset occurs. use the table below to find the proper register value based on the clk reference frequenc y. for example, the user would write 0x87h to this location when providing a 15 mhz input clock. clock divisor register settings for input clock rates min clk frequency (mhz) max clk frequency (mhz) divider ratio div2 div1 div0 pre1 pre0 4.0 < 5.0 4 0 1 0 0 0 5.0 < 6.0 5 0 0 0 1 0 6.0 < 7.0 6 0 0 1 0 1 7.0 < 8.0 7 0 0 0 1 1 8.0 < 10.0 8 0 1 1 0 0 10.0 < 12.0 10 0 0 1 1 0 12.0 < 14.0 12 0 1 0 0 1 14.0 < 16.0 14 0 0 1 1 1 16.0 < 20.0 16 1 0 0 0 0 20.0 < 24.0 20 0 1 0 1 0 24.0 < 28.0 24 0 1 1 0 1 28.0 < 32.0 28 0 1 0 1 1 32.0 < 40.0 32 1 0 1 0 0 40.0 < 48.0 40 0 1 1 1 0 48.0 < 56.0 48 1 0 0 0 1 56.0 < 64.0 56 0 1 1 1 1 64.0 < 80.0 64 1 1 0 0 0 80.0 < 96.0 80 1 0 0 1 0 96.0 < 112.0 96 1 0 1 0 1 112.0 < 128.0 112 1 0 0 1 1 operation ? master control various 1-wire devices utilize different communicati on protocols in order to properly function and report back to the master in an efficient manner. the cont rol register adds the robustness needed to handle all of the major conditions expected from each ibutton and 1-wire chip family. control register default: 00h addr. 05h x od bit_ctl stp_sply stpen en_fow ppm llm msb lsb
DS1WM 11 of 20 od: overdrive. setting this bit to a 1 will place the ma ster into overdrive mode that effectively changes the master?s 1-wire timings to matc h those outlined for overdrive in the book of ibutton standards. clearing this bit to a 0 leaves the mast er operating in standard mode speed. bit_ctl: bit control. setting this bit to a 1 will place the master into its ?bit banging? mode of operation. in this mode, only the least significan t bit of the transmit/receive register would be sent/received before enabling the inte rrupt flags that signal the end of th e transmission. clearing this bit to 0 leaves the master operating in full byte boundaries. stp_sply: strong pull-up supply. setting this bit to a 1 while stpen is also set to a 1 will enable the stpz output while the master is in an idle state. this will provide a stiff supply to devices requiring high current during operations. clearing th is bit to a 0 disables the stpz output while the master is in an idle state. the stp_sply bit is a don?t care if stpen is set to a 0. stpen: strong pull-up enable. setting this bit to a 1 enables the strong pull-up output enable (stpz) pin?s functionality which allows this output pin to enab le an external strong pull-up any time the master is not pulling the line low or waiting to read a value from a slave device. this functionality is used for meeting the recovery time requirement in overdriv e mode and long-line standard communications. clearing this bit to a 0 will disable the stpz output pin. en_fow: enable force one wire. setting this bit to a 1 w ill enable the functionality of the force one wire (fow) register bit in the command register. cl earing this bit will disable the functionality of the fow bit. ppm: presence pulse masking mode. setting this bit to a 1 will enable presence pulse masking mode. this mode causes the master to initiate the falling edge of a presence pulse during a 1-wire reset before the fastest slave would initiate one. this enables th e master to prevent the larger amount of ringing caused by the slave devices when initiating a low on the dq line. if the ppm bit is set, the pdr result bit in the interrupt register will always be set to a 0 s howing that a slave device was on the line even if there were none. clearing this bit to a 0 disa bles the presence pulse masking mode. llm: long line mode. setting this bit to a 1 will enab le long line mode timings on the 1-wire line during standard mode communications. this mode e ffectively moves the write one release, the data sampling, and the time slot recovery times out to r oughly 8s, 22s, and 14s respectively. this provides a less strict environment for long line transmissions. cl earing this bit to 0 leaves the write one release, the data sampling, and the time slot recovery ti mes at roughly 5s, 15s, and 7s respectively.
DS1WM 12 of 20 i/0 signaling the 1-wire bus requires strict signaling protocols to in sure data integrity. th e four protocols used by the 1-wire master are the initialization sequence (reset pulse followed by presence pulse), write 0, write 1, and read data. the master initiates all of these types of si gnaling except the presence pulse. the initialization sequence required to begin any communication with th e bus slave is shown in figure 1. a presence pulse following a reset pulse indicat es the slave is ready to accept a rom command. the 1-wire master transm its a reset pulse for t rstl . the 1-wire bus line is then pulled high by the pull- up resistor. after detecting the rising edge on the dq pin, the slave waits for t pdh and then transmits the presence pulse for t pdl . the master samples the bus at t pds after the slave respond s to test for a valid presence pulse or after waiting for t pdhcnt following the start of t rsth . the result of this sample is stored in the pdr bit of the interrupt re gister. the reset time slot ends t rsth after the master releases the bus. 1-wire initialization sequen ce (reset pulse and presence pulse) figure 1. write time slots a write time slot is initiated when the 1-wire ma ster pulls the 1-wire bus line from a logic high (inactive) level to a logic low level. the master gene rates a write 1 time slot by releasing the line at t low1 and allowing the line to pull up to a logic high level. the line is held low for t low0 to generate a write 0 time slot. a slave device will sample the 1-wire bus line between 15 and 60s after the line falls. if the line is high when sampled, a write 1 occurs. if th e line is low when sampled, a write 0 occurs (see figure 2). read time slots a read time slot is initiated when the 1-wire master pul ls the bus low for at least 1s and then releases it. if the slave device is responding with a 0 it will conti nue to hold the line low for up to 60s, otherwise it will release it immediately. the master will sample the data t rdv from the start of the read time slot. the master will end the read slot after a time of t slot. see figure 2 for more information. line type legend: 1 - wire master active low slave device active low resistor pullup both master and slave device active low t r s tl t pdl t r s th t pdh t pdhcnt v cc gnd dq t pds
DS1WM 13 of 20 1-wire write and read time slots figure 2. 1-wire stpz reset and read write timing figure 3. dq dq t s l o t v cc gnd write 0 slot slave device sample window min typ max 15s 15s 30s write 1 slot t s l o t t re c slave device sample window min typ max 15s 15s 30s t l o w 0 t l o w1 t s l o t v cc gnd read 0 slot t rdv read 1 slot t s l o t t re c t rdv line type legend: 1 - wire master active lo w slave device active low resistor pullup both master and slave device active low t l o w1 t l o w1 reset timing read/write timing dq stpz stpen=1 t on1 t on2 t on3 t on4 t dly2 t dly1 t off2 dq stpz stpen=stp_sply=1 t on1 t on3 t dly2 t dly1 t off2 t off2 t off1 t dly3 t dly3 t dly3 t dly3
DS1WM 14 of 20 write cycle read cycle ads a1,a0 en rd wr data d7-d0 valid valid data t ads t as t ah t es t rd t rvd t hz t ren t ar ads a1,a0 en wr rd data d7-d0 valid valid data t ads t as t ah t es t wr t ds t dh t wen t aw
DS1WM 15 of 20 generating a 1-wire reset ads a1,a0 en wr rd data d7-d0 0x01 0x00 dq intrpt t rstl t rsth t r t pdh t pdl t pdi t wrst t pds note : the 1-wire reset is initiated as a command written to address 0x00. the standard write cycle timing applies, as shown on the previous page.
DS1WM 16 of 20 timing specifications: data bus interface timing symbol parameter conditions min max units t ads address strobe width note 1,3 60 ns t ah address hold time note 1,3 0 ns t ar address latch to read note 1,3 60 ns t as address setup time note 1,3 60 ns t aw address latch to write note 1,3 60 ns t dh data hold time note 1 30 ns t ds data setup time note 1 30 ns t es enable setup time note 1 60 ns t hz rd to floating data delay note 1 0 100 ns t pdi presence detect to intr note 1 0 100 ns t rd rd strobe width note 1 125 ns t ren enable hold time from rd note 1 20 ns t rvd delay from rd to data note 1 60 ns t wen enable hold time from wr note 1 20 ns t wr wr strobe width note 1 100 ns t wrst wr high to reset note 1 0 100 ns one wire interface timing (note 2) symbol parameter conditions min max units t low0 write 0 low time standard 62.4 78 s overdrive 8 10 s t low1 write 1 low time standard 4.8 6 s standard ? long line mode 7.2 9 s overdrive 0.8 1 s t pdh presence detect high standard 15 60 s overdrive 2 6 s t pdl presence detect low standard 60 240 s overdrive 6 24 s t pds presence detect sample standard 24 31 s standard ? long line mode 30.4 38 s overdrive 2.4 4 s t rdv read data value standard 12 15 s standard ? long line mode 20 25 s overdrive 1.6 2 s t rec recovery time standard 6.4 8 s standard ? long line mode 11.2 14 s overdrive 4 5 s t rsth reset time high standard 508.8 636 s overdrive 59.2 74 s t rstl reset time low standard 500.8 626 s overdrive 50.4 63 s t slot time slot standard 68.8 86 s overdrive 12 15 s timebase period 0.8 1 s
DS1WM 17 of 20 one wire strong pull-up control (stpz) timing (note 2) symbol parameter conditions min max units notes t on1 active time for presence detect standard 6.4 8 s overdrive 0.8 1 s t on2 active time for presence detect recovery standard 8 10 s overdrive 8 10 s t on3 active time for write 1 recovery standard 51.2 64 s 4,5 overdrive 7.2 9 s 4,5 t on4 active time for write 0 recovery standard 6.4 8 s 4,5 overdrive 0.8 1 s 4,5 t dly1 delay time for presence detect standard 0.8 1 s overdrive 0.8 1 s t dly2 delay time for presence detect recovery standard 399.2 499 s 6 overdrive 31.2 39 s 6 t dly3 delay time for write1/write0 recovery standard 0.8 1 s overdrive 0.8 1 s t off1 turn off time for 1-wire reset standard 1.6 2 s overdrive 1.6 2 s t off2 turn off time for write1/write0 standard 0.8 1 s 7 overdrive 0.8 1 s 7 notes: 1. these values will depend upon the process used to re alize the circuit. values shown are for example purposes only. 2. the 1-wire master timing values are the times de pending upon the internal logi c. if the i/o drivers are slow, these times will change accordingly . 3. if ads is tied low, t ar and t aw are referred from t es ; thus rd or w r must occur at least t es + t ar or t es + t aw after en goes low. 4. there is no timing difference for sending out and r eceiving bits within a byte. the difference comes when the last bit of the byte is finished being se nt out. at this point, th e signal is either enabled continuously until the next reset or time slot begins, or enabled only for t on3 or t on4 . 5. when performing a read versus a write time slot, the master provides the same active time for write 1 and write 0. however, the input from the dq line is sensed every 1s for a hi gh value. if dq is high, the stpz signal is enabled. if the dq line is low, the stpz signal remains disabled until the high is sensed. in all write time slots, a high is sensed immediately. 6. this parameter is the time delay until the master begi ns to monitor the dq input level. if the line is already high, then stpz will be enabled. if not, it will wait to enable stpz until the next state machine clock after the dq line has recovered. 7. the very first bit in a byte tran smission will have an extended t off2 of 4s due to the order of states the master?s state machine runs through. references: [1] book of i button standards , dallas semiconductor, online at http://www.ibutton.com/ibuttons/standard.pdf
DS1WM 18 of 20 revision history 0.1 ? june 15, 1999 1. first release 0.2 ? july 12, 1999 1. clarification added that rd and w r should never be low simultaneously; if they are, w r takes precedence. 2. first draft of search rom driver code example added in section 6.0. 0.3 ? august 17, 1999 1. en is not latched by ads ; ads only controls an internal addr ess latch, which may be made transparent by tying ads low. en is a level-enabled signal, a nd does not need to be latched. 2. changed lower clock rate to 3.1 mhz. upda ted timing specifications to reflect this. 3. removed divsel0, divsel1, and divsel2 pins. clock division selection is now performed by writing to the clock divisor register; this makes it necessary to add an additional address line, a2, in order to select this register. 4. the 1-wire master is now double-buffered for recei ve and transmit operations; the data register is no longer a physical register but two registers ? the transmit buffer and the receive buffer. these two buffers are memory mapped to the same loca tion, where a write operati on selects the transmit buffer, and a read selects the receive buffer. fl ags tbe, temt, rbf, a nd rsrf are defined to signal when buffers are empty or full. 5. setting the 1-wire reset bit in the command regist er now automatically disables the search rom accelerator bit. 6. interrupts are automatically cleared by reading the interrupt register. 7. the result of a presence detect is now reported in the interrupt register instead of in the data register. this allows the pd interru pt service routine to read the re sult of a presence detect interrupt when it reads the interrupt register. 8. changed the way the interrupt and interrupt enable registers work ? it was backward initially. the interrupt register now is more of a status register, whose bits ge t anded with the interrupt enable register to determine if any of the flags set in that register cause the intr pin to go active. the active state of the intr pin is now programmable; defaul t is high on master reset. 9. removed example code. will need to be rewritten to comprehend changes made in specification of the hardware device. 0.4 ? august 20, 1999 1. clarified that master reset causes intr to go to its inactive state. this is further clarified in section 4.5 by defining the reset state of the interru pt enable register as cleared to all zeros, masking all interrupt sources and defining the active state of the intr pin as low. this implies that intr will go high upon mr. 2. by restricting the lower clock frequency to 3.2m hz, internal timing can now be between 1s and 1.25s. 3. corrected several grammatical, ty pographical, and spelling errors. 4. since the internal clock is the result of differe nt division ratios, the duty cycle may not be 50%. this is not a problem for the circui t, so all references to high and low times of the internal timebase have been deleted. the internal cl ock period is now referred to as , to simplify timing diagrams. 5. timing diagrams have been updated to reflect changes in nomenclature, and to clarify timing. 6. note 4 added to timing specification table. 7. section 6 renamed to ? applications hints and examples?. notes were added in this section regarding 1-wire wave shaping and power management.
DS1WM 19 of 20 0.5 ? august 24, 1999 1. in section 1.0, changed ?four registers? to ?five regi sters?, to reflect current actual register count. note that receive and transmit registers ar e actually 1 register in the memory map. 2. corrected block diagram to reflect 1.25s timebase maximum. 3. removed voltage specifications on logic high and low in section 3.0, as these will be process- specific. 4. changed lower clock rate to 3.2mhz in the text description of the clk pin. 5. removed t r specification. 6. t pds is now specified from the falling edge of the dq line after the line has been released by the master. the master will wait for up to 60s to detect a falling edge; but if the edge occurs before 60s, the master will wait 30s after that edge to sa mple the data line to read the presence detect. 7. fixed errors in timing specification table left ove r from the change to maximum internal timebase period of 1.25s. 0.6 ? september 17, 1999 1. tbe and temt default states changed to 1 instead of 0, to reflect their actual state (empty) upon a master reset. 1.0 ? september 20, 1999 1. changed the operation of the interrupt register. the rbf and rsrf flags are no longer automatically cleared when a read operation is performed on the interrupt register. doing so would allow for data to be overwritten if the in terrupt handler did not do a read of the receive buffer immediately following the interrupt. these fl ags are now cleared when the data has actually been read or shifted out. 2. revision 1.000 of the vhdl code is complete, and this specification reflects th e current operation of that vhdl code. thus, the revision number for this specification is changed to 1.0 and t operation 31 october, 1999. 3. revision 1.2 of the datasheet comple te. format has been changed to lo ok like a standard ds datasheet. verilog version of the code is also complete. both types undergoing testing on the bench. 21 november, 2000. 1. receive data no longer double buffere d. data is now immediately transferred to the receive buffer even if already full. 2. shift register flags removed from the interrupt a nd interrupt enable registers. no longer needed. 3. dqo and dqi added to the command regist er to control the bus directly. 4. low pulse widths for a write 1 changed from 1 s to 2s and for a write 0 from 75s to 30s. 5. interrupt register ? flags are no longer cleared on a read except for pd. intr is set inactive automatically on a read. 6. gate count updated to 1492 to re flect newest re vision on page 1. 13 september, 2001. 1. updated specification to match th e changes made to the verilog version of the master in the ds80c400. these changes have been placed into the verilog standalone version for which this document pertains. 2. added new interrupts, the control re gister, and all of the features included in the control register. 18 august, 2004 1. updated verilog version to not hardwi re ias bit. was hard-wired to active-low. it now performs as specified in this datasheet. 2. vhdl version updated to match this new spec, version number in source updated to 2.0.
DS1WM 20 of 20 3. gate count updated to 3470 to reflect newest revision on page 1. 14 may 2007 1. first release of reva mped verilog testbench 2. re-write of vhdl with rtl c onfirmed equivalent to verilog

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