integrated circuit systems, inc. ics95v157 0501c?11/24/08 block diagram 2.5v single-ended to sstl_2 clock driver (45mhz - 233mhz) pin configuration 48-pin tssop recommended application: single-ended clock input with zero delay board fan out product description/features: low skew, low jitter pll clock driver 1 to 10 differential clock distribution (sstl_2) feedback pin for input to output synchronization pd# for power management spread spectrum tolerant inputs switching characteristics: cycle - cycle jitter: <60ps output - output skew: <60ps period jitter: 30ps duty cycle: 49.5% - 50.5% functionality 6.10 mm. body, 0.50 mm. pitch = tssop s t u p n is t u p t u o e t a t s l l p d d v a# d pt n i _ k l ct k l cc k l ct t u o _ b f d n ghl lh l f f o / d e s s a p y b d n ghhhl h f f o / d e s s a p y b v 5 . 2 ) m o n ( llzz z f f o v 5 . 2 ) m o n ( lhzz z f f o v 5 . 2 ) m o n ( hl lh l n o v 5 . 2 ) m o n ( hhhl h n o
2 ics95v157 0501c?11/24/08 pin descriptions this pll clock buffer is designed for a v dd of 2.5v, an av dd of 2.5v and differential data input and output levels. ics95v157 is a zero delay buffer that distributes a single-ended clock input (clk_int) to ten differential pair of clock outputs (clkt[0:9], clkc[0:9]) and one single-ended feedback clock output (fb_outt). the clock outputs are controlled by the input clocks (clk_int), the feedback clock (fb_int), the 2.5-v lvcmos input (pd#) and the analog power input (av dd ). when input (pd#) is low while power is applied, the receivers are disabled, the pll is turned off and the differential clock outputs are tri-stated. when av dd is grounded, the pll is turned off and bypassed for test purposes. the pll in the ics95v157 clock driver uses the input clocks (clk_int) and the feedback clock (fb_int) to provide high-performance, low-skew, low-jitter, output differential clocks (clkt [0:9], clkc [0:9]). ics95v157 is also able to track spread spectrum clock (ssc) for reduced emi. ics95v157 is characterized for operation from 0c to 85c. r e b m u n n i pe m a n n i pe p y tn o i t p i r c s e d , 1 2 , 5 1 , 2 1 , 1 1 , 4 , 5 4 , 8 3 , 4 3 , 8 2 d d vr w pv 5 . 2 , y l p p u s r e w o p , 5 2 , 4 2 , 8 1 , 8 , 7 , 1 8 4 , 2 4 , 1 4 , 1 3 d n gr w pd n u o r g 6 1d d v ar w pv 5 . 2 , y l p p u s r e w o p g o l a n a 7 1d n g ar w pd n u o r g g o l a n a , 6 4 , 4 4 , 9 3 , 9 2 , 7 2 3 , 5 , 0 1 , 0 2 , 2 2 ] 0 : 9 [ t k l ct u os t u p t u o r i a p l a i t n e r e f f i d f o k c o l c " e u r t " , 7 4 , 3 4 , 0 4 , 0 3 , 6 2 2 , 6 , 9 , 9 1 , 3 2 ] 0 : 9 [ c k l ct u os t u p t u o r i a p l a i t n e r e f f i d f o s k c o l c " y r a t n e m e l p m o c " 3 1t n i _ k l cn it u p n i k c o l c e c n e r e f e r " e u r t " 2 3t t u o _ b ft u o s e h c t i w s t i . k c a b d e e f l a n r e t x e r o f d e t a c i d e d , t u p t u o k c a b d e e f " " e u r t " o t d e r i w e b t s u m t u p t u o s i h t . k l c e h t s a y c n e u q e r f e m a s e h t t a t n i _ b f 6 3t n i _ b fn i r o f l l p l a n r e t n i e h t o t l a n g i s k c a b d e e f s e d i v o r p , t u p n i k c a b d e e f " e u r t " r o r r e e s a h p e t a n i m i l e o t t n i _ k l c h t i w n o i t a z i n o r h c n y s 5 3 , 3 3 , 4 1c / n-d e t c e n n o c t o n 7 3# d pn it u p n i s o m c v l . n w o d r e w o p
3 ics95v157 0501c?11/24/08 absolute maximum ratings supply voltage (vdd & avdd) . . . . . . . . . . . -0.5v to 4.6v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd + 0.5 v ambient operating temperature . . . . . . . . . . 0c to +85c storage temperature . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters t a = 0 - 85c; supply voltage a vdd , v dd = 2.5 v +/- 0.2v (unless otherwise stated) parameter symbol conditions min typ max units input high current i ih v i = v dd or gnd 5 a input low current i il v i = v dd or gnd 5 a i dd2. 5 c l = 0pf @ 200mhz 148 ma i ddpd c l = 0pf 100 a high impedance output current i oz v dd = 2.7v, vout = v dd or gnd 10 ma input clamp voltage v ik v dd = 2.3v iin = -18ma -1.2 v i oh = -1 ma v dd - 0.1 v i oh = -12 ma 1.7v v i ol =1 ma 0.1 v i oh =12 ma 0.6 v input capacitance 1 c in v i = gnd or v dd 2.5 3.5 pf 1 guaranteed by design at 233mhz, not 100% tested in production. operating supply current high-level output voltage v oh low-level output voltage v ol
4 ics95v157 0501c?11/24/08 recommended operating condition (see note1) t a = 0 - 85c; supply voltage avdd, vdd = 2.5 v +/- 0.2v (unless otherwise stated) parameter symbol conditions min typ max units supply voltage v dd , a vdd 2.3 2.5 2.7 v clk_int, fb_int 0.4 v dd /2 - 0.18 v pd# -0.3 0.7 v clk_int, fb_int v dd /2 + 0.18 2.1 v pd# 1.7 v dd + 0.6 v dc input signal voltage (note 2) v in -0.3 v dd + 0.3 v output differential cross- voltage (note 4) v ox v dd /2 - 0.15 v dd /2 + 0.15 v high level output current i oh -6.4 ma low level output current i ol 5.5 ma operating free-air temperature t a 085c low level input voltage v il high level input voltage v ih notes: 1. unused inputs must be held high or low to prevent them from floating. 2. dc input signal voltage specifies the allowable dc execution of differential input. 3. differential inputs signal voltages specifies the differential voltage [vtr-vcp] required for switching, where vt is the true input level and vcp is the complementary input level. 4. differential cross-point voltage is expected to track variations of v dd and is the voltage at which the differential signal must be crossing.
5 ics95v157 0501c?11/24/08 notes: 1. refers to transition on noninverting output in pll bypass mode. 2. while the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. this is due to the formula: duty cycle=t wh /t c , where the cycle (t c ) decreases as the frequency goes up. 3. switching characteristics guaranteed for application frequency range. 4. static phase offset shifted by design. timing requirements t a = 0 - 85c; supply voltage a vdd , v dd = 2.5 v +/- 0.2v (unless otherwise stated) parameter symbol conditions min max units max clock frequency freq op 2.5v+ 0.2v @ 25 o c 45 233 mhz application frequency range freq app 2.5v+ 0.2v @ 25 o c 95 210 mhz input clock duty cycle d tin 40 60 % clk stabilization t stab 15 s switching characteristics (see note 3) parameter symbol condition min typ max units low-to high level propagation delay time t plh 1 clk_in to any output 5.5 ns high-to low level propagation delay time t pll 1 clk_in to any output 5.5 ns output enable time t en pd# to any output 5 ns output disable time tdis pd# to any output 5 ns period jitter t jit (per) 100mhz to 200mhz -30 30 ps half-period jitter t(jit_hper) 100mhz to 200mhz -75 30 ps input clock slew rate t sl(i) 14v/ns output clock slew rate t sl(o) 12.5v/ns cycle to cycle jitter 1 t cyc -t cyc 100mhz to 200mhz 60 ps phase error t (phase error) 4 -50 0 50 ps output to output skew t skew 60 ps
6 ics95v157 0501c?11/24/08 y x , fb_outc y x , fb_outt
7 ics95v157 0501c?11/24/08 (n is a large number of samples) t ( ) n+1 t ()n t () = 1 n= n t ()n n clk_inc clk_int fb_inc fb_int t (sk_o) y # x y , fb_outc x y , fb_outt x y , fb_outc x y , fb_outt x y , fb_outc x y , fb_outt x y x parameter measurement information figure 4. static phase offset figure 5. output skew 1 f o t = t - (jit_per) c(n) 1 f o figure 6. period jitter
8 ics95v157 0501c?11/24/08 clock inputs and outputs 80% 20% 80% 20% rise t sl fall t sl v id ,v od figure 8. input and output slew rates parameter measurement information t (hper_n) t (hper_n+1) 1 f o y , fb_outc x y , fb_outt x figure 7. half-period jitter t =- (jit_hper) t (jit_hper_n) 1 2xf o
9 ics95v157 0501c?11/24/08 ordering information 95v157 y g - t index area index area 12 1 2 n d e1 e seating plane seating plane a1 a a2 e -c- - c - b c l aaa c 6.10 mm. body, 0.50 mm. pitch tssop (240 mil) (20 mil) min max min max a--1.20--.047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 d e e1 6.00 6.20 .236 .244 e l 0.45 0.75 .018 .030 n 0 8 0 8 aaa -- 0.10 -- .004 variations min max min max 48 12.40 12.60 .488 .496 10-0039 n d mm. d (inch) ref er ence do c.: jedec pub licat io n 9 5, m o- 153 0.50 basic 0.020 basic see variations see variations see variations see variations 8.10 basic 0.319 basic symbol in millimeters in inches common dimensions common dimensions example: designation for tape and reel packaging package type g = tssop revision designator (will not correlate with datasheet revision) device type xxxx y g - t
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